Chiplet interconnect power state management

Abstract

The disclosed apparatus for power management of chiplet interconnects includes a plurality of chiplets connected via a plurality of interconnects. The device also includes a control circuit that detects an active state of the chiplets and manages a power state of the interconnects based on the detected active state. Various other methods, systems, and computer readable media are also disclosed.

Description

Background Art

[0001] As computing demands increase, different types of processor architectures have allowed for improved computing performance. For example, chiplet architectures can distribute a device's processing tasks across multiple chiplets that can be dedicated to certain processing tasks (e.g., graphics processing). As power demands increase for improved performance, device power management includes managing the power states of the chiplets. However, the interconnects connecting the chiplets themselves can draw power. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings illustrate several exemplary implementations and are a part of the specification. Together with the following description, these drawings illustrate and explain the various principles of the present disclosure.

[0003] Figure 1 is a block diagram of an exemplary system for chiplet interconnect power state management.

[0004] Figure 2 is a block diagram of an exemplary chiplet interconnect architecture.

[0005] Figures 3A to 3C A table illustrating various power states of the interconnect based on chiplet activity levels.

[0006] Figure 4 is a flow chart of an exemplary method for chiplet interconnect power state management.

[0007] Throughout the drawings, the same reference numerals and descriptions indicate similar, but not necessarily identical, elements. Although the exemplary embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the specific forms disclosed. On the contrary, this disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims. DETAILED DESCRIPTION

[0008] The present disclosure generally relates to managing the power states of chiplet interconnects. As will be explained in more detail below, specific implementations of the present disclosure can use the activity level of a chiplet to place the corresponding interconnect in an appropriate power state. By managing the interconnect power state, power consumption can be reduced, particularly during idle states, without significantly degrading performance.

[0009] In one embodiment, an apparatus for managing the power state of chiplet interconnects includes a plurality of chiplets connected via a plurality of interconnects and a control circuit configured to detect an activity state of at least one of the plurality of chiplets and manage the power state of at least one of the plurality of interconnects based on the detected activity state.

[0010] In some examples, the control circuitry is configured to manage a power state of at least one of the plurality of interconnects by reducing a power state of the interconnect when the corresponding chiplet is idle. In some examples, the control circuitry is configured to increase a power state of the interconnect when the corresponding chiplet becomes active.

[0011] In some examples, the control circuitry is configured to manage a power state of at least one of the plurality of interconnects by placing the interconnect in a deep power state when the corresponding chiplet and a chiplet in communication with the corresponding chiplet are idle. In some examples, the control circuitry is configured to increase the power state of the interconnect from the deep power state when at least one of the chiplets in communication with the corresponding chiplet becomes active.

[0012] In some examples, the control circuitry is configured to manage a power state of at least one interconnect of the plurality of interconnects by placing the interconnect in a shallow power state when the corresponding chiplet is idle and at least one chiplet in communication with the corresponding chiplet is active.

[0013] In some examples, the device further includes a second plurality of chiplets connected via a second plurality of interconnects, and the control circuitry is further configured to manage a power state of the second plurality of interconnects based on an activity state of the second plurality of chiplets. In some examples, the control circuitry manages the power state of the second plurality of interconnects independently of the activity state of the plurality of chiplets.

[0014] In some examples, the reduced power state of the interconnect limits the probing traffic.In some examples, the control circuitry is configured to manage a power state of each of the plurality of interconnects based on a power management policy associated with an activity state of a corresponding chiplet.

[0015] In one embodiment, a system for managing power states of chiplet interconnects includes a physical memory, at least one physical processor including a plurality of chiplets configured to communicate with each other via a plurality of interconnects, and a control circuit configured to detect an activity state of each chiplet in the plurality of chiplets and manage the power state of each interconnect in the plurality of interconnects based on the activity state of the corresponding chiplet.

[0016] In some examples, the control circuitry is configured to manage a power state of each of the plurality of interconnects by decreasing a power state of the interconnect when the corresponding chiplet is idle and increasing a power state of the interconnect when the corresponding chiplet becomes active.

[0017] In some examples, the control circuitry is configured to manage the power state of each of the plurality of interconnects by placing the interconnect in a deep power state when the corresponding chiplet and chiplets communicating with the corresponding chiplet are idle and increasing the power state of the interconnect from the deep power state when at least one of the chiplets communicating with the corresponding chiplet becomes active.

[0018] In some examples, the control circuitry is configured to manage a power state of each of the plurality of interconnects by placing the interconnect in a shallow power state when the corresponding chiplet is idle and at least one chiplet in communication with the corresponding chiplet is active.

[0019] In some examples, the system also includes a second plurality of chiplets connected via a second plurality of interconnects, and the control circuit is further configured to manage a power state of each interconnect in the second plurality of interconnects based on an activity state of a corresponding chiplet in the second plurality of chiplets independently of an activity state of the plurality of chiplets.

[0020] In some examples, the reduced power state of the interconnect limits the probing traffic.In some examples, the control circuitry is configured to manage a power state of each of the plurality of interconnects based on a power management policy associated with an activity state of a corresponding chiplet.

[0021] In one embodiment, a method for managing a power state of a chiplet interconnect includes: (i) detecting an activity state of a chiplet among a plurality of chiplets; (ii) using the detected activity state to apply a power management policy to select a power state for an interconnect among the plurality of interconnects that corresponds to the chiplet; and (iii) placing the interconnect in the selected power state.

[0022] In some examples, the power management strategy includes selecting a shallow power state for the interconnect when the chiplet is idle and at least one chiplet in communication with the chiplet is active. In some examples, the power management strategy includes selecting a deep power state when the chiplet and the chiplets in communication with the chiplet are idle.

[0023] According to the general principles described herein, the features of any specific implementation described herein can be used in combination with each other. These and other specific implementations, features and advantages will be more fully understood after reading the following detailed description in conjunction with the accompanying drawings and claims.

[0024] The following will refer to Figures 1 to 4 Provides a detailed description of managing the power states of chiplet interconnects. Figure 1 and Figure 2 A detailed description of an example system for chiplet interconnect power state management is provided. Figures 3A to 3C Provides a detailed description of an example chiplet interconnect power state management strategy. Figure 4 A detailed description of the corresponding computer-implemented method is provided.

[0025] Figure 1 1 is a block diagram of an example system 100 for power state management of chiplet interconnects. System 100 corresponds to a computing device such as a desktop computer, a laptop computer, a server, a tablet device, a mobile device, a smartphone, a wearable device, an augmented reality device, a virtual reality device, a network device, and / or an electronic device. Figure 1 As illustrated, system 100 includes one or more memory devices, such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical disk drive, cache, variations or combinations of one or more of the foregoing, and / or any other suitable memory.

[0026] like Figure 1 As illustrated, the example system 100 includes one or more physical processors, such as processor 110. Processor 110 generally represents any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In some examples, processor 110 accesses and / or modifies data and / or instructions stored in memory 120. Examples of processor 110 include, but are not limited to, chiplets (e.g., smaller and, in some examples, more specialized processing units that can be coordinated into a single chip), microprocessors, microcontrollers, central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs) implementing soft-core processors, application-specific integrated circuits (ASICs), systems on chip (SoCs), digital signal processors (DSPs), neural network engines (NNEs), accelerators, graphics processing units (GPUs), one or more portions of the foregoing, variations or combinations of one or more of the foregoing, and / or any other suitable physical processors.

[0027] like Figure 1As further shown, processor 110 includes control circuitry 112, chiplets 114, and interconnects 116. Control circuitry 112 corresponds to one or more controllers for power management of chiplet interconnects (e.g., interconnects 116) and includes circuitry and / or instructions for placing the chiplet interconnects into a desired power state. In some examples, control circuitry 112 may manage the power state of additional components, such as chiplets 114. Chiplets 114 may correspond to one or more chiplets of processor 110. Interconnects 116 correspond to one or more interconnects for linking chiplets 114 to various other components of processor 110. In some examples, system 100 may correspond to a computing system, such as a server system, having multiple processors (e.g., processor 110 may correspond to multiple processors), each having a chiplet (e.g., one or more chiplets 114) with an interconnect (e.g., one or more interconnects 116). In some examples, the control circuitry 112 can correspond to a plurality of control circuits or controllers that, in some implementations, can communicate with one another or otherwise coordinate for power management of the chiplet interconnects as described herein.

[0028] Figure 2 Illustrated is a device 200 (corresponding to system 100) having a chiplet architecture including a chiplet 214A (corresponding to an instance of chiplet 114), a chiplet 214B (corresponding to another instance of chiplet 114), a chiplet 214C (corresponding to another instance of chiplet 114, and more specifically, a graphics chiplet), a chiplet 214D (corresponding to another instance of chiplet 114, and more specifically, another graphics chiplet), and an IO chiplet 218. In some examples, a chiplet refers to a small integrated circuit designed for a specific functionality or subset of functionality that can work together as a single larger integrated circuit and can individually and / or collectively correspond to one or more of the following: a microprocessor, a microcontroller, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), a system on a chip (SoC), a digital signal processor (DSP), a neural network engine (NNE), an accelerator, a graphics processing unit (GPU), one or more portions of the foregoing, one or more variations or combinations of the foregoing, and / or any other suitable physical processor.

[0029] IO chiplet 218 corresponds to a host die, such as an input / output die (IOD) or other central die for coordinating the inputs and outputs of the various chiplets, such as chiplets 214A through 214D. In some examples, IO chiplet 218 may include control circuitry (e.g., control circuitry 112) for power management, but in other examples, the control circuitry may be separate. Figure 2 Not illustrated in the figure, the IO chiplet 218 can be connected to various other interfaces, peripherals, buses, etc.

[0030] Figure 2 Further illustrated are chiplet links or interconnects 216A (corresponding to an instance of interconnect 116), interconnect 216B (corresponding to another instance of interconnect 116), interconnect 216C (corresponding to another instance of interconnect 116), and interconnect 216D (corresponding to another instance of interconnect 116). In some examples, a link or interconnect refers to a circuit or other communication path that allows direct communication between connected dies and / or chiplets. Although in Figure 2 In the example embodiment, interconnects (e.g., interconnects 216A to 216D) connect chiplets (e.g., chiplets 214A to 214D) to a host die (e.g., IO chiplet 218), respectively, but in other examples, the interconnects may connect the chiplets themselves (e.g., connecting chiplet 214A to chiplet 214B, etc.). The interconnects may also allow communication between the respective caches of the chiplets, such as probes for the caches. When managing the cache hierarchy, probes are sent to maintain coherency between the caches (e.g., to prevent operations on stale cache data).

[0031] As will be further described herein, a power management policy may be applied to the interconnect based at least in part on the corresponding chiplet of the interconnect. While in some examples a global policy may be applied to all chiplets (e.g., chiplets 214A through 214D), in other examples individual policies may be used for groups of chiplets. For example, in Figure 2 In the example embodiment, chiplets 214A and 214B may correspond to compute chiplets that can operate separately and / or independently from chiplets 214C and 214D (e.g., graphics chiplets). In other words, chiplets 214A and 214B do not necessarily share workloads with chiplets 214C and 214D, such that the activity state of each chiplet group is independent of the power management of the other group. Therefore, chiplets 214C and 214D and interconnects 216C and 216D can be managed with separate policies.

[0032] Figures 3A to 3CVarious tables are illustrated, such as table 300, table 301, and table 302. Each of table 300, table 301, and table 302 represents an interconnect power state management strategy and refers to Figure 2 In some examples, a controller (e.g., control circuitry 112) can implement one or more of these strategies by, for example, observing the activity levels of the chiplets and commanding the interconnects to enter desired power states using various hardware and / or software tools.

[0033] Table 300 corresponds to a simple management strategy in which an interconnect can be placed in an on state or a reduced power state (e.g., a shallow power state) based on the activity level of the corresponding chiplet (e.g., active or idle). For example, when chiplet 214A is active, the corresponding interconnect 216A is on, and when chiplet 214A is idle, the controller reduces the power state of interconnect 216A to a shallow power state. More specifically, when both chiplet 214A and chiplet 214B are idle (e.g., chiplets that can communicate with each other for some processing tasks are both idle, indicating little or no current workload), the corresponding interconnect 216A and interconnect 216B can be placed in a shallow power state.

[0034] By placing the interconnect in a shallow power state rather than a deep power state, the delay or latency overhead of powering up the interconnect when the corresponding chiplet becomes active can be avoided. For example, if chiplet 214A becomes active and needs to communicate with chiplet 214B, interconnect 216A can be powered up more quickly than if interconnect 216A were in a deep power state. Exiting a reduced power state can incur a latency that can affect probe traffic, such as affecting the timeline being serviced by components requiring probes, and can also affect the requested bandwidth of components requiring probes for chiplets. Therefore, in some examples, a shallow power state can further allow probes to be sent / received along the interconnect. In other examples, a shallow power state can pause the sending / receiving of probes along the interconnect for a shorter period of time than a deep power state. However, even in a shallow power state, the interconnect does not draw power unnecessarily even though the corresponding chiplet is idle.

[0035] Table 301 presents an improved power management strategy. When both chiplet 214A and chiplet 214B are idle (indicating little or no current workload), no communication between the chiplets is expected. Therefore, interconnects 216A and 216B can be placed in a further reduced power state (e.g., a deep power state) to further reduce power consumption. In other words, because chiplets 214A and 214B are themselves idle and in a low power state, the risk of the chiplets needing to communicate for workload (and requiring a rapid power-up of the interconnects) is minimized. Additionally, because chiplets 214A and 214B are idle, their corresponding caches are also not in use, making probing of these caches unnecessary (e.g., the probing bandwidth for flushing caches can be zero). Therefore, placing interconnects 216A and 216B in a deep power state further avoids spending power on interconnects 216A and 216B when they are not being used by any coherent traffic (including probing).

[0036] Table 302 presents another improved power management strategy. In Table 302, an additional scenario is included where chiplet 214A is active and chiplet 214B is idle. In this scenario, interconnect 216A remains on because chiplet 214A is active. Interconnect 216B is placed in a shallow power state because chiplet 214B is idle. Instead of placing interconnect 216B in a deep power state, interconnect 216B is placed in a shallow power state to reduce the overhead of powering up interconnect 216B when chiplet 214A is communicating with chiplet 214B (e.g., compared to a deep power state). Thus, power savings are achieved through a simple strategy without significantly reducing performance.

[0037] In some implementations, the power management policy can be adjusted. For example, the power management policy can be adjusted to favor performance (e.g., toward shallower power states) or for aggressive power savings (e.g., toward deeper power states). In some implementations, the controller can dynamically update the power management policy, for example, by learning and / or otherwise determining which chiplets tend to communicate with which other chiplets for managing the corresponding interconnects, detecting usage patterns of the interconnects relative to the activities of the corresponding chiplets, and the like. For example, the power management policy can be updated to include different contexts between chiplets, such as adding a scenario between chiplets 214C and / or 214D and chiplets 214A and / or 214B, removing a scenario, and the like.

[0038] In addition, despite Figures 3A to 3CTwo chiplet / interconnect pairs and two low-power states (e.g., shallow and deep) are illustrated as a simplified example, but in other examples, various permutations of chiplets and states (e.g., scenarios) can be combined with various other power states as desired. Additionally, in other examples, the power management policy can be defined by rules, heuristics, factor-based decisions, etc.

[0039] Figure 4 is a flow chart of an exemplary method 400 for chiplet interconnect power state management. Figure 4 The steps shown in FIG. 1 may be implemented by any suitable circuit, computer executable code, and / or computing system (including Figure 1 and / or Figure 2 In one example, Figure 4 Each of the steps shown in represents an algorithm whose structure includes and / or is represented by a plurality of sub-steps, examples of which are provided in more detail below.

[0040] like Figure 4 As shown, at step 402, one or more of the systems described herein detects an activity state of a chiplet in a plurality of chiplets. For example, the control circuit 112 detects or otherwise identifies an activity state of the chiplet 114.

[0041] The systems described herein can perform step 402 in a variety of ways. In one example, control circuitry 112 can observe the activity level of chiplet 114 and / or read a corresponding status register.

[0042] At step 404, one or more of the systems described herein uses the detected activity state to apply a power management policy to select a power state for an interconnect of the plurality of interconnects corresponding to the chiplet. For example, the control circuitry 112 may use the detected activity state of the chiplet 114 to select a power state for the interconnect 116 to apply a power management policy.

[0043] The systems described herein can perform step 404 in a variety of ways. In one example, the power management policy can include selecting a shallow power state for the interconnect when the chiplet is idle and at least one chiplet in communication with the chiplet is active (see, e.g., Table 302). In some examples, the power management policy can include selecting a deep power state when the chiplet and the chiplets in communication with the chiplet are idle (see, e.g., Table 302).

[0044] At step 406, one or more of the systems described herein places the interconnect in the selected power state.For example, the control circuitry 112 may place the interconnect 116 in the selected power state.

[0045] The systems described herein can perform step 406 in a variety of ways. In one example, control circuitry 112 can instruct interconnect 116 to enter a selected power state.

[0046] As described in detail above, the systems and methods described herein provide power state management of chiplet interconnect links based on the activity levels of all chiplets. For a chiplet architecture, there is a need to manage the link states between chiplets. Chiplet interconnect links can draw a lot of power, and by keeping the links open, probe request traffic can increase. Therefore, it can be advantageous to reduce power draw and limit probe requests through these links through intelligent management of the link power states. Additionally, such management can be extended to have asymmetric power states between chiplets and interconnect links. Such chiplet interconnect power state management can help with power savings, but the accelerated processing unit (APU) needs to ensure that it does not put the links into power states at non-optimal times that will impact performance. Therefore, the systems and methods described herein monitor the activity of all chiplets and use that activity to influence the power state that the links transition to.

[0047] Specifically, when not all chiplets are active, the APU can save power by placing inactive chiplet interconnect links into shallow power states. Since some chiplets are active, this means that the APU is still working, just not at maximum capacity. Shallow power states are beneficial in this scenario because moderate levels of activity can quickly increase and require the resources of inactive chiplets. Therefore, waking up the interconnect links from a shallow power state limits the performance degradation of putting the links to sleep while saving as much power as possible. If the activity level decreases instead, more individual chiplets can be placed in shallow states until all chiplets become inactive. At this point, the APU will be considered idle and all chiplet interconnect links can be transitioned to deep power states to save maximum power when maximum performance is not needed. When the APU begins to see increased activity, all chiplet interconnect links can be brought back to a shallow power state where the number of links required for activity are fully awake.

[0048] As mentioned above, the computing devices and systems described and / or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions (such as those contained in the modules described herein). In its most basic configuration, these computing devices each include at least one storage device and at least one physical processor.

[0049] In some examples, the term "memory device" generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. In one example, a memory device stores, loads, and / or maintains one or more of the modules and / or circuits described herein. Examples of storage devices include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, a hard disk drive (HDD), a solid-state drive (SSD), an optical drive, a cache, variations or combinations of one or more of the foregoing, or any other suitable memory.

[0050] In some examples, the term "physical processor" generally refers to any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, the physical processor accesses and / or modifies one or more modules stored in the above-mentioned memory device. Examples of physical processors include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a field programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), a system on a chip (SoC), a digital signal processor (DSP), a neural network engine (NNE), an accelerator, a graphics processing unit (GPU), one or more portions of the foregoing, one or more variations or combinations of the foregoing, or any other suitable physical processor.

[0051] In some implementations, the term "computer-readable medium" generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media such as carrier waves, and non-transitory media such as magnetic storage media (e.g., hard drives, tape drives, and floppy disks), optical storage media (e.g., compact disks (CDs), digital video disks (DVDs), and Blu-ray disks), electronic storage media (e.g., solid-state drives and flash memory media), and other distribution systems.

[0052] The order of process parameters and steps described and / or illustrated herein is provided by way of example only and may be varied as needed. For example, although the steps illustrated and / or described herein are shown or discussed in a particular order, these steps do not necessarily need to be performed in the order illustrated or discussed. The various exemplary methods described and / or illustrated herein may also omit one or more steps described or illustrated herein, or include additional steps in addition to those disclosed.

[0053] The foregoing description has been provided to enable others skilled in the art to best utilize the various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein should be considered in all respects as illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0054] Unless otherwise indicated, the terms "connected to" and "coupled to" (and their derivatives) as used in the specification and claims will be construed to allow both direct and indirect (i.e., via other elements or components) connections. Additionally, the terms "a" or "an" as used in the specification and claims will be construed to mean "at least one." Finally, for ease of use, the terms "including" and "having" (and their derivatives) as used in the specification and claims are interchangeable with the word "comprising" and have the same meaning.

Claims

1. A device, comprising: a plurality of chiplets connected via a plurality of interconnects; and A control circuit, the control circuit being configured to: detecting an activity state of at least one of the plurality of chiplets; and managing a power state of at least one of the plurality of interconnects based on the detected activity state.

2. The apparatus of claim 1 , wherein the control circuitry is configured to manage the power state of at least one of the plurality of interconnects by lowering the power state of the interconnect when a corresponding chiplet is idle.

3. The apparatus of claim 2, wherein the control circuit is configured to increase the power state of the interconnect when the corresponding chiplet becomes active.

4. The apparatus of claim 1 , wherein the control circuitry is configured to manage the power state of at least one of the plurality of interconnects by placing the interconnect in a deep power state when the corresponding chiplet and a chiplet communicating with the corresponding chiplet are idle.

5. The apparatus of claim 4 , wherein the control circuit is configured to increase the power state of the interconnect from the deep power state when at least one of the chiplets in communication with the corresponding chiplet becomes active.

6. The apparatus of claim 1 , wherein the control circuitry is configured to manage the power state of at least one of the plurality of interconnects by placing the interconnect in a shallow power state when the corresponding chiplet is idle and at least one chiplet in communication with the corresponding chiplet is active.

7. The device of claim 1 , wherein the device further comprises a second plurality of chiplets connected via a second plurality of interconnects, and the control circuitry is further configured to manage a power state of the second plurality of interconnects based on an activity state of the second plurality of chiplets.

8. The apparatus of claim 7, wherein the control circuit manages the power state of the second plurality of interconnects independently of an activity state of the plurality of chiplets.

9. The apparatus of claim 1, wherein the reduced power state of the plurality of interconnects limits probing traffic.

10. The apparatus of claim 1, wherein the control circuit is configured to manage the power state of each of the plurality of interconnects based on a power management policy associated with an activity state of a corresponding chiplet.

11. A system, comprising: physical memory; at least one physical processor comprising a plurality of chiplets configured to communicate with each other via a plurality of interconnects; and A control circuit, the control circuit being configured to: detecting an activity state of each chiplet in the plurality of chiplets; as well as A power state of each of the plurality of interconnects is managed based on an activity state of a corresponding chiplet.

12. The system of claim 11 , wherein the control circuit is configured to manage the power state of each of the plurality of interconnects by lowering the power state of the interconnect when the corresponding chiplet is idle and increasing the power state of the interconnect when the corresponding chiplet becomes active.

13. The system of claim 11 , wherein the control circuitry is configured to manage the power state of each of the plurality of interconnects by placing the interconnect in a deep power state when the corresponding chiplet and the chiplets communicating with the corresponding chiplet are idle and increasing the power state of the interconnect from the deep power state when at least one of the chiplets communicating with the corresponding chiplet becomes active.

14. The system of claim 11 , wherein the control circuit is configured to manage the power state of each of the plurality of interconnects by placing the interconnect in a shallow power state when the corresponding chiplet is idle and at least one chiplet in communication with the corresponding chiplet is active.

15. The system of claim 11 , further comprising a second plurality of chiplets connected via a second plurality of interconnects, and wherein the control circuit is further configured to manage a power state of each of the second plurality of interconnects based on an activity state of a corresponding chiplet in the second plurality of chiplets independently of an activity state of the plurality of chiplets.

16. The system of claim 11, wherein the reduced power state of the plurality of interconnects limits probing traffic.

17. The system of claim 11, wherein the control circuit is configured to manage the power state of each of the plurality of interconnects based on a power management policy associated with the activity state of the corresponding chiplet.

18. A method comprising: detecting an activity state of a chiplet among a plurality of chiplets; applying a power management policy using the detected activity state to select a power state for an interconnect of a plurality of interconnects corresponding to the chiplet; and The interconnect is placed in a selected power state.

19. The method of claim 18, wherein the power management strategy comprises selecting a shallow power state for the interconnect when the chiplet is idle and at least one chiplet in communication with the chiplet is active.

20. The method of claim 18, wherein the power management strategy comprises selecting a deep power state when the chiplet and chiplets in communication with the chiplet are idle.

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