Temperature compensation circuit for logarithmic detector and logarithmic detector thereof

Abstract

The present application belongs to the technical field of integrated circuit signal processing, and discloses a temperature compensation circuit for a logarithmic detector and the logarithmic detector, wherein the temperature compensation circuit for the logarithmic detector comprises a first temperature compensation module, a second temperature compensation module and a third temperature compensation module; the first temperature compensation module is used for temperature compensation of a current summation module, the second temperature compensation module is used for temperature compensation of a bias voltage and a current of a limiting amplifier module, and the third temperature compensation module is used for temperature compensation of a bias voltage and a current of a rectifier module. The present application is suitable for temperature compensation of a current summation module, a limiting amplifier module and a rectifier module of a logarithmic detector, and improves the output precision and consistency of the logarithmic detector.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit signal processing technology, and relates to a temperature compensation circuit for a logarithmic detector and the logarithmic detector thereof. Background Technology

[0002] A logarithmic detector is an important component that converts radio frequency power signals logarithmically to baseband signals, and is widely used in fields such as automatic gain control and pulse detection. Ideally, the output voltage of a logarithmic detector changes linearly with the amplitude or power of the input signal, and can be quantified as slope and intercept. However, in practical applications, when the amplitude of the input signal remains constant, temperature changes can cause the intercept of the linear voltage to drift. Therefore, temperature compensation is required to ensure the output accuracy and consistency of the logarithmic detector under different temperature conditions.

[0003] Existing temperature compensation methods typically employ, for example... Figure 1 The first temperature compensation module shown uses positive and negative thermocurrents to compensate for the temperature of the current summation module. However, it only compensates for the current summation module, ignoring the temperature characteristics of the other modules of the logarithmic detector. Furthermore, the effect of temperature compensation only in the current summation module is limited, and the temperature compensation is not efficient. Summary of the Invention

[0004] The purpose of this invention is to provide a temperature compensation circuit for a logarithmic detector. By introducing first to third temperature compensation modules, the current summation module, rectifier module and limiting amplifier module of the logarithmic detector are respectively temperature compensated, thereby reducing the deviation of the logarithmic detector output under different temperature conditions.

[0005] Another objective of this invention is to provide a logarithmic detector that improves output accuracy and consistency by introducing an effective temperature compensation circuit.

[0006] To achieve the above objectives, the technical solution adopted by this invention is as follows:

[0007] A temperature compensation circuit for a logarithmic detector includes a first temperature compensation module, the output of which is connected to the input of a current summing module in the logarithmic detector for temperature compensation of the current summing module, and also includes a second temperature compensation module and a third temperature compensation module.

[0008] The first output terminal of the second temperature compensation module is connected to the first input terminal of the limiting amplifier bias module in the logarithmic detector, and the second output terminal of the second temperature compensation module is connected to the second input terminal of the limiting amplifier bias module. The second temperature compensation module is used to perform temperature compensation on the bias voltage and current of the limiting amplifier module in the logarithmic detector.

[0009] The output of the third temperature compensation module is connected to the input of the rectifier bias module, and is used to perform temperature compensation on the bias voltage and current of the rectifier module in the logarithmic detector.

[0010] As a limitation, the second temperature compensation module includes a fourth resistor, a fifth resistor, a sixth resistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0011] The emitter of the sixth transistor is connected to the input current. The base and collector of the sixth transistor are connected to one end of the fourth resistor, one end of the fifth resistor, and one end of the sixth resistor, respectively. The other end of the fourth resistor is grounded. The other end of the fifth resistor is connected to the base of the seventh transistor. The emitter of the seventh transistor is grounded. The collector of the seventh transistor serves as the first output terminal of the second temperature compensation module and is connected to the first input terminal of the limiting amplifier bias module. The other end of the sixth resistor is connected to the base of the eighth transistor. The emitter of the eighth transistor is grounded. The collector of the eighth transistor serves as the second output terminal of the second temperature compensation module and is connected to the second input terminal of the limiting amplifier bias module.

[0012] As a second limitation, the third temperature compensation module includes a tenth resistor, an eleventh resistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and a first MOSFET, and also includes a plurality of second MOSFETs, the same number as the number of rectifiers in the rectifier module of the logarithmic detector.

[0013] One end of the tenth resistor is grounded and connected to the emitter of the seventeenth transistor, and the other end of the tenth resistor is connected to the emitter of the fifteenth transistor. The base of the fifteenth transistor is connected to the collector of the seventeenth transistor and the emitter of the sixteenth transistor, respectively. The collector of the fifteenth transistor is connected to the emitter of the fourteenth transistor and the base of the seventeenth transistor, respectively. The base of the fourteenth transistor is connected to the base of the sixteenth transistor, one end of the eleventh resistor, and the collector of the sixteenth transistor, respectively. The collector of the fourteenth transistor is connected to the drain of the first MOSFET, the gate of the first MOSFET, and the gate of each second MOSFET, respectively. The other end of the eleventh resistor, the source of the first MOSFET, and the source of each second MOSFET are all connected to the power supply terminal. The drain of each second MOSFET serves as the output terminal of the third temperature compensation module and is connected to the input terminal of the rectifier bias module.

[0014] The present invention also provides a logarithmic detector, comprising: a limiting amplifier module, a rectifier module, a current summing module, a DC offset elimination module, a reference module, a bias module, a voltage-to-current module, a current-to-voltage module, and the temperature compensation circuit for the above-mentioned logarithmic detector;

[0015] A limiting amplifier module includes N stages of limiting amplifiers, which are cascaded in sequence. The input terminal of the first stage limiting amplifier is connected to the radio frequency signal input terminal, where N is a natural number not less than 1. The limiting amplifier module is used to limit and amplify the input signal.

[0016] The rectifier module includes N+1 rectifiers. The input terminal of the first-stage limiting amplifier is connected to a rectifier, and the output terminal of each stage limiting amplifier is connected to a rectifier. The rectifier module is used to convert the input signal of the limiting amplifier module into a detection current.

[0017] A current summing module is connected to the output terminal of each rectifier in the rectifier module and is used to sum the detected current of the rectifier module to the filter capacitor.

[0018] The current-to-voltage module is used to convert the detected current, which is summed by the current summation module and fed to the filter capacitor, into a voltage output.

[0019] The voltage-to-current module is used to convert the input voltage into current to achieve a feedback closed loop;

[0020] A DC offset cancellation module is connected between the input terminal of the first-stage limiting amplifier and the output terminal of the Nth-stage limiting amplifier to reduce the DC deviation generated after passing through the limiting amplifier module.

[0021] The reference module is used to generate a reference that is provided to the bias module.

[0022] The bias module includes a limiting amplifier bias module and a rectifier bias module. The limiting amplifier bias module is used to provide a stable bias voltage and current for the limiting amplifier module; the rectifier bias module is used to provide a stable bias voltage and current for the rectifier module.

[0023] As a limitation, the limiting amplifier bias module includes a seventh resistor, an eighth resistor, a ninth resistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0024] The emitter of the ninth transistor is connected to the power supply terminal, the base of the ninth transistor is connected to the first bias voltage, the collector of the ninth transistor is connected to the emitter of the tenth transistor through the seventh resistor, the base of the tenth transistor is connected to the second bias voltage, the collector of the tenth transistor is connected to the collector of the eleventh transistor and the base of the twelfth transistor respectively, and then serves as the first input terminal of the limiting amplifier bias module and is connected to the first output terminal of the second temperature compensation module. The base of the eleventh transistor is connected to the third bias voltage and the base of the thirteenth transistor respectively, and the emitter of the eleventh transistor is grounded. The collector of the twelfth transistor is connected to the power supply terminal, the emitter of the twelfth transistor is connected to one end of the eighth resistor and one end of the ninth resistor respectively, and then serves as the output terminal of the limiting amplifier bias module and is connected to the input terminal of the limiting amplifier module. The other end of the eighth resistor is connected to the collector of the thirteenth transistor, and the emitter of the thirteenth transistor is grounded. The other end of the ninth resistor serves as the second input terminal of the limiting amplifier bias module and is connected to the second output terminal of the second temperature compensation module.

[0025] As a second limitation, the rectifier bias module includes a plurality of rectifier bias circuits, the same number as the number of rectifiers in the rectifier module;

[0026] Each rectifier bias circuit includes a twelfth resistor and an eighteenth transistor. The emitter of the eighteenth transistor is connected to one end of the twelfth resistor, and the other end of the twelfth resistor is grounded. The bases of the eighteenth transistors in each rectifier bias circuit are connected together and connected to the fourth bias voltage. The collector of each eighteenth transistor is connected to the drain of the corresponding second MOSFET in the third temperature compensation module, and the collector of the eighteenth transistor is connected as the output terminal to the bias input terminal of the corresponding rectifier.

[0027] The present invention, by adopting the above-described technical solution, achieves the following technical advancements compared to existing technologies:

[0028] (1) The temperature compensation circuit for the logarithmic detector of the present invention includes a first temperature compensation module, a second temperature compensation module and a third temperature compensation module, wherein the first temperature compensation module is used to perform temperature compensation on the current summation module, the second temperature compensation module is used to perform temperature compensation on the bias voltage and current of the limiting amplifier module, and the third temperature compensation module is used to perform temperature compensation on the bias voltage and current of the rectifier module; by using three independently adjustable temperature compensation modules, the compensation effect of different modules can be adjusted according to different situations to achieve better compensation results for the overall circuit;

[0029] (2) The second temperature compensation circuit in this invention adopts a multi-stage transistor structure, which generates a stable temperature compensation current, providing a temperature compensation basis for the limiting amplifier module.

[0030] (3) In this invention, the third temperature compensation module provides a temperature compensation basis for the rectifier module through a positive temperature current generation circuit and a current mirror composed of multiple second MOSFETs.

[0031] (4) The present invention introduces a first temperature compensation module, a second temperature compensation module and a third temperature compensation module into the logarithmic detector. Compared with the existing logarithmic detector that performs single temperature compensation on the circuit summation module, the present invention performs temperature compensation on the current summation module, the limiting amplifier module and the rectifier module respectively, realizing comprehensive temperature compensation for the modules of the logarithmic detector that are easily affected, thereby improving the temperature compensation effect as a whole and improving the output accuracy of the logarithmic detector.

[0032] (5) By introducing an effective temperature compensation module into the logarithmic detector, the present invention reduces the deviation of the logarithmic detector output under different temperature conditions, thereby improving its output accuracy and consistency and meeting the needs of practical applications.

[0033] In summary, this invention is applicable to temperature compensation of the current summation module, limiting amplifier module, and rectifier module of a logarithmic detector, thereby improving the output accuracy and consistency of the logarithmic detector. Attached Figure Description

[0034] Figure 1 The diagram shown is a circuit schematic of the first temperature compensation module in the prior art.

[0035] Figure 2 The diagram shown is a circuit schematic of the second temperature compensation module in Embodiment 1 of the present invention.

[0036] Figure 3 The diagram shown is a circuit schematic of the third temperature compensation module in Embodiment 1 of the present invention.

[0037] Figure 4 The diagram shown is a circuit schematic of the logarithmic detector of Embodiment 2 of the present invention;

[0038] Figure 5 The diagram shown is a circuit schematic of the current summation module in Embodiment 2 of the present invention;

[0039] Figure 6 The diagram shown is a circuit schematic of the second temperature compensation module and the limiting amplifier bias module in Embodiment 2 of the present invention.

[0040] Figure 7 The diagram shown is a circuit diagram of the third temperature compensation module and the rectifier bias module in Embodiment 2 of the present invention.

[0041] Figure 8 The diagram shown is a circuit schematic of the voltage-to-current module in Embodiment 2 of the present invention.

[0042] Figure 9 The diagram shown is a schematic diagram of the external radio frequency signal input circuit in Embodiment 2 of the present invention.

[0043] Figure 10 The diagram shown is a circuit schematic of the logarithmic detector in Embodiment 2 of the present invention, which uses only the first temperature compensation module.

[0044] Figure 11 The figure shown is a simulation diagram of the logarithmic detector in Embodiment 2 of the present invention using only the first temperature compensation module;

[0045] Figure 12 The figure shown is a simulation diagram of the logarithmic detector using the first to third temperature compensation modules in Embodiment 2 of the present invention. Detailed Implementation

[0046] To better explain and facilitate understanding of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] Example 1: Temperature Compensation Circuit for Logarithmic Detector

[0048] This embodiment is a temperature compensation circuit for a logarithmic detector, including a first temperature compensation module, a second temperature compensation module, and a third temperature compensation module. The output of the first temperature compensation module is connected to the input of the current summation module in the logarithmic detector, and is used to perform temperature compensation on the current summation module to improve the temperature consistency of the logarithmic detector output. The first output of the second temperature compensation module is connected to the first input of the limiting amplifier bias module in the logarithmic detector, and the second output of the second temperature compensation module is connected to the second input of the limiting amplifier bias module. The second temperature compensation module is used to perform temperature compensation on the bias voltage and current of the limiting amplifier module in the logarithmic detector. The output of the third temperature compensation module is connected to the input of the rectifier bias module, and is used to perform temperature compensation on the bias voltage and current of the rectifier module in the logarithmic detector.

[0049] like Figure 1As shown, the first temperature compensation module includes a first resistor R1, a second resistor R2, a third resistor R3, an adjustable resistor RT, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, and a first operational amplifier; the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 are all NPN type transistors. In this circuit, one end of the adjustable resistor RT is grounded, and the other end of the adjustable resistor RT is connected to one end of the first resistor R1, one end of the second resistor R2, and the positive input terminal of the first operational amplifier. The other end of the first resistor R1 is connected to the voltage input terminal Vb, and the other end of the second resistor R2 is grounded. The negative input terminal of the first operational amplifier is connected to the emitter of the fifth transistor Q5 and one end of the third resistor R3, and the other end of the third resistor R3 is grounded. The output terminal of the first operational amplifier is connected to the base of the fifth transistor Q5. The collector of the fifth transistor Q5 is connected to the emitters of the first transistor Q1 and the second transistor Q2. The base of the first transistor Q1 is connected to the emitter of the third transistor Q3 and then to the input current Ib. The collector of the first transistor Q1 serves as the first output terminal Iout1 of the first temperature compensation module and is connected to the first input terminal ISETO of the current summation module in the logarithmic detector. The base of the second transistor Q2 is connected to the emitter of the fourth transistor Q4 and then to the input current Ib. ptat The collector of the second transistor Q2 is connected to the second output terminal Iout2 of the first temperature compensation module and the second input terminal IDET of the current summation module in the logarithmic detector; the base, collector, base, and collector of the third transistor Q3, the fourth transistor Q4, and the fourth transistor Q4 are respectively connected to the power supply terminal VDD.

[0050] like Figure 2 As shown, the second temperature compensation module includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8; the sixth transistor Q6 is a PNP type transistor, while the seventh transistor Q7 and the eighth transistor Q8 are NPN type transistors. The emitter of the sixth transistor Q6 is connected to the input current I... PTAT The sixth transistor Q6 is connected to its base and collector, which are then connected to one end of the fourth resistor R4, one end of the fifth resistor R5, and one end of the sixth resistor R6, respectively. The other end of the fourth resistor R4 is grounded. The other end of the fifth resistor R5 is connected to the base of the seventh transistor Q7, and the emitter of the seventh transistor Q7 is grounded. The collector of the seventh transistor Q7 serves as the first output terminal I of the second temperature compensation module. OUT1The first input terminal of the limiting amplifier bias module is connected; the other end of the sixth resistor R6 is connected to the base of the eighth transistor Q8, the emitter of the eighth transistor Q8 is grounded, and the collector of the eighth transistor Q8 serves as the second output terminal I of the second temperature compensation module. OUT2 Connect to the second input terminal of the limiting amplifier bias module.

[0051] like Figure 3 As shown, the third temperature compensation module includes a tenth resistor R10, an eleventh resistor R11, a fourteenth transistor Q14, a fifteenth transistor Q15, a sixteenth transistor Q16, a seventeenth transistor Q17, and a first MOSFET M1. It also includes multiple second MOSFETs M2, the same number as the rectifiers in the logarithmic detector's rectifier module. The fifteenth transistor Q15, sixteenth transistor Q16, and seventeenth transistor Q17 are all NPN transistors. One end of the tenth resistor R10 is grounded and connected to the emitter of the seventeenth transistor Q17. The other end of the tenth resistor R10 is connected to the emitter of the fifteenth transistor Q15. The base of the fifteenth transistor Q15 is connected to the collector of the seventeenth transistor Q17 and the emitter of the sixteenth transistor Q16. The collector of the fifteenth transistor Q15 is connected to the emitter of the fourteenth transistor Q14 and the base of the seventeenth transistor Q17. The base of the fourteenth transistor Q14 is connected to the base of the sixteenth transistor Q16... One end of the eleventh resistor R11 is connected to the collector of the sixteenth transistor Q16. The collector of the fourteenth transistor Q14 is connected to the drain of the first MOSFET M1, the gate of the first MOSFET M1, and the gate of each second MOSFET M2. The other end of the eleventh resistor R11, the source of the first MOSFET M1, and the source of each second MOSFET M2 are all connected to the power supply terminal VDD. The drain of each second MOSFET M2 is connected to the input terminal of the rectifier bias module as the output terminal of the third temperature compensation module.

[0052] Example 2: A Logarithmic Detector

[0053] like Figure 4 As shown, this embodiment is a logarithmic detector, including: a limiting amplifier module, a rectifier module, a current summation module Σ, a DC offset cancellation module DC_OC, a reference module VREF, a bias module BIAS, a voltage-to-current module VI, a current-to-voltage module IV, and a temperature compensation circuit for the logarithmic detector of Embodiment 1.

[0054] The limiting amplifier module includes N-stage limiting amplifiers, which are cascaded sequentially. The input terminal of the first-stage limiting amplifier is connected to the RF signal input terminal V. IP V IN The connection is made up of N, a natural number not less than 1. The limiting amplifier module is used to limit and amplify the input signal. Figure 4 In the diagram, N=6, which includes a six-stage limiting amplifier, labeled LA1 to LA6.

[0055] The rectifier module includes N+1 rectifiers. The input terminal of the first-stage limiting amplifier is connected to a rectifier, and the output terminal of each stage limiting amplifier is connected to a rectifier. The rectifier module is used to convert the input signal of the limiting amplifier module into a detection current. Figure 4 It includes seven rectifiers, labeled DET1 to DET7 in the diagram.

[0056] The current summation module Σ is connected to the output terminal of each rectifier in the rectifier module and is used to sum the detected current of the rectifier module to the filter capacitor.

[0057] The current-to-voltage module IV converts the detected current V, which is summed by the current summation module Σ and fed to the filter capacitor, into a voltage V. O Output.

[0058] The voltage-to-current module VI is used to convert the input voltage Vs into current to achieve a feedback closed loop.

[0059] The DC offset cancellation module DC_OC is connected between the input of the first-stage limiting amplifier and the output of the Nth-stage limiting amplifier to reduce the DC deviation generated after passing through the limiting amplifier module.

[0060] The reference module VREF is used to generate a reference that is provided to the bias module BIAS.

[0061] The bias module BIAS includes a limiting amplifier bias module and a rectifier bias module. The limiting amplifier bias module is used to provide a stable bias voltage and current for the limiting amplifier module; the rectifier bias module is used to provide a stable bias voltage and current for the rectifier module.

[0062] The temperature compensation circuit for the logarithmic detector includes a first temperature compensation module TEMPCOMP1, a second temperature compensation module TEMP COMP2, and a third temperature compensation module TEMP COMP3. The first temperature compensation module TEMP COMP1 is used to perform temperature compensation on the current summing module Σ. The second temperature compensation module TEMP COMP2 is used to perform temperature compensation on the bias voltage and current of the limiting amplifier module. The third temperature compensation module TEMPCOMP3 is used to perform temperature compensation on the bias voltage and current of the rectifier module.

[0063] like Figure 5The diagram shows the circuit schematic of the current summing module Σ. The first input terminal ISETO of the current summing module Σ is connected to the collector of the first transistor Q1 in the first temperature compensation module TEMPCOMP1, i.e., the first output terminal Iout1. The second input terminal IDET of the current summing module Σ is connected to the collector of the second transistor Q2, i.e., the second output terminal Iout2. Furthermore, the ISET terminal of the current summing module Σ is connected to the output terminal of the voltage-to-current module VI. The IDET terminal of the current summing module Σ is also connected to the output terminal of each rectifier. The output terminal of the current summing module Σ is the CLPF terminal, which is externally connected to a filter capacitor and then connected to the current-to-voltage module IV.

[0064] Specifically, through Figure 1 The working principle of the first temperature compensation module TEMPCOMP1 when performing temperature compensation on the current summation module Σ is as follows: The adjustable resistor RT, the first resistor R1 and the second resistor R2 in the circuit form a voltage divider circuit. Adjusting the resistance value of the adjustable resistor RT can change the resistance value of the adjustable resistor RT and the second resistor R2 in parallel, thereby changing the voltage division with the first resistor R1. Due to the presence of the first operational amplifier, the voltage on the third resistor R3 will also change with the change of the voltage divider circuit, thereby changing the magnitude of the current flowing through the third resistor R3. The first temperature compensation module TEMPCOMP1 has two input currents, Ib and Iptat, with different temperature coefficients. It has two outputs, including a first output terminal Iout1 and a second output terminal Iout2. The first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are BJTs of the same size. Because the temperature coefficients of the input currents Ib and Iptat are different, and the third transistor Q3 and the fourth transistor Q4 are the same, the base current temperatures of the first transistor Q1 and the second transistor Q2 are also different. Through the circuit design of the first temperature compensation module TEMPCOMP1, the output currents of the first transistor Q1 and the second transistor Q2 have two temperature coefficients: the first output terminal Iout1 has a positive temperature coefficient, and the second output terminal Iout2 has a negative temperature coefficient. The first output terminal Iout1 is connected to the ISETO terminal of the current summing module Σ circuit, and the second output terminal Iout2 is connected to the IDET terminal of the current summing module Σ circuit. Temperature compensation for the current summing module Σ is performed through the first output terminal Iout1 and the second output terminal Iout2.

[0065] like Figure 6As shown, the limiting amplifier bias module includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, and a thirteenth transistor Q13. The emitter of the ninth transistor Q9 is connected to the power supply terminal VDD, the base of the ninth transistor Q9 is connected to the first bias voltage Vb1, the collector of the ninth transistor Q9 is connected to the emitter of the tenth transistor Q10 through the seventh resistor R7, the base of the tenth transistor Q10 is connected to the second bias voltage Vb2, and the collector of the tenth transistor Q10 is connected to the collector of the eleventh transistor Q11 and the base of the twelfth transistor Q12, respectively, serving as the first input terminal of the limiting amplifier bias module and the first output terminal I of the second temperature compensation module TEMPCOMP2. OUT1 The eleventh transistor Q11's base is connected to the third bias voltage Vb3 and the base of the thirteenth transistor Q13, respectively, and the emitter of the eleventh transistor Q11 is grounded. The collector of the twelfth transistor Q12 is connected to the power supply terminal VDD. The emitter of the twelfth transistor Q12 is connected to one end of the eighth resistor R8 and one end of the ninth resistor R9, respectively, and then serves as the output terminal VB_LA of the limiting amplifier bias module, which is connected to the input terminal of the limiting amplifier module, i.e., connected to the base of the tail current transistor in each limiting amplifier in the limiting amplifier module. The other end of the eighth resistor R8 is connected to the collector of the thirteenth transistor Q13, and the emitter of the thirteenth transistor Q13 is grounded. The other end of the ninth resistor R9 serves as the second input terminal of the limiting amplifier bias module and is connected to the second output terminal I of the second temperature compensation module TEMPCOMP2. OUT2 connect.

[0066] Specifically, the working principle of the second temperature compensation module TEMPCOMP2, which performs temperature compensation on the limiting amplifier module through the limiting amplifier bias module, is as follows: the second temperature compensation module TEMPCOMP2 circuit has one input current I. PTAT There are two output currents, including the first output terminal I. OUT1 Second output terminal I OUT2 When the temperature is low, the input current I... PTAT The voltage across the fourth resistor R4 is relatively low, therefore the seventh transistor Q7 and the eighth transistor Q8 are in the off state; as the temperature gradually increases, the input current I... PTAT As the voltage gradually increases, the voltage across the fourth resistor R4 increases, turning on the seventh transistor Q7 and the eighth transistor Q8, and the first output terminal I... OUT1 Second output terminal I OUT2 Both channels are enabled, first output terminal I OUT1 The base of the twelfth transistor Q12 in the limiting amplifier bias module circuit is compensated, and the second output terminal I... OUT2One end of the ninth resistor R9 is connected, and the other end of the ninth resistor R9 is connected to the emitter of the twelfth transistor Q12 for compensation, thereby achieving bias compensation for the limiting amplifier module. By setting the second temperature compensation module TEMPCOMP2, the output of the limiting amplifier module is adjusted, thereby adjusting the output of the subsequent rectifier module, current summation module Σ and current-to-voltage module IV, thus achieving the purpose of temperature compensation.

[0067] The rectifier bias module includes multiple rectifier bias circuits, the same number as the rectifiers in the rectifier module. Each rectifier bias circuit includes a twelfth resistor R12 and an eighteenth transistor Q18. The emitter of the eighteenth transistor Q18 is connected to one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 is grounded. The bases of the eighteenth transistors Q18 in each rectifier bias circuit are all connected together and to the fourth bias voltage Vb4. The collectors of each eighteenth transistor Q18 are respectively connected to... Figure 3 The drain of the second MOSFET M2 in the third temperature compensation module TEMP COMP3 is connected, and the collector of the eighteenth transistor Q18 is connected to the bias input of the corresponding rectifier as the output terminal.

[0068] like Figure 7 As shown, when the number of rectifiers in the rectifier module is seven, the rectifier bias module includes seven rectifier bias circuits, the third temperature compensation module TEMPCOMP3 includes seven second MOSFETs M2, and the collector of the eighteenth transistor Q18 in the rectifier bias circuit is connected to the rectifier and the second MOSFETs M2 in a one-to-one correspondence.

[0069] by Figure 7 For example, when the third temperature compensation module TEMPCOMP3 performs temperature compensation on the bias voltage and current of the rectifier module, the fourteenth transistor Q14, fifteenth transistor Q15, sixteenth transistor Q16, seventeenth transistor Q17, tenth resistor R10, and eleventh resistor R11 in the TEMPCOMP3 circuit form a positive temperature current generation circuit. Multiple second MOSFETs M2 act as current mirrors, used to replicate the positive temperature current generated by the positive temperature current generation circuit. The replicated current is then compared with the current generated by the eighteenth transistor Q18 in each rectifier bias circuit. The resulting currents are then output through the NIBO terminal. <0> ~NIBO <6> Output, NIBO output terminal <0> ~NIBO <6> The compensation is supplied to the seven rectifiers in the rectifier module, and then to the voltage output terminal through the current summation module Σ and the current-to-voltage module IV, thereby achieving the purpose of temperature compensation.

[0070] like Figure 8The diagram shows the circuit schematic of the voltage-to-current module VI, which includes a second operational amplifier, a twenty-third resistor R23, and a twenty-ninth transistor Q29. The positive input terminal of the second operational amplifier is connected to the input voltage Vs, and the negative input terminal is connected to one end of the twenty-third resistor R23 and the emitter of the twenty-ninth transistor Q29. The other end of the twenty-third resistor R23 is grounded. The output terminal of the second operational amplifier is connected to the base of the twenty-ninth transistor Q29, and the collector of the twenty-ninth transistor Q29 is connected to the ISET terminal of the current summing module Σ.

[0071] The voltage-to-current module VI is an approximately linear regulator structure. The voltages at the two input terminals of the second operational amplifier are equal, that is, the voltage across the twenty-third resistor R23 is Vs. The collector output ISET = VS / R29 of the twenty-ninth transistor Q29 is sent to the ISET terminal of the current summing module Σ.

[0072] The working principle of the logarithmic detector in this embodiment is as follows:

[0073] The first temperature compensation module TEMPCOMP1 performs temperature compensation on the current summation module Σ, the second temperature compensation module TEMPCOMP2 performs temperature compensation on the bias voltage and current of the limiting amplifier module, and the third temperature compensation module TEMPCOMP3 performs temperature compensation on the bias voltage and current of the rectifier module.

[0074] Radio frequency signals pass through, such as Figure 9 The external RF signal input circuit shown is input to the RF input port V. IP and V IN The radio frequency signal is amplified sequentially by six-stage limiting amplifiers LA1 to LA6, and then the input signal of the limiting amplifiers is converted into a detection current by rectifiers DET1 to DET7. The output terminals of all rectifiers are connected to the IDET terminal of the current summing module Σ. The current summing module Σ sums the detection current of the rectifier module to the filter capacitor, and then the detection current is converted into a voltage V by the current-to-voltage module IV. O Output.

[0075] To verify the effectiveness of this embodiment, this embodiment will be compared with... Figure 10 The logarithmic detector that uses only the first temperature compensation module TEMPCOMP1 to perform temperature compensation on the current summation module Σ is compared. The results are... Figure 11 The simulation diagram shown is a comparative example, and Figure 12 The simulation diagram shown is from this embodiment. Figure 11 and Figure 12The simulation results were obtained under the following conditions: an input RF signal frequency of 100MHz, a power of -60dBm to 10dBm, and temperatures of -40℃, 25℃, and 105℃. ERROR represents the output error of the logarithmic detector at each temperature. Figure 11 and Figure 12 As can be seen from the data, except when the input power is -60dBm, the output error of this embodiment is smaller than that of the comparative embodiment, indicating that the logarithmic detector of this embodiment has high output accuracy.

[0076] It should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art can still modify the technical solutions described in the above embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A temperature compensation circuit for a logarithmic detector, comprising a first temperature compensation module, the output terminal of the first temperature compensation module being connected to the input terminal of a current summing module in the logarithmic detector, for performing temperature compensation on the current summing module, characterized in that, It also includes a second temperature compensation module and a third temperature compensation module; The first output terminal of the second temperature compensation module is connected to the first input terminal of the limiting amplifier bias module in the logarithmic detector, and the second output terminal of the second temperature compensation module is connected to the second input terminal of the limiting amplifier bias module. The second temperature compensation module is used to perform temperature compensation on the bias voltage and current of the limiting amplifier module in the logarithmic detector. The output of the third temperature compensation module is connected to the input of the rectifier bias module, and is used to perform temperature compensation on the bias voltage and current of the rectifier module in the logarithmic detector. The second temperature compensation module includes a fourth resistor, a fifth resistor, a sixth resistor, a sixth transistor, a seventh transistor, and an eighth transistor; The emitter of the sixth transistor is connected to the input current. The base and collector of the sixth transistor are connected to one end of the fourth resistor, one end of the fifth resistor, and one end of the sixth resistor, respectively. The other end of the fourth resistor is grounded. The other end of the fifth resistor is connected to the base of the seventh transistor. The emitter of the seventh transistor is grounded. The collector of the seventh transistor serves as the first output terminal of the second temperature compensation module and is connected to the first input terminal of the limiting amplifier bias module. The other end of the sixth resistor is connected to the base of the eighth transistor. The emitter of the eighth transistor is grounded. The collector of the eighth transistor serves as the second output terminal of the second temperature compensation module and is connected to the second input terminal of the limiting amplifier bias module. The third temperature compensation module includes a tenth resistor, an eleventh resistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and a first MOSFET, and also includes a plurality of second MOSFETs, the same number as the rectifiers in the rectifier module of the logarithmic detector. One end of the tenth resistor is grounded and connected to the emitter of the seventeenth transistor, and the other end of the tenth resistor is connected to the emitter of the fifteenth transistor. The base of the fifteenth transistor is connected to the collector of the seventeenth transistor and the emitter of the sixteenth transistor, respectively. The collector of the fifteenth transistor is connected to the emitter of the fourteenth transistor and the base of the seventeenth transistor, respectively. The base of the fourteenth transistor is connected to the base of the sixteenth transistor, one end of the eleventh resistor, and the collector of the sixteenth transistor, respectively. The collector of the fourteenth transistor is connected to the drain of the first MOSFET, the gate of the first MOSFET, and the gate of each second MOSFET, respectively. The other end of the eleventh resistor, the source of the first MOSFET, and the source of each second MOSFET are all connected to the power supply terminal. The drain of each second MOSFET serves as the output terminal of the third temperature compensation module and is connected to the input terminal of the rectifier bias module.

2. A logarithmic detector, characterized in that, include: A limiting amplifier module, a rectifier module, a current summing module, a DC offset elimination module, a reference module, a bias module, a voltage-to-current module, a current-to-voltage module, and a temperature compensation circuit for a logarithmic detector as described in claim 1; A limiting amplifier module includes N stages of limiting amplifiers, which are cascaded in sequence. The input terminal of the first stage limiting amplifier is connected to the radio frequency signal input terminal, where N is a natural number not less than 1. The limiting amplifier module is used to limit and amplify the input signal. The rectifier module includes N+1 rectifiers. The input terminal of the first-stage limiting amplifier is connected to a rectifier, and the output terminal of each stage limiting amplifier is connected to a rectifier. The rectifier module is used to convert the input signal of the limiting amplifier module into a detection current. A current summing module is connected to the output terminal of each rectifier in the rectifier module and is used to sum the detected current of the rectifier module to the filter capacitor. The current-to-voltage module is used to convert the detected current, which is summed by the current summation module and fed to the filter capacitor, into a voltage output. The voltage-to-current module is used to convert the input voltage into current to achieve a feedback closed loop; A DC offset cancellation module is connected between the input terminal of the first-stage limiting amplifier and the output terminal of the Nth-stage limiting amplifier to reduce the DC deviation generated after passing through the limiting amplifier module. The reference module is used to generate a reference that is provided to the bias module. The bias module includes a limiting amplifier bias module and a rectifier bias module. The limiting amplifier bias module is used to provide a stable bias voltage and current for the limiting amplifier module; the rectifier bias module is used to provide a stable bias voltage and current for the rectifier module.

3. The logarithmic detector according to claim 2, characterized in that, The limiting amplifier bias module includes a seventh resistor, an eighth resistor, a ninth resistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The emitter of the ninth transistor is connected to the power supply terminal, the base of the ninth transistor is connected to the first bias voltage, the collector of the ninth transistor is connected to the emitter of the tenth transistor through the seventh resistor, the base of the tenth transistor is connected to the second bias voltage, the collector of the tenth transistor is connected to the collector of the eleventh transistor and the base of the twelfth transistor respectively, and then serves as the first input terminal of the limiting amplifier bias module and is connected to the first output terminal of the second temperature compensation module, the base of the eleventh transistor is connected to the third bias voltage and the base of the thirteenth transistor respectively, and the emitter of the eleventh transistor is grounded; the collector of the twelfth transistor is connected to the power supply terminal, and the emitter of the twelfth transistor is connected to one end of the eighth resistor and one end of the ninth resistor respectively, and then serves as the output terminal of the limiting amplifier bias module and is connected to the input terminal of the limiting amplifier module. The other end of the eighth resistor is connected to the collector of the thirteenth transistor, and the emitter of the thirteenth transistor is grounded; the other end of the ninth resistor is connected as the second input terminal of the limiting amplifier bias module and the second output terminal of the second temperature compensation module.

4. The logarithmic detector according to claim 2, characterized in that, The rectifier bias module includes multiple rectifier bias circuits, the same number of which are rectifiers in the rectifier module. Each rectifier bias circuit includes a twelfth resistor and an eighteenth transistor. The emitter of the eighteenth transistor is connected to one end of the twelfth resistor, and the other end of the twelfth resistor is grounded. The bases of the eighteenth transistors in each rectifier bias circuit are connected together and connected to the fourth bias voltage. The collector of each eighteenth transistor is connected to the drain of the corresponding second MOSFET in the third temperature compensation module, and the collector of the eighteenth transistor is connected as the output terminal to the bias input terminal of the corresponding rectifier.

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