Pseudo-random number generation method and device, equipment and medium

Abstract

The invention relates to a pseudo-random number generation method and device, equipment and a medium, and the method comprises the steps: obtaining an original random seed, and carrying out the extension of the original random seed through employing a Galois linear feedback shift register, and obtaining an extension sequence; utilizing a system timer to select a splicing mode at a low position to obtain a first bit key value; obtaining a second bit key value by adopting a low-order selection complementing mode of a last round of random number generation result; splicing the first bit key value and the second bit key value, and performing Hash operation on a splicing result to obtain a Hash sequence; taking the hash sequence as a temporary random number, constructing a discarding period according to a previous round of random number generation result, and selectively discarding the temporary random number according to the discarding period; filling the residual temporary random numbers into the random number pool in sequence; and selecting the random number from the random number pool according to the random number calling request. According to the invention, the generation bandwidth and security of the random number can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of pseudo-random number generation, and in particular to a pseudo-random number generation method, device, equipment and medium. Background Art

[0002] Random number generation has multiple evaluation criteria, making it difficult to assign fixed scores and rankings to random number generators using limited testing and theoretical proof. Currently, both random number quality and random number bandwidth can be used to evaluate random number generators. In the digital realm, high-quality random numbers rely on entropy sources and entropy extraction algorithms. The former is the basis for disorder, while the latter is the means of sampling disorder and digitizing it according to specific rules. High-bandwidth random number generation mechanisms can effectively reduce system latency and bring significant performance benefits.

[0003] Currently, common random number generation methods include using random number generation functions from common libraries, true random generators, and pseudo-random generators. Using random number generation functions to generate random numbers is limited by the granularity of general-purpose processor instruction set architectures. The function is broken down into a large number of logical operations and basic calculations, occupying a large amount of instruction space and resulting in extremely low efficiency. True random generators primarily rely on amplifying extremely small signals, often with low bandwidth and susceptibility to interference, requiring significant overhead for interference shielding. Pseudo-random number generators simulate random functions according to a specific algorithm and typically rely on a random number seed. Pseudo-random numbers exhibit regularity and periodicity, but due to their long period, they can approximate true, absolutely random sequences in specific scenarios. Because the algorithm is relatively fixed, knowing the random seed is often sufficient to predict the random outcome. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a pseudo-random number generation method, device, equipment and medium, which can improve the generation bandwidth and security of random numbers.

[0005] The technical solution adopted by the present invention to solve the technical problem is: to provide a pseudo-random number generation method, comprising the following steps:

[0006] Obtaining an original random seed, and extending the original random seed using a Galois linear feedback shift register to obtain an extended sequence;

[0007] Using the system timer low bit selection splicing mode, the system timer and the extended sequence are spliced to obtain the first bit key value;

[0008] Use the low-order bit selection and filling method of the previous round of random number generation result to obtain the second bit key value;

[0009] Concatenate the first bit key value and the second bit key value, and perform a hash operation on the concatenation result to obtain a hash sequence;

[0010] Using the hash sequence as a temporary random number, establishing a discarding cycle based on the random number generation result of the previous round, and selectively discarding the temporary random number according to the discarding cycle;

[0011] Fill the remaining temporary random numbers into the random number pool in sequence;

[0012] A random number is selected from the random number pool according to a random number call request.

[0013] The original random seed is obtained by:

[0014] The original random seed is obtained by using the timestamp unidirectional growth method;

[0015] Use the chip private key as the original random seed;

[0016] Use the reset default value as the original random seed.

[0017] The method of using a Galois linear feedback shift register to expand the original random seed to obtain an extended sequence is specifically as follows: using a Galois linear feedback shift register to perform an exclusive OR operation and a shift operation on the original random seed to obtain an extended sequence, and then cyclically inputting the extended sequence of the previous clock cycle into the Galois linear feedback shift register in each subsequent clock cycle to generate a new extended sequence.

[0018] The system timer low bit is used to select the splicing mode, and the system timer and the extended sequence are spliced to obtain the first bit key value, which is specifically:

[0019] When the low bit of the system timer is 000, the splicing method is: {timer[22:0],A′b0,lfsr,B′b0,timer[31:23]};

[0020] When the low bit of the system timer is 001, the splicing mode is: {timer[14:0],A′b0,lfsr,B′b0,timer[31:15]};

[0021] When the low bit of the system timer is 010, the splicing method is: {timer[6:0],A′b0,lfsr,B′b0,timer[31:7]};

[0022] When the low bit of the system timer is 011, the splicing method is: {A′b0, lfsr, B′b0, timer[31:0]};

[0023] When the low bit of the system timer is 100, the splicing method is: {C′b0, lfsr, B′b0, timer[31:0], D′b0};

[0024] When the low bit of the system timer is 101, the splicing method is: {E′b0, lfsr, B′b0, timer[31:0], F′b0};

[0025] When the low bit of the system timer is 110, the splicing method is: {G′b0, lfsr, B′b0, timer[31:0], H′b0};

[0026] When the low bit of the system timer is 111, the splicing method is: {I′b0, lfsr, B′b0, timer[31:0], J′b0};

[0027] Where timer[a:b] represents the b-th to a-th bits of the system timer, lfsr is the extended sequence, X′b0 represents an X-bit all-0 constant, A, B, C, D, E, F, G, H, I, and J are all positive integers, and C+D=A, E+F=A, G+H=A, and I+J=A.

[0028] The second bit key value is obtained by selecting and filling the low bit of the random number generation result of the previous round, specifically:

[0029] When the low bit of the random number generated in the previous round is 000, the padding method is: {1′b1,191′b0,64′d256};

[0030] When the low bit of the random number generation result of the previous round is 001, the filling method is: {1′b0,1′b1,190′b0,64′d257};

[0031] When the low bit of the random number generated in the previous round is 010, the filling method is: {2′b0,1′b1,189′b0,64′d258};

[0032] When the low bit of the random number generated in the previous round is 011, the filling method is: {3′b0,1′b1,188′b0,64′d259};

[0033] When the low bit of the random number generated in the previous round is 100, the filling method is: {4′b0,1′b1,187′b0,64′d260};

[0034] When the low bit of the random number generated in the previous round is 101, the filling method is: {5′b0,1′b1,186′b0,64′d261};

[0035] When the low bit of the random number generated in the previous round is 110, the filling method is: {6′b0,1′b1,185′b0,64′d262};

[0036] When the low bit of the random number generated in the previous round is 110, the filling method is: {7′b0,1′b1,184′b0,64′d263};

[0037] Where X′b0 represents an X-bit all-0 constant, X′b1 represents an X-bit all-1 constant, and 64′dY represents a 64-bit decimal constant with a value of Y.

[0038] The discarding cycle is constructed according to the random number generation result of the previous round, and the temporary random number is selectively discarded according to the discarding cycle, specifically:

[0039] The first temporary random number is discarded, and the discarding period is determined according to the low bit of the first temporary random number;

[0040] The temporary random number corresponding to the discarding period is discarded, and the next discarding period is determined according to the low bit of the discarded temporary random number, and the cycle is repeated.

[0041] The selecting a random number from the random number pool according to the random number call request specifically includes:

[0042] Obtain a random number call request, wherein the random number call request carries length information;

[0043] Taking the low bit of the system timer as a modulus, performing modulo calculation on the length information to obtain a modulo calculation result;

[0044] The modulo result is used as the redundant length and added to the length information to obtain the random number length;

[0045] A random number of a random number length is taken from the random number pool and intercepted according to the length information to respond to the call request.

[0046] The technical solution adopted by the present invention to solve the technical problem is to provide a pseudo-random number generating device, comprising:

[0047] An acquisition expansion module is used to obtain an original random seed and expand the original random seed using a Galois linear feedback shift register to obtain an extended sequence;

[0048] A first bit key value generating module is used to select a splicing mode by using the low bit of the system timer, splicing the system timer and the extended sequence to obtain a first bit key value;

[0049] The second bit key value generation module uses the low-order bit selection and filling method of the previous round of random number generation result to obtain the second bit key value;

[0050] a concatenation calculation module, configured to concatenate the first bit key value and the second bit key value, and perform a hash operation on the concatenation result to obtain a hash sequence;

[0051] a discarding module, configured to use the hash sequence as a temporary random number, establish a discarding cycle according to the random number generation result of the previous round, and selectively discard the temporary random number according to the discarding cycle;

[0052] The filling module is used to fill the remaining temporary random numbers into the random number pool in sequence;

[0053] The calling module is used to select a random number from the random number pool according to a random number calling request.

[0054] The technical solution adopted by the present invention to solve its technical problem is: to provide an electronic device, including a memory, a processor and a computer program stored in the memory and capable of running on the processor, and the processor implements the steps of the above-mentioned pseudo-random number generation method when executing the computer program.

[0055] The technical solution adopted by the present invention to solve its technical problem is: providing a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned pseudo-random number generation method are implemented.

[0056] Beneficial effects

[0057] Due to the adoption of the above-mentioned technical solution, the present invention has the following advantages and positive effects compared with the prior art: the present invention simulates the entropy source by means of cyclic shift, real-time sampling, mixed length, random discarding, etc., and extracts entropy by means of digital summary, etc. The pseudo-random number generation method of the present invention has a high random number generation bandwidth and high random number security, which meets the complex usage scenarios of SOC chips, avoids dynamic power consumption waste when the accumulated number of random numbers is sufficient, breaks the periodic defects commonly present in pseudo-random sequences despite having regularity, and avoids performance and storage overhead caused by software operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 4 is a flowchart of a pseudo-random number generation method according to a first embodiment of the present invention. DETAILED DESCRIPTION

[0059] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0060] The first embodiment of the present invention relates to a pseudo-random number generation method, such as Figure 1 As shown, the following steps are included:

[0061] Step 1: Obtain an original random seed, and use a Galois linear feedback shift register to expand the original random seed to obtain an expanded sequence.

[0062] In this step, methods for obtaining the original random seed include: obtaining the original random seed using a timestamp unidirectional increment method; using the chip private key as the original random seed; and using a reset default value as the original random seed. Using a timestamp unidirectional increment method can provide an initial random seed with low repeatability. Using the chip private key as the original random seed ensures the uniqueness of the random seed. Using a reset default value as the original random seed can supplement the above two methods of obtaining the original random seed.

[0063] In this step, a Galois linear feedback shift register (LFSR) is used to expand the original random seed to obtain an extended sequence. Specifically, the Galois LFSR is used to perform an XOR operation and a shift operation on the original random seed to obtain an extended sequence, and the extended sequence of the previous clock cycle is cyclically input into the Galois LFSR in each subsequent clock cycle to generate a new extended sequence.

[0064] In this implementation, the current chip's private key is used as the original random seed. This is clipped to obtain 20 bits of xxxx. These 20 bits of xxxx are input into the Galois LFSR to obtain the extended sequence yyyy. In the next clock cycle, the extended sequence yyyy is input into the Galois LFSR again to obtain the new extended sequence y'y'y'y'. The Galois LFSR can be used to extend the original random seed, providing a longer initial cyclic sequence.

[0065] Step 2: Use the low bit of the system timer to select the splicing method, splice the system timer and the extended sequence to obtain the first bit key value. The specific splicing method in this step is as follows:

[0066] When the low bit of the system timer is 000, the splicing method is: {timer[22:0],A′b0,lfsr,B′b0,timer[31:23]};

[0067] When the low bit of the system timer is 001, the splicing mode is: {timer[14:0],A′b0,lfsr,B′b0,timer[31:15]};

[0068] When the low bit of the system timer is 010, the splicing method is: {timer[6:0],A′b0,lfsr,B′b0,timer[31:7]};

[0069] When the low bit of the system timer is 011, the splicing method is: {A′b0, lfsr, B′b0, timer[31:0]};

[0070] When the low bit of the system timer is 100, the splicing method is: {C′b0, lfsr, B′b0, timer[31:0], D′b0};

[0071] When the low bit of the system timer is 101, the splicing method is: {E′b0, lfsr, B′b0, timer[31:0], F′b0};

[0072] When the low bit of the system timer is 110, the splicing method is: {G′b0, lfsr, B′b0, timer[31:0], H′b0};

[0073] When the low bit of the system timer is 111, the splicing method is: {I′b0, lfsr, B′b0, timer[31:0], J′b0};

[0074] Where timer[a:b] represents the b-th to a-th bits of the system timer, lfsr is the extended sequence, X′b0 represents an X-bit all-0 constant, A, B, C, D, E, F, G, H, I, and J are all positive integers, and C+D=A, E+F=A, G+H=A, and I+J=A.

[0075] In this embodiment, the selection of A, B, C, D, E, F, G, H, I, and J is shown in Table 1 below.

[0076] Table 1

[0077] System timer low bit Splicing method 000 {timer[22:0],96′b0,lfsr,108′b0,timer[31:23]} 001 {timer[14:0],96′b0,lfsr,108′b0,timer[31:15]} 010 {timer[6:0],96′b0,lfsr,108′b0,timer[31:7]} 011 {96′b0,lfsr,108′b0,timer[31:0]} 100 {88′b0,lfsr,108′b0,timer[31:0],8′b0} 101 {80′b0,lfsr,108′b0,timer[31:0],16′b0} 110 {72′b0,lfsr,108′b0,timer[31:0],24′b0} 111 {64′b0,lfsr,108′b0,timer[31:0],32′b0}

[0078] When generating the first bit key value, inserting the real-time value of the system timer can reduce the repeatability again, and the fuzzy time value can be inserted into the position by selecting the combination method according to the low bit of the system timer.

[0079] Step 3: Use the low-order bit selection method of the previous round of random number generation result to obtain the second bit key value. The specific filling method in this step is as follows:

[0080] When the low bit of the random number generated in the previous round is 000, the padding method is: {1′b1,191′b0,64′d256};

[0081] When the low bit of the random number generation result of the previous round is 001, the filling method is: {1′b0,1′b1,190′b0,64′d257};

[0082] When the low bit of the random number generated in the previous round is 010, the filling method is: {2′b0,1′b1,189′b0,64′d258};

[0083] When the low bit of the random number generated in the previous round is 011, the filling method is: {3′b0,1′b1,188′b0,64′d259};

[0084] When the low bit of the random number generated in the previous round is 100, the filling method is: {4′b0,1′b1,187′b0,64′d260};

[0085] When the low bit of the random number generated in the previous round is 101, the filling method is: {5′b0,1′b1,186′b0,64′d261};

[0086] When the low bit of the random number generated in the previous round is 110, the filling method is: {6′b0,1′b1,185′b0,64′d262};

[0087] When the low bit of the random number generated in the previous round is 110, the filling method is: {7′b0,1′b1,184′b0,64′d263};

[0088] Where X′b0 represents an X-bit all-0 constant, X′b1 represents an X-bit all-1 constant, and 64′dY represents a 64-bit decimal constant with a value of Y.

[0089] When generating the second bit key value, padding is performed to meet the needs of subsequent algorithms. The random number result of the previous round is used as the effective key value length, which provides randomness for the padding method.

[0090] Step 4: Concatenate the first bit key value and the second bit key value, and perform a hash operation on the concatenated result to obtain a hash sequence. When performing the hash operation in this step, the SM3 encryption algorithm can be used, and multiple hash sequences can be obtained after multiple rounds of calculation.

[0091] Step 5: Use the hash sequence as a temporary random number. At this time, multiple temporary random numbers can be obtained. Then, a discard cycle is constructed according to the random number generation result of the previous round, and the temporary random numbers are selectively discarded according to the discard cycle.

[0092] In this step, when discarding, the first temporary random number is discarded, and the discarding period is determined based on the low bit of the first temporary random number; the temporary random number corresponding to the discarding period is discarded, and the next discarding period is determined based on the low bit of the discarded temporary random number, and the cycle is repeated. For example: the lowest 4 bits of the first temporary random number A0 are 4'd10, and the discarding period is constructed starting from the next temporary random number A1. The length of this discarding period is 10. In this process, the temporary random numbers A1 to A9 are all retained, and the temporary random number A10 will be discarded. At the same time, the low bit of the temporary random number A10 is used to construct the next discarding period. Assume that the low bit of the temporary random number A10 is 4'd0. At this time, only the temporary random number A10 needs to be discarded and is not used to construct the discarding period. The next temporary random number A11 is not discarded by default, but the low bit of A11 needs to be used to construct the next discarding period.

[0093] Step 6: Fill the remaining temporary random numbers into the random number pool in sequence. In this step, the temporary random numbers retained in the previous step are filled into the random number pool in sequence. If the random number pool is not full, repeat the above steps until the random number pool is full.

[0094] Step 7: Select a random number from the random number pool according to the random number call request. This step specifically includes:

[0095] First, a random number call request is obtained, wherein the random number call request carries length information;

[0096] Next, the length information is modulo-calculated using the low bit of the system timer as a modulus to obtain a modulo-calculated result.

[0097] Then, the modulo result is used as the redundant length and added to the length information to obtain the random number length;

[0098] Finally, a random number of a random number length is taken from the random number pool and intercepted according to the length information to respond to the call request.

[0099] For example, the CPU generates a random number call request and changes the length information carried in the random number call request to 16 bits. After obtaining the random number call request, assuming that the low bit of the system timer is 011, the modulus is 3 at this time, and the modulus result of 16 is 1. The modulus result and the length information are added to obtain a random number length of 17. Finally, a 17-bit random number is taken from the random number pool, and the lower 16 bits are intercepted according to the original request to respond to the call request, and returned to the CPU, and the random number is removed from the random number pool at the same time.

[0100] This implementation pre-fills the random number sequence pool before an external random number request is made, decoupling the random number generator's system timer from the length of the external random number request. This conceals random number generation latency and leverages its high bandwidth to prevent traffic-like attacks, shielding the system from the potential impact of external random number requests on the random number generator. Because computer architectures typically use bytes, halfwords, and words as characteristic data lengths, this implementation redundantly extends the length of external random number requests to avoid potential impacts caused by strong regularity. This means that excess random numbers exceeding the actual request length are read each time.

[0101] It is not difficult to find that the present invention simulates the entropy source by means of cyclic shift, real-time sampling, mixed length, random discard, etc., and uses digital summary and other methods to extract entropy. The pseudo-random number generation method of the present invention has a high random number generation bandwidth and high random number security, which meets the complex usage scenarios of SOC chips. When the accumulated number of random numbers is sufficient, it avoids dynamic power consumption waste. Although it has a regularity, it breaks the periodic defects that usually exist in pseudo-random sequences, and avoids the performance and storage overhead caused by software operations.

[0102] A second embodiment of the present invention relates to a pseudo-random number generating device, comprising:

[0103] An acquisition expansion module is used to obtain an original random seed and expand the original random seed using a Galois linear feedback shift register to obtain an extended sequence;

[0104] A first bit key value generating module is used to select a splicing mode by using the low bit of the system timer, splicing the system timer and the extended sequence to obtain a first bit key value;

[0105] The second bit key value generation module uses the low-order bit selection and filling method of the previous round of random number generation result to obtain the second bit key value;

[0106] a concatenation calculation module, configured to concatenate the first bit key value and the second bit key value, and perform a hash operation on the concatenation result to obtain a hash sequence;

[0107] a discarding module, configured to use the hash sequence as a temporary random number, establish a discarding cycle according to the random number generation result of the previous round, and selectively discard the temporary random number according to the discarding cycle;

[0108] The filling module is used to fill the remaining temporary random numbers into the random number pool in sequence;

[0109] The calling module is used to select a random number from the random number pool according to a random number calling request.

[0110] The acquisition extension module includes:

[0111] The first acquisition unit is used to acquire the original random seed by using a timestamp unidirectional growth method;

[0112] A second acquisition unit is used to use the chip private key as the original random seed;

[0113] The third obtaining unit is configured to use a reset default value as an original random seed.

[0114] The acquisition expansion module uses a Galois linear feedback shift register to expand the original random seed. When obtaining an extended sequence, the Galois linear feedback shift register is used to perform an exclusive OR operation and a shift operation on the original random seed to obtain an extended sequence, and the extended sequence of the previous clock cycle is cyclically input into the Galois linear feedback shift register in each subsequent clock cycle to generate a new extended sequence.

[0115] The first bit key value generation module uses the system timer low bit selection splicing mode to splice the system timer and the extended sequence to obtain the first bit key value.

[0116] When the low bit of the system timer is 000, the splicing method is: {timer[22:0],A′b0,lfsr,B′b0,timer[31:23]};

[0117] When the low bit of the system timer is 001, the splicing mode is: {timer[14:0],A′b0,lfsr,B′b0,timer[31:15]};

[0118] When the low bit of the system timer is 010, the splicing method is: {timer[6:0],A′b0,lfsr,B′b0,timer[31:7]};

[0119] When the low bit of the system timer is 011, the splicing method is: {A′b0, lfsr, B′b0, timer[31:0]};

[0120] When the low bit of the system timer is 100, the splicing method is: {C′b0, lfsr, B′b0, timer[31:0], D′b0};

[0121] When the low bit of the system timer is 101, the splicing method is: {E′b0, lfsr, B′b0, timer[31:0], F′b0};

[0122] When the low bit of the system timer is 110, the splicing method is: {G′b0, lfsr, B′b0, timer[31:0], H′b0};

[0123] When the low bit of the system timer is 111, the splicing method is: {I′b0, lfsr, B′b0, timer[31:0], J′b0};

[0124] Where timer[a:b] represents the b-th to a-th bits of the system timer, lfsr is the extended sequence, X′b0 represents an X-bit all-0 constant, A, B, C, D, E, F, G, H, I, and J are all positive integers, and C+D=A, E+F=A, G+H=A, and I+J=A.

[0125] The second bit key value generation module adopts the low bit selection and filling method of the previous round of random number generation result to obtain the second bit key value.

[0126] When the low bit of the random number generated in the previous round is 000, the padding method is: {1′b1,191′b0,64′d256};

[0127] When the low bit of the random number generation result of the previous round is 001, the filling method is: {1′b0,1′b1,190′b0,64′d257};

[0128] When the low bit of the random number generated in the previous round is 010, the filling method is: {2′b0,1′b1,189′b0,64′d258};

[0129] When the low bit of the random number generated in the previous round is 011, the filling method is: {3′b0,1′b1,188′b0,64′d259};

[0130] When the low bit of the random number generated in the previous round is 100, the filling method is: {4′b0,1′b1,187′b0,64′d260};

[0131] When the low bit of the random number generated in the previous round is 101, the filling method is: {5′b0,1′b1,186′b0,64′d261};

[0132] When the low bit of the random number generated in the previous round is 110, the filling method is: {6′b0,1′b1,185′b0,64′d262};

[0133] When the low bit of the random number generated in the previous round is 110, the filling method is: {7′b0,1′b1,184′b0,64′d263};

[0134] Where X′b0 represents an X-bit all-0 constant, X′b1 represents an X-bit all-1 constant, and 64′dY represents a 64-bit decimal constant with a value of Y.

[0135] The discarding module constructs a discarding cycle according to the result of the previous round of random number generation, and when selectively discarding the temporary random number according to the discarding cycle, discards the first temporary random number and determines the discarding cycle according to the low bit of the first temporary random number; discards the temporary random number corresponding to the discarding cycle, and determines the next discarding cycle according to the low bit of the discarded temporary random number, and repeats the process.

[0136] The calling module includes:

[0137] A request obtaining unit, configured to obtain a random number call request, wherein the random number call request carries length information;

[0138] A modulo unit, configured to perform modulo calculation on the length information using the low bit of the system timer as a modulus to obtain a modulo calculation result;

[0139] a summing unit, configured to add the modulo result as a redundant length to the length information to obtain a random number length;

[0140] The response unit is used to take out a random number of a random number length from the random number pool and intercept it according to the length information to respond to the call request.

[0141] A third embodiment of the present invention relates to an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the pseudo-random number generation method of the first embodiment when executing the computer program.

[0142] A fourth embodiment of the present invention relates to a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program implements the steps of the pseudo-random number generation method of the first embodiment.

[0143] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) that contain computer-usable program code.

[0144] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0145] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction method, which is implemented in the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0146] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0147] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A pseudo-random number generation method, characterized in that: The following steps are involved: Obtaining an original random seed and expanding the original random seed using a Galois linear feedback shift register, Get the extended sequence; Using the system timer low bit selection splicing mode, the system timer and the extended sequence are spliced to obtain the first bit key value; Use the low-order bit selection and filling method of the previous round of random number generation result to obtain the second bit key value; Concatenate the first bit key value and the second bit key value, and perform a hash operation on the concatenation result to obtain a hash sequence; Using the hash sequence as a temporary random number, establishing a discarding cycle based on the random number generation result of the previous round, and selectively discarding the temporary random number according to the discarding cycle; Fill the remaining temporary random numbers into the random number pool in sequence; A random number is selected from the random number pool according to a random number call request.

2. The pseudo-random number generation method according to claim 1, wherein The original random seed is obtained by: The original random seed is obtained by using the timestamp unidirectional growth method; Use the chip private key as the original random seed; Use the reset default value as the original random seed.

3. The pseudo-random number generation method according to claim 1, wherein: The method of using a Galois linear feedback shift register to expand the original random seed to obtain an extended sequence is specifically as follows: using a Galois linear feedback shift register to perform an exclusive OR operation and a shift operation on the original random seed to obtain an extended sequence, and then cyclically inputting the extended sequence of the previous clock cycle into the Galois linear feedback shift register in each subsequent clock cycle to generate a new extended sequence.

4. The pseudo-random number generation method according to claim 1, wherein: The system timer low bit is used to select the splicing mode, and the system timer and the extended sequence are spliced to obtain the first bit key value, which is specifically: When the low bit of the system timer is 000, the splicing method is: {timer[22:0],A′b0,lfsr,B′b0,timer[31:23]}; When the low bit of the system timer is 001, the splicing method is: {timer[14:0],A′b0,lfsr,B′b0,timer[31:15]}; When the low bit of the system timer is 010, the splicing method is: {timer[6:0],A′b0,lfsr,B′b0,timer[31:7]}; When the low bit of the system timer is 011, the splicing method is: {A′b0, lfsr, B′b0, timer[31:0]}; When the low bit of the system timer is 100, the splicing method is: {C′b0, lfsr, B′b0, timer[31:0], D′b0}; When the low bit of the system timer is 101, the splicing method is: {E′b0, lfsr, B′b0, timer[31:0], F′b0}; When the low bit of the system timer is 110, the splicing method is: {G′b0, lfsr, B′b0, timer[31:0], H′b0}; When the low bit of the system timer is 111, the splicing method is: {I′b0, lfsr, B′b0, timer[31:0], J′b0}; Where timer[a:b] represents the b-th to a-th bits of the system timer, lfsr is the extended sequence, X′b0 represents an X-bit all-0 constant, A, B, C, D, E, F, G, H, I, and J are all positive integers, and C+D=A, E+F=A, G+H=A, and I+J=A.

5. The pseudo-random number generating method according to claim 1, wherein: The second bit key value is obtained by selecting and filling the low bit of the random number generation result of the previous round, specifically: When the low bit of the random number generated in the previous round is 000, the padding method is: {1′b1,191′b0,64′d256}; When the low bit of the random number generation result of the previous round is 001, the filling method is: {1′b0,1′b1,190′b0,64′d257}; When the low bit of the random number generated in the previous round is 010, the filling method is: {2′b0,1′b1,189′b0,64′d258}; When the low bit of the random number generated in the previous round is 011, the filling method is: {3′b0,1′b1,188′b0,64′d259}; When the low bit of the random number generated in the previous round is 100, the filling method is: {4′b0,1′b1,187′b0,64′d260}; When the low bit of the random number generated in the previous round is 101, the filling method is: {5′b0,1′b1,186′b0,64′d261}; When the low bit of the random number generated in the previous round is 110, the filling method is: {6′b0,1′b1,185′b0,64′d262}; When the low-order bit of the random number generation result in the previous round is 110, the padding method is: {7′b0, 1′b1, 184′b0, 64′d263}; where X′b0 represents an X-bit all-0 constant, X′b1 represents an X-bit all-1 constant, and 64′dY represents a 64-bit decimal constant with a value of Y.

6. The pseudo-random number generating method according to claim 1, wherein: The discarding period is constructed according to the result of the previous round of random number generation, and the temporary random number is selectively discarded according to the discarding period, specifically: the first temporary random number is discarded, and the discarding period is determined according to the low bit of the first temporary random number; The temporary random number corresponding to the discarding period is discarded, and the next discarding period is determined according to the low bit of the discarded temporary random number, and the cycle is repeated.

7. The pseudo-random number generating method according to claim 1, wherein: The selecting a random number from the random number pool according to the random number call request specifically includes: Obtain a random number call request, wherein the random number call request carries length information; Taking the low bit of the system timer as a modulus, performing modulo calculation on the length information to obtain a modulo calculation result; The modulo result is used as the redundant length and added to the length information to obtain the random number length; A random number of a random number length is taken from the random number pool and intercepted according to the length information to respond to the call request.

8. A pseudo-random number generating device, characterized in that: include: An acquisition expansion module is used to obtain an original random seed and expand the original random seed using a Galois linear feedback shift register to obtain an extended sequence; A first bit key value generating module is used to select a splicing mode by using the low bit of the system timer, splicing the system timer and the extended sequence to obtain a first bit key value; The second bit key value generation module uses the low-order bit selection and filling method of the previous round of random number generation result to obtain the second bit key value; a concatenation calculation module, configured to concatenate the first bit key value and the second bit key value, and perform a hash operation on the concatenation result to obtain a hash sequence; a discarding module, configured to use the hash sequence as a temporary random number, establish a discarding cycle according to the random number generation result of the previous round, and selectively discard the temporary random number according to the discarding cycle; The filling module is used to fill the remaining temporary random numbers into the random number pool in sequence; The calling module is used to select a random number from the random number pool according to a random number calling request.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the pseudo-random number generation method according to any one of claims 1 to 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the pseudo-random number generation method according to any one of claims 1 to 8 are implemented.

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