Modeling method for estimating service life of memory device, method for calculating remaining service life of memory device, and calculation system

Abstract

A modeling method for estimating a useful life of a memory device, a method of calculating a remaining useful life of a memory device, and a computing system are disclosed. In one example modeling method for estimating a useful life of a memory device, a plurality of performance measurement data associated with a plurality of performances of a plurality of unused memory devices is obtained based on performing an accelerated aging test on the plurality of unused memory devices. A plurality of statistical data is calculated based on performing a statistical distribution approximation on the plurality of performance measurement data. A plurality of conditional probabilities are calculated based on a plurality of sample performance data associated with the plurality of performances and the plurality of statistical data. And training a life calculation model based on the plurality of conditional probabilities. The life calculation model outputs estimated service life data and uncertainty data. The estimated service life data corresponds to the plurality of sample performance data. The uncertainty data represents an uncertainty of the estimated useful life data.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2024-0019315 filed on February 8, 2024, in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a modeling method for estimating the useful life of a memory device, a method for calculating the remaining useful life of a memory device, and a computing system. Background Art

[0003] Semiconductor memory devices can be divided into two categories based on whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and non-volatile memory devices, which retain stored data when disconnected from power. Although volatile memory devices can perform read and write operations at high speeds, the data stored therein may be lost when power is removed. Since non-volatile memory devices retain their stored data even when power is removed, they are useful for storing data that needs to be retained.

[0004] As semiconductor memory devices operate, components (such as transistors) included in the semiconductor memory devices may wear out, and the remaining useful life of the semiconductor memory devices may decrease. Recently, there has been a high demand for recertification services to reuse already used semiconductor memory devices, and the remaining useful life of already used semiconductor memory devices should be identified for recertification services. The remaining useful life may depend on the usage history of the semiconductor memory device, but it is difficult to accurately identify the usage history. Summary of the Invention

[0005] The present disclosure relates to a modeling method capable of generating an estimation model for effectively estimating the service life of a memory device without requiring a usage history of the memory device and without requiring an application-specific integrated circuit (IC).

[0006] The present disclosure relates to a method for calculating the remaining useful life of a memory device using an estimation model generated by a modeling method.

[0007] The present disclosure relates to a system for performing a modeling method and / or a method for calculating remaining useful life.

[0008] In some embodiments, in a modeling method for estimating the useful life of a memory device, the modeling method is performed by executing program code by at least one processor, and the program code is stored in a non-transitory computer-readable medium. While performing an accelerated aging test on a plurality of unused memory devices, a plurality of performance measurement data associated with a plurality of properties of the plurality of unused memory devices is obtained. A plurality of statistical data is calculated by performing statistical distribution approximation on the plurality of performance measurement data. A plurality of conditional probabilities are calculated based on a plurality of sample performance data associated with the plurality of properties and the plurality of statistical data. A life calculation model is trained based on the plurality of conditional probabilities. The life calculation model outputs estimated useful life data and uncertainty data. The estimated useful life data corresponds to the plurality of sample performance data. The uncertainty data represents the uncertainty of the estimated useful life data.

[0009] In some embodiments, in a method for calculating the remaining useful life of a memory device, the method is performed by executing program code on at least one processor, and the program code is stored in a non-transitory computer-readable medium. A lifetime calculation model is generated using a plurality of unused memory devices. Multiple performance data associated with multiple properties of at least one target memory device that has been used is measured. The remaining useful life of the at least one target memory device is obtained based on the lifetime calculation model and the multiple performance data associated with the multiple properties. When generating the lifetime calculation model, multiple performance measurement data associated with the multiple properties of the unused memory devices is obtained while performing an accelerated aging test on the multiple unused memory devices. Multiple statistics are calculated by performing statistical distribution approximation on the multiple performance measurement data. Multiple first conditional probabilities are calculated based on multiple sample performance data associated with the multiple properties and the multiple statistics. The lifetime calculation model is trained based on the multiple first conditional probabilities. The lifetime calculation model outputs first estimated useful life data and first uncertainty data. The first estimated useful life data corresponds to the multiple sample performance data. The first uncertainty data represents the uncertainty of the first estimated useful life data.

[0010] In some embodiments, a system includes: a reliability testing device, a performance measurement device, at least one processor, and a non-transitory computer-readable medium. The reliability testing device performs an accelerated aging test on a memory device. The performance measurement device measures multiple properties of the memory device. The non-transitory computer-readable medium stores program code, which is executed by the at least one processor to generate a lifespan calculation model for obtaining the remaining useful life of the memory device. While performing the accelerated aging test on multiple unused memory devices, the at least one processor uses the reliability testing device and the performance measurement device to obtain multiple performance measurement data associated with multiple properties of the multiple unused memory devices, calculates multiple statistics by performing statistical distribution approximation on the multiple performance measurement data, calculates multiple conditional probabilities based on multiple sample performance data associated with the multiple properties and the multiple statistics, and trains the lifespan calculation model based on the multiple conditional probabilities. The memory device and the multiple unused memory devices are of the same type. The lifespan calculation model outputs estimated useful life data and uncertainty data. The estimated useful life data corresponds to the multiple sample performance data. The uncertainty data indicates the uncertainty of the estimated useful life data.

[0011] In some embodiments, a modeling method for estimating the useful life of a memory device, a method for calculating the remaining useful life of a memory device, and a system thereof utilize actual performance parameters measured through actual operating paths within the memory device, thereby enabling estimation of the useful life of the memory device and / or calculation of the remaining useful life of the memory device without requiring additional on-chip IP or dedicated integrated circuits within the memory device. For example, a performance distribution can be modified to fit a statistical distribution, and a probability-based useful life calculation can be performed based on the statistical distribution. For example, a conservative useful life calculation can be performed based on a custom worst-case scenario. For example, an accurate useful life calculation can be performed based on various performance parameters. Thus, operations for estimating the useful life of a memory device and / or calculating the remaining useful life of a memory device can be performed efficiently, and the useful life and / or remaining useful life can be applied to recertification services to reuse already used memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a flow chart illustrating an example of a modeling method for estimating the useful life of a memory device.

[0014] Figure 2 and Figure 3 is a block diagram illustrating an example of a system.

[0015] Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D is a diagram for describing an example of a life calculation model.

[0016] Figure 6 It shows that Figure 1 A flowchart of an example of multiple performance measurement data in FIG.

[0017] Figure 7 、 Figure 8 and Figure 9 is used to describe Figure 6 An illustration of an example operation of .

[0018] Figure 10 It shows that Figure 1 A flowchart of an example of multiple performance measurement data in FIG.

[0019] Figure 11 It shows the calculation Figure 1 Flowchart of an example of multiple statistics in .

[0020] Figure 12 It shows the calculation Figure 1 Flowchart of an example of multiple conditional probabilities in .

[0021] Figure 13 is a flow chart illustrating an example of a modeling method for estimating the useful life of a memory device.

[0022] Figure 14 and Figure 15 is a flow chart illustrating an example of a modeling method for estimating the useful life of a memory device.

[0023] Figure 16A 、 Figure 16B and Figure 16C is a diagram for describing an example of a modeling method for estimating the useful life of a memory device.

[0024] Figure 17A and Figure 17B is a block diagram illustrating an example of a memory device.

[0025] Figure 18A 、 Figure 18B and Figure 18C is a diagram illustrating an implementation example of a memory device.

[0026] Figure 19 is a flowchart illustrating an example of a method of calculating a remaining useful life of a memory device.

[0027] Figure 20 and Figure 21 It shows that Figure 19 Flowchart of an example of the remaining useful life.

[0028] Figure 22 、 Figure 23 、 Figure 24 and Figure 25 is a flowchart illustrating an example of a method of calculating a remaining useful life of a memory device. DETAILED DESCRIPTION

[0029] Various example embodiments will be described more fully with reference to the accompanying drawings, in which the embodiments are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, like reference numerals represent like elements.

[0030] Figure 1 is a flow chart illustrating an example of a modeling method for estimating the useful life of a memory device.

[0031] Reference Figure 1 The modeling method may be executed to model or generate a life calculation model, which is applied to estimate the service life (or usage period) of a memory device and / or calculate the remaining useful life (RUL) of the memory device. For example, the modeling method may be executed on a computer-based system and / or tool, at least part of which is implemented in hardware and / or software. For example, the system and / or tool may include a program (or program code) including a plurality of instructions executed by at least one processor. Reference will be made to Figure 2 and Figure 3 Describe the system and / or tool.

[0032] In the modeling method, while performing an accelerated aging test on a plurality of unused memory devices, a plurality of performance measurement data associated with a plurality of performances of the plurality of unused memory devices is obtained (operation S100). The plurality of unused memory devices may be the same product as a memory device (e.g., a target memory device) whose service life is to be estimated and / or whose remaining service life is to be calculated. The plurality of unused memory devices may be new products that have not yet been used. For example, the plurality of unused memory devices and the target memory device may be memory devices of the same type having the same structure and manufactured by the same process. Figure 6 and Figure 10 Operation S100 is described.

[0033] Accelerated aging testing can be or may refer to an operation that measures how performance changes over time under accelerated conditions. For example, in accelerated aging testing, a product may be operated based on a known worst-case scenario. For example, a worst-case scenario may be defined by a combination of specific conditions, such as command type (e.g., idle operation, write operation, read operation), address, and timing. For example, accelerated conditions may include applying higher voltages, temperatures, and other conditions than those encountered during actual product use (e.g., compared to actual usage conditions).

[0034] In some embodiments, the memory device (e.g., each of the plurality of unused memory devices and the target memory device) may be a dynamic random access memory (DRAM) device. In some embodiments, the memory device (e.g., each of the plurality of unused memory devices and the target memory device) may be a flash memory device. However, example embodiments are not limited thereto, and the memory device may be one of various volatile memory devices and / or one of various non-volatile memory devices. Figure 17A 、 Figure 17B 、 Figure 18A 、 Figure 18B and Figure 18C Describe the configuration of the memory device.

[0035] A plurality of statistical data are calculated by performing statistical distribution approximation on a plurality of performance measurement data (operation S200). For example, it may be assumed that the plurality of performance measurement data are formed according to a normal distribution, and various statistical values may be calculated based on the normal distribution. Figure 11 Operation S200 is described.

[0036] A plurality of conditional probabilities are calculated based on a plurality of sample performance data and a plurality of statistical data associated with a plurality of performances (operation S300). For example, the plurality of sample performance data may have a configuration similar to that of the plurality of performance measurement data. For example, the plurality of conditional probabilities may represent probabilities under the condition that the plurality of sample performance data are input. Figure 12 Operation S300 is described.

[0037] The life calculation model may be trained or learned based on a plurality of conditional probabilities (operation S400). The life calculation model outputs estimated life data and uncertainty data, the estimated life data corresponding to a plurality of sample performance data, and the uncertainty data indicating the uncertainty of the estimated life data. For example, the life calculation model may be implemented in the form of a machine learning model, a neural network model, an artificial intelligence (AI) model, etc. Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5DDescribes the configuration of the lifetime calculation model.

[0038] In some embodiments, the lifespan calculation model may be implemented using Bayesian inference. However, example embodiments are not limited thereto.

[0039] In this modeling approach, actual performance parameters measured through actual operating paths within a memory device can be used to estimate the useful life of a memory device and / or calculate the remaining useful life of the memory device, without requiring additional on-chip intellectual property (IP) or an additional application-specific integrated circuit (IC) within the memory device. For example, a performance distribution can be modified to fit a statistical distribution, and a probability-based useful life calculation can be performed based on this statistical distribution. For example, a conservative useful life calculation can be performed based on a custom worst-case condition (e.g., an operation sequence). For example, an accurate useful life calculation can be performed based on various performance parameters. Thus, operations for estimating the useful life of a memory device and / or calculating the remaining useful life of a memory device can be performed efficiently, and the useful life and / or remaining useful life can be applied to requalification operations to reuse already used memory devices.

[0040] Figure 2 and Figure 3 is a block diagram illustrating an example of a system.

[0041] Reference Figure 2 The system 1000 includes a processor 1100 , a storage device 1200 , a modeling and estimation module 1300 , a reliability testing device 1400 , and a performance measurement device 1500 .

[0042] Herein, the term "module" may refer to, but is not limited to, software and / or hardware components (such as field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs)) that perform specific tasks. A "module" may be configured to reside in a tangible, addressable storage medium and to execute on one or more processors. For example, a "module" may include: components (such as software components, object-oriented software components, class components, and task components), as well as processes, functions, routines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. A "module" may be divided into multiple "modules" that perform detailed functions.

[0043] When the modeling and estimation module 1300 performs calculations or operations, the processor 1100 may be used. For example, the processor 1100 may include a microprocessor, an application processor (AP), a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), a neural processing unit (NPU), etc. Figure 2The system 1000 is shown to include one processor 1100, but example embodiments are not limited thereto. For example, the semiconductor design system 1000 may include multiple processors. In addition, the processor 1100 may include a cache memory to increase computing capacity.

[0044] The storage device 1200 can store data used for the operation of the processor 1100 and the modeling and estimation module 1300. In some embodiments, the storage device (or storage medium) 1200 may include any non-transitory computer-readable storage medium for providing commands and / or data to a computer. For example, the non-transitory computer-readable storage medium may include volatile memory (such as static random access memory (SRAM), dynamic random access memory (DRAM), etc.) and non-volatile memory (such as flash memory, magnetic random access memory (MRAM), phase change random access memory (PRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FRAM), etc.). The non-transitory computer-readable storage medium may be inserted into the computer, may be integrated into the computer, or may be coupled to the computer via a communication medium (such as a network and / or wireless link).

[0045] The reliability testing apparatus 1400 may perform accelerated aging tests (eg, high temperature operating life (HTOL) tests) on the memory device. The performance measurement apparatus 1500 may measure the operating performance of the memory device (eg, various performance parameters associated with or related to input / output (I / O) timing).

[0046] The modeling and estimation module 1300 may perform reference Figure 1 The modeling method for estimating the useful life of a memory device is described and may be performed with reference to Figure 19 A method for calculating the remaining useful life of a memory device is described.

[0047] The modeling and estimation module 1300 may include a data collection module 1310 , a training (or learning) module 1320 , and an inference and calculation module 1330 .

[0048] The data collection module 1310 may perform data collection operations for executing a modeling method for estimating the useful life of a memory device and / or a method for calculating the remaining useful life of a memory device. For example, the data collection module 1310 may collect performance measurement data and performance data via the performance measurement device 1500, may collect sample performance data, and may collect and / or generate various other data.

[0049] The training module 1320 may perform a training operation (or a retraining operation) for executing a modeling method for estimating the useful life of a memory device and / or a method for calculating the remaining useful life of a memory device. For example, the training module 1320 may perform various operations, processes, data generation and storage, etc., for generating and training a life calculation model (LCM).

[0050] The inference and calculation module 1330 can perform inference operations and calculation operations for executing the method for calculating the remaining useful life of a memory device. For example, the inference and calculation module 1330 can calculate the remaining useful life of an already used memory device based on a trained and generated life calculation model LCM and using performance data obtained by the performance measurement device 1500 and the data collection module 1310, without requiring additional IP or IC.

[0051] The data collection module 1310 can perform a reference Figure 1 The operation S100 described and executable will refer to Figure 19 The training module 1320 may perform operations S1100 and S1200 described above. Figure 1 The operations S200, S300 and S400 described above and executable by reference to Figure 19 Another part of the operation S1100 described. The inference and calculation module 1330 may perform the reference Figure 19 Operation S1300 is described.

[0052] In some embodiments, the lifespan calculation model LCM, the data collection module 1310, the training module 1320, and the inference and calculation module 1330 may be implemented as instructions or program code executable by the processor 1100. For example, the instructions or program code of the lifespan calculation model LCM, the data collection module 1310, the training module 1320, and the inference and calculation module 1330 may be stored in a computer-readable medium. For example, the processor 1100 may load the instructions or program code into a working memory (e.g., DRAM).

[0053] In other embodiments, the processor 1100 may be configured to efficiently execute instructions or program codes included in the lifespan calculation model LCM, the data collection module 1310, the training module 1320, and the inference and calculation module 1330. For example, the processor 1100 may efficiently execute instructions or program codes from various AI modules and / or machine learning modules. For example, the processor 1100 may receive information corresponding to the lifespan calculation model LCM, the data collection module 1310, the training module 1320, and the inference and calculation module 1330 to operate the lifespan calculation model LCM, the data collection module 1310, the training module 1320, and the inference and calculation module 1330.

[0054] In some embodiments, the data collection module 1310, the training module 1320, and the inference and calculation module 1330 can be implemented as a single integrated module. In other embodiments, the data collection module 1310, the training module 1320, and the inference and calculation module 1330 can be implemented as separate and distinct modules.

[0055] Reference Figure 3 , the system 2000 includes a processor 2100 , an input / output (I / O) device 2200 , a network interface 2300 , a random access memory (RAM) 2400 , a read-only memory (ROM) 2500 , and a storage device 2600 . Figure 3 Show Figure 2 In the example, all the data collection modules 1310, training modules 1320 and inference and calculation modules 1330 are implemented in software. Figure 2 Components corresponding to the reliability testing device 1400 and the performance measurement device 1500 implemented as separate devices or facilities.

[0056] The system 2000 may be a computing system. For example, the computing system may be a stationary computing system such as a desktop computer, a workstation, or a server, or a portable computing system such as a laptop computer.

[0057] Processor 2100 can be used with Figure 2 The processor 1100 in FIG. 2 is substantially the same as the processor 1100 in FIG. For example, the processor 2100 may include a core or processor core for executing any instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit extensions to IA-32, x86-64, PowerPC, Scalable Processor Architecture (Sparc), MIPS, ARM, IA-64, etc.). For example, the processor 2100 may access a memory (e.g., RAM 2400 or ROM 2500) through a bus and may execute instructions stored in the RAM 2400 or ROM 2500. Figure 3 As shown in FIG, RAM 2400 can store Figure 2 The data collection module 1310, the training module 1320, and the inference and calculation module 1330 in the program PR or at least some elements of the program PR, and the program PR may allow the processor 2100 to perform operations for generating a life calculation model LCM and / or calculating the remaining useful life (for example, Figure 1 Operations S100, S200, S300, S400 and S500 and / or Figure 19 Operations S1100, S1200 and S1300 in FIG.

[0058] In other words, the program PR may include multiple instructions and / or programs executable by the processor 2100, and the multiple instructions and / or programs included in the program PR may allow the processor 2100 to perform operations for generating the life calculation model LCM and / or calculating the remaining useful life. Each of the programs may represent a series of instructions for performing a specific task. A program may be referred to as a function, routine, subroutine, or subprogram. Each of the programs may process data provided from an external source and / or data generated by another program.

[0059] The storage device 2600 can be used with Figure 2 2. The storage device 2600 is substantially the same as the storage device 1200 in FIG. For example, the storage device 2600 may store the program PR. The program PR or at least some elements of the program PR may be loaded from the storage device 2600 to the RAM 2400 before being executed by the processor 2100. The storage device 2600 may store files written in a program language, and the program PR or at least some elements of the program PR generated by a compiler or the like may be loaded into the RAM 2400.

[0060] The storage device 2600 may store data to be processed by the processor 2100 or data obtained through processing by the processor 2100. The processor 2100 may process the data stored in the storage device 2600 based on the program PR to generate new data, and may store the generated data in the storage device 2600.

[0061] The I / O device 2200 may include an input device (such as a keyboard, a pointing device, etc.) and an output device (such as a display device, a printer, etc.). For example, a user may trigger the processor 2100 to execute the program PR through the I / O device 2200, and may provide or check various inputs, outputs, and / or data.

[0062] The network interface 2300 can provide access to a network external to the system 2000. For example, the network can include multiple computing systems and communication links, and the communication links can include wired links, optical links, wireless links, or any other type of links. Various inputs can be provided to the system 2000 through the network interface 2300, and various outputs can be provided to another computing system through the network interface 2300.

[0063] In some embodiments, the computer program code, lifespan calculation model (LCM), data collection module 1310, training module 1320, and inference and calculation module 1330 may be stored on a transitory or non-transitory computer-readable medium. In some embodiments, values obtained from arithmetic processing performed by a processor may be stored on a transitory or non-transitory computer-readable medium. In some embodiments, intermediate values generated during training operations may be stored on a transitory or non-transitory computer-readable medium. In some embodiments, various data (such as performance measurement data (or performance data), statistical data, estimated data (or predicted data), and / or uncertainty data) may be stored on a transitory or non-transitory computer-readable medium. However, example embodiments are not limited in this regard.

[0064] Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D is a diagram for describing an example of a life calculation model.

[0065] Reference Figure 4 The lifespan calculation model 100 may include a statistical distribution approximation block 110 , a conditional probability calculation block 120 , and a post computing block 130 .

[0066] The statistical distribution approximation block 110 may calculate a plurality of statistical data STDAT1 , STDAT2 , . . . , STDATK by performing statistical distribution approximation on the plurality of performance measurement data PMDAT1 , PMDAT2 , . . . , PMDATK.

[0067] For example, the statistical distribution approximation block 110 may calculate first statistical data STDAT1 including various statistical values of the first performance measurement data PMDAT1 based on the assumption that the first performance measurement data PMDAT1 obtained by the performance measurement device 1500 and the data collection module 1310 follows a normal distribution. Similarly, the statistical distribution approximation block 110 may calculate second statistical data STDAT2 based on the second performance measurement data PMDAT2, and may calculate a Kth statistical data STDATK based on the Kth performance measurement data PMDATK, where K is a positive integer greater than or equal to 3.

[0068] The conditional probability calculation block 120 may calculate a plurality of conditional probabilities CP1, CP2, ..., CPK based on one of the plurality of sample performance data SPDAT and the plurality of performance data TPDAT and the plurality of statistical data STDAT1 to STDATK. Figure 1When the modeling method described in the following example is used, multiple sample performance data SPDAT can be provided as input. Figure 19 The method described for calculating the remaining useful life can be provided with a plurality of performance data TPDAT as input.

[0069] For example, the conditional probability calculation block 120 may calculate a first conditional probability CP1 that, when a plurality of sample performance data SPDAT or a plurality of performance data TPDAT is input, a first estimated usage time corresponding to the first performance measurement data PMDAT1 and the first statistical data STDAT1 will be output. Similarly, the conditional probability calculation block 120 may calculate a second conditional probability CP2 based on the second statistical data STDAT2 and based on the plurality of sample performance data SPDAT or the plurality of performance data TPDAT, and may calculate a Kth conditional probability CPK based on the Kth statistical data STDATK and based on the plurality of sample performance data SPDAT or the plurality of performance data TPDAT.

[0070] Post-calculation block 130 may output estimated useful life data ELDAT and uncertainty data UCDAT based on multiple conditional probabilities CP1 to CPK. The estimated useful life data ELDAT may correspond to multiple sample performance data SPDAT or multiple performance data TPDAT. The uncertainty data UCDAT may indicate the uncertainty of the estimated useful life data ELDAT. In some embodiments, only the configuration corresponding to post-calculation block 130 may be referred to as a useful life calculation model.

[0071] In some embodiments, at least a portion of the statistical distribution approximation block 110 , the conditional probability calculation block 120 , and the post-calculation block 130 may be implemented in software and / or hardware.

[0072] Reference Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D , showing Figure 4 An example of the post-calculation block 130 in FIG.

[0073] Figure 5A An example of a conventional neural network (or artificial neural network) is shown. For example, a conventional neural network may include an input layer IL, a plurality of hidden layers HL1, HL2, ..., HLn, and an output layer OL.

[0074] The input layer IL may include i input nodes x1, x2, ..., x i , where i is a positive integer. Input data (e.g., vector input data) IDAT of length i can be input to input nodes x1, x2, ..., x i , so that each element of the input data IDAT is input to the input nodes x1, x2, ..., xi The input data IDAT may include information associated with various features of different categories to be classified.

[0075] The plurality of hidden layers HL1, HL2, ..., HLn may include n hidden layers, where n is a positive integer, and may include a plurality of hidden nodes h 1 1.h 1 2. h 1 3. ..., h 1 m 、h 2 1.h 2 2. h 2 3. ..., h 2 m 、h n 1.h n 2. h n 3. ..., h n m For example, the hidden layer HL1 may include m hidden nodes h 1 1.h 1 2. h 1 3. ..., h 1 m , the hidden layer HL2 may include m hidden nodes h 2 1.h 2 2. h 2 3. ..., h 2 m , and the hidden layer HLn may include m hidden nodes h n 1.h n 2. h n 3. ..., h n m , where m is a positive integer.

[0076] The output layer OL may include j output nodes y1, y2, ..., y j , where j is a positive integer. Output nodes y1, y2, ..., y j Each of the input data IDAT may correspond to a corresponding one of the categories to be classified. The output layer OL may generate an output value (e.g., a category score or a numerical output (such as a regression variable)) and / or output data ODAT associated with the input data IDAT for each of the categories. In some embodiments, the output layer OL may be a fully connected layer and may indicate, for example, a probability that the input data IDAT corresponds to a car.

[0077] Figure 5AThe structure of the neural network shown in can be represented by information about branches (or connections) between nodes shown as lines and weight values (not shown) assigned to each branch. In some neural network models, nodes within a layer may not be connected to each other, but nodes in different layers may be fully or partially connected to each other. In some other neural network models (such as unrestricted Boltzmann machines), at least some nodes within a layer may also be connected to other nodes within a layer in addition to one or more nodes in other layers (or alternatively, connected to other nodes within a layer together with one or more nodes in other layers).

[0078] Each node (for example, node h 1 1) can receive the output of the previous node (e.g., node x1), can perform a computation, calculation, or operation on the received output, and can output the result of the computation, calculation, or operation as output to the next node (e.g., node h 2 1). Each node can calculate the value to be output by applying a specific function (e.g., a nonlinear function) to the input. This function can be called the node's activation function.

[0079] In some embodiments, the structure of the neural network is pre-set, and the weight values of the connections between nodes are appropriately set by using sample data with sample answers (also called "labels") that indicate the category of the data corresponding to the sample input value. The data with the sample answers can be referred to as "training data," and the process of determining the weight values can be referred to as "training." The neural network "learns" to associate data with corresponding labels during the training process. A set of independently trainable neural network structures and weight values that have been trained using an algorithm can be referred to as a "model," and the process of predicting which category new input data belongs to using the model with the determined weight values and then outputting the predicted value can be referred to as a "testing" process or operating the neural network in inference mode.

[0080] Figure 5B Shown by included in Figure 5A An example of an operation (e.g., a calculation or operation) performed by a node in a neural network.

[0081] Based on the N inputs a1, a2, a3, ..., a provided to the node ND N , node ND can respectively input N from a1 to a N Multiply by the corresponding N weights w1, w2, w3, ..., w N , N values obtained by multiplication can be summed, a bias "b" can be added to the summed value, and the value to which the bias "b" is added can be applied to a specific function " " to generate an output value (e.g., "z"), where N is a positive integer greater than or equal to 2.

[0082] In some embodiments and as Figure 5B As shown in, included in Figure 5A One layer in the neural network shown in may include M nodes ND, where M is a positive integer greater than or equal to 2, and the output value of one layer may be obtained by Formula 1.

[0083] [Formula 1]

[0084] In Formula 1, “W” represents a weight set including weights for all connections included in one layer and can be implemented in the form of an M×N matrix. “A” represents N inputs a1 to a1 received by one layer. N The input set can be implemented in the form of an N×1 matrix. "Z" represents the M outputs z1, z2, z3, ..., z output from a layer. M The output set of , and can be implemented in the form of an M × 1 matrix.

[0085] Because each node (for example, node h 1 1) Connected to all nodes in the previous layer (e.g., nodes x1, x2, ..., x2 in layer IL) i ), and then the number of weighted values increases dramatically as the size of the input image data increases, so Figure 5A The conventional neural network shown in may not be suitable for processing input image data (or input sound data). Therefore, a convolutional neural network (CNN) has been studied, which is implemented by combining filtering technology with a conventional neural network, so that a two-dimensional image (as an example of input image data) can be efficiently trained by the convolutional neural network.

[0086] Figure 5C An example of a convolutional neural network is shown. For example, a convolutional neural network may include a plurality of layers CONV1, RELU1, CONV2, RELU2, POOL1, CONV3, RELU3, CONV4, RELU4, POOL2, CONV5, RELU5, CONV6, RELU6, POOL3, and FC. Here, "CONV" represents a convolutional layer, "RELU" represents a rectified linear unit activation function, "POOL" represents a pooling layer, and "FC" represents a fully connected layer.

[0087] Unlike conventional neural networks, each layer of a convolutional neural network may have three dimensions of width, height, and depth, and thus the data input to each layer may be volume data with three dimensions of width, height, and depth. For example, if Figure 5C If the input image in has a size of 32 widths (eg, 32 pixels) and 32 heights and three color channels R, G, and B, the input data IDAT corresponding to the input image may have a size of 32×32×3. Figure 5C The input data IDAT in can be referred to as input volume data or input activation volume.

[0088] Each of the convolution layers CONV1, CONV2, CONV3, CONV4, CONV5, and CONV6 can perform a convolution operation on the input volume data. In image processing operations, a convolution operation refers to an operation in which image data is processed based on a mask having weighted values, and an output value is obtained by multiplying the input value by the weighted value and adding the total multiplication results. The mask can be called a filter, a window, or a kernel.

[0089] The parameters of each convolutional layer may include a set of learnable filters. Each filter may be small spatially (along width and height) but may extend through the full depth of the input volume. For example, during the forward pass, each filter may slide across the width and height of the input volume (e.g., convolution), and dot products may be calculated between the entries of the filter and the input at any position. As the filter slides across the width and height of the input volume, a two-dimensional activation map corresponding to the response of the filter at each spatial position may be generated. As a result, the output volume may be generated by stacking these activation maps along the depth dimension. For example, if input volume data having a size of 32×32×3 passes through a convolutional layer CONV1 having four filters with zero-padding, the output volume data of the convolutional layer CONV1 may have a size of 32×32×12 (e.g., the depth of the volume data increases).

[0090] Each of the RELU layers RELU1, RELU2, RELU3, RELU4, RELU5, and RELU6 may perform a rectified linear unit (RELU) operation corresponding to an activation function defined by, for example, a function f(x) = max(0, x) (e.g., for all negative inputs x, the output is zero). For example, if input volume data having a size of 32×32×12 passes through the RELU layer RELU1 to perform the rectified linear unit operation, the output volume data of the RELU layer RELU1 may have a size of 32×32×12 (e.g., the size of the volume data is maintained).

[0091] Each of the pooling layers POOL1, POOL2, and POOL3 may perform a downsampling operation on the input volume data along the spatial dimensions of width and height. For example, four input values arranged in a 2×2 matrix may be converted into one output value based on a 2×2 filter. For example, the maximum value of the four input values arranged in a 2×2 matrix may be selected based on 2×2 maximum pooling, or the average value of the four input values arranged in a 2×2 matrix may be obtained based on 2×2 average pooling. For example, if input volume data having a size of 32×32×12 passes through the pooling layer POOL1 having a 2×2 filter, the output volume data of the pooling layer POOL1 may have a size of 16×16×12 (for example, the width and height of the volume data are reduced, and the depth of the volume data is maintained).

[0092] Generally, convolutional layers may be repeatedly arranged in a convolutional neural network, and pooling layers may be periodically inserted into the convolutional neural network, thereby reducing the spatial size of an image and extracting characteristics of the image.

[0093] The output layer, or fully connected layer FC, can output the result (e.g., class score) for the input volume data IDAT. For example, by repeating convolution and downsampling operations, the input volume data IDAT corresponding to a two-dimensional image can be converted into a one-dimensional matrix or vector, which is called an embedding. For example, the fully connected layer FC can indicate the probability that the input volume data IDAT corresponds to a car, truck, airplane, boat, or horse.

[0094] The type and number of layers included in the convolutional neural network may not be limited to those in FIG. Figure 5C Examples described, and may be determined differently. In addition, although not in Figure 5C Although shown in FIG, the convolutional neural network may further include other layers (such as a softmax layer for converting the score value corresponding to the prediction result into a probability value, a bias addition layer for adding at least one bias, etc.). The bias may also be incorporated into the activation function.

[0095] Figure 5D An example of the post-computation block 130 is shown. For example, the post-computation block 130a may include a first layer LY1 and a second layer LY2.

[0096] The first layer LY1 may include a plurality of nodes N11, N12, ..., N1K, and the second layer LY2 may include a plurality of nodes N21 and N22. For example, the first layer LY1 may be a sigmoid layer using a sigmoid function as an activation function. For example, the second layer LY2 may be a linear summation layer performing a linear summation operation. However, the layers LY1 and LY2 are not limited thereto.

[0097] Furthermore, example embodiments may not be limited to a particular neural network and may apply or employ various other neural networks (e.g., generative adversarial networks (GANs), regional convolutional neural networks (R-CNNs), region generation networks (RPNs), recurrent neural networks (RNNs), stacked deep neural networks (S-DNNs), state-space dynamic neural networks (S-SDNNs), deconvolution networks, deep belief networks (DBNs), restricted Boltzmann machines (RBMs), fully convolutional networks, long short-term memory (LSTM) networks). Alternatively or additionally, the neural network may include other forms of machine learning models (e.g., linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction (e.g., principal component analysis), and expert systems, and / or combinations thereof including ensembles such as random forests).

[0098] Figure 6 It shows that Figure 1 A flowchart of an example of multiple performance measurement data in FIG. Figure 7 、 Figure 8 and Figure 9 is used to describe Figure 6 An illustration of an example operation of .

[0099] Reference Figure 1 、 Figure 4 、 Figure 6 and Figure 7 In operation S100, at a first time point t1 before the accelerated aging test begins, first performance measurement data PMDAT1 associated with a plurality of performances of a plurality of unused memory devices may be obtained (operation S110). At a second time point t2 after the first time point t1, while the accelerated aging test is being performed, second performance measurement data PMDAT2 associated with a plurality of performances of the plurality of unused memory devices may be obtained (operation S120). At a Kth time point tK after the second time point t2, while the accelerated aging test is being performed, Kth performance measurement data PMDATK associated with a plurality of performances of the plurality of unused memory devices may be obtained (operation S130).

[0100] exist Figure 7 , “RTE” may represent an operation using the reliability testing equipment 1400 (e.g., an operation of performing an accelerated aging test), and “PME” may represent a data measurement operation and a data collection operation using the performance measurement equipment 1500 and the data collection module 1310. Arrows shown on “RTE” may represent performance measurement events that occur while the accelerated aging test is being performed.

[0101] Accelerated aging testing uses aggravated conditions such as heat, humidity, oxygen, sunlight, and vibration to accelerate the normal aging process of an item. Accelerated aging testing can be used to help determine the long-term effects of expected stress levels in a relatively short period of time, typically in a laboratory, using controlled, standard test methods. When actual lifetime data is unavailable, accelerated aging testing can be used to estimate a product's useful life or shelf life.

[0102] In some embodiments, HTOL testing can be performed as an accelerated aging test. HTOL testing is a reliability test applied to an integrated circuit (IC) to determine the inherent reliability of the IC. HTOL testing can stress the IC under elevated temperatures, high voltages, and dynamic operation for a predetermined period of time. Typically, the IC is monitored under stress and tested at intermediate intervals. HTOL testing can also be referred to as a life test, device life test, or extended burn-in test, and can be used to trigger potential failure modes and assess IC lifespan.

[0103] At and before the first time point t1, the reliability testing device 1400 may not be operating (e.g., may be in the off state ROFF), and may represent a state before the start of the accelerated aging test. In other words, the first time point t1 may represent a state in which the accelerated aging test has been performed during the first time interval (e.g., within zero hours). The first performance measurement data PMDAT1 of the plurality of unused memory devices measured at the first time point t1 using the performance measurement device 1500 and the data collection module 1310 may represent the initial performance of the plurality of unused memory devices.

[0104] After the first time point t1, the reliability testing apparatus 1400 may be operable (eg, may have an on state RON) to start the accelerated aging test. The performance of a plurality of unused memory devices may be measured while performing the accelerated aging test at a specific time point.

[0105] The second time point t2 may indicate that an accelerated aging test has been performed during the second time interval T2. At the second time point t2, the performance measurement device 1500 and the data collection module 1310 may be used to obtain second performance measurement data PMDAT2 of the plurality of unused memory devices. The Kth time point tK may indicate that an accelerated aging test has been performed during the Kth time interval TK. At the Kth time point tK, the performance measurement device 1500 and the data collection module 1310 may be used to obtain Kth performance measurement data PMDATK of the plurality of unused memory devices.

[0106] Reference Figure 8, showing examples of a plurality of performance measurement data PMDAT1 to PMDATK.

[0107] In some embodiments, the plurality of performances of the plurality of unused memory devices may include first performance PF1 to Lth performance PFL different from each other, where L is a positive integer greater than or equal to 2. For example, the plurality of performances PF1 to PFL may be performances associated with I / O timing of the plurality of unused memory devices. For example, when each of the plurality of unused memory devices is a DRAM device, the plurality of performances PF1 to PFL may include a first performance t CK , the second performance t DV , the third performance t PD , fourth performance, etc. For example, the first performance t CK It can represent the minimum period of the clock signal required for normal operation of DRAM. The second performance t DV It can represent the size of the valid data window, the third performance t PD The fourth performance may represent a propagation delay, and the fourth performance may represent a duty cycle of a clock signal. However, example embodiments are not limited thereto. For example, the plurality of performances PF1 to PF2 may include at least a portion of all possible performance parameters, and a performance parameter having a relatively large variation over time compared to the distribution of the manufacturing process may be selected and used.

[0108] For example, the first performance measurement data PMDAT1 obtained at the first time point t1 may include first-first performance measurement data PMDAT1-1 associated with the first performance PF1 of the plurality of unused memory devices to first-Lth performance measurement data PMDAT1-L associated with the Lth performance PFL of the plurality of unused memory devices. Similarly, the second performance measurement data PMDAT2 may include second-first performance measurement data PMDAT2-1 associated with the first performance PF1 to second-Lth performance measurement data PMDAT2-L associated with the Lth performance PFL. The Kth performance measurement data PMDATK may include Kth-first performance measurement data PMDATK-1 associated with the first performance PF1 to Kth-Lth performance measurement data PMDATK-L associated with the Lth performance PFL.

[0109] Reference Figure 9 , shows an example where K=3 and L=2. For example, Figure 9 The two different performances of multiple unused memory devices are shown by measuring the performance at three different time points. CK and t DVFor example, as accelerated aging tests are performed on a plurality of unused memory devices (eg, as the service life of DRAM increases), the first performance t representing the minimum period of the clock signal is obtained. CK The second property t that can be increased and represents the size of the data valid window DV Can be reduced.

[0110] Figure 10 It shows that Figure 1 For the sake of brevity, the flowchart of the example of multiple performance measurement data will be omitted. Figure 6 Duplicate or overlapping descriptions.

[0111] Reference Figure 1 、 Figure 7 and Figure 10 In operation S100, operations S110, S120 and S130 may be performed with reference to Figure 6 The operations described are essentially the same.

[0112] Thereafter, a plurality of estimated usage times of the plurality of unused memory devices may be obtained (operation S140). Each of the plurality of estimated usage times may correspond to a corresponding one of the first time point t1 to the Kth time point tK. In other words, the time experienced by the product under accelerated conditions may be converted into the time expected to be experienced by the product under actual usage conditions.

[0113] For example, a first estimated usage time of the plurality of unused memory devices may be obtained based on a first time point t1 (operation S141), a second estimated usage time of the plurality of unused memory devices may be obtained based on a second time point t2 (operation S143), and a Kth estimated usage time of the plurality of unused memory devices may be obtained based on a Kth time point tK (operation S145). For example, the first estimated usage time may correspond to a first time interval (e.g., zero hours) during which the accelerated aging test is performed, the second estimated usage time may correspond to a second time interval T2 during which the accelerated aging test is performed, and the Kth estimated usage time may correspond to a Kth time interval TK during which the accelerated aging test is performed.

[0114] In some embodiments, the first estimated usage time to the Kth estimated usage time may be calculated using at least one of an Arrhenius formula and / or various empirically obtained transformation formulas.

[0115] As a result, the first performance measurement data PMDAT1 obtained at the first time point t1 can be regarded or handled as a performance parameter obtained when the plurality of unused memory devices will be used for the first estimated usage time under actual usage conditions (e.g., a performance parameter obtained when the plurality of unused memory devices are not used). Similarly, the second performance measurement data PMDAT2 can be regarded as a performance parameter obtained when the plurality of unused memory devices will be used for the second estimated usage time under actual usage conditions, and the Kth performance measurement data PMDATK can be regarded as a performance parameter obtained when the plurality of unused memory devices will be used for the Kth estimated usage time under actual usage conditions.

[0116] although Figure 10 Operation S140 is shown to be performed after operations S110, S120, and S130, but example embodiments are not limited thereto. For example, operation S141 may be performed after operation S110, operation S143 may be performed after operation S120, and operation S145 may be performed after operation S130.

[0117] Figure 11 It shows the calculation Figure 1 Flowchart of an example of multiple statistics in .

[0118] Reference Figure 1 、 Figure 4 and Figure 11 In operation S200, first statistical data STDAT1 including a first average value and a first standard deviation of the first performance measurement data PMDAT1 may be obtained (operation S210), second statistical data STDAT2 including a second average value and a second standard deviation of the second performance measurement data PMDAT2 may be obtained (operation S220), and K-th statistical data STDATK including a K-th average value and a K-th standard deviation of the K-th performance measurement data PMDATK may be obtained (operation S230). For example, each statistical data may be obtained as in Formula 2.

[0119] [Formula 2]

[0120] In Formula 2, " "and" " denote a mean value and a standard deviation, respectively, and can be obtained by performing probability distribution fitting (or data fitting) by assuming that each performance measurement data follows a normal distribution. For example, a K-dimensional Gaussian distribution can be formed by the first statistical data STDAT1 to the K-th statistical data STDATK.

[0121] However, example embodiments are not limited thereto. For example, “ " may represent the mean, and "Σ" may represent the standard deviation and covariance. For example, if " " indicates only the standard deviation, and there may be no correlation between the performance measurements. For example, if " " represents the standard deviation and covariance, then there may be correlation between the performance measurement data. In " In an example where " represents a standard deviation and a covariance, the first statistical data STDAT1 obtained in operation S210 may include a first mean, a first standard deviation, and a first covariance, the second statistical data STDAT2 obtained in operation S220 may include a second mean, a second standard deviation, and a second covariance, and the K-th statistical data STDATK obtained in operation S230 may include a K-th mean, a K-th standard deviation, and a K-th covariance.

[0122] In some embodiments, when the plurality of performance measurement data PMDAT1 to PMDATK are implemented as follows Figure 8 As shown in , they can be obtained in the form of L×1 vector and L×L matrix respectively. and For example, in the first statistical data STDAT1 obtained based on the first performance measurement data PMDAT1, the first average value (eg, " ”) can be expressed in the form of an L×1 vector including the average value of the first-first performance measurement data PMDAT1-1 to the average value of the first-Lth performance measurement data PMDAT1-L, and the first standard deviation (e.g., “ ”) can be expressed in the form of an L×L matrix, which includes the standard deviation of the first-first performance measurement data PMDAT1-1 to the standard deviation of the first-Lth performance measurement data PMDAT1-L.

[0123] although Figure 11 Operations S210, S220, and S230 are shown to be performed sequentially, but example embodiments are not limited thereto. For example, at least a portion or all of operations S210, S220, and S230 may be performed in parallel (eg, substantially simultaneously).

[0124] Figure 12 It shows the calculation Figure 1 Flowchart of an example of multiple conditional probabilities in .

[0125] Reference Figure 1 、 Figure 4 and Figure 12In operation S300, a first conditional probability CP1 may be obtained that, when a plurality of sample performance data SPDAT is input, a "first estimated usage time corresponding to the first performance measurement data PMDAT1 and the first statistical data STDAT1" will be output (operation S310). A second conditional probability CP2 may be obtained that, when a plurality of sample performance data SPDAT is input, a "second estimated usage time corresponding to the second performance measurement data PMDAT2 and the second statistical data STDAT2" will be output (operation S320). Furthermore, a K-th conditional probability CPK may be obtained that, when a plurality of sample performance data SPDAT is input, a "K-th estimated usage time corresponding to the K-th performance measurement data PMDATK and the K-th statistical data STDATK" will be output (operation S330). For example, each conditional probability may be obtained as shown in Formula 3.

[0126] [Formula 3]

[0127] In Formula 3, "yr" and "Tx" represent the estimated usage time and sample performance data, respectively. When a specific performance parameter of a memory device (e.g., sample performance data "Tx") is measured, the probability that the memory device has been used for the estimated usage time "yr" under actual usage conditions can be calculated. For example, the estimated usage time "yr" can be expressed in units of years. For example, similar to each performance measurement data, the sample performance data "Tx" can include L performance values associated with the first performance PF1 to the Lth performance PFL.

[0128] although Figure 12 Operations S310, S320, and S330 are shown to be performed sequentially, but example embodiments are not limited thereto. For example, at least some or all of operations S310, S320, and S330 may be performed in parallel (eg, substantially simultaneously).

[0129] Subsequently, the process of training the lifespan calculation model 100 in operation S400 may be performed based on methods known in the art. For example, when training the lifespan calculation model 100, a plurality of sample performance data SPDAT and sample usage time data may be prepared, with the sample usage time data serving as ground truth (or correct answer information) for the plurality of sample performance data SPDAT. Estimated lifespan data ELDAT may then be obtained by applying the plurality of sample performance data SPDAT to the lifespan calculation model 100 (e.g., by inputting the plurality of sample performance data SPDAT into the lifespan calculation model 100 and sequentially performing a plurality of computational operations on the plurality of sample performance data SPDAT). The consistency of the lifespan calculation model 100 may then be checked by comparing the sample usage time data with the estimated lifespan data ELDAT.

[0130] In some embodiments, the lifespan calculation model 100 may be trained by updating tuning parameters and / or hyperparameters included in the lifespan calculation model 100 .

[0131] In some embodiments, the lifespan calculation model 100 can be trained by performing forward propagation and backpropagation on the lifespan calculation model 100. Forward propagation can be part of a process while the training operation is being performed, and backpropagation can be another part of a process performed while the training operation is being performed. Forward propagation can refer to a process of calculating an output (or output data) by passing an input (or input data) through the lifespan calculation model 100 in a forward direction. Backpropagation can refer to a process of calculating a loss by comparing the output with a label that is a previously obtained ground truth value, calculating the gradient of the weights so that the loss is reduced by passing the calculated loss through the lifespan calculation model 100 in a backward direction, and updating the weights. Backpropagation can be referred to as error backpropagation.

[0132] In some embodiments, when the lifespan calculation model 100 is trained, a plurality of weights included in the lifespan calculation model 100 may be updated.

[0133] Figure 13 is a flow chart illustrating an example of a modeling method for estimating the useful life of a memory device. Figure 1 Duplicate or overlapping descriptions.

[0134] Reference Figure 13 In the modeling method, operations S100, S200, S300 and S400 can be compared with reference Figure 1 The operations described are essentially the same.

[0135] Thereafter, the life calculation model may be retrained based on the uncertainty data output from the life calculation model (operation S500). For example, the estimated uncertainty may be quantified. For example, the validity of the life calculation model may be verified based on the estimated uncertainty, and the estimated uncertainty may be used as an indicator of potential errors in the measurement process. In other words, when the consistency of the life calculation model does not reach the target consistency, the life calculation model may be retrained, which will refer to the target consistency. Figure 14 and Figure 15 Provide a description.

[0136] although Figure 13 Operation S500 is shown to be performed once, but example embodiments are not limited thereto. For example, operation S500 may be performed multiple times until the consistency of the life calculation model reaches a target consistency.

[0137] Figure 14 and Figure 15is a flow chart illustrating an example of a modeling method for estimating the useful life of a memory device. Figure 1 and Figure 13 Duplicate or overlapping descriptions.

[0138] Reference Figure 14 In the modeling method, operations S100 and S200 can be compared with reference Figure 1 The operations described are substantially the same, and operations S301 and S401 can be respectively Figure 1 Operations S300 and S400 are similar.

[0139] In some embodiments, the uncertainty data may include a data uncertainty value that represents or indicates uncertainty in the estimated useful life data caused by noise in the plurality of sample performance data.

[0140] In operation S500 , a data uncertainty value included in the uncertainty data may be compared with a data reference value (operation S511 ).

[0141] When the data uncertainty value is greater than the aforementioned data reference value (operation S511: Yes), for example, when the consistency of the lifespan calculation model does not meet the target consistency, a plurality of additional sample performance data different from (or in addition to) the plurality of sample performance data may be provided (operation S513), and the lifespan calculation model may be retrained based on the plurality of additional sample performance data. For example, the plurality of conditional probabilities may be recalculated by performing operation S301 based on the plurality of additional sample performance data, and the lifespan calculation model may be retrained by performing operation S401 based on the recalculated plurality of conditional probabilities. In this example, operations S301 and S401, which are first performed, may be substantially the same as operations S300 and S400, and operations S301 and S401, which are performed after operations S511 and S513, may be part of operation S500.

[0142] When the data uncertainty value is less than or equal to the data reference value (operation S511: No), for example, when the consistency of the life calculation model reaches the target consistency, the process may be terminated without retraining the life calculation model. In other words, the operation of retraining the life calculation model may be repeatedly performed until the consistency of the life calculation model reaches the target consistency.

[0143] Reference Figure 15 In the modeling method, operations S100, S200 and S300 can be compared with reference Figure 1 The operations described are substantially the same, and operation S401 can be used with Figure 1 The operation S400 is similar to that in FIG.

[0144] In some embodiments, the uncertainty data may include a model uncertainty value that represents or indicates uncertainty in the estimated useful life data caused by errors and / or problems in the useful life calculation model itself.

[0145] In operation S500 , a model uncertainty value included in the uncertainty data may be compared with a model reference value (operation S521 ).

[0146] When the model uncertainty value is greater than the model reference value (operation S521: Yes), for example, when the consistency of the life calculation model does not meet the target consistency, the life calculation model may be corrected or modified (operation S523), and the corrected life calculation model may be retrained based on the plurality of sample performance data. For example, the life calculation model may be corrected in operation S523 by changing hyperparameters, weights, or layer structures, and then the corrected life calculation model may be retrained by performing operation S401 based on the plurality of conditional probabilities of operation S300.

[0147] When the model uncertainty value is less than or equal to the model reference value (operation S521 : No), for example, when the consistency of the life calculation model reaches the target consistency, the process may be terminated without retraining the life calculation model.

[0148] In some embodiments, the uncertainty data may include both data uncertainty values and model reference values. Figure 14 and Figure 15 The examples of FIG. 1 and FIG. 2 can be combined to implement example implementations.

[0149] Figure 16A 、 Figure 16B and Figure 16C is a diagram for describing an example of a modeling method for estimating the useful life of a memory device.

[0150] Reference Figure 16A , showing an example of an implementation of the modeling method. For example, performing the "given measurement value" phase, the "statistics-fitting" phase (wherein, Indicates the result of statistics-fitting), "measurement for unknown chips" stage, "conditional probability & layer" stage (where, represents the result of calculating the "conditional probability") and the "final estimate (year)" stage (where, Represents the result of calculating the "Final Estimate (Year)"). In the "Given Measurement Value" stage, an accelerated aging test is performed on sixty devices under test (DUTs) (wherein DUT ID may represent the identification of each DUT), five different performance values are measured for each DUT at six different time points, and the estimated usage time (e.g., year) corresponding to the six time points is obtained. Thereafter, in the "Statistics-Fitting" stage, the "Measurement for Unknown Chips" stage, and the "Conditional Probability & Layer" stage, statistical distribution approximation and conditional probability calculation are performed, and the sigmoid layer and the linear summation layer are executed. Thereafter, in the "Final Estimate (Year)" stage, a lifespan calculation model for obtaining an estimated service life is implemented. For example, for the parameter " "Perform model fitting (e.g., data training, parameter calibration, etc.).

[0151] Reference Figure 16B and 16C , showing a simulation example of the modeling approach.

[0152] exist Figure 16B In FIG, the X-axis and the Y-axis represent the measured performance values associated with the I / O timing of the DRAM, and the Z-axis represents the number of service life (eg, years of use). For example, the X-axis and the Y-axis may represent t DV and t CK In addition, points with the same color represent measured performance values corresponding to the same year of use. Figure 16C is with Figure 16B A two-dimensional representation of the same information. Figure 16C , the results of fitting the distribution of performance values corresponding to each year of use to a normal distribution are shown as contour lines.

[0153] exist Figure 16B In FIG. 1 , the curve represents an estimated result from a life calculation model generated based on such measured performance values (eg, the points shown). In other words, the curve may represent an estimated useful life N output by inputting arbitrary X and Y values. yr .exist Figure 16B and Figure 16C In FIG, X marks and square marks represent an example of estimating the age of a memory device whose information is unknown. For example, if the measured performance value of a particular memory device corresponds to an X mark on a plane where Z=0, the estimated age of the particular memory device may correspond to the Z value at which the square mark connected to the X mark is located.

[0154] Figure 17A and Figure 17B is a block diagram illustrating an example of a memory device.

[0155] Reference Figure 17AMemory device 200 may include control logic 210, refresh control circuit 215, address register 220, bank control logic 230, row address (RA) multiplexer (MUX) 240, column address (CA) latch 250, row decoder, column decoder, memory cell array, sense amplifier unit, input / output (I / O) gating circuit 290, data I / O buffer 295, and data I / O pad 299. For example, memory device 200 may be one of various volatile memory devices such as a DRAM device.

[0156] The memory cell array may include a plurality of memory cells. The memory cell array may include a plurality of memory bank arrays (e.g., first to fourth memory bank arrays 280a, 280b, 280c, and 280d). The row decoder may include a plurality of memory bank row decoders (e.g., first to fourth memory bank row decoders 260a, 260b, 260c, and 260d, respectively, connected to the first to fourth memory bank arrays 280a, 280b, 280c, and 280d). The column decoder may include a plurality of memory bank column decoders (e.g., first to fourth memory bank column decoders 270a, 270b, 270c, and 270d, respectively, connected to the first to fourth memory bank arrays 280a, 280b, 280c, and 280d). The sense amplifier unit may include a plurality of bank sense amplifiers, for example, first to fourth bank sense amplifiers 285a, 285b, 285c, and 285d connected to first to fourth bank arrays 280a, 280b, 280c, and 280d, respectively.

[0157] The first to fourth bank arrays 280a to 280d, the first to fourth bank row decoders 260a to 260d, the first to fourth bank column decoders 270a to 270d, and the first to fourth bank sense amplifiers 285a to 285d may form first to fourth banks, respectively. For example, the first memory cell array 280a, the first memory cell row decoder 260a, the first memory cell column decoder 270a and the first memory cell sense amplifier 285a may form a first memory cell; the second memory cell array 280b, the second memory cell row decoder 260b, the second memory cell column decoder 270b and the second memory cell sense amplifier 285b may form a second memory cell; the third memory cell array 280c, the third memory cell row decoder 260c, the third memory cell column decoder 270c and the third memory cell sense amplifier 285c may form a third memory cell; and the fourth memory cell array 280d, the fourth memory cell row decoder 260d, the fourth memory cell column decoder 270d and the fourth memory cell sense amplifier 285d may form a fourth memory cell.

[0158] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a controller located outside the memory device 200. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

[0159] The bank control logic 230 may generate a bank control signal in response to receiving the bank address BANK_ADDR. In response to the bank control signal generated by the bank control logic 230, one of the first to fourth bank row decoders 260a to 260d corresponding to the received bank address BANK_ADDR may be activated, and in response to the bank control signal generated by the bank control logic 230, one of the first to fourth bank column decoders 270a to 270d corresponding to the received bank address BANK_ADDR may be activated.

[0160] The refresh control circuit 215 may generate a refresh address REF_ADDR in response to receipt of a refresh command or entry into any self-refresh mode. For example, the refresh control circuit 215 may include a refresh counter configured to sequentially change the refresh address REF_ADDR from the first address of the memory cell array to the last address of the memory cell array. The refresh control circuit 215 may receive a control signal from the control logic 210.

[0161] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220 and a refresh address REF_ADDR from the refresh control circuit 215. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh address REF_ADDR. The row address output from the row address multiplexer 240 (e.g., the row address ROW_ADDR or the refresh address REF_ADDR) may be applied to the first to fourth bank row decoders 260a to 260d.

[0162] The activated one of the first to fourth bank row decoders 260a to 260d may decode the row address output from the row address multiplexer 240 and activate a word line corresponding to the row address. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address.

[0163] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or received column address COL_ADDR to the first to fourth bank column decoders 270a to 270d.

[0164] An activated one of the first to fourth bank column decoders 270 a to 270 d may decode the column address COL_ADDR output from the column address latch 250 and may control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR.

[0165] The I / O gating circuit 290 may include a circuit for gating I / O data. For example, although not shown, the I / O gating circuit 290 may include input data mask logic, a read data latch for storing data output from the first to fourth memory bank arrays 280 a to 280 d, and a write driver for writing data to the first to fourth memory bank arrays 280 a to 280 d.

[0166] Data DQ to be read from one of the first to fourth bank arrays 280a to 280d may be sensed by a sense amplifier coupled to the one bank array and may be stored in a read data latch. The data DQ stored in the read data latch may be provided to a controller via a data I / O buffer 295 and a data I / O pad 299. Data DQ received via the data I / O pad 299 to be written to one of the first to fourth bank arrays 280a to 280d may be provided from the controller to the data I / O buffer 295. The data DQ received via the data I / O pad 299 and provided to the data I / O buffer 295 may be written to one bank array via a write driver in the I / O gating circuit 290.

[0167] The control logic 210 may control the operation of the memory device 200. For example, the control logic 210 may generate a control signal for the memory device 200 to perform a data write operation or a data read operation. The control logic 210 may include a command decoder 211 that decodes a command CMD received from a controller and a mode register 212 that sets an operation mode of the memory device 200.

[0168] Reference Figure 17B Memory device 300 may include a memory cell array 310, an address decoder 320, a page buffer circuit 330, a data input / output (I / O) circuit 340, a voltage generator 350, and a control circuit 360. For example, memory device 300 may be one of various nonvolatile memory devices such as a NAND flash memory device.

[0169] The memory cell array 310 may be connected to the address decoder 320 via a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL. The memory cell array 310 may also be connected to the page buffer circuit 330 via a plurality of bit lines BL. The memory cell array 310 may include a plurality of memory cells (e.g., a plurality of nonvolatile memory cells) connected to the plurality of word lines WL and the plurality of bit lines BL. The memory cell array 310 may be divided into a plurality of memory blocks BLK1, BLK2, ..., BLKz, each of which includes a memory cell.

[0170] In some embodiments, a plurality of memory cells may be arranged in a two-dimensional (2D) array structure or a three-dimensional (3D) vertical array structure. The 3D vertical array structure may include a vertical cell string oriented vertically such that at least one memory cell is positioned above another memory cell. At least one memory cell may include a charge trapping layer. The following patent documents (U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Publication No. 2011 / 0233648), which are incorporated herein by reference in their entirety, describe suitable configurations for a memory cell array including a 3D vertical array structure in which the three-dimensional memory array is configured into multiple layers, with word lines and / or bit lines shared between the layers.

[0171] The control circuit 360 may receive a command CMD and an address ADDR from a controller located outside the memory device 300, and may control an erase operation, a program operation, and a read operation of the memory device 300 based on the command CMD and the address ADDR. An erase operation may include executing an erase cycle sequence, and a program operation may include executing a program cycle sequence. Each program cycle may include a program operation and a program verification operation. Each erase cycle may include an erase operation and an erase verification operation. A read operation may include a normal read operation and a data recovery read operation.

[0172] For example, based on the command CMD, the control circuit 360 may generate a control signal CON for controlling the voltage generator 350 and a control signal PBC for controlling the page buffer circuit 330. The control circuit 360 may also generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit 360 may provide the row address R_ADDR to the address decoder 320 and the column address C_ADDR to the data I / O circuit 340.

[0173] The address decoder 320 may be connected to the memory cell array 310 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. For example, in a data erase operation / write operation / read operation, the address decoder 320 may determine at least one of the plurality of word lines WL as a selected word line, determine at least one of the plurality of string selection lines SSL as a selected string selection line, and determine at least one of the plurality of ground selection lines GSL as a selected ground selection line based on the row address R_ADDR.

[0174] The voltage generator 350 may generate a voltage VS required for the operation of the memory device 300 based on the power PWR and the control signal CON. The voltage VS may be applied to a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL via the address decoder 320. Furthermore, the voltage generator 350 may generate an erase voltage VERS required for an erase operation based on the power PWR and the control signal CON.

[0175] The page buffer circuit 330 may be connected to the memory cell array 310 via a plurality of bit lines BL. The page buffer circuit 330 may include a plurality of page buffers. The page buffer circuit 330 may store data DAT to be programmed into the memory cell array 310, or may read data DAT sensed from the memory cell array 310. In other words, the page buffer circuit 330 may operate as a write driver or a sense amplifier according to an operating mode of the memory device 300.

[0176] The data I / O circuit 340 may be connected to the page buffer circuit 330 via the data line DL. The data I / O circuit 340 may provide data DAT from outside the memory device 300 to the memory cell array 310 via the page buffer circuit 330 based on the column address C_ADDR or may provide data DAT from the memory cell array 310 to outside the memory device 300.

[0177] Although the memory devices are described based on DRAM devices and NAND flash memory devices, the memory devices may be any volatile memory device and / or any non-volatile memory device (e.g., static random access memory (SRAM) devices, phase change random access memory (PRAM) devices, resistive random access memory (ReRAM) devices, magnetic random access memory (MRAM) devices, ferroelectric random access memory (FRAM) devices, etc.).

[0178] Figure 18A 、 Figure 18B and Figure 18C is a diagram illustrating an implementation example of a memory device.

[0179] Reference Figure 18A and 18B , illustrating an example of a memory device provided in the form of a memory package including a memory chip.

[0180] For example, Figure 18A As shown in FIG, a memory package 700 may include a base substrate 710 and a plurality of memory chips CHP1, CHP2, and CHP3 stacked on the base substrate 710. Each of the memory chips CHP1 to CHP3 may include at least one memory device.

[0181] In some embodiments, the memory chips CHP1 to CHP3 may be stacked on the base substrate 710 so that the surfaces on which the I / O pads are formed face upward. In some embodiments, the I / O pads of each of the memory chips CHP1 to CHP3 may be arranged close to one side of the semiconductor substrate. In this manner, the memory chips CHP1 to CHP3 may be stacked in a ladder-like manner (i.e., in a stepped shape) so that the I / O pads of each memory chip are exposed. In this stacked state, the memory chips CHP1 to CHP3 may be electrically connected to the base substrate 710 via a plurality of bonding wires BW.

[0182] The stacked memory chips CHP1 to CHP3 and a plurality of bonding wires BW may be fixed by a sealing member 740, and an adhesive member 730 may be interposed between the base substrate 710 and the memory chips CHP1 to CHP3. Conductive bumps 720 may be formed on the bottom surface of the base substrate 710 to be electrically connected to an external device.

[0183] For example, Figure 18B As shown in FIG, a memory package 800 may include a base substrate 810 and a plurality of memory chips CHP1, CHP2, and CHP3 stacked on the base substrate 810. For the sake of brevity, the memory package 800 will be omitted. Figure 18A Duplicate or overlapping descriptions.

[0184] Each of the memory chips CHP1 to CHP3 may further include a plurality of through silicon vias (TSVs, or through silicon vias) 830. The conductive bumps 820 and the sealing member 850 may be respectively connected to the conductive bumps 820 and the sealing member 850. Figure 18A The conductive bumps 720 and the sealing member 740 in FIG. 7 are substantially the same.

[0185] In some embodiments, multiple TSVs 830 may be arranged at the same location within each of the memory chips CHP1 to CHP3. In this manner, the memory chips CHP1 to CHP3 may be stacked such that the multiple TSVs 830 of each memory chip are completely stacked (e.g., the arrangement of the multiple TSVs 830 may perfectly match within the memory chips CHP1 to CHP3). In this stacked state, the memory chips CHP1 to CHP3 may be electrically connected to each other and to the base substrate 810 via the multiple TSVs 830 and the conductive material 840.

[0186] Reference Figure 18C , illustrating an example of a memory device provided in the form of a memory module including a memory package.

[0187] For example, the memory module 500 may include a circuit board 501, a buffer chip 590 (e.g., a registered clock driver, RCD), a plurality of memory devices 601a, 601b, 601c, 601d, 601e, 602a, 602b, 602c, 602d, 602e, 603a, 603b, 603c, 603d, 604a, 604b, 604c and 604d, module resistor units 560 and 570, a serial presence detect (SPD) chip 580 and / or a power management integrated circuit (PMIC) 585. For example, multiple memory devices 601a to 601e, 602a to 602e, 603a to 603d and 604a to 604d, module resistance units 560 and 570, SPD chip 580, PMIC 585 and / or buffer chip 590 may be provided, arranged or mounted on or in circuit board 501.

[0188] The buffer chip 590 may control the plurality of memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d and the PMIC 585 under the control of a memory controller located outside the memory module 500. For example, the buffer chip 590 may receive an address ADDR, a command CMD, and data DAT from the memory controller.

[0189] The SPD chip 580 may be a programmable read-only memory (PROM) (e.g., an electrically erasable PROM (EEPROM)). The SPD chip 580 may include initial information and / or device information DI of the memory module 500. In some embodiments, the SPD chip 580 may include initial information and / or device information DI (such as the module form, module configuration, storage capacity, module type, execution environment, etc. of the memory module 500). When a memory system including the memory module 500 is booted, the memory controller may read the device information DI from the SPD chip 580 and may identify the memory module 500 based on the device information DI. The memory controller may control the memory module 500 based on the device information DI from the SPD chip 580. For example, the memory controller may identify the type of memory device included in the memory module 500 based on the device information DI from the SPD chip 580.

[0190] The circuit board 501 may extend in a second direction D2 perpendicular to the first direction D1 between a first edge portion 503 and a second edge portion 505. The first edge portion 503 and the second edge portion 505 may extend in the first direction D1. For example, the circuit board 501 may be a printed circuit board (PCB). The buffer chip 590 may be arranged in the center of the circuit board 501. The memory devices 601a to 601e and 602a to 602e may be arranged in multiple rows between the buffer chip 590 and the first edge portion 503, or along the multiple rows between the buffer chip 590 and the first edge portion 503. The memory devices 603a to 603d and 604a to 604d may be arranged in multiple rows between the buffer chip 590 and the second edge portion 505, or along the multiple rows between the buffer chip 590 and the second edge portion 505.

[0191] The buffer chip 590 can store data DAT in the plurality of memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d. The buffer chip 590 can provide command / address (CA) signals (e.g., command / address (CA) signals corresponding to commands CMD and addresses ADDR) to the plurality of memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d via CA transmission lines 561, 563, 571, and 573. In some embodiments, the operations described herein as being performed by the buffer chip 590 can be performed by a processing circuit.

[0192] CA transmission lines 561 and 563 may be commonly connected to the module resistance unit 560 adjacent to the first edge portion 503, and CA transmission lines 571 and 573 may be commonly connected to the module resistance unit 570 adjacent to the second edge portion 505. Each of the module resistance units 560 and 570 may include a termination resistor connected to a termination voltage Vtt. .

[0193] For example, each or at least one of the plurality of memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d may be or include a DRAM device.

[0194] The PMIC 585 may be disposed adjacent to the buffer chip 590. The PMIC 585 may generate a power supply voltage VDD based on an input voltage VIN and may provide the power supply voltage VDD to the plurality of memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d.

[0195] Figure 19is a flowchart illustrating an example of a method of calculating a remaining useful life of a memory device.

[0196] Reference Figure 19 The method for calculating the remaining useful life may be performed using a useful life calculation model. For example, the method for calculating the remaining useful life may be performed on a computer-based system and / or tool, at least a portion of which is implemented in hardware and / or software.

[0197] In the method of calculating the remaining service life, a life calculation model is generated using a plurality of unused memory devices (operation S1100). Figures 1 to 16C The modeling method described herein may be used to perform operation S1100. For example, in operation S1100, while an accelerated aging test is being performed on a plurality of unused memory devices, a plurality of performance measurement data associated with a plurality of properties of the plurality of unused memory devices may be obtained. A plurality of statistical data may be calculated by performing statistical distribution approximation on the plurality of performance measurement data. A plurality of first conditional probabilities may be calculated based on a plurality of sample performance data associated with the plurality of properties and the plurality of statistical data. A lifespan calculation model may be trained based on the plurality of first conditional probabilities. The lifespan calculation model may output first estimated service life data and first uncertainty data. The first estimated service life data may correspond to the plurality of sample performance data, and the first uncertainty data may represent uncertainty in the first estimated service life data.

[0198] A plurality of performance data associated with a plurality of performances of at least one target memory device that has been used is measured (operation S1200). As described above, the at least one target memory device may be the same product as the plurality of unused memory devices, and may be a product that has been used by a user in a scenario and has been restored after being exposed to a specific environment and / or damaged. The plurality of performance data may be implemented similarly to the plurality of performance measurement data PMDAT1 to PMDATK and the plurality of sample performance data SPDAT. For example, operation S1200 may be performed by Figure 2 The performance measurement device 1500 and the data collection module 1310 are executed.

[0199] The remaining service life of at least one target memory device is obtained based on the life calculation model and a plurality of performance data associated with a plurality of performances (operation S1300). For example, operation S1300 may be performed by Figure 2 The inference and calculation module 1330 in Figure 20 and Figure 21 Operation S1300 is described.

[0200] Figure 20 and Figure 21 It shows that Figure 19Flowchart of an example of the remaining useful life.

[0201] Reference Figure 19 and Figure 20 In operation S1300, a plurality of second conditional probabilities may be calculated based on a plurality of performance data and a plurality of statistical data (operation S1310), and second estimated service life data may be obtained based on the plurality of second conditional probabilities and a service life calculation model (operation S1320). The second estimated service life data may correspond to the plurality of performance data. Operations S1310 and S1320 may be respectively Figure 1 In order to distinguish operations S300 and S400 from operations S1310 and S1320, the data obtained in operations S300 and S400 of operation S1100 may be referred to as a plurality of first conditional probabilities and first estimated useful life data, and the data obtained in operations S1310 and S1320 may be referred to as a plurality of second conditional probabilities and second estimated useful life data.

[0202] The remaining useful life of the at least one target memory device may be calculated by subtracting the useful life of the at least one target memory device from the initial guaranteed useful life of the at least one target memory device (operation S1330). The useful life may correspond to the second estimated useful life data. For example, the initial guaranteed useful life may represent a warranty period determined during the design phase of the target memory device and specified in the product specification. For example, if the initial guaranteed useful life is 20 years and the useful life is estimated to be 8 years, the remaining useful life may be calculated as 12 years.

[0203] Reference Figure 19 and Figure 21 In operation S1300, operations S1310 and S1330 may be performed with reference to Figure 20 The operations described are essentially the same.

[0204] Second estimated service life data and second uncertainty data may be obtained based on the plurality of second conditional probabilities and the service life calculation model (operation S1321). The second estimated service life data may correspond to the plurality of performance data, and the second uncertainty data may represent uncertainty in the second estimated service life data. In addition to obtaining the second uncertainty data in operation S1321, operation S1321 may be performed in conjunction with Figure 20 To distinguish between operation S400 and operation S1321, the data obtained in operation S400 of operation S1100 may be referred to as first uncertainty data, and the data obtained in operation S1321 may be referred to as second uncertainty data.

[0205] The second estimated useful life data may be selectively retrieved based on the second uncertainty data (operation S1340). Figure 14 and Figure 15 As described above, when the uncertainty value included in the second uncertainty data is greater than the reference value, the second estimated useful life data may be re-obtained by re-performing operations S1310 and S1321 (e.g., by re-performing only the calculation), or the second estimated useful life data may be re-obtained by re-performing operations S1200, S1310, and S1321 (e.g., by re-performing the performance measurement and calculation). For example, when the uncertainty value included in the second uncertainty data is less than or equal to the reference value, the second estimated useful life data may not be re-obtained.

[0206] Figure 22 、 Figure 23 、 Figure 24 and Figure 25 is a flow chart illustrating an example of a method for calculating the remaining useful life of a memory device. Figure 19 Duplicate or overlapping descriptions.

[0207] Reference Figure 22 In the method for calculating the remaining service life, operations S1100 and S1200 can be compared with reference to Figure 19 The operations described are essentially the same.

[0208] In some embodiments, even if the plurality of unused memory devices and the at least one target memory device are the same product and have the same structure, the specific provision schemes may be different from each other. Figure 18A and Figure 18B A plurality of unused memory devices are provided in the form of a memory package as described, and a life calculation model can be generated based on the memory package. Figure 18C At least one target memory device is provided in the form of a memory module as described.

[0209] Therefore, the plurality of performance data measured in operation S1200 may be compensated or corrected (operation S1250). For example, the plurality of performance data may be compensated by simply adding an offset value to the plurality of performance data or subtracting an offset value from the plurality of performance data. For example, the plurality of performance data may be compensated by reflecting the substrate included in the memory module (e.g., Figure 18C The RLC load characteristics of the circuit board 501 in the embodiment are used to compensate for the multiple performance data.

[0210] Thereafter, the remaining useful life of at least one target memory device may be obtained based on the life calculation model and the plurality of compensated performance data (operation S1301). In addition to using the plurality of compensated performance data in operation S1301, operation S1301 may be performed with Figure 19 The operation S1300 in is basically the same.

[0211] Reference Figure 23 In the method for calculating the remaining useful life, operation S1100 may be performed with reference to Figure 19 The operations described are essentially the same.

[0212] A plurality of performance data associated with a plurality of performances of a plurality of target memory devices that have been used is measured (operation S1203), and an average remaining useful life of the plurality of target memory devices is obtained based on a lifespan calculation model and the plurality of performance data measured from the plurality of target memory devices (operation S1303). For example, a single remaining useful life may be obtained for a memory device group including the plurality of target memory devices. For example, the plurality of performance data may be averaged, and an average remaining useful life may be obtained based on the average performance data. For example, a plurality of remaining useful lives may be obtained from the plurality of performance data, and the average remaining useful life may be obtained by averaging the plurality of remaining useful lives.

[0213] Reference Figure 24 In the method for calculating the remaining useful life, operation S1100 may be performed with reference to Figure 19 The operations described are essentially the same.

[0214] A plurality of performance data associated with a plurality of performances of a portion of the plurality of target memory devices that have been used is measured (operation S1205), and an average remaining useful life of the plurality of target memory devices is obtained based on the life calculation model and the plurality of performance data measured from the portion of the plurality of target memory devices (operation S1305). In addition to the fact that operations S1205 and S1305 are performed on selected samples from among the plurality of target memory devices, operations S1205 and S1305 may be respectively performed on a plurality of target memory devices. Figure 23 Operations S1203 and S1303 in are basically the same.

[0215] Reference Figure 25 In the method of calculating the remaining service life, the service life calculation model generated by operation S1100 may be loaded (operation S1400), and operations S1200 and S1300 may be performed based on the loaded service life calculation model. In other words, Figure 19 In some embodiments, operation S1100 may be replaced by operation S1400, and the lifetime calculation model that has been generated may be used as in operation S1400, rather than generating the lifetime calculation model each time. Figure 22 、 Figure 23 and Figure 24 substituted by operation S1400 in the example of FIG.

[0216] Example embodiments may be applied to various electronic devices and systems that include memory devices. For example, example embodiments may be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, and automobiles.

[0217] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope of protection that can be claimed, but rather as descriptions of features that can be specific to a particular embodiment of a particular invention. Specific features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable subcombination. Furthermore, although features may be described above as working in a particular combination, one or more features from a combination may be excluded from the combination in some cases, and the combination may involve subcombinations or variations of subcombinations.

[0218] The foregoing is illustrative of example embodiments and should not be construed as limiting the same. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Therefore, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Therefore, it will be understood that the foregoing is illustrative of various example embodiments and should not be construed as limiting the specific example embodiments disclosed, and that modifications of the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A modeling method for estimating the useful life of a memory device, the modeling method being performed by executing program code using at least one processor, the program code being stored in a non-transitory computer-readable medium, the modeling method comprising: obtaining a plurality of performance measurement data based on performing an accelerated aging test on a plurality of unused memory devices, the plurality of performance measurement data being associated with a plurality of properties of the plurality of unused memory devices; calculating a plurality of statistics based on performing statistical distribution approximation on the plurality of performance measurement data; calculating a plurality of conditional probabilities based on a plurality of sample performance data and the plurality of statistical data, the plurality of sample performance data being associated with the plurality of performances; as well as A life calculation model is trained based on the multiple conditional probabilities, the life calculation model being configured to output estimated life data and uncertainty data, the estimated life data corresponding to the multiple sample performance data, the uncertainty data representing uncertainty of the estimated life data.

2. The modeling method according to claim 1, wherein: The step of obtaining the plurality of performance measurement data comprises: obtaining, at a first point in time before the accelerated aging test begins, first performance measurement data associated with the plurality of properties of the plurality of unused memory devices; At a second time point after the first time point, while the accelerated aging test is being performed, obtaining second performance measurement data associated with the plurality of properties of the plurality of unused memory devices; and At a Kth time point after the second time point, while the accelerated aging test is being performed, Kth performance measurement data associated with the plurality of performances of the plurality of unused memory devices is obtained, where K is a positive integer greater than or equal to 3.

3. The modeling method according to claim 2, wherein: The step of obtaining the plurality of performance measurement data comprises: A plurality of estimated usage times of the plurality of unused memory devices is obtained, each of the plurality of estimated usage times corresponding to a respective time point between a first time point and a Kth time point.

4. The modeling method according to claim 3, wherein: The step of obtaining the plurality of estimated usage times comprises: obtaining a first estimated usage time of the plurality of unused memory devices based on a first point in time; obtaining a second estimated usage time of the plurality of unused memory devices based on a second point in time; and A K-th estimated usage time of the plurality of unused memory devices is obtained based on the K-th time point.

5. The modeling method according to claim 2, in, The plurality of performances of the plurality of unused memory devices include first to Lth performances that are different from each other, wherein L is a positive integer greater than or equal to 2, The first performance measurement data includes first-first performance measurement data associated with the first performance to first-Lth performance measurement data associated with the Lth performance, The second performance measurement data includes second-first performance measurement data associated with the first performance to second-Lth performance measurement data associated with the Lth performance, and The Kth performance measurement data includes K-first performance measurement data associated with the first performance to K-Lth performance measurement data associated with the Lth performance.

6. The modeling method according to claim 5, wherein: Each of the first to Lth performances is a performance for input / output timing of the plurality of unused memory devices.

7. The modeling method according to claim 2, wherein: The step of calculating the plurality of statistical data comprises: obtaining first statistical data, the first statistical data comprising a first plurality of means and a first plurality of standard deviations calculated from the first performance measurement data; obtaining second statistical data, the second statistical data comprising a second plurality of means and a second plurality of standard deviations calculated from the second performance measurement data; and A Kth statistical data is obtained, the Kth statistical data including a Kth plurality of means and a Kth plurality of standard deviations calculated from the Kth performance measurement data.

8. The modeling method according to claim 7, wherein: The step of calculating the multiple conditional probabilities includes: obtaining a first conditional probability, wherein in the first conditional probability, based on the plurality of sample performance data being input, a first estimated usage time corresponding to the first performance measurement data and the first statistical data is output; obtaining a second conditional probability, wherein in the second conditional probability, based on the plurality of sample performance data being input, a second estimated usage time corresponding to the second performance measurement data and the second statistical data is output; and A K-th conditional probability is obtained, wherein in the K-th conditional probability, based on the plurality of sample performance data being input, a K-th estimated usage time corresponding to the K-th performance measurement data and the K-th statistical data is output.

9. The modeling method according to claim 1, further comprising: Retrain the lifespan calculation model based on uncertainty data.

10. The modeling method according to claim 9, wherein: The steps to retrain the lifespan calculation model include: comparing the data uncertainty value included in the uncertainty data with the data reference value; providing a plurality of additional sample performance data different from the plurality of sample performance data based on the data uncertainty value being greater than the data reference value; and The life calculation model is retrained based on the plurality of additional sample performance data.

11. The modeling method according to claim 9, wherein: The steps to retrain the lifespan calculation model include: comparing the model uncertainty values included in the uncertainty data with the model reference values; Correcting the life calculation model based on the model uncertainty value being greater than the model reference value; and The corrected lifespan calculation model is retrained based on the plurality of sample performance data.

12. The modeling method according to claim 1, wherein: Each of the plurality of unused memory devices is a dynamic random access memory device or a flash memory device.

13. A method for calculating the remaining useful life of a memory device, the method being performed by executing program code using at least one processor, the program code being stored in a non-transitory computer-readable medium, the method comprising: generating a life calculation model based on a plurality of unused memory devices; measuring a plurality of performance data associated with a plurality of performances of at least one target memory device; as well as obtaining a remaining useful life of the at least one target memory device based on a life calculation model and the plurality of performance data associated with the plurality of performances, The steps of generating a life calculation model include: obtaining a plurality of performance measurement data based on performing an accelerated aging test on the plurality of unused memory devices, the plurality of performance measurement data being associated with the plurality of properties of the plurality of unused memory devices; calculating a plurality of statistics based on performing statistical distribution approximation on the plurality of performance measurement data; calculating a plurality of first conditional probabilities based on a plurality of sample performance data and the plurality of statistical data, the plurality of sample performance data being associated with the plurality of performances; and Based on the multiple first conditional probability training life calculation models, the life calculation model outputs first estimated service life data and first uncertainty data, the first estimated service life data corresponds to the multiple sample performance data, and the first uncertainty data represents the uncertainty of the first estimated service life data.

14. The method of claim 13, wherein: The steps to obtain the remaining useful life include: calculating a plurality of second conditional probabilities based on the plurality of performance data and the plurality of statistical data; obtaining second estimated service life data based on the plurality of second conditional probabilities and the service life calculation model, the second estimated service life data corresponding to the plurality of performance data; and A remaining useful life of the at least one target memory device is calculated based on subtracting a useful life of the at least one target memory device from an initial guaranteed lifespan of the at least one target memory device, the useful life corresponding to the second estimated useful life data.

15. The method according to claim 14, in, obtaining second uncertainty data representing uncertainty of the second estimated useful life data based on the plurality of second conditional probabilities and the life calculation model, and Wherein, second estimated useful life data is selectively retrieved based on the second uncertainty data.

16. The method of claim 13, wherein: The plurality of unused memory devices and the at least one target memory device are memory devices of the same type having the same structure and manufactured by the same process.

17. The method according to claim 16, in, Each of the plurality of unused memory devices is provided as a memory package including two or more memory chips, wherein the at least one target memory device is configured as a memory circuit comprising two or more memory packages, The method further comprises: Compensating the plurality of performance data, and The remaining service life of the at least one target memory device is obtained based on the service life calculation model and the compensated plurality of performance data.

18. The method of claim 13, in, The at least one target memory device includes a plurality of target memory devices, and The average remaining useful lives of the plurality of target memory devices are obtained based on the plurality of performance data measured from the plurality of target memory devices.

19. The method of claim 18, wherein: The plurality of performance data is measured from only a first target memory device among the plurality of target memory devices.

20. A computing system comprising: reliability testing equipment configured to perform accelerated aging testing on the memory device; a performance measurement device configured to measure a plurality of performances of the memory device; at least one processor; as well as A non-transitory computer-readable medium configured to store program code, the program code being executed using the at least one processor to generate a lifespan calculation model for obtaining a remaining useful life of a memory device, Wherein, by executing the program code, the at least one processor is configured to: obtaining, based on a reliability testing device and a performance measurement device, a plurality of performance measurement data associated with the plurality of performances of the plurality of unused memory devices based on performing an accelerated aging test on the plurality of unused memory devices, the memory device and the plurality of unused memory devices being of the same type of memory device; calculating a plurality of statistics based on performing statistical distribution approximation on the plurality of performance measurement data; calculating a plurality of conditional probabilities based on a plurality of sample performance data and the plurality of statistical data, the plurality of sample performance data being associated with the plurality of performances; and A life calculation model is trained based on the multiple conditional probabilities, the life calculation model being configured to output estimated life data and uncertainty data, the estimated life data corresponding to the multiple sample performance data, the uncertainty data representing uncertainty of the estimated life data.

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