On-chip bus system and data receiving method and device

Abstract

The invention provides an on-chip bus system and a data receiving method and device.The on-chip bus system comprises a host end, a slave end and a DBUS, and the host end and the slave end are connected through the DBUS; the host end is used for sending M write data signals to the slave end through a DBUS bus; wherein M is determined based on the data length of target valid data to be transmitted and the bit width of the DBUS; wherein the M write data signals comprise the target valid data; the slave end is used for receiving M data writing signals and acquiring target effective data based on the M data writing signals; all data in the previous (M-1) data writing signals are target valid data, and all or part of data in the Mth data writing signal are target valid data. According to the technical scheme, the number of signal lines of the DBUS is small, and the hardware overhead of the DBUS is small.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to an on-chip bus system and a data receiving method and device. Background Art

[0002] An on-chip bus is a set of buses used for internal chip communication, such as the AXI (Advanced eXtensible Interface) bus. An on-chip bus can be composed of three types: address bus, data bus, and control bus. These buses perform functions such as address signal transmission, data exchange, and operational control. Transmission between a host and a slave over the on-chip bus typically involves five steps: read command, write command, write data, write response, and read data (read response). This on-chip bus has numerous signal lines and complex protocol control timing. This results in high hardware overhead, making it unsuitable for high-bandwidth, low-power, and small-area applications. Summary of the Invention

[0003] The present application provides an on-chip bus system, the on-chip bus system comprising: a host end, a slave end and a DBUS bus, wherein the host end and the slave end are connected via the DBUS bus; The host end is configured to send M write data signals to the slave end via the DBUS bus; wherein M is determined based on the data length of the target valid data to be transmitted and the bit width of the DBUS bus; wherein the M write data signals include the target valid data; The slave end is used to receive M write data signals and obtain target valid data based on the M write data signals; wherein all data in the first M-1 write data signals are target valid data, and all data or part of the data in the Mth write data signal are target valid data.

[0004] The present application provides a data receiving method at a slave end, the method comprising: Receiving M write data signals via a DBUS bus; wherein M is determined based on the data length of target valid data to be transmitted and the bit width of the DBUS bus; wherein the M write data signals include the target valid data; Target valid data is acquired based on the M write data signals; wherein all data in the first M-1 write data signals are target valid data, and all or part of the data in the Mth write data signal are target valid data.

[0005] The present application provides a data receiving device at a slave end, the device comprising: A receiving module, configured to receive M write data signals via a DBUS bus; wherein M is determined based on the data length of target valid data to be transmitted and the bit width of the DBUS bus; wherein the M write data signals include the target valid data; A determination module is used to obtain target valid data based on the M write data signals; wherein all data in the first M-1 write data signals are target valid data, and all or part of the data in the Mth write data signal are target valid data.

[0006] It can be seen from the above technical solution that in the embodiment of the present application, a new type of on-chip bus is designed, called the DBUS bus (i.e., on-chip data bus). The host end and the slave end are connected through the DBUS bus. When transmission is based on the DBUS bus between the host end and the slave end, the DBUS bus has fewer signal lines and the protocol control timing is simple. The hardware overhead of the DBUS bus is small and is suitable for high-bandwidth, low-power consumption, and small-area applications. That is, the DBUS bus has the advantages of high bandwidth, low latency, low power consumption, and small area. In system integration and use, the bus protocol of the DBUS bus is simple and easy to integrate, and is not prone to errors.

[0007] The DBUS bus eliminates the need for a mask flag signal (MASK). This eliminates the need for a mask flag signal, allowing masking to be implemented even without it. This reduces the number of mask flag signals, resulting in fewer signal lines, simpler protocol control timing, and lower hardware overhead. By implementing the mask function without a mask flag signal, the target valid data can be found from among all data (both valid and invalid). For example, if the host transmits M write data signals and the slave receives M write data signals, the slave treats all data in the first M-1 write data signals as valid data and treats all or part of the data in the Mth write data signal as valid data. This allows the slave to identify the target valid data. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic structural diagram of an on-chip bus system in one embodiment of the present application; Figure 2 is a schematic structural diagram of an on-chip bus system in one embodiment of the present application; Figure 3A This is a schematic diagram of the write timing of the DBUS bus in one embodiment of the present application; Figure 3B This is a flow chart of a data writing method in one embodiment of the present application; Figure 3C This is a schematic diagram of a write transmission of a DBUS bus in one embodiment of the present application; Figure 4A This is a schematic diagram of the read timing of the DBUS bus in one embodiment of the present application; Figure 4B It is a flowchart of a data reading method in one embodiment of the present application; Figure 4C This is a schematic diagram of a read transmission of a DBUS bus in one embodiment of the present application; Figure 5 is a schematic structural diagram of an on-chip bus system in one embodiment of the present application; Figure 6 This is a flow chart of a method for receiving data from a slave in one embodiment of the present application; Figure 7 It is a structural diagram of a slave-side data receiving device in one embodiment of the present application. DETAILED DESCRIPTION

[0009] In the embodiment of the present application, an on-chip bus system is proposed. Figure 1 Figure 2 shows a schematic diagram of the structure of an on-chip bus system, which may include a host, a slave, and a DBUS (on-chip data bus) bus. The host and slave are connected via the DBUS bus. The host is configured to send M write data signals to the slave via the DBUS bus. M is determined based on the data length of the target valid data to be transmitted and the bit width of the DBUS bus. The M write data signals include the target valid data. The slave is configured to receive the M write data signals and obtain the target valid data based on the M write data signals. The entire data in the first M-1 write data signals is the target valid data, and the entire data or a portion of the data in the Mth write data signal is the target valid data. Based on this, the slave can use the entire data in the first M-1 write data signals as the target valid data, and the slave can use the entire data or a portion of the data in the Mth write data signal as the target valid data.

[0010] Exemplarily, M is the quotient of the data length of the target valid data and the bit width of the DBUS bus, rounded up, and can be a positive integer. The fact that all or part of the data in the Mth write data signal is the target valid data may include: if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, then all the data in the Mth write data signal may be the target valid data; or, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then N units of data in the Mth write data signal may be the target valid data. The target valid data occupies N units (e.g., N bytes) of the high-order bits of the Mth write data signal, or the target valid data may occupy N units (e.g., N bytes) of the low-order bits of the Mth write data signal.

[0011] Exemplarily, when the slave end obtains the target valid data based on M write data signals, it is specifically used to: determine all the data in the previous M-1 write data signals as the target valid data; generate a mask signal corresponding to the Mth write data signal based on the data length of the target valid data and the bit width of the DBUS bus, and determine all or part of the data in the Mth write data signal as the target valid data based on the mask signal.

[0012] Exemplarily, when the slave end determines all or part of the data in the Mth write data signal as the target valid data based on the mask signal, it is specifically used as follows: if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, then all bits of the mask signal are the first value (such as 1), and a mask operation is performed based on the mask signal and the Mth write data signal to obtain a first post-operation signal, and all data in the first post-operation signal are determined as the target valid data. If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then all bits of the high-order N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value. A mask operation is performed based on the mask signal and the Mth write data signal to obtain a second calculated signal, and the high-order N bytes in the second calculated signal are determined as the target valid data; or, all bits of the low-order N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value. A mask operation is performed based on the mask signal and the Mth write data signal to obtain a third calculated signal, and the low-order N bytes in the third calculated signal are determined as the target valid data.

[0013] Exemplarily, the slave end is further used to obtain the data length of the configured target valid data; wherein, if the target valid data includes a line of image data of the image to be transmitted, the data length is the length corresponding to a line of image data; if the target valid data includes multiple lines of image data of the image to be transmitted, the data length is the length corresponding to the multiple lines of image data; if the target valid data includes all image data of the image to be transmitted, the data length is the length corresponding to the image to be transmitted; or, the slave end is further used to receive a length signal sent by the host end through the DBUS bus, and determine the data length of the target valid data based on the length signal; wherein, the length signal can represent the data length of the target valid data.

[0014] Exemplarily, the slave side is configured to send a write-ready signal to the host side via the DBUS bus. The write-ready signal may indicate that the slave side allows or does not allow the reception of write data signals. The host side is configured to send a write-valid signal to the slave side via the DBUS bus. The write-valid signal may indicate that the host side allows or does not allow the transmission of write data signals. The host side is configured to send M write data signals to the slave side via the DBUS bus when the write-ready signal indicates that the slave side allows the reception of write data signals and the write-valid signal indicates that the host side allows the transmission of write data signals.

[0015] Exemplarily, the host side is used to send a read ready signal to the slave side through the DBUS bus, and the read ready signal indicates that the host side allows receiving the read data signal or does not allow receiving the read data signal; the slave side is used to send a read valid signal to the host side through the DBUS bus, and the read valid signal indicates that the slave side allows sending the read data signal or does not allow sending the read data signal; the host side is used to receive the read data signal sent by the slave side through the DBUS bus when the read ready signal indicates that the host side allows receiving the read data signal and the read valid signal indicates that the slave side allows sending the read data signal, and the read data signal includes valid data to be read.

[0016] Exemplarily, the host side is used to send a read / write flag signal, a length signal and a starting address signal to the slave side via the DBUS bus; wherein the read / write flag signal indicates that a write data signal or a read data signal is transmitted via the DBUS bus; if the read / write flag signal indicates that a write data signal is transmitted via the DBUS bus, the length signal indicates the length of the target valid data, and the starting address signal indicates the starting address of the target valid data; if the read / write flag signal indicates that a read data signal is transmitted via the DBUS bus, the length signal indicates the length of the valid data to be read, and the starting address signal indicates the starting address of the valid data to be read.

[0017] Exemplarily, the host side is used to send a request signal to the slave side through the DBUS bus until it receives a response signal returned by the slave side, and then the host side can stop sending the request signal to the slave side through the DBUS bus; the slave side is used to send a response signal to the host side through the DBUS bus when it receives a request signal through the DBUS bus and if the slave side is in an idle state.

[0018] For example, see Figure 2 Figure 1 is a schematic diagram of the structure of the on-chip bus system. The on-chip bus system may also include an arbiter. The host and the arbiter are connected via a DBUS bus, and the arbiter and the slave are also connected via the DBUS bus. The host is configured to send M write data signals to the arbiter via the DBUS bus; the arbiter is configured to send M write data signals to the slave via the DBUS bus.

[0019] Exemplarily, the slave end is used to send a write ready signal to the arbitrator via the DBUS bus; the arbitrator is used to send a write ready signal to the host end via the DBUS bus; the host end is used to send a write valid signal to the arbitrator via the DBUS bus; the arbitrator is used to send a write valid signal to the slave end via the DBUS bus; the host end is used to send M write data signals to the arbitrator via the DBUS bus when the write ready signal indicates that the slave end is allowed to receive the write data signal and the write valid signal indicates that the host end is allowed to send the write data signal; the arbitrator is used to send M write data signals to the slave end via the DBUS bus.

[0020] Alternatively, the host side is used to send a read ready signal to the arbitrator via the DBUS bus; the arbitrator is used to send a read ready signal to the slave side via the DBUS bus; the slave side is used to send a read valid signal to the arbitrator via the DBUS bus; the arbitrator is used to send a read valid signal to the host side via the DBUS bus; the slave side is used to send a read data signal to the arbitrator via the DBUS bus when the read ready signal indicates that the host side allows receiving the read data signal and the read valid signal indicates that the slave side allows sending the read data signal; the arbitrator is used to send a read data signal to the host side via the DBUS bus.

[0021] For example, taking the target valid data as image data, the target valid data may include a row of image data of the image to be transmitted, or the target valid data may include multiple rows of image data of the image to be transmitted, or the target valid data may include all image data of the image to be transmitted.

[0022] It can be seen from the above technical solution that in the embodiment of the present application, a new type of on-chip bus is designed, called the DBUS bus (i.e., on-chip data bus). The host end and the slave end are connected through the DBUS bus. When transmission is based on the DBUS bus between the host end and the slave end, the DBUS bus has fewer signal lines and the protocol control timing is simple. The hardware overhead of the DBUS bus is small and is suitable for high-bandwidth, low-power consumption, and small-area applications. That is, the DBUS bus has the advantages of high bandwidth, low latency, low power consumption, and small area. In system integration and use, the bus protocol of the DBUS bus is simple and easy to integrate, and is not prone to errors.

[0023] The DBUS bus eliminates the need for a mask flag signal (MASK). This eliminates the need for a mask flag signal, allowing masking to be implemented even without it. This reduces the number of mask flag signals, resulting in fewer signal lines, simpler protocol control timing, and lower hardware overhead. By implementing the mask function without a mask flag signal, the target valid data can be found from among all data (both valid and invalid). For example, if the host transmits M write data signals and the slave receives M write data signals, the slave treats all data in the first M-1 write data signals as valid data and treats all or part of the data in the Mth write data signal as valid data. This allows the slave to identify the target valid data.

[0024] The above technical solutions of the embodiments of the present application are described below in conjunction with specific application scenarios.

[0025] On-chip buses are a set of buses used for internal chip communication, such as the AXI bus, AHB (Advanced High-Performance Bus), and APB (Advanced Peripheral Bus). AHB and APB are not suitable for high-throughput data transmission scenarios, while the AXI bus is a relatively mainstream high-speed bus protocol. Transmission between a host and a slave over the AXI bus typically involves five steps: read command, write command, write data, write response, and read data (read response). The AXI bus has numerous signal lines and complex protocol control timing. This results in high hardware overhead, making it unsuitable for high-bandwidth, low-power, and small-area applications.

[0026] In response to the above findings, a new on-chip bus is designed in the embodiments of the present application. The new on-chip bus is called a DBUS bus (i.e., an on-chip data bus), and the host end and the slave end are connected via the DBUS bus.

[0027] The DBUS bus is suitable for applications involving continuous data, meaning that all data is valid and there is no invalid data. For example, in image processing scenarios (such as infrared image processing), the host needs to send image data to the slave. All image data is valid, meaning there is no invalid data in the image data (invalid data means that certain bytes are invalid, such as in CPU instruction or data fetching scenarios). Another example is a data packet transmission scenario where the host needs to send a network data packet to the slave. All data in the network data packet is valid, meaning there is no invalid data in the network data packet. Of course, the above are just examples and are not limiting, as long as all data is valid.

[0028] In this embodiment, the host side can be a CPU (Central Processing Unit), and the slave side can be a DRAM (Dynamic Random Access Memory). The host side can be a CPU, and the slave side can be a DMA (Direct Memory Access) controller. The host side can be a CPU, and the slave side can be a Flash memory. Of course, the above are just a few examples, and there is no limitation on the host and slave sides, as long as the host and slave sides are located on-chip.

[0029] In this embodiment, a DBUS bus is provided between the host and the slave. The host and the slave can be connected via the DBUS bus. Table 1 shows an example of a write operation signal for the DBUS bus, and Table 2 shows an example of a read operation signal for the DBUS bus. In subsequent processes, write and read operations can be performed independently. For example, only write operations can be performed, only read operations can be performed, or both write and read operations can be performed simultaneously.

[0030] Table 1

[0031] Table 2

[0032] In Tables 1 and 2, dbus_addr (starting address signal), dbus_lens (length signal), and dbus_wren (read / write flag signal) can represent command information. This command information can include starting address information, data length information (in bytes or bits), and read / write flag information. The read / write flag information can indicate whether a write data signal or a read data signal is being transmitted via the DBUS bus. For example, if dbus_wren is at a first level, it indicates that write data is being transmitted via the DBUS bus. If dbus_wren is at a second level, it indicates that read data is being transmitted via the DBUS bus. The first level can be high, the second level can be low, or both.

[0033] dbus_wrdy (write ready signal), dbus_wvld (write valid signal), and dbus_wdata (write data signal) can represent write data information. If dbus_wren is at level 1, this write data information is transmitted over the DBUS bus. dbus_wrdy and dbus_wvld represent the handshake signals for write data, while dbus_wdata represents the actual write data. It's important to note that the write data information does not include the write data mask signal, meaning that the DBUS bus saves multiple bits of mask flag signal lines.

[0034] dbus_rrdy (read ready signal), dbus_rvld (read valid signal), and dbus_rdata (read data signal) can be read data information. If dbus_wren is at the second level, these read data information can be transmitted over the DBUS bus. In the read data information, dbus_rrdy and dbus_rvld can represent the handshake signals for read data, and dbus_rdata can represent the read data, that is, the data that actually needs to be read.

[0035] In summary, the DBUS bus consists of three parts: command information, write data information, and read data information. Compared to the AXI bus, which involves five parts: read command, write command, write data, write response, and read data (read response), the DBUS bus has fewer signal lines and a simpler protocol control sequence. This results in lower hardware overhead, a simpler bus protocol, and ease of integration.

[0036] As shown in Tables 1 and 2, before transmitting write and read data, the host can also send a dbus_req (request signal) to the slave. After receiving the dbus_req, the slave can also send a dbus_ack (response signal) to the host. The dbus_req and dbus_ack handshake ensures the transmission of write and read data. For example, the host will only send write data to the slave after receiving the dbus_ack, and vice versa. Conversely, the host will not send write data to the slave before receiving the dbus_ack, nor will it send read data to the slave before receiving the dbus_ack.

[0037] The DBUS bus uses dbus_req and dbus_ack for handshake. The handshake process is not prone to errors. During the handshake process, the host actively initiates dbus_req, and the host does not need to consider the current status of the slave when initiating dbus_req. The slave only needs to make a reasonable response according to dbus_req.

[0038] For the data writing process, see Figure 3A As shown in FIG, a DBUS bus write timing diagram is shown. In combination with the DBUS bus write timing, a data writing method based on the DBUS bus is proposed in the embodiment of the present application. Figure 3B FIG. 1 is a flow chart of the data writing method, which may include: Step 301: The host sends a request signal (dbus_req) to the slave via the DBUS bus.

[0039] Step 302: When the slave receives the request signal through the DBUS bus, if the slave is in an idle state, the slave sends a response signal (dbus_ack) to the host through the DBUS bus.

[0040] For example, before the host writes data to the slave, the host may send a request signal to the slave via the DBUS bus. The host stops sending the request signal to the slave via the DBUS bus until it receives a response signal from the slave. Before receiving a response signal from the slave, the host continues sending the request signal to the slave via the DBUS bus. Figure 3A As shown in the figure, taking the request signal being valid at a high level as an example (the request signal can also be valid at a low level), the host side continues to send the request signal (dbus_req is high level) from time 4 until time 7, when the host side receives the response signal returned by the slave side (the response signal is a pulse signal, and dbus_ack is high level from time 7 to time 8). Thus, starting from time 8, the host side stops sending the request signal (dbus_req is low level).

[0041] For example, when a slave receives a request signal via the DBUS bus and is in an idle state, it can send a response signal to the master via the DBUS bus. For example, if the response signal is active high (the response signal can also be active low), the slave begins sending the response signal at time 7 (dbus_ack is high). This response signal can be a pulse signal, meaning it only lasts for one moment, corresponding to time 7 to time 8. The response signal can also last for multiple moments, without limitation. Starting at time 8, the slave stops sending the response signal (dbus_ack is low).

[0042] When a slave receives a request signal via the DBUS bus, if it is busy, it will not send a response signal to the host via the DBUS bus until it is idle. For example, an idle slave means it is not currently processing any tasks and can handle the current write task to write data. A busy slave means it is currently processing tasks and cannot handle the current write task.

[0043] Exemplarily, the bit width of the request signal can be 1 bit or multiple bits, or 1 byte or multiple bytes, and there is no restriction on the bit width of the request signal. The bit width of the response signal can be 1 bit or multiple bits, or 1 byte or multiple bytes, and there is no restriction on the bit width of the response signal.

[0044] Step 303: The host sends a read / write flag signal (dbus_wren) to the slave via the DBUS bus.

[0045] Exemplarily, the read / write flag signal indicates that a write data signal or a read data signal is transmitted via the DBUS bus. For example, for a write data process, the read / write flag signal indicates that a write data signal is transmitted via the DBUS bus, and for a read data process, the read / write flag signal indicates that a read data signal is transmitted via the DBUS bus.

[0046] For example, if the read / write flag signal is at the first level, it indicates that a write data signal is transmitted via the DBUS bus. If the read / write flag signal is at the second level, it indicates that a read data signal is transmitted via the DBUS bus. The first level can be a high level, and the second level can be a low level, or the first level can be a low level, and the second level can be a high level. In this embodiment, the data is written. Therefore, the read / write flag signal is at the first level. Figure 3A In the example, the first level is a low level, that is, the read / write flag signal can be valid at a low level to indicate that the write data signal is transmitted through the DBUS bus.

[0047] For example, after the host sends a request signal to the slave via the DBUS bus, it can send a read / write flag signal to the slave via the DBUS bus, i.e. the read / write flag signal is low starting from time 4. Of course, the host can also send a read / write flag signal to the slave via the DBUS bus after receiving a response signal, i.e. the read / write flag signal is low starting from time 8. Figure 3A In the process, the read / write flag signal is always at a low level, and the read / write flag signal starting at time 4 indicates the transmission of the write data signal.

[0048] Illustratively, the bit width of the read / write flag signal may be 1 bit or multiple bits, or 1 byte or multiple bytes. This embodiment does not impose any limitation on the bit width of the read / write flag signal.

[0049] Step 304: The host sends a length signal (dbus_lens) to the slave via the DBUS bus.

[0050] For example, if the read / write flag signal indicates that the write data signal is transmitted via the DBUS bus, the length signal can indicate the length of the target valid data. The content of the target valid data can be found in the subsequent embodiments. For example, after the host sends a request signal to the slave via the DBUS bus, it can send a length signal to the slave via the DBUS bus, that is, the length signal starts transmitting the length of the target valid data (denoted as burst_lens) from time 4. Of course, the host can also send a length signal to the slave via the DBUS bus after receiving the response signal, that is, the length signal starts transmitting the length of the target valid data from time 8. Figure 3A In the example, the host starts transmitting the length of the target valid data from time 4.

[0051] When the length signal starts transmitting the length of the target valid data from time 4, the length of the target valid data transmitted by the host side cannot be changed before receiving the response signal to avoid transmission abnormality. After receiving the response signal, the host side can retransmit the length of the target valid data, that is, the length of the target valid data can be changed. In addition, when the length signal starts transmitting the length of the target valid data from time 8, the length of the target valid data transmitted by the host side can be changed.

[0052] When transmitting the length of target valid data, the length of the target valid data may be expressed in bytes, bits, or other units without limitation.

[0053] For example, the bit width of the length signal is related to the length of the target valid data. The bit width of the length signal can be denoted as LW. The bit width LW is a parameter related to the length of the target valid data. As long as the length of the target valid data can be represented by the length signal, there is no restriction on the bit width of the length signal. For example, the bit width of the length signal supports parameterizable configuration, that is, the bit width of the length signal can be configured.

[0054] Step 305: The host sends a start address signal (dbus_addr) to the slave via the DBUS bus.

[0055] For example, if the read / write flag signal indicates that the write data signal is transmitted via the DBUS bus, the start address signal indicates the start address of the target valid data. For example, after the host sends a request signal to the slave via the DBUS bus, it can send a start address signal to the slave via the DBUS bus, that is, the start address signal starts transmitting the start address of the target valid data from time 4 (recorded as start_addr). Of course, the host can also send a start address signal to the slave via the DBUS bus only after receiving a response signal, that is, the start address signal starts transmitting the start address of the target valid data from time 8. Figure 3A In the example, the host starts transmitting the starting address of the target valid data from time 4.

[0056] When the start address signal begins transmitting the start address of the target valid data at time 4, the start address of the target valid data transmitted by the host side cannot be changed before receiving the response signal to avoid transmission abnormalities. After receiving the response signal, the host side can retransmit the start address of the target valid data, that is, the start address can be changed. When the start address signal begins transmitting the start address of the target valid data at time 8, the start address of the target valid data transmitted by the host side can be changed.

[0057] For example, the bit width of the start address signal is related to the start address of the target valid data. The bit width of the start address signal can be denoted as AW. The bit width AW is a parameter related to the start address of the target valid data. As long as the start address can be represented by the start address signal, there is no restriction on the bit width. For example, the bit width of the start address signal supports parameterizable configuration, that is, the bit width can be configured.

[0058] Step 306: The host sends a write-valid signal (dbus_wvld) to the slave via the DBUS bus. The write-valid signal may indicate that the host allows or does not allow the sending of a write data signal.

[0059] For example, after the host sends a request signal to the slave through the DBUS bus, it can send a write-valid signal to the slave through the DBUS bus. For example, if the write-valid signal is high-level valid (the write-valid signal can also be low-level valid), the write-valid signal is high-level starting from moment 4 (the write-valid signal can be high-level at any time after moment 4). Of course, the host can also send a write-valid signal to the slave through the DBUS bus only after receiving the response signal, that is, the write-valid signal is high-level starting from moment 8 (the write-valid signal can be high-level at any time after moment 8). Figure 3AIn the example, the write-valid signal is at a high level starting from time 9 (this time 9 is just an example). In this way, the write-valid signal can indicate that the host side allows sending the write data signal starting from time 9. Before time 9, the write-valid signal can indicate that the host side does not allow sending the write data signal.

[0060] Illustratively, the bit width of the write-valid signal may be 1 bit or multiple bits, or 1 byte or multiple bytes. This embodiment does not impose any limitation on the bit width of the write-valid signal.

[0061] Step 307: The slave sends a write ready signal (dbus_wrdy) to the host via the DBUS bus. The write ready signal may indicate whether the slave allows or does not allow the slave to receive a write data signal.

[0062] For example, after receiving the request signal through the DBUS bus, the slave end can send a write ready signal to the host end through the DBUS bus. Taking the write ready signal as being valid at a high level as an example (the write ready signal can also be valid at a low level), the write ready signal is high starting from time 4 (the write ready signal is high at any time after time 4). After sending a response signal to the host end, the slave end can send a write ready signal to the host end through the DBUS bus, that is, the write ready signal is high starting from time 8 (the write ready signal is high at any time after time 8). Figure 3A In the write-ready state, the write-ready signal is always at a high level, that is, the write-ready signal indicates that the slave end is always allowed to receive write data signals.

[0063] Illustratively, the bit width of the write ready signal may be 1 bit or multiple bits, or 1 byte or multiple bytes. This embodiment does not impose any limitation on the bit width of the write ready signal.

[0064] Step 308: When the write ready signal indicates that the slave is allowed to receive write data signals and the write valid signal indicates that the host is allowed to send write data signals, the host sends a write data signal (dbus_wdata) to the slave via the DBUS bus. The write data signal may include target valid data.

[0065] For example, the host will not send a write data signal to the slave via the DBUS bus before receiving a response signal (dbus_ack). After receiving the response signal, the host can send a write data signal to the slave via the DBUS bus, i.e., the response signal indicates permission to send the write data signal.

[0066] After receiving the response signal, the host can query the write-ready signal and the write-valid signal. If the write-ready signal indicates that the slave is allowed to receive write data signals (e.g., the write-ready signal is high), and the write-valid signal indicates that the host is allowed to send write data signals (e.g., the write-valid signal is high), the host sends the write data signal to the slave via the DBUS bus. If the write-ready signal indicates that the slave is not allowed to receive write data signals, and / or the write-valid signal indicates that the host is not allowed to send write data signals, the host will not send the write data signal to the slave via the DBUS bus until the write-ready signal indicates that the slave is allowed to receive write data signals, and the write-valid signal indicates that the host is allowed to send write data signals.

[0067] See also Figure 3A As shown in the figure, the write ready signal is always at a high level, that is, the write ready signal indicates that the slave end is always allowed to receive the write data signal, and the write valid signal is high from time 9, that is, the write valid signal indicates that the host end is allowed to send the write data signal from time 9. On this basis, the host end sends the write data signal to the slave end through the DBUS bus from time 9 (or a certain time after time 9).

[0068] For example, the bit width of the write data signal is related to the actual length of the target valid data. The bit width of the write data signal can be denoted as DW. The bit width DW is a parameter related to the actual length of the target valid data. As long as the write data signal can carry the target valid data, there is no restriction on the bit width DW. For example, the bit width of the write data signal supports parameterized configuration, that is, the bit width can be configured.

[0069] In one possible implementation, the valid data to be transmitted is referred to as target valid data. Target valid data is continuous data, meaning that all data within the target valid data is valid data. For example, in an image processing scenario (such as infrared image processing), a host needs to send image data to a slave. All image data is valid data, and the target valid data can include the image data. Another example is a data packet transmission scenario where a host needs to send a network data packet to a slave. All data in the network data packet is valid data, and the target valid data can include the network data packet.

[0070] For example, if the target valid data is image data, the target valid data may include one row of image data for the image to be transmitted. For example, the host obtains the first row of image data for the image to be transmitted and sends a write data signal to the slave via the DBUS bus. This write data signal may include the first row of image data. Then, the host obtains the second row of image data for the image to be transmitted and sends a write data signal to the slave via the DBUS bus. This write data signal may include the second row of image data. This process continues until all rows of image data for the image to be transmitted have been sent to the slave via the DBUS bus, completing the transmission of the image to be transmitted.

[0071] Alternatively, the target valid data may include multiple lines of image data for the image to be transmitted. For example, taking five lines of image data as an example, the host side obtains the image data for lines 1-5 of the image to be transmitted and sends a write data signal to the slave side via the DBUS bus. The write data signal may include the image data for lines 1-5. Then, the host side obtains the image data for lines 6-10 of the image to be transmitted and sends a write data signal to the slave side via the DBUS bus. The write data signal may include the image data for lines 6-10, and so on.

[0072] Alternatively, the target valid data may include all image data of the image to be transmitted. For example, the host side obtains the image data of all rows of the image to be transmitted and sends a write data signal to the slave side through the DBUS bus. The write data signal may include the image data of all rows of the image to be transmitted.

[0073] For the convenience of description, it is taken as an example that the target valid data includes a line of image data of the image to be transmitted.

[0074] It's important to note that when the master sends a write data signal to the slave, the actual transmitted data will completely include the target valid data. However, the length of the actual transmitted data is related to the bit width of the write data signal and must be an integer multiple of the bit width of the write data signal. Therefore, if the length of the target valid data is an integer multiple of the bit width of the write data signal, the actual transmitted data will only include the target valid data. If the length of the target valid data is not an integer multiple of the bit width of the write data signal, the actual transmitted data will include the target valid data and some invalid data, and the length of the actual transmitted data will be an integer multiple of the bit width of the write data signal.

[0075] On this basis, the number of cycles M can be determined based on the data length of the target valid data and the bit width of the DBUS bus, indicating that the host side needs to send the target valid data through M clock cycles. In each clock cycle, data of one bit width (the bit width of the DBUS bus) can be sent, and M bit widths of data are sent through M clock cycles (the M bit widths of data represent the actual transmission data, that is, the length of the actual transmission data is M times the bit width of the write data signal. If the length of the target valid data is exactly M bit widths, the actual transmission data only includes the target valid data. If the length of the target valid data is not M bit widths, the actual transmission data includes the target valid data and some invalid data). Among them, M is the quotient of the data length of the target valid data and the bit width of the DBUS bus rounded up, and M can be a positive integer.

[0076] For example, in the field of image processing, image data can be transmitted row by row. Therefore, by splitting the data at the row granularity, the image data of one row of the image to be transmitted can be obtained as the target valid data. Assuming that the data length of the target valid data is 30 bytes (i.e., the length signal (dbus_lens) represents 30 bytes), and the bit width of the DBUS bus is set to 32 bits (i.e., 4 bytes), then the quotient of the data length of the target valid data and the bit width of the DBUS bus (30 / 4) is rounded up to obtain the number of cycles M of 8, that is, the host sends 8-bit wide data through 8 clock cycles.

[0077] For example, when the host sends a write data signal to the slave via the DBUS bus, M write data signals may be sent to the slave via the DBUS bus. These M write data signals then carry target valid data. For example, within a total of 8 clock cycles, the host sends 8 write data signals to the slave. For the M write data signals, all data in the first M-1 write data signals are valid data, and all or part of the data in the Mth write data signal are valid data.

[0078] For example, in the first clock cycle, the host sends write data signal 1 to the slave via the DBUS bus. All data in write data signal 1 is valid data. For example, if the target valid data includes 30 bytes of image data, write data signal 1 includes bytes 1-4 of image data. In the second clock cycle, the host sends write data signal 2 to the slave via the DBUS bus. All data in write data signal 2 is valid data. For example, if write data signal 2 includes bytes 5-8 of image data. Similarly, in the seventh clock cycle, the host sends write data signal 7 to the slave via the DBUS bus. All data in write data signal 7 is valid data. For example, if write data signal 7 includes bytes 25-28 of image data. In summary, all data in the first seven write data signals is valid data.

[0079] For example, for the Mth write data signal, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, then all data in the Mth write data signal is valid data. If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then N units (e.g., N bytes) of data in the Mth write data signal are valid data, and the remaining data is invalid data.

[0080] For example, in image processing, image data can be transmitted row by row. Therefore, when splitting data at row granularity, the total data size of a row (the target valid data length) has only two possible values during transmission: one is exactly divisible by the DBUS bus width, and the other is not. These two conditions only occur in the last DBUS data being transmitted; the remaining DBUS data is all valid data. Therefore, all data in the first M-1 write data signals is valid data, and all or part of the data in the Mth write data signal is valid data.

[0081] For example, during the 8th clock cycle, the host sends write data signal 8 to the slave via the DBUS bus. If the target valid data includes 32 bytes of image data, then all data in write data signal 8 is valid data, e.g., write data signal 8 includes bytes 29-32 of image data. In this example, the target valid data includes 30 bytes of image data, so part of the data in write data signal 8 is valid data, i.e., write data signal 8 includes bytes 29-30 of image data. Considering that write data signal 8 needs to carry 4 bytes of data, the remaining two bytes are padded with invalid data.

[0082] To summarize, if the remainder of the target valid data length (30) divided by the DBUS bus bit width (4) is 2, then the N (2) bytes of data in write data signal 8 are valid data, and the remaining 2 bytes (the difference between the DBUS bus bit width and N bytes) are invalid data. Within write data signal 8, the target valid data can occupy the lower N (2) bytes, and invalid data can occupy the upper 2 bytes. Alternatively, the target valid data can occupy the upper 2 bytes, and invalid data can occupy the lower 2 bytes. In this embodiment, the target valid data occupies the lower 2 bytes as an example.

[0083] To sum up, the host side can send M write data signals to the slave side through the DBUS bus, and the M write data signals carry the target valid data. All the data in the first M-1 write data signals are valid data, and all or part of the data in the Mth write data signal is valid data.

[0084] Step 309: The slave receives M write data signals via the DBUS bus and obtains target valid data based on the M write data signals, wherein all data in the first M-1 write data signals are valid data, and all or part of the data in the Mth write data signal is valid data.

[0085] Exemplarily, before the slave end sends a response signal to the host end, it will not receive the write data signal through the DBUS bus. After the slave end sends the response signal to the host end, it can receive the write data signal through the DBUS bus. For example, the slave end queries the write-ready signal and the write-valid signal. If the write-ready signal indicates that the slave end is allowed to receive the write data signal, and the write-valid signal indicates that the host end is allowed to send the write data signal, the slave end receives the write data signal through the DBUS bus. If the write-ready signal indicates that the slave end is not allowed to receive the write data signal, and / or the write-valid signal indicates that the host end is not allowed to send the write data signal, the slave end will not receive the write data signal through the DBUS bus until the write-ready signal indicates that the slave end is allowed to receive the write data signal, and the write-valid signal indicates that the host end is allowed to send the write data signal.

[0086] Exemplarily, when the slave receives a length signal via the DBUS bus, the data length of the target valid data can be determined based on the length signal, and the slave knows the bit width of the DBUS bus. In this way, the slave can determine the number of cycles M based on the data length of the target valid data and the bit width of the DBUS bus. Alternatively, the slave can obtain the data length of the configured target valid data, that is, obtain the data length of the target valid data based on the configuration information. In this way, there is no need to transmit the length signal via the DBUS bus, thereby saving the length signal and further reducing the number of signal lines on the DBUS bus. When configuring the data length of the target valid data, taking the image to be transmitted as an example, if the target valid data includes a line of image data of the image to be transmitted, the data length is the length corresponding to a line of image data; if the target valid data includes multiple lines of image data of the image to be transmitted, the data length is the length corresponding to the multiple lines of image data; if the target valid data includes all image data of the image to be transmitted, the data length is the length corresponding to the image to be transmitted.

[0087] Based on this, after obtaining the number of cycles M, for the first write data signal received by the slave, all data (e.g., 4 bytes) in the write data signal is used as the target valid data. For the second write data signal received by the slave, all data in the write data signal is used as the target valid data. Similarly, for the M-1th write data signal received by the slave, all data in the write data signal is used as the target valid data. In summary, it can be seen that all data in the first M-1 write data signals is valid data.

[0088] Exemplarily, the slave end can also calculate the remainder of the data length of the target valid data divided by the bit width of the DBUS bus. If the remainder is 0, for the Mth write data signal received by the slave end, all the data in the write data signal are used as the target valid data. If the remainder is not 0, such as the remainder is N, for the Mth write data signal received by the slave end, the N bytes of data in the write data signal are used as the target valid data. For example, the low-order N bytes of data in the write data signal are used as the target valid data, or the high-order N bytes of data in the write data signal are used as the target valid data. Whether the low-order N bytes or the high-order N bytes are used as the target valid data can be configured on the host end and the slave end. In summary, it can be seen that all or part of the data in the Mth write data signal is valid data.

[0089] In one possible implementation, for the Mth write data signal, the slave end can determine the target valid data by generating a mask signal. It should be noted that the mask signal here is generated by the slave end itself through an algorithm, rather than the host end sending the mask signal to the slave end. In this way, even if the DBUS bus does not support the mask signal, the slave end can calculate the mask signal by itself to complete the mask function.

[0090] For example, the slave end determines all the data in the previous M-1 write data signals as the target valid data; the slave end generates a mask signal corresponding to the Mth write data signal based on the data length of the target valid data and the bit width of the DBUS bus (that is, the slave end itself calculates the mask signal), and determines all or part of the data in the Mth write data signal as the target valid data based on the mask signal.

[0091] For example, if the remainder of the target valid data length divided by the DBUS bus bit width is 0, all bits of the mask signal are assigned the first value (e.g., 1). A mask operation is performed on the mask signal and the Mth write data signal to obtain the first calculated signal. Since all bits of the mask signal are assigned the first value, all bits of the first calculated signal are valid data. Therefore, all data in the first calculated signal can be determined as the target valid data. Since all bits of the first calculated signal are identical to all bits of the Mth write data signal, all data in the Mth write data signal is determined as the target valid data.

[0092] For example, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then all bits of the high-order N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value. A mask operation is performed based on the mask signal and the Mth write data signal to obtain the second signal after operation.

[0093] Since all bits of the upper N bytes of the mask signal have the first value, all bits of the upper N bytes of the second calculated signal are valid data. Therefore, the upper N bytes of the second calculated signal can be determined as the target valid data. Since all bits of the upper N bytes of the second calculated signal are identical to all bits of the upper N bytes of the Mth write data signal, the upper N bytes of the Mth write data signal can be determined as the target valid data.

[0094] For example, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then all bits of the low-order N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value. A mask operation is performed based on the mask signal and the Mth write data signal to obtain a third signal after operation.

[0095] Since all bits of the lower N bytes of the mask signal have the first value, all bits of the lower N bytes of the third calculated signal are valid data. Therefore, the lower N bytes of the third calculated signal can be determined as the target valid data. Since all bits of the lower N bytes of the third calculated signal are identical to all bits of the lower N bytes of the Mth write data signal, the lower N bytes of the Mth write data signal can be determined as the target valid data.

[0096] In summary, the slave acquires target valid data based on M write data signals. The target valid data includes all data in the preceding M-1 write data signals, and the target valid data includes all or part of the data in the Mth write data signal. Furthermore, based on the starting address of the target valid data transmitted by the start address signal, the slave can store the target valid data, completing the data write process.

[0097] In this embodiment, although the DBUS bus does not have a mask flag signal (MASK), the DBUS bus still has a masking function. For example, for the 4 bytes of data transmitted in the Mth (e.g., the 8th) clock cycle, when the slave receives the Mth write data signal, it calculates the total number of received bytes (e.g., 8*4=32 bytes, i.e., a total of 32 bytes are received in 8 clock cycles) and compares the total number of received bytes with the data length of the target valid data (dbus_sizes). If the total number of received bytes is equal to dbus_sizes, there is no need to mask the data in the Mth write data signal, and all data in the Mth write data signal is valid data. If the total number of received bytes is greater than dbus_sizes, it means that the extra bytes are invalid data, and the data in the Mth write data signal needs to be masked, such as masking the upper 2 bytes in the Mth write data signal, so that correct data transmission can be achieved.

[0098] In summary, given the data continuity of image processing algorithms, the DBUS bus does not require a mask flag signal (MASK). Instead, the bus's internal logic performs a calculation to obtain the mask flag for the Mth write data signal. The calculation principle is: divide the amount of data in a row of the image (the data length of the target valid data) by the bus data bit width to determine whether the result is divisible. If it is divisible, all data in that row is valid. If not, the mask of the last data entry is marked as valid or invalid based on the remainder. Since the bus bit width is a multiple of 2, division can be simply performed using a shift method, which conveniently calculates the remainder of the target valid data length divided by the DBUS bus bit width.

[0099] For example, see Figure 3CFigure 2 shows a schematic diagram of a DBUS bus write transmission. The host can send address signals (such as a starting address signal) and control command signals (such as read / write flag signals and length signals) to the slave. After the address and control command signals are received by the slave, the host can send multiple write data signals to the slave. These write data signals carry the write data (such as write data D0, write data D1, write data D2, write data D3, write data D4, and write data D5), completing the data write process.

[0100] For the data reading process, see Figure 4A As shown in FIG. 1 , a DBUS bus read timing diagram is shown. In combination with the DBUS bus read timing diagram, a method for reading data based on the DBUS bus is proposed in the embodiment of the present application. Figure 4B FIG. 1 is a flow chart of the data reading method, which may include: Step 401: The host sends a request signal (dbus_req) to the slave via the DBUS bus.

[0101] Step 402: When the slave receives the request signal through the DBUS bus, if the slave is in an idle state, the slave sends a response signal (dbus_ack) to the host through the DBUS bus.

[0102] Step 403: The host sends a read / write flag signal (dbus_wren) to the slave via the DBUS bus.

[0103] For example, the read / write flag signal indicates that a write data signal or a read data signal is transmitted via the DBUS bus. For the data reading process, the read / write flag signal indicates that a read data signal is transmitted via the DBUS bus. For example, if the read / write flag signal is at the second level, it indicates that a read data signal is transmitted via the DBUS bus. The second level can be a low level or a high level. Figure 3A In the example, the second level is a high level, that is, the read / write flag signal can be valid at a high level to indicate that the read data signal is transmitted through the DBUS bus.

[0104] For example, after the host sends a request signal to the slave via the DBUS bus, it can then send a read / write flag signal to the slave via the DBUS bus, i.e., the read / write flag signal is high starting at time 4. Of course, the host can also send a read / write flag signal to the slave via the DBUS bus only after receiving a response signal, i.e., the read / write flag signal is high starting at time 8.

[0105] Step 404: The host sends a length signal (dbus_lens) to the slave via the DBUS bus.

[0106] For example, if the read / write flag signal indicates that a read data signal is transmitted via the DBUS bus, the length signal indicates the length of the valid data to be read (in Figure 4A denoted as burst_lens in the figure).

[0107] Step 405: The host sends a start address signal (dbus_addr) to the slave via the DBUS bus.

[0108] For example, if the read / write flag signal indicates that a read data signal is transmitted via the DBUS bus, the start address signal indicates the start address of the valid data to be read (in Figure 4A It is recorded as start_addr in the command output.

[0109] Step 406: The host sends a read ready signal (dbus_rrdy) to the slave via the DBUS bus. The read ready signal indicates whether the host allows or does not allow the slave to receive a read data signal.

[0110] For example, after the host sends a request signal to the slave through the DBUS bus, it can send a read ready signal to the slave through the DBUS bus. For example, if the read ready signal is high and valid (the read ready signal can also be low and valid), the read ready signal will be high from time 4 (the read ready signal can be high at any time after time 4). Of course, the host can also send a read ready signal to the slave through the DBUS bus only after receiving a response signal, that is, the read ready signal will be high from time 8 (the read ready signal can be high at any time after time 8). Figure 4A In the embodiment, the read ready signal is at a high level starting from time 11 (this time 11 is just an example). In this way, the read ready signal can indicate that the host end is allowed to receive the read data signal starting from time 11.

[0111] Illustratively, the bit width of the read ready signal may be 1 bit or multiple bits, or 1 byte or multiple bytes. This embodiment does not impose any limitation on the bit width of the read ready signal.

[0112] Step 407: The slave sends a read valid signal (dbus_rvld) to the host via the DBUS bus. The read valid signal indicates that the slave is allowed to send a read data signal or is not allowed to send a read data signal.

[0113] For example, after receiving the request signal through the DBUS bus, the slave end can send a read valid signal to the host end through the DBUS bus. Taking the read valid signal as being high-level valid (the read valid signal can also be low-level valid), the read valid signal is high-level starting from time 4 (the read valid signal is high-level at any time after time 4). After sending a response signal to the host end, the slave end can send a read valid signal to the host end through the DBUS bus, that is, the read valid signal is high-level starting from time 8 (the read valid signal is high-level at any time after time 8). Figure 4A In the example, the read valid signal is at a high level starting from time 11, indicating that the slave end is allowed to send a read data signal starting from time 11.

[0114] Illustratively, the bit width of the read valid signal may be 1 bit or multiple bits, or 1 byte or multiple bytes. This embodiment does not impose any limitation on the bit width of the read valid signal.

[0115] Step 408: When the read ready signal indicates that the host is allowed to receive the read data signal, and the read valid signal indicates that the slave is allowed to send the read data signal, the slave sends a read data signal (dbus_rdata) to the host via the DBUS bus. The read data signal may include valid data to be read.

[0116] For example, the slave will not send a read data signal to the host via the DBUS bus before sending a response signal (dbus_ack). After sending the response signal, the slave can send a read data signal to the host via the DBUS bus, that is, the response signal indicates that the read data signal is allowed to be sent.

[0117] After sending the response signal, the slave can query the read ready signal and read valid signal. If the read ready signal indicates that the host allows the reception of read data signals (e.g., the read ready signal is high), and the read valid signal indicates that the slave allows the transmission of read data signals (e.g., the read valid signal is high), the slave sends the read data signal to the host via the DBUS bus. If the read ready signal indicates that the host does not allow the reception of read data signals, and / or the read valid signal indicates that the slave does not allow the transmission of read data signals, the slave does not send the read data signal to the host via the DBUS bus until the read ready signal indicates that the host allows the reception of read data signals, and the read valid signal indicates that the slave allows the transmission of read data signals.

[0118] See also Figure 4A As shown, the read ready signal is high from time 11, and the read valid signal is high from time 11. On this basis, the slave end can send a read data signal to the host end through the DBUS bus from time 11 (or a moment after time 11).

[0119] For example, the bit width of the read data signal is related to the actual length of the valid data to be read. The bit width of the read data signal can be denoted as DW. The bit width DW is a parameter related to the actual length of the valid data to be read. As long as the valid data to be read can be carried by the read data signal, there is no restriction on the bit width DW. For example, the bit width of the read data signal supports parameterizable configuration, that is, the bit width can be configured.

[0120] In one possible implementation, the slave can start at the starting address (start_addr), read data of a data length (burst_lens) as valid data to be read, and send the valid data to be read to the master via a read data signal. There are no restrictions on this data transmission process. The starting address can be determined based on the start address signal, and the data length can be determined based on the length signal.

[0121] Step 409: When the read ready signal indicates that the host is allowed to receive the read data signal and the read valid signal indicates that the slave is allowed to send the read data signal, the host receives the read data signal sent by the slave through the DBUS bus. The read data signal may include valid data to be read.

[0122] Exemplarily, the host side will not receive the read data signal through the DBUS bus before receiving the response signal. After receiving the response signal, the host side can receive the read data signal through the DBUS bus. For example, the host side queries the read ready signal and the read valid signal. If the read ready signal indicates that the host side allows the reception of the read data signal, and the read valid signal indicates that the slave side allows the transmission of the read data signal, the host side receives the read data signal through the DBUS bus and then obtains the valid data to be read. If the read ready signal indicates that the host side does not allow the reception of the read data signal, and / or the read valid signal indicates that the slave side does not allow the transmission of the read data signal, the host side does not receive the read data signal through the DBUS bus until the read ready signal indicates that the host side allows the reception of the read data signal, and the read valid signal indicates that the slave side allows the transmission of the read data signal.

[0123] For example, see Figure 4C Figure 2 shows a schematic diagram of a DBUS bus read transmission. The host can send address signals (such as a starting address signal) and control command signals (such as read / write flag signals and length signals) to the slave. After the address and control command signals are received by the slave, the host can wait for the slave to return data. The slave can then send multiple read data signals to the host, carrying the read data (such as read data D0 and read data D1), completing the data read process.

[0124] In one possible implementation, the on-chip bus system may further include an arbitrator, the host side is connected to the arbitrator via a DBUS bus, and the arbitrator is connected to the slave side via a DBUS bus. In this application scenario, it can be understood that the DBUS bus between the host side and the slave side is relayed through the arbitrator.

[0125] For the data writing process, the host can send a request signal (dbus_req) to the arbitrator through the DBUS bus, and the arbitrator can send a request signal (dbus_req) to the slave through the DBUS bus.

[0126] When the slave receives a request signal through the DBUS bus, if the slave is in an idle state, the slave can send a response signal (dbus_ack) to the arbitrator through the DBUS bus, and the arbitrator can send a response signal (dbus_ack) to the host through the DBUS bus.

[0127] The host can send a read / write flag signal (dbus_wren) to the arbitrator via the DBUS bus, and the arbitrator can send a read / write flag signal (dbus_wren) to the slave via the DBUS bus.

[0128] The host can send a length signal (dbus_lens) to the arbitrator via the DBUS bus, and the arbitrator can send a length signal (dbus_lens) to the slave via the DBUS bus.

[0129] The host can send a starting address signal (dbus_addr) to the arbitrator via the DBUS bus, and the arbitrator can send a starting address signal (dbus_addr) to the slave via the DBUS bus.

[0130] The host can send a write-valid signal (dbus_wvld) to the arbitrator via the DBUS bus, and the arbitrator can send a write-valid signal (dbus_wvld) to the slave via the DBUS bus.

[0131] The slave end can send a write ready signal (dbus_wrdy) to the arbitrator through the DBUS bus, and the arbitrator can send a write ready signal (dbus_wrdy) to the host end through the DBUS bus.

[0132] When the write-ready signal indicates that the slave is allowed to receive write data signals, and the write-valid signal indicates that the host is allowed to send write data signals, the host can send write data signals (dbus_wdata) to the arbiter via the DBUS bus. For example, if there are M write data signals, the arbiter can send M write data signals (dbus_wdata) to the slave via the DBUS bus. Based on this, the slave can receive M write data signals via the DBUS bus and obtain the target valid data based on the M write data signals.

[0133] For the data reading process, the host can send a request signal (dbus_req) to the arbitrator through the DBUS bus, and the arbitrator can send a request signal (dbus_req) to the slave through the DBUS bus.

[0134] When the slave receives a request signal through the DBUS bus, if the slave is in an idle state, the slave can send a response signal (dbus_ack) to the arbitrator through the DBUS bus, and the arbitrator can send a response signal (dbus_ack) to the host through the DBUS bus.

[0135] The host can send a read / write flag signal (dbus_wren) to the arbitrator via the DBUS bus, and the arbitrator can send a read / write flag signal (dbus_wren) to the slave via the DBUS bus.

[0136] The host can send a length signal (dbus_lens) to the arbitrator via the DBUS bus, and the arbitrator can send a length signal (dbus_lens) to the slave via the DBUS bus.

[0137] The host can send a starting address signal (dbus_addr) to the arbitrator via the DBUS bus, and the arbitrator can send a starting address signal (dbus_addr) to the slave via the DBUS bus.

[0138] The host can send a read ready signal (dbus_rrdy) to the arbitrator via the DBUS bus, and the arbitrator can send a read ready signal (dbus_rrdy) to the slave via the DBUS bus.

[0139] The slave end can send a read valid signal (dbus_rvld) to the arbitrator through the DBUS bus, and the arbitrator can send a read valid signal (dbus_rvld) to the host end through the DBUS bus.

[0140] When the read-ready signal indicates that the host is allowed to receive read data signals, and the read-valid signal indicates that the slave is allowed to send read data signals, the slave can send a read data signal (dbus_rdata) to the arbitrator via the DBUS bus, and the arbitrator can send the read data signal (dbus_rdata) to the host via the DBUS bus. Based on this, the host receives the read data signal via the DBUS bus.

[0141] In one possible implementation, the on-chip bus system may include a host, an arbitrator, and a slave, wherein the host is connected to the arbitrator via a DBUS bus, and the slave is connected to the arbitrator via a DBUS bus. The on-chip bus system may include a host, multiple arbitrators, and multiple slaves, wherein the host is connected to each arbitrator via a DBUS bus. The number of arbitrators and the number of slaves may be the same, and the multiple arbitrators correspond one-to-one to the multiple slaves. For example, arbitrator 1 is connected to slave 1 via a DBUS bus, arbitrator 2 is connected to slave 2 via a DBUS bus, and so on.

[0142] The on-chip bus system may include multiple host terminals, an arbitrator and a slave terminal. The arbitrator is connected to each host terminal via a DBUS bus, and the arbitrator is connected to the slave terminal via a DBUS bus.

[0143] The on-chip bus system can include multiple hosts, multiple arbiters, and multiple slaves. Each host is connected to each arbiter via a DBUS bus. The number of arbiters can be the same as the number of slaves, with multiple arbiters corresponding to multiple slaves. For example, arbiter 1 is connected to slave 1 via a DBUS bus, arbiter 2 is connected to slave 2 via a DBUS bus, and so on.

[0144] For the convenience of description, in this embodiment, an on-chip bus system including multiple host terminals, multiple arbitrators, and multiple slave terminals is taken as an example. Figure 5 The figure shows the structure of the on-chip bus system.

[0145] The on-chip bus system includes host M0, host M1, host M2, host M3, host M4, slave S0, slave S1, arbiter WRR0, and arbiter WRR1. Arbiter WRR0 is connected to slave S0 via the DBUS bus, while arbiter WRR1 is connected to slave S1 via the DBUS bus. Host M0, host M1, host M2, host M3, and host M4 are each connected to arbiter WRR0 via the DBUS bus, while host M0, host M1, host M2, host M3, and host M4 are each connected to arbiter WRR1 via the DBUS bus.

[0146] For example, when host m0 writes data to slave s0, host m0 sends a write data signal (s_w0) to arbiter WRR0 via the DBUS bus, and arbiter WRR0 sends a write data signal (m_w0) to slave s0 via the DBUS bus. When host m0 writes data to slave s1, host m0 sends a write data signal (s_w0) to arbiter WRR1 via the DBUS bus, and arbiter WRR1 sends a write data signal (m_w1) to slave s1 via the DBUS bus.

[0147] When the host m1 writes data to the slave s0, the host m1 sends a write data signal (s_w1) to the arbiter WRR0 via the DBUS bus, and the arbiter WRR0 sends a write data signal (m_w0) to the slave s0 via the DBUS bus. When the host m1 writes data to the slave s1, the host m1 sends a write data signal (s_w1) to the arbiter WRR1 via the DBUS bus, and the arbiter WRR1 sends a write data signal (m_w1) to the slave s1 via the DBUS bus, and so on.

[0148] For example, when host m0 reads data from slave s0, slave s0 sends a read data signal (m_r0) to arbiter WRR0 via the DBUS bus, and arbiter WRR0 sends a read data signal (s_r0) to host m0 via the DBUS bus. When host m0 reads data from slave s1, slave s1 sends a read data signal (m_r1) to arbiter WRR1 via the DBUS bus, and arbiter WRR1 sends a read data signal (s_r0) to host m0 via the DBUS bus.

[0149] When the host side m1 reads data from the slave side s0, the slave side s0 sends a read data signal (m_r0) to the arbiter WRR0 via the DBUS bus, and the arbiter WRR0 sends a read data signal (s_r1) to the host side m1 via the DBUS bus. When the host side m1 reads data from the slave side s1, the slave side s1 sends a read data signal (m_r1) to the arbiter WRR1 via the DBUS bus, and the arbiter WRR1 sends a read data signal (s_r1) to the host side m1 via the DBUS bus, and so on.

[0150] For example, when multiple hosts simultaneously write data to slave s0, arbiter WRR0 can select one host from the multiple hosts. There is no restriction on the selection method. Arbiter WRR0 allows the selected host to write data to slave s0, while other hosts do not write data to slave s0. When multiple hosts simultaneously read data from slave s0, arbiter WRR0 can select one host from the multiple hosts and allow the selected host to read data from slave s0.

[0151] When the master end M0 writes data to the slave end S0, and the master end M1 writes data to the slave end S1 at the same time, the arbiter WRR0 allows the master end M0 to write data to the slave end S0, and the arbiter WRR1 allows the master end M1 to write data to the slave end S1. When the master end M0 reads data from the slave end S0, and the master end M1 reads data from the slave end S1 at the same time, the arbiter WRR0 allows the master end M0 to read data from the slave end S0, and the arbiter WRR1 allows the master end M1 to read data from the slave end S1.

[0152] When the host side m0 writes data to the slave side s0 and the host side m1 reads data from the slave side s0 at the same time, the arbiter WRR0 allows the host side m0 to write data to the slave side s0, and the arbiter WRR0 allows the host side m1 to read data from the slave side s1, that is, it supports data writing and reading synchronization for the slave side.

[0153] To sum up, in this embodiment, the arbitrator can be applicable to application scenarios with multiple masters and multiple slaves, the arbitrator can be applicable to application scenarios with one master and multiple slaves, the arbitrator can be applicable to application scenarios with multiple masters and one slave, the arbitrator can be applicable to application scenarios with one master and one slave, etc., and has strong reusability.

[0154] As can be seen from the above technical solutions, in the embodiments of the present application, a DBUS bus is designed. The DBUS bus has fewer signal lines, a simple protocol control sequence, and a low hardware overhead. It is suitable for high-bandwidth, low-power, and small-area applications. That is, the DBUS bus has the advantages of high bandwidth, low latency, low power consumption, and a small area. In system integration, the bus protocol of the DBUS bus is simple and easy to integrate, and is not prone to errors. The DBUS bus reduces the mask flag signal, that is, the DBUS bus does not need to provide a mask flag signal. Even if the mask flag signal is not provided, the mask function can be realized, and the mask flag signal can be saved, so that the DBUS bus has fewer signal lines, a simple protocol control sequence, and a low hardware overhead.

[0155] In the embodiment of the present application, a data receiving method from the machine is proposed. Figure 6 FIG. 5 is a flow chart of the method, which may include: Step 601: Receive M write data signals via the DBUS bus; wherein M is determined based on the data length of target valid data to be transmitted and the bit width of the DBUS bus; wherein the M write data signals include the target valid data.

[0156] Step 602 : Obtain target valid data based on M write data signals; wherein, all data in the first M-1 write data signals are target valid data, and all or part of the data in the Mth write data signal are target valid data.

[0157] Exemplarily, M is obtained by rounding up the quotient of the data length of the target valid data and the bit width of the DBUS bus; if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, then all the data in the Mth write data signal is the target valid data; or, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then N units of data in the Mth write data signal are the target valid data; wherein, the target valid data occupies the N units of the high order of the Mth write data signal, or, the target valid data occupies the N units of the low order of the Mth write data signal.

[0158] Exemplarily, obtaining target valid data based on M write data signals may include: determining all data in the previous M-1 write data signals as target valid data; generating a mask signal corresponding to the Mth write data signal based on the data length of the target valid data and the bit width of the DBUS bus, and determining all or part of the data in the Mth write data signal as target valid data based on the mask signal.

[0159] Exemplarily, determining all or part of the data in the Mth write data signal as the target valid data based on the mask signal may include: if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all bits of the mask signal are the first value, a mask operation is performed based on the mask signal and the Mth write data signal to obtain a first calculated signal, and all data in the first calculated signal are determined as the target valid data; if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, all bits of the high-order N bytes of the mask signal are the first value, all bits of the remaining bytes are the second value, a mask operation is performed based on the mask signal and the Mth write data signal to obtain a second calculated signal, and the high-order N bytes in the second calculated signal are determined as the target valid data; or, all bits of the low-order N bytes of the mask signal are the first value, all bits of the remaining bytes are the second value, a mask operation is performed based on the mask signal and the Mth write data signal to obtain a third calculated signal, and the low-order N bytes in the third calculated signal are determined as the target valid data.

[0160] Exemplarily, the data length of the configured target valid data may also be obtained; Alternatively, a length signal is received via a DBUS bus, and the data length of the target valid data is determined based on the length signal; wherein the length signal indicates the data length of the target valid data.

[0161] In the embodiment of the present application, a data receiving device at the slave end is proposed. Figure 7 FIG. 1 is a schematic diagram of the structure of the device, which includes: A receiving module 71 is configured to receive M write data signals via a DBUS bus, wherein M is determined based on the data length of target valid data to be transmitted and the bit width of the DBUS bus, and wherein the M write data signals include the target valid data; The determination module 72 is configured to obtain target valid data based on the M write data signals; wherein all data in the first M-1 write data signals are target valid data, and all or part of the data in the Mth write data signal are target valid data.

[0162] Exemplarily, M is obtained by rounding up the quotient of the data length of the target valid data and the bit width of the DBUS bus; if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, then all the data in the Mth write data signal is the target valid data; or, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then N units of data in the Mth write data signal are the target valid data; wherein, the target valid data occupies N units of the high order of the Mth write data signal, or, the target valid data occupies N units of the low order of the Mth write data signal.

[0163] Exemplarily, when the determination module 72 obtains the target valid data based on the M write data signals, it is specifically used to: determine all the data in the previous M-1 write data signals as the target valid data; generate a mask signal corresponding to the Mth write data signal based on the data length of the target valid data and the bit width of the DBUS bus, and determine all or part of the data in the Mth write data signal as the target valid data based on the mask signal.

[0164] Exemplarily, when the determination module 72 determines all or part of the data in the Mth write data signal as the target valid data based on the mask signal, it is specifically used to: if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, then all bits of the mask signal are the first value, a mask operation is performed based on the mask signal and the Mth write data signal to obtain a first calculated signal, and all data in the first calculated signal are determined as the target valid data; if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then All bits of the high-order N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value. A mask operation is performed based on the mask signal and the M-th write data signal to obtain a second calculated signal, and the high-order N bytes in the second calculated signal are determined as the target valid data; or, all bits of the low-order N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value. A mask operation is performed based on the mask signal and the M-th write data signal to obtain a third calculated signal, and the low-order N bytes in the third calculated signal are determined as the target valid data.

[0165] Exemplarily, the determination module 72 is further used to obtain the data length of the configured target valid data; or, the receiving module 71 is further used to receive a length signal through the DBUS bus; the determination module 72 is further used to determine the data length of the target valid data based on the length signal; wherein, the length signal represents the data length of the target valid data.

[0166] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. An on-chip bus system, characterized in that: The on-chip bus system includes: a host end, a slave end and a DBUS bus, wherein the host end and the slave end are connected via the DBUS bus; The host end is configured to send M write data signals to the slave end via the DBUS bus; wherein M is determined based on the data length of the target valid data to be transmitted and the bit width of the DBUS bus; wherein the M write data signals include the target valid data; The slave end is used to receive M write data signals and obtain target valid data based on the M write data signals; wherein all data in the first M-1 write data signals are target valid data, and all data or part of the data in the Mth write data signal are target valid data.

2. The on-chip bus system according to claim 1, wherein: M is obtained by rounding up the quotient of the data length of the target valid data and the bit width of the DBUS bus; All or part of the data in the Mth write data signal is target valid data, including: If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, then all the data in the Mth write data signal is the target valid data; or, If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then the N units of data in the Mth write data signal are the target valid data; wherein, the target valid data occupies the N units of the high bit of the Mth write data signal, or, the target valid data occupies the N units of the low bit of the Mth write data signal.

3. The on-chip bus system according to claim 1, wherein: The slave end is specifically used to obtain target valid data based on the M write data signals: Determine all data in the preceding M-1 write data signals as the target valid data; A mask signal corresponding to the Mth write data signal is generated based on the data length of the target valid data and the bit width of the DBUS bus, and all or part of the data in the Mth write data signal is determined as the target valid data based on the mask signal.

4. The on-chip bus system according to claim 3, wherein: The slave end determines all or part of the data in the Mth write data signal as the target valid data based on the mask signal, specifically for: If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all bits of the mask signal are taken as the first value, a mask operation is performed based on the mask signal and the Mth write data signal to obtain a first calculated signal, and all data in the first calculated signal are determined as the target valid data; If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then all bits of the high-order N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value. A mask operation is performed based on the mask signal and the M-th write data signal to obtain a second calculated signal, and the high-order N bytes in the second calculated signal are determined as the target valid data; or, all bits of the low-order N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value. A mask operation is performed based on the mask signal and the M-th write data signal to obtain a third calculated signal, and the low-order N bytes in the third calculated signal are determined as the target valid data.

5. The on-chip bus system according to any one of claims 2 to 4, characterized in that: The slave end is also used to obtain the data length of the configured target valid data; Alternatively, the slave end is further configured to receive a length signal sent by the host end via the DBUS bus, and determine the data length of the target valid data based on the length signal; wherein the length signal indicates the data length of the target valid data.

6. The on-chip bus system according to claim 1, wherein: The on-chip bus system further includes an arbiter, the host end is connected to the arbiter via a DBUS bus, and the arbiter is connected to the slave end via a DBUS bus; The host end is used to send the M write data signals to the arbitrator via the DBUS bus; The arbiter is used to send the M write data signals to the slave end via the DBUS bus.

7. A data receiving method at a slave end, characterized in that: The method comprises: Receiving M write data signals via a DBUS bus; wherein M is determined based on the data length of target valid data to be transmitted and the bit width of the DBUS bus; wherein the M write data signals include the target valid data; Target valid data is acquired based on the M write data signals; wherein all data in the first M-1 write data signals are target valid data, and all or part of the data in the Mth write data signal are target valid data.

8. The method according to claim 7, characterized in that M is obtained by rounding up the quotient of the data length of the target valid data and the bit width of the DBUS bus; If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all the data in the Mth write data signal is the target valid data; or, If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then the N units of data in the Mth write data signal are the target valid data; wherein, the target valid data occupies the N units of the high order of the Mth write data signal, or, the target valid data occupies the N units of the low order of the Mth write data signal.

9. The method according to claim 7, characterized in that The acquiring target valid data based on the M write data signals includes: Determine all data in the preceding M-1 write data signals as the target valid data; A mask signal corresponding to the Mth write data signal is generated based on the data length of the target valid data and the bit width of the DBUS bus, and all or part of the data in the Mth write data signal is determined as the target valid data based on the mask signal.

10. The method according to claim 9, characterized in that The determining, based on the mask signal, all or part of the data in the Mth write data signal as the target valid data includes: If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all bits of the mask signal are taken as the first value, a mask operation is performed based on the mask signal and the Mth write data signal to obtain a first calculated signal, and all data in the first calculated signal are determined as the target valid data; If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then all bits of the high-order N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value. A mask operation is performed based on the mask signal and the M-th write data signal to obtain a second calculated signal, and the high-order N bytes in the second calculated signal are determined as the target valid data; or, all bits of the low-order N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value. A mask operation is performed based on the mask signal and the M-th write data signal to obtain a third calculated signal, and the low-order N bytes in the third calculated signal are determined as the target valid data.

11. The method according to any one of claims 7 to 10, characterized in that: The method further comprises: Get the data length of the configured target valid data; Alternatively, a length signal is received via the DBUS bus, and the data length of the target valid data is determined based on the length signal; wherein the length signal indicates the data length of the target valid data.

12. A data receiving device at a slave end, characterized in that: The device comprises: A receiving module, configured to receive M write data signals via a DBUS bus; wherein M is determined based on the data length of target valid data to be transmitted and the bit width of the DBUS bus; wherein the M write data signals include the target valid data; A determination module is used to obtain target valid data based on the M write data signals; wherein all data in the first M-1 write data signals are target valid data, and all or part of the data in the Mth write data signal are target valid data.

13. The device according to claim 12, It is characterized by: in, M is obtained by rounding up the quotient of the data length of the target valid data and the bit width of the DBUS bus; if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, then all the data in the M-th write data signal is the target valid data; or, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then N units of data in the M-th write data signal are the target valid data; wherein, the target valid data occupies N units of the high order bits of the M-th write data signal, or, the target valid data occupies N units of the low order bits of the M-th write data signal; Wherein, when the determination module obtains the target valid data based on the M write data signals, it is specifically configured to: determine all data in the previous M-1 write data signals as the target valid data; generate a mask signal corresponding to the Mth write data signal based on the data length of the target valid data and the bit width of the DBUS bus, and determine all or part of the data in the Mth write data signal as the target valid data based on the mask signal; Wherein, when the determination module determines all or part of the data in the Mth write data signal as the target valid data based on the mask signal, it is specifically configured to: if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, then all bits of the mask signal are first values, a mask operation is performed based on the mask signal and the Mth write data signal to obtain a first calculated signal, and all data in the first calculated signal is determined as the target valid data; If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, then all bits of the upper N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value, a mask operation is performed based on the mask signal and the M-th write data signal to obtain a second calculated signal, and the upper N bytes in the second calculated signal are determined as the target valid data; or, all bits of the lower N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value, a mask operation is performed based on the mask signal and the M-th write data signal to obtain a third calculated signal, and the lower N bytes in the third calculated signal are determined as the target valid data; Wherein, the determining module is further used to obtain the data length of the configured target valid data; Alternatively, the receiving module is further used to receive a length signal through the DBUS bus; the determining module is further used to determine the data length of the target valid data based on the length signal; wherein the length signal represents the data length of the target valid data.

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