Device and method for reading data of external memory

Abstract

The invention relates to the technical field of integrated chips, and discloses a device and a method for reading data of an external memory, the device comprises a programmable interface access module and an interface controller, the programmable interface access module comprises a first data register, a first address register and an instruction execution unit; the interface controller is used for storing data state information; wherein the data state information is used for indicating whether cache data is stored in the interface controller or not, and the cache data is acquired by the interface controller from an external memory; the first data register is used for mapping data state information stored by the interface controller; the first address register is used for sending a first storage address corresponding to the cache data to the instruction execution unit; and the instruction execution unit is used for reading the data state information from the first data register, and storing the cache data to the memory corresponding to the first storage address when the data state information indicates that the cache data is stored in the interface controller.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated chips, and in particular to a device and method for reading data from an external memory. Background Art

[0002] Most System-on-Chip (SoC) chips include a microcontroller unit (MCU) or a central processing unit (CPU). The instructions of the MCU or CPU come from external memory, such as Flash memory. The data processed can be real-time sampled data, such as sampling through an analog to digital converter (ADC), or it can come from external memory. Therefore, the SoC will access external memory extensively. To access external storage devices, the SoC will have a built-in interface controller for communicating with external memory. This interface controller will provide many control registers and status registers. The MCU accesses the external storage device by configuring the control registers and obtains the status of data transmission through the status registers.

[0003] In the related art, the interface of the external memory is a low-speed device compared to the operating frequency of the SoC, and it takes multiple MCU clock cycles to return a piece of data. Figure 1 As shown, there are two specific methods: First, MCU polling method, the processing flow is as follows:

[0004] (1) The MCU starts data transmission through the control register of the bus configuration interface controller;

[0005] (2) MCU reads the FIFO status register in the interface controller;

[0006] (3) If the status register indicates that the data from the Flash memory has been received, go to (4) for execution; otherwise, go to (2) for execution;

[0007] (4) MCU reads data from the interface controller and saves it to the memory;

[0008] (5) If there is still data to be read, go to (2) to execute, otherwise end.

[0009] However, the above method has the following disadvantages: (1) the MCU cannot process other transactions when querying the FIFO status of the interface controller, which does not fully utilize the MCU; (2) the MCU continuously reads the status register, and there are a large number of requests on the bus, which results in high system power consumption.

[0010] Second, Direct Memory Access (DMA) + interrupt mode, the processing flow is as follows:

[0011] (1) MCU configures DMA;

[0012] (2) The MCU configures the control registers of the interface controller to start data transmission and then proceeds to handle other tasks;

[0013] (3) The interface controller receives the data from the Flash memory and stores it in the FIFO, while updating the FIFO status.

[0014] (4) When the FIFO stores enough data, the interface controller issues a DMA request;

[0015] (5) After receiving the request, DMA reads multiple data from the interface controller through the bus and saves them into the memory.

[0016] However, if DMA transmits multiple data at a time, such as 8 data, then the interface controller needs to be able to store multiple data at a time, such as 16 data. This will increase the area of the interface controller, and thus increase the area and cost of the SoC. Summary of the Invention

[0017] In view of this, an embodiment of the present invention provides an apparatus and method for reading data from an external memory.

[0018] In a first aspect, an embodiment of the present invention provides a device for reading data from an external memory, the device comprising: a programmable interface access module and an interface controller, the programmable interface access module comprising a first data register, a first address register and an instruction execution unit; an interface controller for storing data status information; wherein the data status information is used to indicate whether the interface controller stores cached data, the cached data being obtained by the interface controller from an external memory; a first data register for mapping the data status information stored by the interface controller; a first address register for sending a first storage address corresponding to the cached data to the instruction execution unit; and an instruction execution unit for reading the data status information from the first data register, and saving the cached data to the memory corresponding to the first storage address when the data status information indicates that the interface controller stores cached data.

[0019] In one possible implementation, the programmable interface access module also includes: a second data register; a second data register for temporarily storing cache data read from the interface controller; an instruction execution unit, further for saving the cache data temporarily stored in the second data register to the memory corresponding to the first storage address when the data status information indicates that the interface controller stores cache data.

[0020] In one possible implementation, the programmable interface access module also includes: a second address register, which stores a second storage address; a second address register, which is used to send the second storage address corresponding to the cache data to the instruction execution unit; the instruction execution unit is further used to read the cache data from the interface controller according to the second storage address, and save the cache data to the second data register.

[0021] In one possible implementation, the programmable interface access module also includes: a third data register, which stores the transmission length of the cached data; an instruction execution unit, which is further used to read the cached data from the interface controller according to the second storage address and the transmission length of the cached data, and save the cached data to the second data register.

[0022] In one possible implementation, the programmable interface access module also includes: a fourth data register, in which the data length of the cached data is stored; an instruction execution unit, further used to update the data length of the cached data according to the transmission length of the cached data after saving the cached data to the memory corresponding to the storage address, and determine the remaining data length stored in the fourth data register, wherein when the remaining data length is greater than the preset length, the data status information is read from the first data register again.

[0023] In one possible implementation, the instruction execution unit includes: a programmable instruction queue, an instruction fetch circuit, and a decoding execution circuit; the programmable instruction queue is used to store multiple operation instructions; the instruction fetch circuit is used to read the target operation instruction from the programmable instruction queue in sequence according to the storage sequence of the operation instructions in each clock cycle; the decoding execution circuit is used to receive and parse the target operation instruction, and execute the operation corresponding to the target operation instruction based on the parsing result of the target operation instruction.

[0024] In a possible implementation, the programmable interface access module further includes: a plurality of other data registers and a plurality of other address registers; the plurality of data registers and the plurality of address registers are respectively connected to the instruction execution unit.

[0025] In a possible implementation, there are multiple interface controllers, and accordingly, there are multiple programmable interface access modules; each interface controller is connected to multiple programmable interface access modules.

[0026] In one possible implementation, the interface controller includes a status register and a data memory; the status register is used to store data status information; the first data register is further used to map the data status information stored in the status register; the data memory is used to obtain and store cache data from an external memory; and the instruction execution unit is further used to read the cache data in the data memory according to the second address register and temporarily store the cache data in the second data register.

[0027] In a second aspect, an embodiment of the present invention provides a method for reading data from an external memory, which is applied to a device for reading data from an external memory, the method comprising: reading data status information of an interface controller from a first data register; wherein the data status information is used to indicate whether the interface controller stores cache data, and the cache data is obtained from an external memory; when the data status information indicates that the interface controller stores cache data, reading a first storage address corresponding to the cache data in a first address register, and saving the cache data to a memory corresponding to the first storage address.

[0028] In a third aspect, an embodiment of the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, computer instructions being stored in the memory, and the processor executing the method of the second aspect or any corresponding embodiment thereof by executing the computer instructions.

[0029] In an apparatus for reading data from an external memory provided by an embodiment of the present invention, a first data register of a programmable interface access module can map data status information stored in an interface controller, so that an instruction execution unit reads the data status information directly from the first data register, and when the data status information indicates that the interface controller stores cached data, the cached data is saved to a memory corresponding to the first storage address. Compared with the method of configuring DMA through an MCU in the related art, the RX FIFO inside the interface controller is avoided from storing a large amount of cached data, thereby eliminating the need to increase the area of the interface controller and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 This is a diagram showing a conventional system structure for reading data from an external memory provided by an embodiment of the present invention;

[0032] Figure 2 2 is a schematic diagram of the structure of an apparatus for reading data from an external memory according to an embodiment of the present invention.

[0033] Figure 3 is a schematic structural diagram of another device for reading data from an external memory provided according to an embodiment of the present invention;

[0034] Figure 4 1 is a schematic structural diagram of another device for reading data from an external memory provided according to an embodiment of the present invention;

[0035] Figure 5 2 is a schematic structural diagram of another device for reading data from an external memory provided according to an embodiment of the present invention;

[0036] Figure 6 2 is a schematic structural diagram of another device for reading data from an external memory provided according to an embodiment of the present invention;

[0037] Figure 7 2 is a schematic structural diagram of another device for reading data from an external memory provided according to an embodiment of the present invention;

[0038] Figure 8 2 is a schematic structural diagram of another device for reading data from an external memory provided according to an embodiment of the present invention;

[0039] Figure 9 2 is a schematic structural diagram of another device for reading data from an external memory provided according to an embodiment of the present invention;

[0040] Figure 10 2 is a schematic structural diagram of an apparatus for reading data from an external memory according to an embodiment of the present invention;

[0041] Figure 11 2 is a schematic structural diagram of an apparatus for reading data from an external memory according to an embodiment of the present invention;

[0042] Figure 12 is a flow chart of a method for reading data from an external memory according to an embodiment of the present invention;

[0043] Figure 13 A schematic diagram of the structure of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0045] Please refer to Figure 2 , Figure 2 2 is a schematic diagram of the structure of an apparatus for reading data from an external memory according to an embodiment of the present invention.

[0046] An embodiment of the present invention provides a device for reading data from an external memory, the device comprising: a programmable interface access module 1 and an interface controller 2, the programmable interface access module 1 comprising a first data register 11, a first address register 12 and an instruction execution unit 13; the interface controller 2, for storing data status information; wherein the data status information is used to indicate whether the interface controller 2 stores cached data, the cached data being obtained by the interface controller 2 from an external memory 3; the first data register 11, for mapping the data status information stored by the interface controller 2; the first address register 12, for sending a first storage address corresponding to the cached data to the instruction execution unit 13; the instruction execution unit 13, for reading the data status information from the first data register 11, and when the data status information indicates that the interface controller 2 stores cached data, saving the cached data to the memory corresponding to the first storage address.

[0047] The interface controller 2 can be connected to the external memory 3, and the interface controller 2 can obtain cache data from the external memory 3. The external memory 3 can be a Flash memory, or a phase change memory, etc., which is not specifically limited here.

[0048] The programmable interface access module 1 may include a first data register 11, wherein the first data register 11 is used to map data status information stored by the interface controller 2. The data status information may indicate whether the interface controller 2 stores cache data.

[0049] As an example, the interface controller 2 may include a status register 21, which may be used to store data status information. When data status information is stored in the status register 21, a status flag in the status register 21 may be a non-empty flag or a data presence flag, indicating whether the interface controller 2 stores cached data. When no cached data is stored in the interface controller 2, the status register 21 may not contain a flag or may be an empty flag.

[0050] As an example, when the status flag in the status register 21 is a non-empty flag, cache data is stored in the interface controller 2, that is, there is cache data in the interface controller 2 that can be read. At this time, the reading of the current status information of the status register 21 can be paused first, and the cache data can be saved to the memory corresponding to the first storage address through the instruction execution unit 13.

[0051] The first address register 12 can be used to send a first storage address corresponding to the cached data to the instruction execution unit 13. The first storage address can indicate the address where the cached data needs to be stored. When the data status information indicates that the interface controller 2 stores the cached data, and the instruction execution unit 13 receives the first storage address sent by the first address register 12, it saves the cached data to the memory corresponding to the first storage address.

[0052] Optionally, the programmable interface access module 1 may be a field programmable gate array (FPGA) or the like.

[0053] Optionally, the memory may be an SRAM memory.

[0054] In the device for reading external memory data provided by an embodiment of the present invention, the first data register of the programmable interface access module 1 can map the data status information stored in the interface controller, so that the instruction execution unit reads the data status information directly from the first data register, and when the data status information indicates that the interface controller stores cached data, the cached data is saved to the memory corresponding to the first storage address. Compared with the method of configuring DMA through MCU in the related art, the RX FIFO inside the interface controller is avoided from storing a large amount of cached data, thereby eliminating the need to increase the area of the interface controller to reduce costs.

[0055] In a possible implementation, the instruction execution unit 13 is further configured to read the data status information of the interface controller 2 again when the data status information indicates that the interface controller 2 does not store cache data.

[0056] When the status flag in the status register 21 is an empty flag or a data does not exist flag, it means that the interface controller 2 has no cached data to read. At this time, it is necessary to read the data status information of the interface controller 2 again. The reading of the data status information of the interface controller 2 will not be suspended until the status flag in the interface controller 2 becomes a non-empty flag or a data exists flag.

[0057] Please refer to Figure 3 , Figure 3 2 is a schematic structural diagram of another device for reading data from an external memory according to an embodiment of the present invention.

[0058] In one possible implementation, the programmable interface access module 1 also includes: a second data register 14; the second data register 14 is used to temporarily store cache data read from the interface controller 2; an instruction execution unit 13, further used to save the cache data temporarily stored in the second data register 14 to the memory corresponding to the first storage address when the data status information indicates that the interface controller 2 stores cache data.

[0059] The first data register 11 and the second data register 14 can form a data register group, wherein the programmable interface access module 1 can include a data register group, and the first data register 11 and the second data register 14 in the data register group can implement different functions. The second data register 14 can be used to temporarily store cached data read from the interface controller 2. That is, when cached data exists in the interface controller 2, the instruction execution unit 13 can first obtain the cached data from the interface controller 2 and send it to the second register in the register group. The second register can temporarily store the cached data. When the instruction execution unit 13 receives the first storage address corresponding to the cached data sent by the first address register 12, the cached data temporarily stored in the second register can be sent to the memory corresponding to the first storage address according to the first storage address.

[0060] In the device for reading data from an external memory provided by this embodiment, the second data register serves as a temporary storage area for cached data, which can optimize the data transmission path, thereby improving the efficiency and speed of data transmission.

[0061] Please refer to Figure 4 , Figure 4 3 is a schematic structural diagram of another device for reading data from an external memory provided according to an embodiment of the present invention.

[0062] In one possible implementation, the programmable interface access module 1 also includes: a second address register 15, which stores a second storage address; the second address register 15 is used to send the second storage address corresponding to the cache data to the instruction execution unit 13; the instruction execution unit 13 is further used to read the cache data from the interface controller 2 according to the second storage address, and save the cache data to the second data register 14.

[0063] The second address register 15 and the first address register 12 may form an address register group, wherein the programmable interface access module 1 may include the address register group, and the addresses stored in the first address register 12 and the second address register 15 in the address register group may be different.

[0064] The second address register 15 may be used to send a second storage address corresponding to the cached data to the instruction execution unit 13. The second storage address may indicate a temporary storage address of the cached data. When the instruction execution unit 13 reads cached data from the interface controller 2, it may send the cached data to the second data register 14 based on the second storage address.

[0065] In the apparatus for reading data from an external memory provided by this embodiment, the instruction execution unit does not need to recalculate or look up the storage address each time data is accessed, using the second address register. This simplifies the instruction execution process, reduces the burden on the CPU, and thus improves the operating efficiency of the entire system.

[0066] Please refer to Figure 5 , Figure 5 3 is a schematic structural diagram of another device for reading data from an external memory according to an embodiment of the present invention.

[0067] In one possible implementation, the programmable interface access module 1 also includes: a third data register 16, which stores the transmission length of the cached data; an instruction execution unit 13, which is further used to read the cached data from the interface controller 2 according to the second storage address and the transmission length of the cached data, and save the cached data to the second data register 14.

[0068] The third data register 16 can store the transfer length of the cached data. The transfer length can indicate the length of each cached data read, for example, one byte or two bytes at a time. After determining the transfer length of the cached data, the instruction execution unit 13 can read the cached data according to the transfer length and save the cached data to the second data register 14.

[0069] Please refer to Figure 6 , Figure 6 3 is a schematic structural diagram of another device for reading data from an external memory according to an embodiment of the present invention.

[0070] In one possible implementation, the programmable interface access module 1 further includes: a fourth data register 17, in which the data length of the cached data is stored; an instruction execution unit, further configured to update the data length of the cached data according to the transmission length of the cached data after saving the cached data to the memory corresponding to the storage address, and determine the remaining data length stored in the fourth data register 17, wherein when the remaining data length is greater than the preset length, the data status information is read again from the first data register 11.

[0071] The fourth data register 17 can store the data length of the cached data. After the data transmission starts, each time a data is read from the interface controller 2, the data length of the cached data needs to be updated according to the transmission length of the cached data to determine the remaining data length stored in the fourth data register 17.

[0072] More specifically, the total amount of buffered data to be received needs to be set in advance before data transmission. After data transmission begins, the data length of the buffered data is subtracted from the transmission length after each data read from the interface controller 2 to obtain the remaining data length of the updated buffered data.

[0073] The preset length can indicate whether the remaining cache data is zero. When the remaining cache data length is greater than zero, indicating that the total amount of cache data set to be received has not yet been reached, it is necessary to read data status information from the first data register 11 again. Then, when the data status information indicates that cache data exists in the interface controller 2 and the instruction execution unit 13 receives the first storage address sent by the first address register 12, the cache data is saved to the memory corresponding to the first storage address.

[0074] In one possible implementation, while the cached data in the interface controller 2 is continuously retrieved and stored, the length of the cached data stored in the fourth data register 17 gradually approaches zero. When the value of the fourth data register 17 reaches zero, that is, the data stored in the memory has reached a preset total cached data amount, it is no longer necessary to retrieve the cached data in the interface controller 2, and the reading of the data status information is stopped.

[0075] In the device for reading data from an external memory provided by this embodiment, by determining whether the remaining data length is zero, the instruction execution unit can intelligently determine whether to continue reading data from the interface controller, thereby avoiding invalid data reading operations and improving data transmission efficiency.

[0076] Please refer to Figure 7 , Figure 7 3 is a schematic structural diagram of another device for reading data from an external memory according to an embodiment of the present invention.

[0077] In one possible implementation, the instruction execution unit 13 includes: a programmable instruction queue 131, an instruction fetch circuit 133, and a decoding execution circuit 132; the programmable instruction queue 131 is used to store multiple operation instructions; the instruction fetch circuit 133 is used to read the target operation instruction in sequence from the programmable instruction queue 131 according to the storage sequence of the operation instructions in each clock cycle; the decoding execution circuit 132 is used to receive and parse the target operation instruction, and execute the operation corresponding to the target operation instruction according to the parsing result of the target operation instruction.

[0078] The programmable instruction queue 131 is used to store operation instructions for reading data from the external memory 3; the instruction fetch circuit 133 is connected to the programmable instruction queue 131, and the instruction fetch circuit 133 is used to obtain instructions from the programmable instruction queue 131 according to the instruction storage sequence in each clock cycle; the decoding circuit is connected to the instruction fetch circuit 133, and the decoding circuit is used to receive and parse the instructions obtained by the instruction fetch circuit 133, and perform corresponding operations based on the parsing results.

[0079] The programming interface access module of the embodiment of the present invention adopts a programmable instruction queue 131, has software scalability, can expand the function of the interface control module, and can cooperate with different interface controllers 2 to implement access to external memories 3 of various interfaces.

[0080] In one example, the instruction formats supported by the programmable instruction queue 131 are shown in Table 1:

[0081] Table 1

[0082]

[0083] It should be noted that the process of accessing the interface controller 2 is converted into a program in the programmable instruction queue 131 , so that the programmable interface access module 1 can initiate a request to access the external memory 3 .

[0084] The programmable interface access module 1 according to the embodiment of the present invention can replace all functions of DMA.

[0085] The specific execution process is shown in Table 2:

[0086] Table 2

[0087]

[0088]

[0089] It should be noted that when the value circuit takes out instructions from the programmable instruction queue 131, if the nth instruction is a jump instruction, it will choose to take out the n+1th instruction (no jump) or the mth instruction (jump) according to the result of the jump instruction.

[0090] The decoding circuit, comprised of combinational logic, translates instructions according to their encoding rules and executes the corresponding operations based on the result of instruction parsing. Since it only needs to support eight instructions, the entire instruction decoding circuit is very simple, smaller in size than traditional DMA, and more cost-effective.

[0091] Please refer to Figure 8 , Figure 8 3 is a schematic structural diagram of another device for reading data from an external memory according to an embodiment of the present invention.

[0092] In one possible implementation, the device also includes: a bus; a decoding execution circuit 132 and a memory respectively connected to the bus for communication; the decoding execution circuit 132 is further used to save the cached data to the memory corresponding to the first storage address through the bus when the data status information indicates that the interface controller 2 stores cached data.

[0093] The bus is the physical medium for data exchange between the decode execution circuit 132, the memory, and the interface controller 2. When the interface controller 2 has cached data, the decode execution circuit 132 transfers the cached data from the interface controller 2 to the memory via the bus, completing the migration of the cached data from the interface controller 2 to the memory.

[0094] Please refer to Figure 9 , Figure 9 3 is a schematic structural diagram of another device for reading data from an external memory according to an embodiment of the present invention.

[0095] In a possible implementation, the programmable interface access module 1 further includes: a plurality of other data registers 18 and a plurality of other address registers 19 ; the plurality of other data registers 18 and the plurality of other address registers 19 are respectively connected to the instruction execution unit 13 .

[0096] Since the programmable interface access module 1 and the interface controller 2 are connected through a universal bus, and the address of the status register 21 of the interface controller 2 is stored in the address register of the programmable interface access module 1, data transmission between a programmable interface access module 1 and multiple interface controllers 2 can be achieved by modifying the value of the address register that stores the address of the status register 21.

[0097] In a possible implementation, the data register group may further include other registers, each of which may implement different functions.

[0098] As an example, the data register group may include 8 data registers, and the 8 data registers may be D[0] to D[7], respectively. The specific data register allocation method is as follows:

[0099] D[0]: 1 (write D[0] to the startup register of interface controller 2 to start interface controller 2).

[0100] D[1]: transfer length, 1 / 2 / 4 (set according to the length of the cached data, if it is a byte access, it is 1; if it is a half-word access, it is 2; if it is a word access, it is 4).

[0101] D[2]: The starting address of cache data.

[0102] D[3]: Length of cached data.

[0103] D[4]: Working mode of interface controller 2.

[0104] D[5]: stores the data read from interface controller 2.

[0105] D[6]: Result of the comparison instruction (used to save the comparison result between the remaining cache data length and zero).

[0106] D[7]: data status information of the interface controller 2 mapped by the interface controller 2. 0 may indicate that there is no cached data, and 1 may indicate that there is cached data.

[0107] Among them, the above-mentioned D[7] can be the first data register 11, D[5] can be the second data register 14, D[1] can be the third data register 16, and D[3] can be the fourth data register 17.

[0108] In one possible implementation, the address register group may include 8 address registers, and the 8 data registers may be A[0] to A[7], respectively. The specific address register allocation method is as follows:

[0109] A[0]: Address of the startup register of interface controller 2.

[0110] A[1]: Reserved.

[0111] A[2]: Address of the starting address register of interface controller 2.

[0112] A[3]: Address of the length register of interface controller 2.

[0113] A[4]: Address of the working mode register of interface controller 2.

[0114] A[5]: Address of the receive data register of interface controller 2.

[0115] A[6]: Address in memory.

[0116] A[7]: Reserved.

[0117] The address register group stores the addresses of the registers of the interface controller 2 and the memory addresses where data is stored. The registers of the interface controller 2 include: data start address register, transfer mode register, start transfer register, receive data register, etc. 8 registers can be used to store these addresses.

[0118] Among them, the above-mentioned A[6] can be the first address register 12, and A[5] can be the second data register 14.

[0119] Please refer to Figure 10 , Figure 10 2 is a schematic diagram of the structure of an apparatus for reading data from an external memory according to an embodiment of the present invention.

[0120] In a possible implementation, there are multiple interface controllers 2 , and accordingly, there are multiple programmable interface access modules 1 ; each interface controller 2 is connected to multiple programmable interface access modules 1 .

[0121] The embodiment of the present invention can be extended to support the simultaneous operation of multiple interface controllers 2. If the system requires N interface controllers 2 to work simultaneously, only N programmable interface access modules 1 need to be instantiated.

[0122] In one example, each bit of D[7] corresponds to the RX FIFO status of an interface controller 2. For example, for a system with four interface controllers 2, D[7] should include four bits, and the definitions of the bits are shown in Table 3:

[0123] Table 3

[0124]

[0125] The number of interface controllers 2 is the same as the number of bits in the data register D[7]. When N interface controllers 2 are working simultaneously, each programmable interface access module 1 includes N interfaces. At this time, each programmable interface access module 1 can selectively read the cached data in any one or more of the N interface controllers 2.

[0126] Please refer to Figure 11 , Figure 11 2 is a schematic diagram of the structure of an apparatus for reading data from an external memory according to an embodiment of the present invention.

[0127] In one possible implementation, the interface controller 2 includes a status register 21 and a data memory 22; the status register 21 is used to store data status information; the first data register 11 is further used to map the data status information stored in the status register 21; the data memory 22 is used to obtain and store cache data from the external memory 3; the instruction execution unit 13 is further used to read the cache data from the data memory 22 according to the second storage address, and temporarily store the cache data in the second data register 14.

[0128] The cache data in the data memory 22 is read, and the cache data is sent to the second data register 14 according to the second storage address.

[0129] The status register 21 can be used to store data status information. The data memory 22 can be used to obtain and store cache data from the external memory 3. The data memory 22 can be an RX FIFO.

[0130] The first data register 11 can map the data status information stored in the status register 21. The data memory 22 can obtain and store cache data from the external memory 3. In other words, the data memory 22 can obtain cache data from the Flash memory. The instruction execution unit 13 reads the cache data from the data memory 22 according to the second storage address and temporarily stores the cache data in the second data register 14.

[0131] The programmable interface access module 1 and the interface controller 2 are both electrically connected to a bus, which may include an APB bus, an AHB bus, an AXI bus, and the like.

[0132] The interface controller 2 may further include a transmitting / receiving circuit 24 , a data transmitter 23 , and a control register 25 .

[0133] The data transmitter 23 may be a TX FIFO, etc. The data transmitter 23 is configured to send the cached data stored in the memory corresponding to the first storage address to the external memory 3 via the transmit / receive circuit 24. The MCU 4 accesses the external storage device by configuring the control register 25 and obtains the status of the data transmission through the status register 21.

[0134] The present invention uses a programmable interface access module instead of a traditional DMA, enabling timely access to cached data in the RX FIFO. This prevents the interface controller from storing large amounts of cached data in the RX FIFO. This also eliminates the need for a large cache area within the programmable interface access module, reducing the depth of the RX FIFO and, consequently, the area of the interface controller. Furthermore, during data transmission, the MCU is freed up to handle other tasks, thereby improving system processing capabilities.

[0135] Please refer to Figure 12 , Figure 12 FIG. 1 is a flow chart of a method for reading data from an external memory according to an embodiment of the present invention. Figure 12 As shown, the method is applied to a device for reading data from an external memory, and the method comprises the following steps:

[0136] Step S101 , reading data status information of the interface controller from the first data register; wherein the data status information is used to indicate whether the interface controller stores cache data, and the cache data is obtained from the external memory 3 .

[0137] Step S102 : when the data status information indicates that the interface controller stores cache data, read a first storage address corresponding to the cache data in the first address register, and save the cache data to a memory corresponding to the first storage address.

[0138] Data status information indicates whether the data receiving buffer unit RX FIFO contains cached data. When the RX FIFO contains cached data, the status flag in the status register is a non-empty flag or a data-present flag, indicating that cached data is available for reading in the RX FIFO. When the RX FIFO contains cached data, the status flag in the status register is an empty flag or a data-absent flag, indicating that no cached data is available for reading in the RX FIFO. When the status flag in the status register is a non-empty flag or a data-present flag, indicating that cached data is available for reading in the RX FIFO, the reading of the current status information in the status register can be suspended. The cached data in the RX FIFO can then be retrieved and saved via the bus, thereby completing the reading of data from the external memory.

[0139] In the method for reading data from an external memory provided by an embodiment of the present invention, the first data register can map data status information stored in the interface controller, so that the instruction execution unit reads the data status information directly from the first data register, and when the data status information indicates that the interface controller stores cached data, the cached data is saved to the memory corresponding to the first storage address. Compared with the method of configuring DMA through the MCU in the related art, the RX FIFO inside the interface controller is avoided from storing a large amount of cached data, thereby eliminating the need to increase the area of the interface controller, thereby reducing costs.

[0140] In this embodiment, a device for reading data from an external memory is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0141] refer to Figure 13, which shows a structural schematic diagram of a computer device provided by an embodiment of the present invention, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication, and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system).

[0142] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0143] The memory 20 stores instructions that can be executed by at least one processor 10, so as to enable at least one processor 10 to execute the method shown in the above embodiment.

[0144] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0145] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0146] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means.

[0147] The input device 30 can receive input digital or character information and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touch pad, an indicator stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), and a tactile feedback device (e.g., a vibration motor). The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0148] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A device for reading data from an external memory, characterized in that: The device comprises: a programmable interface access module and an interface controller, wherein the programmable interface access module comprises a first data register, a first address register and an instruction execution unit; The interface controller is used to store data status information; wherein the data status information is used to indicate whether the interface controller stores cache data, and the cache data is obtained by the interface controller from the external memory; The first data register is used to map the data status information stored by the interface controller; The first address register is used to send a first storage address corresponding to the cache data to the instruction execution unit; The instruction execution unit is configured to read the data status information from the first data register, and when the data status information indicates that the interface controller stores cache data, save the cache data to the memory corresponding to the first storage address.

2. The device for reading data from an external memory according to claim 1, wherein: The programmable interface access module further includes: a second data register; The second data register is used to temporarily store cache data read from the interface controller; The instruction execution unit is further configured to save the cache data temporarily stored in the second data register to the memory corresponding to the first storage address when the data status information indicates that the interface controller stores cache data.

3. The device for reading data from an external memory according to claim 2, wherein: The programmable interface access module further includes: a second address register, wherein the second address register stores a second storage address; The second address register is used to send a second storage address corresponding to the cache data to the instruction execution unit; The instruction execution unit is further configured to read cache data from the interface controller according to the second storage address, and save the cache data to the second data register.

4. The device for reading data from an external memory according to claim 3, wherein: The programmable interface access module further includes: a third data register, wherein the third data register stores a transmission length of the cached data; The instruction execution unit is further configured to read cache data from the interface controller according to the second storage address and a transmission length of the cache data, and save the cache data to the second data register.

5. The device for reading data from an external memory according to claim 4, wherein: The programmable interface access module further includes: a fourth data register, wherein the fourth data register stores a data length of the cached data; The instruction execution unit is further used to update the data length of the cache data according to the transmission length of the cache data after saving the cache data to the memory corresponding to the storage address, and determine the remaining data length stored in the fourth data register, wherein when the remaining data length is greater than the preset length, the data status information is read from the first data register again.

6. The device for reading data from an external memory according to claim 1, wherein: The instruction execution unit includes: a programmable instruction queue, an instruction fetch circuit and a decoding execution circuit; The programmable instruction queue is used to store multiple operation instructions; The instruction fetch circuit is used to sequentially read target operation instructions from the programmable instruction queue according to the storage sequence of the operation instructions in each clock cycle; The decoding and execution circuit is used to receive and parse the target operation instruction, and execute the operation corresponding to the target operation instruction according to the parsing result of the target operation instruction.

7. The device for reading data from an external memory according to claim 6, wherein: The device further includes: a bus; the decoding execution circuit and the memory are respectively connected to the bus for communication; The decoding execution circuit is further configured to save the cached data to the memory corresponding to the first storage address via a bus when the data status information indicates that the interface controller stores cached data.

8. The device for reading data from an external memory according to claim 1, wherein: The programmable interface access module further includes: a plurality of other data registers and a plurality of other address registers; The plurality of data registers and the plurality of address registers are respectively connected to the instruction execution unit.

9. The device for reading data from an external memory according to claim 1, wherein: There are multiple interface controllers, and correspondingly, there are multiple programmable interface access modules; each interface controller is connected to multiple programmable interface access modules.

10. The device for reading data from an external memory according to claim 3, wherein: The interface controller includes a status register and a data memory; The status register is used to store data status information; The first data register is further used to map the data status information stored in the status register; The data memory is used to obtain and store cache data from the external memory; The instruction execution unit is further configured to read cache data in the data memory according to the second address register, and temporarily store the cache data in the second data register.

11. A method for reading data from an external memory, characterized in that: The method is applied to a device for reading data from an external memory, and the method includes: Reading data status information of the interface controller from the first data register; wherein the data status information is used to indicate whether the interface controller stores cache data, and the cache data is obtained from the external memory; When the data status information indicates that the interface controller stores cache data, a first storage address corresponding to the cache data in the first address register is read, and the cache data is saved in a memory corresponding to the first storage address.

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