Inter-core communication method and device and multi-core processor

Abstract

The invention provides an inter-core communication method and device and a multi-core processor, relates to the technical field of communication, and is used for improving the inter-core communication efficiency of the multi-core processor. The method is applied to a first core in the multi-core processor, the first core is any processor core in the multi-core processor, each processor core in the multi-core processor is pre-configured with an idle descriptor list, and the idle descriptor list comprises idle descriptors capable of being used by the corresponding processor core; the method comprises the following steps: acquiring a first descriptor from a first idle descriptor list; filling the first descriptor with first data to be sent; and sending the filled first descriptor to the second core.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an inter-core communication method, device, and multi-core processor. Background Art

[0002] With the rapid development of computer technology, single-core processors are no longer able to meet the growing demand for parallel computing. To overcome this bottleneck, multi-core processors have emerged, significantly improving overall computing performance by integrating multiple computing cores on a single chip.

[0003] However, when multi-core processors run in parallel, efficient communication between different processor cores becomes a key factor affecting computing performance. Therefore, how to improve the efficiency of inter-core communication in multi-core processors is an urgent problem that needs to be solved. Summary of the Invention

[0004] The present application provides an inter-core communication method, device, and multi-core processor for improving the inter-core communication efficiency of a multi-core processor.

[0005] In a first aspect, an embodiment of the present application provides an inter-core communication method, which is applied to the first core in a multi-core processor, wherein the first core is any processor core in the multi-core processor, and each processor core in the multi-core processor is pre-configured with an idle descriptor list, and the idle descriptor list includes idle descriptors that can be used by the corresponding processor core; the method includes: obtaining a first descriptor from the first idle descriptor list; filling first information into the first descriptor, wherein the first information includes the storage address of the first data to be sent or the first data to be sent; and sending the filled first descriptor to the second core so that the second core obtains the first data through the first information.

[0006] In an embodiment of the present application, each processor core of a multi-core processor is pre-configured with an idle descriptor list, which contains idle descriptors that can be used by the processor core. When inter-core communication is required, each processor core can obtain an idle descriptor from its corresponding idle descriptor list and use the descriptor to actively send data to other processor cores. Compared with traditional inter-core communication methods, the inter-core communication method provided in an embodiment of the present application breaks through the limitation that the receiving core cannot actively send data to the sending core. Through this improvement, two-way active communication can be achieved between any two processor cores in a multi-core processor, thereby improving the inter-core communication efficiency and flexibility of the multi-core processor.

[0007] In a possible implementation, the first descriptor is a descriptor recovered by the first core from a first used queue, and the first used queue is used to store descriptors sent by the first core to the second core and used by the second core.

[0008] In this embodiment, the first core can reclaim the descriptors used by the second core from the first used queue, thereby realizing the recycling of descriptors, solving the communication limitation problem caused by the limited number of descriptors, and improving the efficiency of inter-core communication.

[0009] In one possible embodiment, a first local index list is pre-configured in the first core, and the first local index list is used to record the descriptors that the first core has recovered from the first used queue. Before obtaining the first descriptor from the first free descriptor list, the method also includes: cyclically checking the maximum index value of the first local index list and the maximum index value in the first used queue; when the maximum index value in the first used queue is greater than the maximum index value of the first local index list, determining that the first used queue includes an unrecovered first descriptor; and recycling the unrecovered first descriptor to the first free descriptor list to obtain the first descriptor.

[0010] In this embodiment, a first local index list is used to record descriptors that the first core has recovered from the first used queue. Based on this, the first core can compare the first local index list with the index value of the first used queue to quickly and accurately determine the unrecovered descriptors in the first used queue, which helps reduce access overhead to the first used queue. Furthermore, by scanning the first used queue in a cyclic check, unrecovered descriptors in the first used queue can be promptly discovered and promptly recovered to the first free descriptor list for subsequent communication use, thereby improving descriptor recovery efficiency.

[0011] In a possible implementation, before recycling the unrecycled first descriptor to the first free descriptor list to obtain the first descriptor, the method further includes: determining whether the unrecycled first descriptor is bound to a legal memory address; recycling the unrecycled first descriptor to the first free descriptor list to obtain the first descriptor includes: if the unrecycled first descriptor is bound to a legal memory address, releasing the first memory block corresponding to the memory address, and recycling the unrecycled first descriptor to the first free descriptor list to obtain the first descriptor.

[0012] In this embodiment, when reclaiming an unprocessed first descriptor to the first free descriptor list, it is first necessary to determine whether the descriptor carries a valid buffer. If the descriptor does carry a valid buffer, the memory resources occupied by it should be released in a timely manner to avoid meaninglessly occupying memory resources for a long time, thereby improving memory resource utilization.

[0013] In a possible implementation, sending the filled first descriptor to the second core includes: sending the first descriptor to be filled to the second core through a first shared memory, where the first shared memory is a shared memory corresponding to a communication path from the first core to the second core.

[0014] In this implementation, the first shared memory is a private shared memory configured specifically for the communication path from the first core to the second core, and is isolated from the shared memories corresponding to other communication paths. This design effectively avoids contention or conflicts that may arise from multiple cores concurrently accessing shared memory in a multi-core processor, thereby improving the reliability and stability of inter-core communication in the multi-core processor.

[0015] In a second aspect, an embodiment of the present application provides an inter-core communication method, which is applied to the second core in a multi-core processor, wherein the second core is any processor core in the multi-core processor except the first core, and each processor core in the multi-core processor is pre-configured with an idle descriptor list, and the idle descriptor list includes idle descriptors that can be used by the corresponding processor core; the method includes: obtaining a filled first descriptor sent by the first core, and obtaining first data through first information in the filled first descriptor, the first information including the storage address of the first data or the first data; obtaining a second descriptor from a second idle descriptor list; filling the second information into the second descriptor, the second information including the storage address of the second data to be sent or the second data to be sent; sending the filled second descriptor to the first core, so that the first core obtains the second data through the second information.

[0016] In a possible implementation, the second descriptor is a descriptor recovered by the second core from a second used queue, and the second used queue is used to store descriptors sent by the second core to the first core and used by the first core.

[0017] In one possible embodiment, a second local index list is pre-configured in the second core, and the second local index list is used to record the descriptors that the second core has recovered from the second used queue. Before obtaining the second descriptor from the second free descriptor list, the method also includes: cyclically checking the maximum index value of the second local index list and the maximum index value of the second used queue; when the maximum index value of the second used queue is greater than the maximum index value of the second local index list, determining that the second used queue includes the unrecovered second descriptor; and recycling the unrecovered second descriptor to the second free descriptor list to obtain the second descriptor.

[0018] In a possible implementation, before recycling the unrecycled first descriptor to the second free descriptor list to obtain the second descriptor, the method further includes: determining whether the unrecycled second descriptor is bound to a legal memory address; recycling the unrecycled second descriptor to the second free descriptor list to obtain the second descriptor includes: if the unrecycled second descriptor is bound to a legal memory address, releasing the second memory block corresponding to the memory address, and recycling the unrecycled second descriptor to the second free descriptor list to obtain the second descriptor.

[0019] In one possible embodiment, a third local index list is pre-configured in the second core, and the third local index list is used to record the descriptors that the second core has read from the first sending queue. The first sending queue is used to store the descriptors sent by the first core to the second core, and obtaining the filled first descriptor sent by the first core includes: cyclically checking the maximum index value of the third local index list and the maximum index value of the first sending queue; when the maximum index value of the first sending queue is greater than the maximum index value of the third local index list, determining that the first sending queue includes the unprocessed filled first descriptor; and obtaining the unprocessed filled first descriptor from the first sending queue.

[0020] In a possible implementation, sending the filled second descriptor to the first core includes: sending the filled second descriptor to the first core through a second shared memory, where the second shared memory is a shared memory corresponding to a communication path from the second core to the first core.

[0021] In a third aspect, an embodiment of the present application provides an inter-core communication device, which is applied to the first core in a multi-core processor, where the first core is any processor core in the multi-core processor, and each processor core in the multi-core processor is pre-configured with an idle descriptor list, where the idle descriptor list includes idle descriptors that can be used by the corresponding processor core; the inter-core communication device includes: an acquisition module for acquiring a first descriptor from the first idle descriptor list; a filling module for filling first information into the first descriptor, where the first information includes the storage address of the first data to be sent or the first data to be sent; and a transceiver module for sending the filled first descriptor to the second core, so that the second core obtains the first data through the first information.

[0022] In a fourth aspect, an embodiment of the present application provides an inter-core communication device, which is applied to the second core in a multi-core processor, where the second core is any processor core in the multi-core processor except the first core, and each processor core in the multi-core processor is pre-configured with an idle descriptor list, which includes idle descriptors that can be used by the corresponding processor core; the inter-core communication device includes: a transceiver module, which is used to obtain the filled first descriptor sent by the first core, and obtain the first data through the first information in the filled first descriptor, where the first information includes the storage address of the first data or the first data; an acquisition module, which is used to obtain the second descriptor from the second idle descriptor list; a filling module, which is used to fill the second information into the second descriptor, where the second information includes the storage address of the second data to be sent or the second data to be sent; the transceiver module is also used to send the filled second descriptor to the first core, so that the first core obtains the second data through the second information.

[0023] In a fifth aspect, an embodiment of the present application provides a multi-core processor, comprising: multiple processor cores, the multiple processor cores including at least a first core and a second core; and a memory communicatively connected to the multiple processor cores; wherein the memory stores instructions that can be executed by the multiple processor cores, and the first core or the second core of the multiple processor cores implements the method described in the first aspect and any possible implementation method or the second aspect and any possible implementation method by executing the instructions stored in the memory.

[0024] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a multi-core processor, it implements the method described in the first aspect and any possible implementation method or the second aspect and any possible implementation method.

[0025] In a seventh aspect, an embodiment of the present application provides a computer program product, comprising a computer program, which, when executed by a multi-core processor, implements the method described in the first aspect and any possible implementation method or the second aspect and any possible implementation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A schematic diagram of the structure of a multi-core processor provided in an embodiment of the present application Figure 1 ;

[0028] Figure 2 A schematic diagram of a process for inter-core communication provided in an embodiment of the present application Figure 1 ;

[0029] Figure 3 A flowchart of a method for recovering a first descriptor provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of a process for inter-core communication provided in an embodiment of the present application Figure 2 ;

[0031] Figure 5 A schematic diagram of a communication architecture between a first core and a second core provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of a process for inter-core communication provided in an embodiment of the present application Figure 3 ;

[0033] Figure 7 A schematic diagram of the structure of an inter-core communication device provided in an embodiment of the present application Figure 1 ;

[0034] Figure 8 A schematic diagram of the structure of an inter-core communication device provided in an embodiment of the present application Figure 2 ;

[0035] Figure 9 Schematic diagram of the structure of the multi-core processor provided in the embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0036] The technical solution in this application will be described below with reference to the accompanying drawings.

[0037] In order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the first instruction and the second instruction are intended to distinguish different user instructions and do not limit their order. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0038] It should be noted that, in this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a concrete manner.

[0039] In addition, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c, where a, b, c can be single or multiple.

[0040] In addition, the terms "including" and "having" and any variations thereof in the embodiments and drawings of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to the process, method, product, or apparatus.

[0041] In order to better understand the inter-core communication method provided in the embodiment of the present application, the background technology related to the embodiment of the present application is briefly described below.

[0042] Currently, mainstream inter-core communication methods are primarily based on shared memory and inter-core interrupt mechanisms. Based on this, traditional inter-core communication methods are typically implemented using a master-slave architecture: the master core (sender) manages a descriptor pool and obtains free descriptors to send data to the slave core (receiver). However, the slave core lacks the ability to actively send data, resulting in asymmetric inter-core communication. This master-slave architecture faces significant bottlenecks in high-frequency communication scenarios within multi-core processors. When inter-core communication is frequent and requires low latency, the inefficiency of traditional inter-core communication methods becomes particularly prominent, making it difficult to meet the performance requirements of current multi-core processors.

[0043] To address the above issues, embodiments of the present application provide an inter-core communication method that can be applied to the first core in a multi-core processor. The first core is any processor core in the multi-core processor. Each processor core in the multi-core processor is pre-configured with a free descriptor list, which includes free descriptors available to the corresponding processor core. Based on this, the first core can obtain a first descriptor from the first free descriptor list; fill the first descriptor with first information, where the first information includes the storage address of first data to be sent or the first data to be sent; and finally, the first core sends the filled first descriptor to the second core, so that the second core can obtain the first data through the first information.

[0044] It can be seen that in the inter-core communication method provided in the embodiment of the present application, any processor core in the multi-core processor can obtain the idle descriptor from the corresponding idle descriptor list and send data to other processor cores, thereby achieving communication symmetry between any two cores in the multi-core processor, breaking through the limitation that the slave core cannot actively send data in the traditional master-slave architecture design, and improving the inter-core communication efficiency in the multi-core processor.

[0045] In order to better understand the inter-core communication method provided in the embodiment of the present application, Figure 1 The structural diagram of a multi-core processor shown in the figure introduces the multi-core processor involved in the embodiment of the present application.

[0046] Please refer to Figure 1 , which is a schematic diagram of the structure of a multi-core processor provided in an embodiment of the present application Figure 1 .like Figure 1 As shown, the multi-core processor 100 integrates multiple processor cores in one chip. These processor cores have the same or different functions and structures, are integrated into the same chip in an effective way, and allocate applications to different processor cores for parallel processing in an effective partitioning manner, thereby improving the performance of the processor system. The multi-core processor 100 can be located in any electronic device, such as a computer, a computer, a mobile phone, a tablet, a personal digital assistant, a smart wearable device, a smart car or a smart home appliance. The multi-core processor 100 can specifically be a chip or a chipset or a circuit board equipped with a chip or a chipset. The chip or chipset or the circuit board equipped with a chip or a chipset can work under the necessary software drive.

[0047] Specifically, multiple processor cores ( Figure 1Taking F as an example, F is an integer greater than or equal to 2), such as processor core 1011, processor core 1012... processor core 101F, which is the abbreviation of processor core, also known as kernel, is the most important component of the central processing unit (CPU). It is made of single crystal silicon with a certain production process. All calculations, command reception or storage commands, and data processing of the CPU are performed by the processor core. The processor cores can be homogeneous or heterogeneous, that is, the structure between the processor core (1012...101F) and the processor core 1011 can be the same or different, and the embodiment of the present invention does not make specific restrictions on this. The type of processor core can be a matrix acceleration unit, a vector processor unit, a general processor unit, an AI processor unit, a graphics processor unit, a video processor unit, a direct storage unit, a sensor processing unit, etc., and the embodiment of the present invention does not make specific restrictions on this. It can be understood that the processor core 1011 and the (F-1) processor cores can communicate through a bus or other coupling methods, which is not specifically limited here. When multiple processor cores run the same task in parallel, data synchronization between the cores is inevitable, that is, communication between the processor cores is required.

[0048] Memory 102 (Memory) may be located inside the multi-core processor 100 and may be an internal shared memory of the multi-core processor 100. In an embodiment of the present application, memory 102 can be used to implement inter-core communication of a multi-core processor. For example, memory 102 is used to store descriptors required for transmitting data. It should be noted that memory 102 may be a shared memory of multiple processor cores, that is, a memory that can be accessed by different processor cores in a computer system with multiple processor cores. In specific use, memory 102 may also be divided into multiple storage areas, each used for communication between different processor cores. Memory 102 is, for example, a static random access memory (SRAM).

[0049] The memory 103 may be located outside the multi-core processor 100 and may be an external shared memory of the multi-core processor 100. In an embodiment of the present application, the memory 103 can be used to temporarily store communication data for inter-core communication in the multi-core processor. For example, the memory 103 can store data sent by the processor core 1011 to the processor core 1012. It should be noted that the memory 103 can be a shared memory of multiple processor cores, that is, a memory that can be accessed by different processor cores in a computer system with multiple processor cores. In specific use, the memory 103 can also be divided into multiple storage areas, each used for communication between different processor cores. The memory 103 is, for example, a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), etc. Among them, DRAM includes Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), referred to as DDR, second-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR2), third-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR3), fourth-generation Low Power Double Data Rate 4 (LPDDR4) and fifth-generation Low Power Double Data Rate 5 (LPDDR5).

[0050] In an embodiment of the present application, each processor core in a multi-core processor is pre-configured with an idle descriptor list, which includes idle descriptors that can be used by the corresponding processor core. Each processor core can then obtain idle descriptors from the corresponding idle descriptor list and use the idle descriptors to send data to other processor cores in the multi-core processor to achieve mutual communication between any two cores in the multi-core processor, thereby improving the communication efficiency of the multi-core processor. For the specific implementation method, please refer to the subsequent description of the inter-core communication method.

[0051] It is understandable that Figure 1 The structure of the multi-core processor 100 in the embodiment of the present application is some exemplary implementation methods provided in the embodiments of the present application. The structure of the multi-core processor in the embodiments of the present application includes but is not limited to the above implementation methods.

[0052] The following will be combined Figure 2 The flowchart of an inter-core communication method shown in FIG. 1 is a detailed description of the inter-core communication method provided in an embodiment of the present application.

[0053] Please refer to Figure 2 , which is a flow diagram of an inter-core communication method provided in an embodiment of the present application Figure 1The following is executed by the first core in the multi-core processor. Figure 2 The inter-core communication method shown is explained. Figure 2 The inter-core communication method shown can be applied to Figure 1 In the multi-core processor shown, Figure 2 The multi-core processors involved are, for example, Figure 1 The multi-core processor 100 shown, Figure 2 The first core involved is, for example, any processor core from the processor core 1011 to the processor core 101F. Figure 2 The second core involved is, for example, any core among the processor cores 1011 to 101F except the first core.

[0054] S201, a first core obtains a first descriptor from a first free descriptor list, wherein the first core is any processor core in a multi-core processor, each processor core in the multi-core processor is pre-configured with a free descriptor list, and the free descriptor list includes free descriptors that can be used by the corresponding processor core.

[0055] The first idle descriptor list is an idle descriptor list corresponding to the first core. The first descriptor may be an idle descriptor pre-configured in the first idle descriptor list. In other words, the first descriptor may be an idle descriptor pre-assigned to the first core.

[0056] Specifically, the shared memory of multi-core processors (such as Figure 1 The memory 102 shown may include a descriptor pool that includes all descriptors that can be used by the multi-core processor. During the initialization phase or before startup of the multi-core processor, all descriptors in the descriptor pool will be allocated to each processor core in the multi-core processor, and these allocated descriptors will be placed in the free descriptor list of the corresponding processor core. It should be understood that the process of placing a descriptor in the corresponding free descriptor list is essentially writing the position information of the descriptor in the descriptor pool into the free descriptor list. The position information is, for example, the index of the free descriptor in the descriptor pool.

[0057] Since the number of descriptors in the descriptor pool is limited, the number of descriptors allocated to each processor core is also limited. Therefore, when allocating descriptors, all descriptors in the descriptor pool can be evenly distributed across multiple processor cores; alternatively, descriptors can be dynamically allocated based on the actual communication needs of each processor core, although this is not limited in the present embodiment.

[0058] For example, a multi-core processor includes a first core and a second core, and the descriptor pool includes descriptors 1, 2, 3, 4, 5, and 6. Descriptors 1, 2, and 3 can be assigned to the first core, and descriptors 4, 5, and 6 can be assigned to the second core.

[0059] S202 : The first core fills first information into the first descriptor, where the first information includes a storage address of first data to be sent or the first data to be sent.

[0060] In order to adapt to different transmission requirements, when sending data through the first descriptor, the first core selects an appropriate transmission mode according to the size of the first data.

[0061] Specifically, when the size of the first data is larger than the data size that the first descriptor can carry, the first core may allocate an additional memory block to the first descriptor to store the first data and write the storage address of the first data into the first descriptor. In particular, when allocating the additional memory block, the first core may allocate a memory block that matches the size of the first data to the first descriptor based on the size of the first data, thereby improving memory resource utilization. In this case, the first information includes the storage address of the first data.

[0062] When the size of the first data is less than or equal to the data size that the first descriptor can carry, the first core can fill the first data into the first descriptor without allocating additional memory. In this case, the first information includes the first data.

[0063] For example, if the size of the data that the first descriptor can carry is 64 bytes, if the size of the first data to be sent is 128 bytes and the size of the first data is larger than the carrying capacity of the descriptor, the first core allocates an additional memory block to store the first data and fills the storage address of the memory block into the first descriptor. If the size of the first data to be sent is 32 bytes and the size of the first data is smaller than the carrying capacity of the first descriptor, the first core can directly fill the first data into the first descriptor.

[0064] It should be noted that due to the internal shared memory of the multi-core processor (such as Figure 1 The memory 102 shown in FIG. 102 has fewer resources, so the external shared memory of the multi-core processor (such as Figure 1 The memory 103 shown stores inter-core communication data of the multi-core processor.

[0065] S203: The first core sends the filled first descriptor to the second core, so that the second core obtains the first data through the first information.

[0066] In a multi-core processor, a communication channel is pre-assigned for communication between every two processor cores, that is, the first core and the second core communicate through the pre-assigned communication channel.

[0067] Exemplarily, a multi-core processor includes three processor cores A, B, and C, wherein core A communicates with core B through a pre-allocated first communication channel, core B communicates with core C through a pre-allocated second communication channel, and core A communicates with core C through a pre-allocated third communication channel.

[0068] In the field of inter-core communication, processor cores typically communicate with each other based on shared memory and an inter-core interrupt mechanism. In the embodiment of the present application, the first core sending the filled first descriptor to the second core is also based on shared memory and an inter-core interrupt mechanism.

[0069] Specifically, the first core places the padded first descriptor into a first send queue in the shared memory, which is used to store descriptors sent by the first core to the second core. The first core then triggers an interrupt to notify the second core to receive the padded first descriptor, so that the second core retrieves the padded first descriptor from the first send queue in the shared memory and obtains the first data based on the first information.

[0070] If the first information includes the storage address of the first data, the second core retrieves the first data from the corresponding memory block based on the storage address. In this case, the first information may specifically include an offset relative to the starting address, and based on the offset, the second core can directly calculate the storage address of the first data.

[0071] By transmitting data in this way, the receiving core can directly access the data to be transmitted in the shared memory. Compared with the traditional communication method, it eliminates the step of copying data from the shared memory to the local memory of the receiving core, thereby improving the efficiency of inter-core communication.

[0072] If the first information includes the first data, the second core may directly obtain the first data from the filled first descriptor.

[0073] It should be understood that the first core puts the first descriptor into the first sending queue and also needs to maintain the index of the first sending queue to ensure the correctness of the first sending queue.

[0074] In one possible implementation, the first core may send a to-be-filled first descriptor to the second core via a first shared memory. The first shared memory is the shared memory corresponding to the communication path from the first core to the second core. In layman's terms, the first shared memory is a dedicated shared memory for sending data from the first core to the second core, and the first shared memory is isolated from shared memories corresponding to other communication paths in the multi-core processor.

[0075] That is to say, other processor cores except the first core and the second core in the multi-core processor cannot access the first shared memory. In this way, the problem of multiple cores in the multi-core processor concurrently accessing the same shared memory resource can be avoided, which is conducive to improving the reliability and stability of inter-core communication.

[0076] In one possible implementation, the first descriptor may be retrieved by the first core from a first used queue, where the first used queue is used to store descriptors sent by the first core to the second core and used by the second core. Recycling descriptors from the first used queue enables descriptor recycling, which helps improve descriptor resource utilization.

[0077] The first used queue may also be configured in the first shared memory.

[0078] In this embodiment, the first core may reclaim used descriptors in batches from the first used queue, including the first descriptor, for example, by performing an initialization operation.

[0079] However, in high-frequency communication scenarios, since the number of usable descriptors pre-allocated to each processor core is limited, the batch recovery method may cause recovery delays, affecting the efficiency of inter-core communication. Therefore, an embodiment of the present application also provides a descriptor recovery method, by pre-configuring a first local index list in the first core, the first local index list is used to record the descriptors that the first core has recovered from the first used queue. Based on this, the first core can periodically poll and compare the first local index list with the index value in the first used queue to quickly and accurately recover the unrecovered descriptors from the first used queue. In this way, the problem of untimely recovery in the batch recovery method is solved, the recovery efficiency of the descriptors is improved, and it is beneficial to improve the efficiency of inter-core communication.

[0080] The following takes the first core recycling the first descriptor as an example, combined with Figure 3 The flowchart of a method for recycling a first descriptor shown in FIG. 1 is used to describe in detail the descriptor recycling method provided in an embodiment of the present application.

[0081] Please refer to Figure 3 , is a flow chart of a method for recovering a first descriptor provided in an embodiment of the present application. The following is a flow chart of a method for recovering a first descriptor provided in an embodiment of the present application. Figure 3 The steps shown are explained.

[0082] S301 , the first core cyclically checks the maximum index value of the first local index list and the maximum index value of the first used queue.

[0083] It should be understood that after the second core has used the descriptor, it puts it into the first used queue. Only then can the first core reclaim the descriptor used by the second core from the first used queue. Therefore, the update time of the first used queue is earlier than the update time of the first local index list, and the index of the first local index list should lag behind the index of the first used queue.

[0084] In order to be able to promptly discover the descriptors used by the second core, the first core can use a periodic polling mechanism to cyclically check the maximum index value of the first local index list and the maximum index value of the first used queue, so as to determine whether the first used queue includes unrecycled first descriptors, that is, execute step S302.

[0085] S302 : When the maximum index value in the first used queue is greater than the maximum index value in the first local index list, the first core determines that the first used queue includes an unreclaimed first descriptor.

[0086] If it is found that the maximum index value of the first local index list is equal to the maximum index value of the first used queue, it can be determined that the descriptors in the first used queue have been recycled to the first free descriptor list. If it is found that the maximum index value of the first used queue is greater than the maximum index value of the first local index list, it can be determined that the first used queue includes unrecycled first descriptors and they need to be recycled promptly, i.e., step S303 is executed.

[0087] S303 : The first core recycles the unrecycled first descriptor into a first free descriptor list to obtain the first descriptor.

[0088] Specifically, the first core may read the position information of the unreclaimed first descriptor in the descriptor pool from the first used queue, and write the position information into the first free descriptor list, thereby reclaiming the first descriptor.

[0089] For example, each index in the first used queue corresponds to an item, which records the location information of the corresponding descriptor in the descriptor pool. Therefore, after the first core determines the unreclaimed first descriptor from the first used queue, it can read the corresponding item to obtain the location information of the first descriptor and reclaim the first descriptor.

[0090] In addition, the entry may also include the data length information actually processed by the second core in the corresponding descriptor. Based on this data length information, the first core can also determine whether the descriptor has been effectively used by the second core, thereby further confirming whether the descriptor can be safely recycled.

[0091] The entry may be written by the second core when placing the used first descriptor into the first used queue.

[0092] Since the first local index list records the descriptors that the first core has recovered from the first used queue, and the first used queue records the descriptors used by the second core, the first core can promptly discover the descriptors used by the second core by polling the maximum index value of the first local index list and the maximum index value of the first used queue, and thus promptly recover them to the first free descriptor list for subsequent communication, thereby improving the descriptor recovery efficiency and further improving the efficiency of inter-core communication.

[0093] In one possible implementation, when the first descriptor is used to transmit data, the first descriptor may be associated with an additional memory block. Therefore, when the first core reclaims the first descriptor, if the first descriptor is associated with a valid memory block, the valid memory block must be released, and then the unreclaimed first descriptor is reclaimed into the first free descriptor list.

[0094] Specifically, the first core may determine whether the unrecycled first descriptor is bound to a valid memory address, thereby determining whether the first descriptor is associated with a valid memory block. If the unrecycled first descriptor is bound to a valid memory address, the first memory block corresponding to the memory address is released, and the unrecycled first descriptor is recycled into the first free descriptor list to obtain the first descriptor.

[0095] In actual applications, the first core may also determine whether the first descriptor is associated with a valid memory block by other means. For example, the first core may determine whether the first descriptor is associated with a valid memory block based on a status field in the first descriptor, where the status field indicates the status of the memory block associated with the first descriptor.

[0096] In the case where the first descriptor is associated with a valid memory block, releasing the valid memory block associated with the first descriptor while recycling the first descriptor can ensure that memory resources can be correctly released and improve memory resource utilization.

[0097] In one possible implementation, the first send queue and the first used queue may be a ring buffer structure. In this implementation, the queue indexes of the first send queue and the first used queue may be maintained in a ring logic by performing a modulo operation. For example, if the ring buffer size is N=8 and the current index is 7, the next write index should be 0.

[0098] In one possible implementation, the first sending queue and the first used queue may be combined into one queue, and the status of the descriptors may be distinguished by a flag bit. For example, a flag bit 1 indicates that the descriptor is currently in use, or a flag bit 0 indicates that the descriptor is currently in a waiting state.

[0099] After the first core sends the filled first descriptor to the second core, the second core can obtain the filled first descriptor sent by the first core. In addition, the second core can also send the second data to the first core based on the corresponding second free descriptor list. Figure 4 Schematic diagram of a process of inter-core communication method shown Figure 2 , the inter-core communication process between the second core and the first core is described in detail.

[0100] Please refer to Figure 4 , which is a flow diagram of an inter-core communication method provided in an embodiment of the present application Figure 2 The following is executed by the second core. Figure 4 The steps shown are explained. Figure 4 The inter-core communication method shown can be applied to Figure 1 In the multi-core processor shown, Figure 4 The multi-core processors involved are, for example, Figure 1 The multi-core processor 100 shown, Figure 4 The first core involved is, for example, any processor core from the processor core 1011 to the processor core 101F. Figure 4 The second core involved is, for example, any processor core among the processor cores 1011 to 101F except the first core.

[0101] S401, the second core obtains the filled first descriptor sent by the first core, and obtains the first data through the first information in the filled first descriptor, wherein the first information includes the storage address of the first data or the first data; the first core is any processor core in the multi-core processor, and the second core is any processor core in the multi-core processor except the first core, and each processor core in the multi-core processor is pre-configured with an idle descriptor list, and the idle descriptor list includes idle descriptors that can be used by the corresponding processor core.

[0102] The specific content of the free descriptor list may correspond to the content described in the above step S201 and will not be repeated here.

[0103] In this embodiment of the present application, communication between processor cores is achieved through shared memory and an inter-core interrupt mechanism. Therefore, upon receiving the interrupt signal triggered by the first core, the second core can retrieve the populated first descriptor from the first transmit queue in the shared memory and obtain the first data based on the first information in the populated first descriptor. The specific manner in which the second core obtains the first data based on the first information corresponds to the description of step S203 above and will not be repeated here.

[0104] In one possible implementation, the second core retrieves the populated first descriptor from the first transmit queue of the first shared memory. The first shared memory is the shared memory corresponding to the communication path from the first core to the second core. The contents of the first shared memory may correspond to those described above and are not further described here.

[0105] In one possible implementation, the second core can be preconfigured with a third local index table. This table records descriptors that the second core has read from the first send queue. The first send queue stores descriptors sent by the first core to the second core. Based on this, the second core can periodically poll the index values of the third local index table and the first send queue to quickly and accurately read unprocessed descriptors from the first send queue. This ensures that all descriptors in the first send queue are processed, preventing any descriptors from being missed, thereby improving the reliability of inter-core communication.

[0106] Specifically, the second core may cyclically check the maximum index value of the third local index list and the maximum index value of the first transmit queue. If the maximum index value of the first transmit queue is greater than the maximum index value of the third local index list, it is determined that the first transmit queue includes the unprocessed padded first descriptor. The unprocessed padded first descriptor is then retrieved from the first transmit queue.

[0107] It should be understood that the first core places the filled first descriptor into the first send queue, and only then can the second core retrieve the filled first descriptor from the first send queue. Therefore, the index update time of the first send queue is earlier than the index update time of the third local index list, and the index of the third local index list should lag behind the index of the first send queue.

[0108] In a possible implementation, after obtaining the first data from the filled first descriptor, the second core may place the first descriptor into a first used queue, maintain an index of the first used queue, and write the location information of the first descriptor into a corresponding entry.

[0109] S402: The second core obtains a second descriptor from a second free descriptor list.

[0110] The second free descriptor list is a free descriptor list corresponding to the second core. The second descriptor may be a free descriptor pre-configured in the second free descriptor list, or in other words, the second descriptor may be a free descriptor pre-assigned to the second core. The process of the second core obtaining the pre-assigned free descriptor may correspond to the content described in step S201 above and will not be repeated here.

[0111] In one possible implementation, the second descriptor may be a descriptor retrieved by the second core from a second used queue, where the second used queue is used to store descriptors sent by the second core to the first core and used by the first core. The second used queue may be preconfigured in a shared memory, and in particular, the second used queue may be preconfigured in a second shared memory, where the second shared memory is a shared memory corresponding to a communication path from the second core to the first core.

[0112] In this embodiment, the second core may reclaim used descriptors in batches from the second used queue, including the second descriptor, for example, by performing an initialization operation to reclaim used descriptors in batches.

[0113] Alternatively, embodiments of the present application further provide a descriptor recycling method, wherein a second local index list is preconfigured in the second core, and the second local index list is used to record descriptors that the second core has recycled from the second used queue. Based on this, the second core can periodically poll and compare the second local index list with the index values in the second used queue to quickly and accurately recycle descriptors that have not yet been recycled from the second used queue, thereby improving descriptor recycling efficiency.

[0114] Specifically, the second core may cyclically check the maximum index value of the second local index list and the maximum index value of the second used queue; if the maximum index value of the second used queue is greater than the maximum index value of the second local index list, determine that the second used queue includes an unrecycled second descriptor; recycle the unrecycled second descriptor to the second free descriptor list to obtain the second descriptor. The specific method in which the second core recycles the unrecycled second descriptor to the second free descriptor list may be referred to in the previous text. Figure 3 The content mentioned above will not be repeated here.

[0115] In a possible implementation, when the second core reclaims the second descriptor, it can also determine whether the second descriptor is associated with a valid memory block. If the second descriptor is associated with a valid memory block, the valid memory block is released and the second descriptor is reclaimed to the second free descriptor list.

[0116] Specifically, the second core may determine whether the unrecycled second descriptor is bound to a valid memory address, thereby determining whether the second descriptor is associated with a valid memory block. If the unrecycled second descriptor is bound to a valid memory address, the second memory block corresponding to the memory address is released, and the unrecycled second descriptor is recycled into the second free descriptor list to obtain the second descriptor.

[0117] S403: The second core fills the second information into the second descriptor, where the second information includes a storage address of the second data to be sent or the second data to be sent.

[0118] The content of the second information and the content of the second descriptor filled by the second core with the second information may correspond to the content described in the above step S202 and will not be repeated here.

[0119] S404: The second core sends the filled second descriptor to the first core, so that the first core obtains the second data through the second information.

[0120] In an embodiment of the present application, the second core sends the filled second descriptor to the first core based on the shared memory and inter-core interrupt mechanism.

[0121] Specifically, the second core may place the filled second descriptor into a second send queue of the shared memory, where the second send queue is used to store descriptors sent by the second core to the first core. The second core then triggers an interrupt to notify the first core to obtain the filled second descriptor, so that the first core obtains the filled second descriptor from the first send queue of the shared memory and obtains the second data based on the second information.

[0122] If the second information includes the storage address of the second data, the first core obtains the second data from the corresponding memory block according to the storage address. If the second information includes the second data, the first core can directly obtain the second data from the filled second descriptor.

[0123] Among them, the specific method for the first core to obtain the filled second descriptor and obtain the second data based on the second information can correspond to the specific method for the second core to obtain the filled first descriptor and obtain the first data based on the first information, which will not be repeated here.

[0124] In one possible implementation, the second core may send the filled second descriptor to the first core through the second shared memory, i.e., place the filled second descriptor into the second sending queue of the second shared memory, and the second shared memory is the shared memory corresponding to the communication path from the second core to the first core.

[0125] In one possible implementation, the second send queue and the second used queue may be a ring buffer structure. In this implementation, the queue indexes of the second send queue and the second used queue may be maintained in a ring logic using a modulo operation. For example, if the ring buffer size is N=8 and the current index is 7, the next write index should be 0.

[0126] In one possible implementation, the second sending queue and the second used queue may be combined into one queue, and the status of the descriptors may be distinguished by a flag bit. For example, a flag bit 1 indicates that the descriptor is currently in use, or a flag bit 0 indicates that the descriptor is currently in a waiting state.

[0127] In order to better understand the inter-core communication method provided in the embodiment of the present application, Figure 5 and Figure 6 , taking the first core and the second core as an example, the communication architecture between the first core and the second core and the inter-core communication method are illustrated.

[0128] Please refer to Figure 5 , is a schematic diagram of a communication architecture between a first core and a second core provided in an embodiment of the present application. Figure 5 As shown, the first core and the second core communicate with each other through a pre-allocated communication channel.

[0129] The first core is locally configured with a first local index list, a first free descriptor list, and a fourth local index list. The first local index list is used to record descriptors retrieved by the first core from the first used queue. The first free descriptor list is used to store free descriptors available for use by the first core. The fourth index list is used to record descriptors obtained by the first core from the second receive queue.

[0130] The second core is locally configured with a second local index list, a second free descriptor list, and a third local index list. The second local index list is used to record descriptors that the second core has retrieved from the second used queue. The second free descriptor list is used to store free descriptors that the second core can use. The third local index list is used to record descriptors that the second core has retrieved from the second receive queue.

[0131] The first shared memory is the shared memory corresponding to the communication path from the first core to the second core, that is, the first shared memory is used to store descriptor information when the first core sends data to the second core. The first shared memory includes a first used queue and a first sending queue (that is, a first receiving queue). Among them, the first used queue is used to store descriptors sent by the first core to the second core and used by the second core. The first used queue is read-only by the first core and writable by the second core. The first sending queue (first receiving queue) is used to store descriptors to be processed sent by the first core to the second core. The first sending queue (first receiving queue) is writable by the first core and read-only by the second core.

[0132] The second shared memory is the shared memory corresponding to the communication path from the second core to the first core, that is, the second shared memory is used to store the descriptor information when the second core sends data to the first core. The second shared memory includes a second used queue and a second send queue (i.e., a second receive queue). Among them, the second used queue is used to store descriptors sent by the second core to the first core and used by the first core. The second used queue is writable by the first core and read-only by the second core. The second send queue (first receive queue) is used to store descriptors to be processed sent by the second core to the first core. The second send queue (second receive queue) is read-only by the first core and writable by the second core.

[0133] It should be noted that Figure 5 The lists on either side of the dashed line shown in the figure are for illustrative purposes only, but physically, the first used queue, first send queue, first receive queue, second used queue, second send queue, and second receive queue on either side of the dashed line belong to the same queue. In other words, the first send queue is the first receive queue, and the second send queue is the second receive queue.

[0134] Please refer to Figure 6 , which is a flow diagram of an inter-core communication method provided in an embodiment of the present application Figure 3 .

[0135] S601: A first core obtains a first descriptor from a first free descriptor list.

[0136] The specific contents of the first idle descriptor list and the first descriptor may refer to the contents described above.

[0137] S602: The first core fills the first information into the first descriptor.

[0138] The specific manner in which the first core fills the first information into the first descriptor may correspond to the content described above.

[0139] S603: The first core puts the filled first descriptor into the first sending queue of the first shared memory.

[0140] Correspondingly, the second core obtains the filled first descriptor from the first sending queue of the first shared memory.

[0141] S604: The second core obtains the first data according to the first information.

[0142] Among them, the specific method in which the second core obtains the first data according to the first information can refer to the content described above.

[0143] S605 : The second core puts the used first descriptor into a first used queue.

[0144] S606 : The first core reclaims the first descriptor from the first used queue.

[0145] The first core may reclaim the first descriptor from the first used queue in accordance with the above-mentioned contents.

[0146] S607: The second core obtains a second descriptor from the second free descriptor list.

[0147] The specific contents of the second idle descriptor list and the second descriptor may refer to the contents described above.

[0148] S608: The second core fills the second information into the second descriptor.

[0149] The specific manner in which the second core fills the second information into the second descriptor may correspond to the content described above.

[0150] S609 , the second core puts the filled second descriptor into the second sending queue of the second shared memory.

[0151] Accordingly, the first core obtains the filled second descriptor from the second sending queue of the second shared memory.

[0152] S6010: The first core obtains second data according to the second information.

[0153] Among them, the first core can obtain the content of the second data according to the second information by referring to the content described above.

[0154] S6011: The first core puts the used second descriptor into a second used queue of the second shared memory.

[0155] S6012: The second core reclaims the second descriptor from the second used queue of the second shared memory.

[0156] The specific method of the second core recovering the second descriptor may refer to the content described above.

[0157] It should be noted that the embodiments of this application do not limit Figure 6 The order in which the steps are executed, Figure 6 The various steps shown in can be executed sequentially, synchronously, etc. For example, the second core sending the second data to the first core and the first core recovering the first descriptor can be executed synchronously. The specific details can be determined according to the actual communication situation, and the embodiments of the present application are not limited to this.

[0158] Based on the above, the inter-core communication method for sending first data from the first core to the second core is the same as the inter-core communication method for sending second data from the second core to the first core. This achieves communication symmetry between the first and second cores, while also enabling mutual communication between the first and second cores. Compared to traditional inter-core communication methods in a master-slave architecture, this improves the efficiency of inter-core communication in multi-core processors.

[0159] Based on the same inventive concept, an embodiment of the present application provides an inter-core communication device, which is used to implement the inter-core communication method executed by the first core, such as Figure 2 or Figure 6 The inter-core communication method shown in the figure can also realize the functions of the first core mentioned above.

[0160] Please refer to Figure 7 , which is a schematic diagram of the structure of an inter-core communication device provided in an embodiment of the present application Figure 1 .like Figure 7 As shown, the inter-core communication device 700 includes an acquisition module 701, a filling module 702, and a transceiver module 703. The inter-core communication device 700 can be applied to a first core of a multi-core processor, where the first core is any processor core in the multi-core processor. Each processor core in the multi-core processor is pre-configured with an idle descriptor list, which includes idle descriptors that can be used by the corresponding processor core.

[0161] Exemplarily, the acquisition module 701 is used to obtain the first descriptor from the first free descriptor list; the filling module 702 is used to fill the first information into the first descriptor, the first information including the storage address of the first data to be sent or the first data to be sent; the transceiver module 703 is used to send the filled first descriptor to the second core so that the second core obtains the first data through the first information.

[0162] In a possible implementation, the first descriptor is a descriptor recovered by the first core from a first used queue, and the first used queue is used to store descriptors sent by the first core to the second core and used by the second core.

[0163] In one possible embodiment, a first local index list is pre-configured in the first core, and the first local index list is used to record the descriptors that the first core has recovered from the first used queue. The acquisition module 701 is also used to cyclically check the maximum index value of the first local index list and the maximum index value in the first used queue before obtaining the first descriptor from the first free descriptor list; when the maximum index value in the first used queue is greater than the maximum index value of the first local index list, determine that the first used queue includes an unrecovered first descriptor; and recycle the unrecovered first descriptor to the first free descriptor list to obtain the first descriptor.

[0164] In one possible implementation, the acquisition module 701 is further configured to determine whether the unrecycled first descriptor is bound to a valid memory address before recycling the unrecycled first descriptor to the first free descriptor list to obtain the first descriptor; the acquisition module 701 is specifically configured to: when the unrecycled first descriptor is bound to a valid memory address, release the first memory block corresponding to the memory address, and recycle the unrecycled first descriptor to the first free descriptor list to obtain the first descriptor.

[0165] In a possible implementation, the transceiver module 703 is specifically configured to send the first descriptor to be filled to the second core via a first shared memory, where the first shared memory is a shared memory corresponding to a communication path from the first core to the second core.

[0166] Based on the same inventive concept, an embodiment of the present application provides an inter-core communication device, which is used to implement the above-mentioned inter-core communication method executed by the second core, such as Figure 4 or Figure 6 The inter-core communication method shown in the figure can also realize the functions of the second core mentioned above.

[0167] Please refer to Figure 8 , which is a schematic diagram of the structure of an inter-core communication device provided in an embodiment of the present application Figure 2 .like Figure 8 As shown, the inter-core communication device 800 includes a transceiver module 801, an acquisition module 802, and a filling module 803. The inter-core communication device 800 can be applied to the second core in a multi-core processor, where the second core is any processor core in the multi-core processor except the first core. Each processor core in the multi-core processor is pre-configured with an idle descriptor list, which includes idle descriptors that can be used by the corresponding processor core.

[0168] Exemplarily, the transceiver module 801 is used to obtain the filled first descriptor sent by the first core, and obtain the first data through the first information in the filled first descriptor, where the first information includes the storage address of the first data or the first data; the acquisition module 802 is used to obtain the second descriptor from the second free descriptor list; the filling module 803 is used to fill the second information into the second descriptor, where the second information includes the storage address of the second data to be sent or the second data to be sent; the transceiver module 801 is also used to send the filled second descriptor to the first core, so that the first core obtains the second data through the second information.

[0169] In a possible implementation, the second descriptor is a descriptor recovered by the second core from a second used queue, and the second used queue is used to store descriptors sent by the second core to the first core and used by the first core.

[0170] In one possible embodiment, a second local index list is pre-configured in the second core, and the second local index list is used to record the descriptors that the second core has recovered from the second used queue. The acquisition module 802 is also used to cyclically check the maximum index value of the second local index list and the maximum index value of the second used queue before obtaining the second descriptor from the second free descriptor list; when the maximum index value of the second used queue is greater than the maximum index value of the second local index list, determine that the second used queue includes unrecovered second descriptors; and recycle the unrecovered second descriptors to the second free descriptor list to obtain the second descriptor.

[0171] In one possible implementation, the acquisition module 802 is further configured to determine whether the unrecycled second descriptor is bound to a valid memory address before recycling the unrecycled first descriptor to the second free descriptor list to obtain the second descriptor; the acquisition module 802 is specifically configured to: when the unrecycled second descriptor is bound to a valid memory address, release the second memory block corresponding to the memory address, and recycle the unrecycled second descriptor to the second free descriptor list to obtain the second descriptor.

[0172] In one possible embodiment, a third local index list is pre-configured in the second core, and the third local index list is used to record the descriptors that the second core has read from the first sending queue. The first sending queue is used to store the descriptors sent by the first core to the second core. The transceiver module 803 is specifically used to: cyclically check the maximum index value of the third local index list and the maximum index value of the first sending queue; when the maximum index value of the first sending queue is greater than the maximum index value of the third local index list, determine that the first sending queue includes unprocessed padded first descriptors; and obtain the unprocessed padded first descriptors from the first sending queue.

[0173] In a possible implementation, the transceiver module 803 is specifically configured to send the filled second descriptor to the first core via a second shared memory, where the second shared memory is a shared memory corresponding to a communication path from the second core to the first core.

[0174] Based on the same inventive concept, the present application embodiment provides a multi-core processor. Figure 9 , is a schematic diagram of the structure of a multi-core processor provided in an embodiment of the present application. Figure 9As shown, the multi-core processor 900 includes multiple processor cores 901, including at least a first core and a second core; and a memory 902 communicatively connected to the multiple processor cores 901. The first core can be any processor core in the multiple processor cores 901, and the second core can be any processor core in the multiple processor cores 901 except the first core. Specifically, the multiple processor cores 901 can include processor core 9011, processor core 9012, ..., and processor core 901F, where F is an integer greater than or equal to 2.

[0175] In one embodiment, the memory 902 stores instructions that can be executed by the multiple processor cores 901. The first core among the multiple processor cores 901 can implement the functions of the first core mentioned above by executing the instructions stored in the memory 902, and accordingly, can also implement the steps executed by the first core mentioned above.

[0176] In this embodiment, the first core can also implement the functions of the inter-core communication device 700 mentioned above, and can also implement the functions of the acquisition module 701, the filling module 702 and the transceiver module 703 mentioned above.

[0177] In another embodiment, the memory 902 stores instructions that can be executed by the multiple processor cores 901. The second core among the multiple processor cores 901 can implement the functions of the second core mentioned above by executing the instructions stored in the memory 902, and accordingly, can also implement the steps executed by the second core mentioned above.

[0178] In this embodiment, the second core can also implement the functions of the inter-core communication device 800 mentioned above, and can also implement the functions of the transceiver module 801, the acquisition module 802 and the filling module 803 mentioned above.

[0179] Based on the same inventive concept, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a multi-core processor, implements any of the above-mentioned inter-core communication methods, for example, Figure 2 、 Figure 4 or Figure 6 The inter-core communication method shown.

[0180] Based on the same inventive concept, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a multi-core processor, implements any of the above-mentioned inter-core communication methods, for example, Figure 2 、 Figure 4 or Figure 6 The inter-core communication method shown.

[0181] During implementation, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or by instructions in the form of software. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor executes the instructions in the memory, and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it will not be described in detail here.

[0182] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0183] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0184] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0185] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0186] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0187] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0188] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for inter-core communication, characterized in that: The method is applied to a first core in a multi-core processor, where the first core is any processor core in the multi-core processor, and each processor core in the multi-core processor is pre-configured with an idle descriptor list, where the idle descriptor list includes idle descriptors that can be used by the corresponding processor core; and the method comprises: Get the first descriptor from the first free descriptor list; Filling first information into the first descriptor, where the first information includes a storage address of first data to be sent or the first data to be sent; The filled first descriptor is sent to the second core, so that the second core obtains the first data through the first information.

2. The method according to claim 1, characterized in that The first descriptor is a descriptor recovered by the first core from a first used queue, and the first used queue is used to store descriptors sent by the first core to the second core and used by the second core.

3. The method according to claim 2, characterized in that A first local index list is pre-configured in the first core, and the first local index list is used to record descriptors that have been recovered by the first core from the first used queue. Before obtaining the first descriptor from the first free descriptor list, the method further includes: Loopingly checking the maximum index value of the first local index list and the maximum index value in the first used queue; If the maximum index value in the first used queue is greater than the maximum index value in the first local index list, determining that the first used queue includes an unrecycled first descriptor; The unreclaimed first descriptor is recycled into the first free descriptor list to obtain the first descriptor.

4. The method according to claim 3, characterized in that Before recycling the unrecycled first descriptor into the first free descriptor list to obtain the first descriptor, the method further includes: Determining whether the unreclaimed first descriptor is bound to a legal memory address; The step of recycling the unreclaimed first descriptor to the first free descriptor list to obtain the first descriptor includes: In a case where the unreclaimed first descriptor is bound to a legal memory address, a first memory block corresponding to the memory address is released, and the unreclaimed first descriptor is recycled to the first free descriptor list to obtain the first descriptor.

5. The method according to any one of claims 1 to 4, characterized in that The sending the filled first descriptor to the second core includes: The first descriptor to be filled is sent to the second core through a first shared memory, where the first shared memory is a shared memory corresponding to a communication path from the first core to the second core.

6. A method for inter-core communication, characterized in that: The method is applied to a second core in a multi-core processor, where the second core is any processor core in the multi-core processor except the first core, and each processor core in the multi-core processor is pre-configured with an idle descriptor list, where the idle descriptor list includes idle descriptors that can be used by the corresponding processor core; the method comprising: Obtaining a padded first descriptor sent by the first core, and obtaining first data through first information in the padded first descriptor, where the first information includes a storage address of the first data or the first data; Get the second descriptor from the second free descriptor list; Filling second information into the second descriptor, where the second information includes a storage address of second data to be sent or the second data to be sent; The filled second descriptor is sent to the first core, so that the first core obtains the second data through the second information.

7. The method according to claim 6, characterized in that The second descriptor is a descriptor recovered by the second core from a second used queue, and the second used queue is used to store descriptors sent by the second core to the first core and used by the first core.

8. The method according to claim 7, characterized in that The second core is pre-configured with a second local index list, and the second local index list is used to record descriptors that the second core has recovered from the second used queue. Before obtaining the second descriptor from the second free descriptor list, the method further includes: Loopingly checking the maximum index value of the second local index list and the maximum index value of the second used queue; If the maximum index value of the second used queue is greater than the maximum index value of the second local index list, determining that the second used queue includes unrecycled second descriptors; The unreclaimed second descriptor is recycled into the second free descriptor list to obtain the second descriptor.

9. The method according to claim 8, characterized in that Before recycling the unreclaimed first descriptor into the second free descriptor list to obtain the second descriptor, the method further includes: Determining whether the unreclaimed second descriptor is bound to a legal memory address; The step of recycling the unreclaimed second descriptor to the second free descriptor list to obtain the second descriptor includes: In a case where the unreclaimed second descriptor is bound to a legal memory address, the second memory block corresponding to the memory address is released, and the unreclaimed second descriptor is recycled to the second free descriptor list to obtain the second descriptor.

10. The method according to claim 6, characterized in that The second core is pre-configured with a third local index list, the third local index list is used to record descriptors that the second core has read from the first sending queue, the first sending queue is used to store descriptors sent by the first core to the second core, and obtaining the filled first descriptor sent by the first core includes: Circularly checking the maximum index value of the third local index list and the maximum index value of the first sending queue; In a case where the maximum index value of the first sending queue is greater than the maximum index value of the third local index list, determining that the first sending queue includes the unprocessed filled first descriptor; The unprocessed filled first descriptor is obtained from the first sending queue.

11. The method according to any one of claims 6 to 10, characterized in that: The sending the filled second descriptor to the first core includes: The filled second descriptor is sent to the first core through a second shared memory, where the second shared memory is a shared memory corresponding to a communication path from the second core to the first core.

12. An inter-core communication device, characterized in that: The inter-core communication device is applied to a first core in a multi-core processor, where the first core is any processor core in the multi-core processor, and each processor core in the multi-core processor is pre-configured with an idle descriptor list, where the idle descriptor list includes idle descriptors that can be used by the corresponding processor core; The inter-core communication device includes: An acquiring module, configured to acquire a first descriptor from a first free descriptor list; a filling module, configured to fill first information into the first descriptor, where the first information includes a storage address of first data to be sent or the first data to be sent; The transceiver module is used to send the filled first descriptor to the second core, so that the second core obtains the first data through the first information.

13. An inter-core communication device, characterized in that: The inter-core communication device is applied to a second core in a multi-core processor, where the second core is any processor core in the multi-core processor except the first core, and each processor core in the multi-core processor is pre-configured with an idle descriptor list, where the idle descriptor list includes idle descriptors that can be used by the corresponding processor core; The inter-core communication device includes: a transceiver module, configured to obtain the padded first descriptor sent by the first core, and obtain first data through first information in the padded first descriptor, where the first information includes a storage address of the first data or the first data; An acquiring module, configured to acquire a second descriptor from a second free descriptor list; a filling module, configured to fill second information into the second descriptor, where the second information includes a storage address of second data to be sent or the second data to be sent; The transceiver module is further configured to send the filled second descriptor to the first core, so that the first core obtains the second data through the second information.

14. A multi-core processor, characterized in that: include: a plurality of processor cores, the plurality of processor cores including at least a first core and a second core; as well as a memory communicatively coupled to the plurality of processor cores; The memory stores instructions that can be executed by the multiple processor cores, and the first core or the second core among the multiple processor cores implements the method according to any one of claims 1-5 or 6-11 by executing the instructions stored in the memory.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a multi-core processor, the method according to any one of claims 1 to 5 or 6 to 11 is implemented.

16. A computer program product comprising a computer program, characterized in that When the computer program is executed by a multi-core processor, the method according to any one of claims 1 to 5 or 6 to 11 is implemented.

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