Computing chip and device, data processing method, storage medium and program product

Abstract

Provided are a computing chip and device, a method for processing data, a storage medium, and a program product. The computing chip includes one or more computing modules for executing computing tasks; a command processor for issuing a first computing task to the one or more computing modules; a data transmission module for transmitting data with an external computing chip via remote memory direct access; a transmission control module including: a task queue creation module for receiving the control command and, in accordance with the control command, adding the first computing task to a first task queue created by the task queue creation module; and a task scheduling module for controlling the data transmission module to communicate with an external computing chip in response to the one or more computing modules completing the execution of the first computing task, and transmitting the computation result corresponding to the first computing task to the external computing chip via remote memory direct access.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and more specifically, to a computing chip and device, a method for processing data, a storage medium, and a program product. Background Art

[0002] With the development of artificial intelligence (AI) technology, the computing power provided by a single computing chip (such as a graphics processing unit (GPU)) has gradually been unable to meet the needs of many scenarios. Therefore, multiple computing chips are needed to jointly complete computing tasks.

[0003] When multiple computing chips work together to perform computing tasks, communication and data transmission between them are naturally required. In this case, how to increase data transmission speed and reduce data transmission latency is a problem that needs to be solved. Summary of the Invention

[0004] The present application provides a computing chip and device, a method for processing data, a storage medium and a program product to increase data transmission speed and reduce data transmission delay.

[0005] In a first aspect, a computing chip is provided, comprising: one or more computing modules for executing computing tasks; a command processor for issuing a first computing task to the one or more computing modules; a data transmission module for transmitting data with an external computing chip through direct remote memory access; a transmission control module, comprising: a task queue creation module for creating a first task queue and adding the first computing task to the first task queue created by the task queue creation module; a task scheduling module for controlling the data transmission module to communicate with the external computing chip in response to the one or more computing modules completing the execution of the first computing task, and transmitting the computing result corresponding to the first computing task to the external computing chip through direct remote memory access.

[0006] As a possible implementation, the computing chip further includes: an on-chip processor for performing at least one of the following operations based on firmware: initializing the data transmission module; initializing the transmission control module; and controlling the computing chip to establish a communication connection with the external computing chip.

[0007] As a possible implementation method, the data transmission module is a data transmission module that supports remote direct memory access (RDMA) operations, and the firmware of the on-chip processor includes a driver part and an application part; the driver part is used to drive the data transmission module to perform initialization operations; the application part is used to perform the following operations: assign an identifier to the computing chip; perform a topology discovery process to determine the identifiers of other computing chips in the network where the computing chip is located; and establish a queue pair (QP) connection with the other computing chips based on the identifier of the computing chip and the identifiers of the other computing chips, thereby establishing a full connection supporting RDMA in the network.

[0008] As a possible implementation, the data transmission module is a data transmission module that supports RDMA operations, and the computing chip also includes a memory, which is used to store the QP of the data transmission module; the data transmission module is connected to the memory via a first communication link, the transmission control module is connected to the data transmission module via a second communication link, and the transmission control module is connected to the memory via a third communication link, and the first communication link, the second communication link, and the third communication link are used to control the QP to send and receive data; wherein, the first communication link, the second communication link, and the third communication link do not pass through the on-chip processor.

[0009] As a possible implementation manner, the first communication link between the data transmission module and the memory is an internal bus of the computing chip.

[0010] As a possible implementation manner, the third communication link between the transmission control module and the memory is a direct link between the transmission control module and the memory, and the third communication link includes a first sub-link and a second sub-link, the first sub-link is used to write a work queue element (WQE) to a sending queue (SQ) in the QP, and the second sub-link is used to read a completion queue element (CQE) from a completion queue (CQ) in the QP.

[0011] As a possible implementation manner, the computing chip and the external computing chip are addressed based on a unified physical address (UPA).

[0012] As a possible implementation method, the transmission control module is also used to: after the data transmission module receives the calculation results sent by the external computing chip, transmit the calculation results sent by the external computing chip to the central processing unit through the command processor.

[0013] As a possible implementation manner, the data transmission module is a data transmission module that supports RDMA operations.

[0014] As a possible implementation method, the computing module is a storage and computing integrated chip.

[0015] In a second aspect, a computing device is provided, comprising a computing chip as described in the first aspect or any possible implementation of the first aspect.

[0016] In a third aspect, a method for processing data is provided, which is applied to a computing chip, wherein the computing chip includes a command processor, one or more computing modules, a data transmission module and a transmission control module. The method includes: the command processor issues a first computing task to the one or more computing modules; the transmission control module creates a first task queue, adds the first computing task to the first task queue created by the task queue creation module, and in response to the one or more computing modules completing the execution of the first computing task, controls the data transmission module to communicate with an external computing chip, and transmits the calculation result corresponding to the first computing task to the external computing chip in a remote memory direct access manner.

[0017] As a possible implementation, the computing chip also includes an on-chip processor, and the method also includes: the on-chip processor performs at least one of the following operations based on firmware: initializing the data transmission module; initializing the transmission control module; controlling the computing chip to establish a communication connection with the external computing chip.

[0018] As a possible implementation manner, the computing chip and the external computing chip are addressed based on UPA.

[0019] As a possible implementation manner, the method further includes: after the data transmission module receives the calculation result sent by the external computing chip, the transmission control module transmits the calculation result sent by the external computing chip to the central processing unit through the command processor.

[0020] As a possible implementation method, the computing module is a storage and computing integrated chip.

[0021] In a fourth aspect, a computer-readable storage medium is provided, on which a program code for executing the method described in the third aspect or any one of the implementations of the third aspect is stored.

[0022] In a fifth aspect, a computer program product is provided, comprising a program code for executing the method as described in the third aspect or any one of the implementations of the third aspect.

[0023] The present embodiment integrates the data transmission module into the computing chip, thereby increasing the data transmission speed between the computing chip and the data transmission module and reducing data transmission latency. Furthermore, the present embodiment introduces a transmission control module into the computing chip to control the data transmission module to perform data transmission, eliminating the need for the CPU to control the data transmission process of the data transmission module. This avoids consuming CPU resources and preventing CPU congestion from restricting the computing efficiency of the computing chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application, and other drawings obtained by ordinary technicians in this field based on these drawings fall within the scope of the present application.

[0025] Figure 1 A schematic diagram of the structure of the computing chip provided in an embodiment of the present application.

[0026] Figure 2 for Figure 1 A more specific structural example diagram of a computing chip is shown.

[0027] Figure 3 A flowchart of a method for processing data provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. All other embodiments obtained based on the embodiments in this application are within the scope of protection of this application.

[0029] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0030] It should be understood that the specific embodiments described below are only used to explain the present application and are not intended to limit the present application.

[0031] In recent years, AI technology has experienced explosive growth, with its applications in various fields continuously deepening and expanding. From image recognition and natural language processing to complex predictive models, AI's application scenarios are becoming increasingly diverse. However, this rapid development of technology has also placed increasing demands on computing power.

[0032] For example, the size of AI models is rapidly increasing. For example, in natural language processing, early models might have only a few million parameters, but today, models like the GPT series have hundreds of billions or even trillions of parameters. These massive models require processing massive amounts of data and performing complex calculations to achieve accurate predictions and generation. For example, training a large Transformer model requires encoding and decoding vast amounts of text data and calculating the relationships between individual words. This requires extremely high computing power to process such a large number of parameters and data.

[0033] For another example, the development of AI technology relies on vast amounts of data. With the proliferation of IoT devices, sensor data, image data, and video data are growing exponentially. This data needs to be collected, stored, and processed to train more accurate AI models. For example, in the field of autonomous driving, various sensors on a vehicle generate massive amounts of data every second, including camera images and radar signals. This data needs to be processed in real time so that AI systems can make rapid decisions, such as identifying traffic signs, pedestrians, and obstacles. Processing such massive amounts of data naturally demands significantly higher computing power.

[0034] Therefore, in the fields of high-performance computing and deep learning, computing chips with powerful computing capabilities (such as GPUs) have become indispensable tools.

[0035] However, the computing power provided by a single computing chip is limited. To meet latency performance requirements, it is often necessary to split a large computing task into multiple tasks and have them executed separately by multiple computing chips. Therefore, the coordinated operation of multiple computing chips will gradually become the norm.

[0036] Multiple computing chips can be deployed on a single server or distributed across multiple servers. Regardless of the deployment model, high-speed, high-reliability interconnection communication technology is required to ensure high bandwidth and low latency for data transmission.

[0037] To enable communication between multiple computing chips, one possible solution is to connect each of them to an external network card, using which they can communicate and transmit data. For example, multiple computing chips could each be connected to their corresponding network card via a PCIe interface, with the network card then transmitting the computational results of one computing chip to another. However, this approach would limit the computing performance of the entire system to the capabilities of the PCIe link, which, however, offers limited transmission speeds and often fails to meet practical requirements.

[0038] Therefore, in some implementations, it is possible to integrate the data transmission module within the computing chip to increase data transmission speed and reduce data transmission latency. In other words, the data transmission module can be integrated into the computing chip (such as the GPU) to convert external data transmission into internal data transmission. Because internal data exchange can be carried out via a faster internal bus, this can increase data transmission speed.

[0039] After integrating the data transmission module into the computing chip, the central processing unit (CPU) can still use the operating system to drive the computing chip and data transmission module separately in the traditional manner. In other words, the data transmission module and computing chip can be physically integrated only; from a software perspective, they can still be considered two independent devices. This approach requires no software modifications; the CPU can drive and control the computing chip and data transmission module as if they were two independent devices. The greatest advantage of this approach is its simplicity. However, it requires CPU involvement, which consumes CPU resources. Furthermore, if the CPU is congested, data transmission delays will occur, affecting the computing chip's data processing efficiency.

[0040] Therefore, in some implementations, a processor can be further integrated into the computing chip. This processor can implement data transmission functionality by driving and controlling the data transmission module through firmware. If this solution is adopted, the entire process consumes resources on the computing chip and does not require excessive CPU involvement. However, this solution has the following problems: the processor on the computing chip used to control the data transmission module performs related operations based on firmware control of the data transmission module, and firmware-based control methods may be relatively inefficient (firmware is software, and operations such as software loading and parsing will limit control efficiency). In addition, the processor processing process generates a large amount of power, which increases the heat generated by the computing chip.

[0041] To address the above issues, the embodiment of the present application introduces a transmission control module (the transmission control module is a hardware module) inside the computing chip. The transmission control module can be used to replace the processor to implement part or all of the control functions of the data transmission module. Compared with the implementation based on firmware and processor, the hardware implementation has high processing efficiency and low power consumption, thereby improving the data transmission performance between multiple computing chips. Figure 1 , the embodiments of this application are introduced in detail.

[0042] See also Figure 1 The present invention provides a computing chip 10. The computing chip 10 may be, for example, a CPU, or other types of coprocessors or accelerators. The computing chip 10 includes a command processor 12, one or more computing modules 14, a data transmission module 16, and a transmission control module 18.

[0043] The command processor 12 may be configured to issue a first computing task to one or more computing modules 14. Furthermore, the command processor 12 may be configured to receive communication packets, such as collective communication library (CCL) communication packets. The CCL communication packets may be configured to instruct the command processor 12 to perform communication operations, such as reduce operations or gather operations.

[0044] The computing module 14 can be used to perform computing tasks (such as matrix multiplication or other mathematical operations). This computing module can be, for example, a memory-computing integrated chip, also known as a computing-in-memory chip (CIM Die). A computing chip can include one computing module 14, or multiple computing modules 14 (e.g., eight computing modules). Multiple computing modules 14 can cooperate with each other to jointly complete a computing task. The memory-computing integrated chip can reduce the number of data transfers between the memory and the computing module, thereby improving computing efficiency and reducing energy consumption.

[0045] The data transmission module 16 may be a data transmission module that supports remote memory direct access operations. The remote memory direct access operation may be, for example, an RDMA operation. RDMA is a technology that bypasses a remote host to directly access data in its memory, and is intended to solve the problem of data processing delay in network transmission. RDMA technology enables data transmission between computing chips to bypass their respective corresponding CPUs, thereby directly accessing data through memory, thereby achieving high bandwidth, low latency, and low CPU utilization. The embodiments of the present application do not specifically limit the implementation method of RDMA. For example, one of the following implementation methods may be adopted: InfiniBand, RoCE (such as RoCEv2), iWARP. Exemplarily, the data transmission module may support a data transmission module of the RoCEv2 protocol, so the data transmission module may also be referred to as a RoCEv2 engine.

[0046] The transmission control module 18 can be responsible for scheduling one or more computing modules 14 to execute the first computing task. In addition, the transmission control module 18 can also control the data transmission module 16 to communicate with the external computing chip and transmit the calculation result corresponding to the first computing task to the external computing chip via remote memory direct access.

[0047] like Figure 1 As shown, the transmission control module 18 may include a task queue creation module 181 and a task scheduling module 182. The task queue creation module 181 is used to create a first task queue and add the first computing task to the first task queue created by the task queue creation module. For example, the task queue creation module 181 may add the target task descriptor of the first computing task to the first queue under the control of the command processor 12.

[0048] The task scheduling module 182 is used to control the data transmission module 16 to communicate with the external computing chip in response to the one or more computing modules 14 completing the first computing task, and transmit the calculation result corresponding to the first computing task to the external computing chip in a remote memory direct access manner. For example, the task scheduling module 182 can be connected to one or more computing modules 14. After completing the first computing task, the one or more computing modules 14 can send a synchronization signal (or a synchronization completion signal) to the task scheduling module 182 to indicate that the first computing task is completed. After receiving the synchronization signal, the task scheduling module 182 can send an indication signal (such as a doorbell signal) to the data transmission module 16, instructing the data transmission module 16 to transmit the calculation result corresponding to the first computing task to the external computing chip in a remote memory direct access manner.

[0049] It should be understood that the transmission control module 18 mentioned in the embodiments of this application is different from a processor. It primarily implements the control operations of the data transmission module 16 based on its own hardware, rather than through software or firmware like a processor. Compared to firmware-based implementations, the transmission control module 18 has higher processing efficiency and lower power consumption. For example, if the data transmission module supports RDMA operations, the transmission control module 18 can be called an RDMA interface (RDMA_INTF).

[0050] According to the above content, after the data transmission module is integrated into the computing chip, the embodiment of the present application further introduces a transmission control module, and controls the data transmission module based on the transmission control module to implement transmission operations, thereby improving the data transmission performance between multiple computing chips.

[0051] In some embodiments, the computing chip 10 also includes a memory. The communication link between the data transmission module 16 and the memory can be an internal bus of the computing chip 10. For example, the communication link between the data transmission module 16 and the memory can be an internal bus based on AXI. In another example, the communication link between the data transmission module 16 and the memory can be an internal bus based on UCIe. The data transmission module 16 and the memory are directly connected via the internal bus, without requiring an external interface (such as PCIe). This shortens the data access link between the data transmission module 16 and the memory, thereby reducing data access latency.

[0052] As mentioned above, the transmission control module 18 can be used to control the data transmission module 16 to implement data transmission operations. In addition to data transmission operations, the data transmission module 16 also needs to complete initialization operations during startup. In some implementations, the initialization operations of the data transmission module 16 can be implemented based on the transmission control module 18.

[0053] However, the initialization operation of the data transmission module 16 is relatively complex, and implementing the initialization operation based on the transmission control module 18 will increase the structural complexity of the transmission control module 18 and the development cost of the computing chip. Figure 1, an on-chip processor 19 can be provided in the computing chip 10. The on-chip processor 19 can initialize the data transmission module 16 based on the firmware. Since the on-chip processor 19 does not need to participate in the actual data transmission process of the data transmission module 16 (the data transmission process of the data transmission module 16 is still controlled by the transmission control module 18), it does not cause large power consumption. In addition, the firmware-based implementation method can directly refer to the relevant technical implementation without the need for special hardware development, which simplifies the hardware implementation. As a more specific example, the data transmission module 16 is a RoCEv2 engine, and the on-chip processor 19 can be responsible for initializing the RoCEv2 engine.

[0054] In some implementations, the initialization operation of the transmission control module 18 may also be implemented by the on-chip processor 19 based on firmware.

[0055] In some implementations, the on-chip processor 19 can also be used to control the computing chip 10 to establish a communication connection with an external computing chip based on firmware. Taking a data transmission module that supports RDMA operations as an example, the on-chip processor 19 can independently perform topology discovery and connection establishment based on firmware, establishing a full connection between multiple computing chips (such as GPUs) through the network. For example, the on-chip processor 19 can implement the following operations based on firmware: initialize Ethernet network configuration, perform topology self-discovery between multiple computing chips, and automatically assign unique identifiers to multiple computing chips according to agreed rules; perform socket communication through the initialized Ethernet configuration, establish a QP connection, and ultimately establish a full connection supporting RDMA between multiple computing chips.

[0056] Exemplarily, the data transmission module 16 is a data transmission module that supports RDMA operations. The firmware of the on-chip processor 19 includes a driver portion and an application portion. The driver portion is used to drive the data transmission module to perform initialization operations. The application portion is used to perform the following operations: assign an identifier to the computing chip; perform a topology discovery process to determine the identifiers of other computing chips in the network where the computing chip is located; establish a QP connection with other computing chips based on the identifier of the computing chip and the identifiers of other computing chips, thereby establishing a full connection supporting RDMA in the network. The above operations can be completed entirely by the on-chip processor 19 on the computing chip, without the need for the CPU of the node (such as a server) where the computing chip is located to participate (that is, the CPU of the node is unaware of the initialization and connection establishment process of the data transmission module), thereby saving CPU resources.

[0057] As a more specific example, if the data transmission module is a RoCEv2 engine, the firmware called by the on-chip processor 19 may include two parts, one of which may be called a driver part and the other may be called an application part. The driver part is responsible for hardware initialization of the RoCEv2 engine. The application part may be responsible for initializing the Ethernet network configuration, performing topology self-discovery between multiple computing chips, and automatically assigning unique identifiers to multiple computing chips according to agreed rules; performing socket communication through the initialized Ethernet configuration, establishing an RDMA QP connection, and ultimately establishing an RDMA full connection between multiple GPUs; initializing the transmission control module and configuring the RDMA link-related context; initializing the transmission control module and configuring the RDMA connection-related context.

[0058] In some embodiments, the data transmission module 16 supports RDMA operations. The computing chip 10 also includes a memory for storing the data transmission module's QP. The data transmission module 16 is connected to the memory via a first communication link, the transmission control module 18 is connected to the data transmission module 16 via a second communication link, and the transmission control module 18 is connected to the memory via a third communication link. The first, second, and third communication links are used to control the transmission and reception of data by the QP, and none of the first, second, and third communication links pass through the on-chip processor 19. In other words, the on-chip processor 19 does not participate in the QP-based data transmission and reception process. Instead, the transmission control module 18 controls this process, thereby improving the performance of RDMA operations.

[0059] Data packets transmitted between multiple computing chips can carry addresses, thereby transmitting the data packets to a specified computing chip based on the addresses. The embodiments of the present application do not specifically limit the implementation of this address. In some implementations, the address can be a virtual address, and address resolution is performed during transmission to achieve conversion between virtual and physical addresses. However, this address resolution and conversion operation will reduce the computing efficiency of the computing chip. To improve computing efficiency, in other implementations, multiple computing chips can be uniformly addressed based on UPA.

[0060] Furthermore, in some implementations, various modules or units within the computing chip may also be addressed based on UPA.

[0061] The following combination Figure 2 , describe the embodiments of the present application in more detail. Figure 2 In the example above, the computing chip mentioned above is the GPU in the server. Figure 2The examples are only for helping those skilled in the art to understand the embodiments of the present application, and are not intended to limit the embodiments of the present application to the specific numerical values ​​or specific scenarios illustrated. Figure 2 It is obvious that various equivalent modifications or changes can be made, and such modifications or changes also fall within the scope of the embodiments of the present application.

[0062] first, Figure 2 The GPU shown integrates a data transmission module (such as a RoCEv2 engine), and the data transmission module is directly connected to the memory through an internal bus without passing through a PCIe bus, resulting in a shorter link and reduced link latency.

[0063] In addition, the firmware of the on-chip processor is responsible for driving and initializing the data transmission module and establishing links between multiple GPUs. The CPU in the server is unaware of the data transmission module.

[0064] Furthermore, the firmware of the on-chip processor is responsible for initializing the data transmission module.

[0065] Below Figure 2 The communication process between modules in is illustrated with an example.

[0066] First, the GPU can be initialized. This initialization process includes the following steps: using the driver portion of the on-chip processor's firmware to perform hardware initialization of the data transmission module; using the application portion of the on-chip processor's firmware to perform the following initialization operations: initializing the Ethernet network configuration, performing topology self-discovery between multiple GPUs, and automatically assigning unique GPU IDs according to agreed rules.

[0067] After initialization is completed, the GPU can be used for data transmission. The specific working process is as follows.

[0068] Step 1: The command processor in the GPU schedules the computing module to perform computing tasks and publishes the computing tasks to the transmission control module.

[0069] Step 2: The transmission control module adds the computing task to the first task queue, registers the synchronization signal, and waits for the computing to be completed.

[0070] Step 3: The transmission control module writes the work queue elements into the memory according to the computing task.

[0071] Step 4: The calculation module sends a synchronization signal to the transmission control module to indicate that the calculation task is completed.

[0072] Step 5: The transmission control module controls the data transmission module to obtain the work queue element, and transmits the calculation result of the computing task to other GPUs according to the work queue element.

[0073] Step 6: The data transmission module writes the completion queue element into the memory according to the confirmation message returned by other GPUs.

[0074] Step 7: The transmission control module reads the completion queue element.

[0075] Step 8: The transmission control module sends a task completion signal to the command processor to notify the command processor that the computing task is complete. After receiving the task completion signal, the command processor can notify the GPU application program that the task execution is complete.

[0076] As can be seen from the preceding description, the GPU provided in this example integrates both computing and data transmission modules, saving server hardware and software overhead. Furthermore, the interconnection of multiple GPUs and the collaborative hardware and software simplifies user programming.

[0077] Combined with the above Figures 1 to 2 , describes the device embodiment of the present application in detail, and the following is combined with Figure 3 , the method embodiment of the present application is described in detail. It should be understood that the description of the method embodiment corresponds to the description of the device embodiment, so for parts not described in detail, reference can be made to the previous device embodiment.

[0078] Figure 3 A flowchart of a method for processing data provided in an embodiment of the present application. Figure 3 The method can be applied to the computing chip 10 mentioned above. The computing chip may include a command processor, one or more computing modules, a data transmission module, and a transmission control module. Figure 3 The method includes steps S310 to S320.

[0079] See also Figure 3 In step S310, the command processor issues a first computing task to the one or more computing modules.

[0080] In step S320, the transmission control module creates a first task queue and adds the first computing task to the first task queue created by the task queue creation module. In response to the one or more computing modules completing the execution of the first computing task, the data transmission module is controlled to communicate with the external computing chip to transmit the calculation result corresponding to the first computing task to the external computing chip in a remote memory direct access manner.

[0081] In some implementations, the computing chip further includes an on-chip processor, Figure 3 The method further includes: the on-chip processor performs at least one of the following operations based on the firmware: initializing the data transmission module; initializing the transmission control module; and controlling the computing chip to establish a communication connection with the external computing chip.

[0082] In some implementations, the data transmission module is a data transmission module that supports RDMA operations, and the firmware of the on-chip processor includes a driver part and an application part; the driver part is used to drive the data transmission module to perform initialization operations; the application part is used to perform the following operations: assign an identifier to the computing chip; perform a topology discovery process to determine the identifiers of other computing chips in the RDMA network where the computing chip is located; and establish a QP connection with the other computing chips based on the identifier of the computing chip and the identifiers of the other computing chips, thereby establishing a full connection that supports RDMA in the network.

[0083] In some implementations, the data transmission module is a data transmission module that supports RDMA operations, and the computing chip also includes a memory, which is used to store the QP of the data transmission module; the data transmission module is connected to the memory via a first communication link, the transmission control module is connected to the data transmission module via a second communication link, and the transmission control module is connected to the memory via a third communication link, and the first communication link, the second communication link, and the third communication link are used to control the QP to send and receive data; wherein, the first communication link, the second communication link, and the third communication link do not pass through the on-chip processor.

[0084] In some implementations, the first communication link between the data transmission module and the memory is an internal bus of the computing chip.

[0085] In some implementations, the third communication link between the transmission control module and the memory is a direct link between the transmission control module and the memory, and the third communication link includes a first sub-link and a second sub-link, the first sub-link is used to write WQE to the SQ in the QP, and the second sub-link is used to read CQE from the CQ in the QP.

[0086] In some implementations, the computing chip and the external computing chip are addressed based on UPA.

[0087] In some implementations, Figure 3 The method further includes: after the data transmission module receives the calculation result sent by the external computing chip, the transmission control module transmits the calculation result sent by the external computing chip to the central processing unit through the command processor.

[0088] In some implementations, the computing module is a storage and computing integrated chip.

[0089] The present application also provides a computer-readable storage medium having program code stored thereon, which can be used to execute the method for processing data in any of the above embodiments.

[0090] The present application also provides a computer program product including program code for executing the method for processing data in any of the above embodiments.

[0091] It should be understood that in the embodiment of the present application, determining B based on A does not mean determining B only based on A, but B can also be determined based on A and / or other information.

[0092] It should be understood that in the embodiments of the present application, "B corresponding to A" means that B is associated with A and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B based solely on A, but B can also be determined based on A and / or other information.

[0093] It should be understood that the term "and / or" in this document simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0094] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0095] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0096] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0097] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0098] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be read by a computer or a data storage device such as a server or data center that integrates one or more available media. Available media may be magnetic media (eg, floppy disks, hard disks, tapes), optical media (eg, digital versatile discs (DVDs)), or semiconductor media (eg, solid state disks (SSDs)).

[0099] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A computing chip, characterized in that: include: One or more computing modules for performing computing tasks; A command processor, configured to issue a first computing task to the one or more computing modules; Memory; a data transmission module, which is communicatively connected to the memory via the internal bus of the computing chip, and is used to perform data transmission with an external computing chip by directly accessing the remote memory; Transmission control module, including: A task queue creation module, configured to create a first task queue and add the first computing task to the first task queue; A task scheduling module is used to control the data transmission module to communicate with the external computing chip in response to the one or more computing modules completing the execution of the first computing task, and to transmit the computing result corresponding to the first computing task to the external computing chip by direct access to remote memory.

2. The computing chip according to claim 1, wherein: The computing chip further includes: An on-chip processor is configured to perform at least one of the following operations based on firmware: Initializing the data transmission module; Initializing the transmission control module; Control the computing chip to establish a communication connection with the external computing chip.

3. The computing chip according to claim 2, wherein: The data transmission module is a data transmission module that supports remote direct memory access operations, and the firmware of the on-chip processor includes a driver part and an application part; The driving part is used to drive the data transmission module to perform an initialization operation; The application part is used to perform the following operations: assigning an identifier to the computing chip; Performing a topology discovery process to determine the identities of other computing chips in the network where the computing chip is located; According to the identifier of the computing chip and the identifier of the other computing chip, a queue pair connection is established with the other computing chip, thereby establishing a full connection supporting remote direct memory access in the network.

4. The computing chip according to claim 2 or 3, wherein: The data transmission module is a data transmission module that supports remote direct memory access operations, and the memory is used to store the queue pairs of the data transmission module; The data transmission module is connected to the memory via a first communication link, the transmission control module is connected to the data transmission module via a second communication link, and the transmission control module is connected to the memory via a third communication link, wherein the first communication link, the second communication link, and the third communication link are used to control the queue pair to send and receive data; The first communication link, the second communication link, and the third communication link do not pass through the on-chip processor.

5. The computing chip according to claim 4, characterized in that: The third communication link between the transmission control module and the memory is a direct link between the transmission control module and the memory, and the third communication link includes a first sub-link and a second sub-link, the first sub-link is used to write work queue elements to the sending queue in the queue pair, and the second sub-link is used to read completion queue elements from the completion queue in the queue pair.

6. The computing chip according to claim 1 or 2, characterized in that: The computing chip and the external computing chip are addressed based on a unified physical address.

7. The computing chip according to claim 1 or 2, characterized in that: The transmission control module is further configured to: After the data transmission module receives the calculation result sent by the external computing chip, the calculation result sent by the external computing chip is transmitted to the central processing unit through the command processor.

8. The computing chip according to claim 1 or 2, characterized in that: The computing module is a storage and computing integrated chip.

9. A computing device, characterized in that The method comprises the computing chip according to any one of claims 1 to 8.

10. A method for processing data, characterized in that The method is applied to a computing chip, which includes a command processor, a memory, one or more computing modules, a data transmission module, and a transmission control module. The internal bus of the computing chip is in communication with the memory. The method comprises: The command processor issues a first computing task to the one or more computing modules; The transmission control module creates a first task queue, adds the first computing task to the first task queue, and in response to the one or more computing modules completing the execution of the first computing task, controls the data transmission module to communicate with the external computing chip, and transmits the calculation result corresponding to the first computing task to the external computing chip in a remote memory direct access manner.

11. The method according to claim 10, characterized in that The computing chip further includes an on-chip processor, and the method further includes: The on-chip processor performs at least one of the following operations based on firmware: Initializing the data transmission module; Initializing the transmission control module; Control the computing chip to establish a communication connection with the external computing chip.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores program codes for executing the method according to claim 10 or 11.

13. A computer program product, characterized in that comprising program code for executing the method according to claim 10 or 11.

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