Double-thread parallel read-write shared space system

Abstract

The invention belongs to the technical field of data communication, and particularly relates to a dual-thread parallel read-write shared space system, which comprises an application software module, a PCIE (Peripheral Component Interface Express) dual-address mapping module and a shared space module, a traditional point-to-point data communication mode is broken through, PCIE double-address mapping and an SRIO arbitration mechanism are defined through software, an external shared space can be independently read and written when a processor operates a double-thread application component, it is guaranteed that the number of double threads is not mixed when the double threads communicate between heterogeneous platforms, and the access time is controllable.

Description

Technical Field

[0001] The present invention belongs to the technical field of data communication, and in particular relates to a system for dual-threaded parallel reading and writing of a shared space. Background Art

[0002] With the continuous improvement of chip processing capabilities, in order to reduce R&D costs and improve the degree of product integration, multiple threads are generally built based on a single main processor, integrating multiple functional software or application components. However, there is usually only one physical interface for external access. In order to avoid interference between multiple threads when reading and writing data between heterogeneous platforms and uncertain timing, it is necessary to build a multi-threaded parallel communication architecture through software to achieve multi-threaded parallel reading and writing of external shared space, without serial access and with certain access time. Summary of the Invention

[0003] (1) Technical issues to be resolved

[0004] The technical problem to be solved by the present invention is: how to provide a system for dual-threaded parallel reading and writing of a shared space.

[0005] (2) Technical solution

[0006] In order to solve the above technical problems, the present invention provides a dual-threaded parallel reading and writing shared space system, the system comprising: an application software module, a PCIE dual address mapping module, and a shared space module;

[0007] The application software module includes: application thread 1, application thread 2, and PCIE driver. Application thread 1 and application thread 2 can independently call the PCIE driver.

[0008] The PCIE dual address mapping module includes: a PCIE IP core, an SRIO access arbitration mechanism, and an SRIO IP core; the PCIE IP core internally instantiates two completely independent PCIE decoders, address FIFOs, command FIFOs, write data FIFOs, and read data FIFOs to form two independent PCIE address spaces; the SRIO access arbitration mechanism determines the access order based on the address, data, and command information of the two independent PCIE address spaces to achieve a mapping relationship between the dual PCIE address spaces and the single SRIO address space; the SRIO IP core is used to implement access to the shared space module; wherein the two completely independent PCIE decoders are PCIE decoder 1 and PCIE decoder 2;

[0009] The shared space module includes two independent spaces opened up by underlying hardware logic, which are used by application thread 1 and application thread 2 of the application software module to read and write data respectively.

[0010] Among them, there is only one PCIE physical link between the application software module and the PCIE dual address mapping module. By instantiating two completely independent PCIE address spaces inside the PCIE IP core, dual application threads can read and write two completely independent PCIE address spaces in parallel through virtualized dual PCIE without interfering with each other.

[0011] Among them, there is only one SRIO physical path between the PCIE dual address mapping module and the shared space module. Through the SRIO access arbitration mechanism, the dual PCIE address spaces can access SRIO alternately, realizing the virtualization of the dual PCIE address space. After passing through SRIO, the two shared spaces are read and written without cross-talk, thereby ensuring the access time of the two application threads.

[0012] The system can be rapidly expanded and used, and multiple application software modules can simultaneously access a shared space module in combination with a PCIE dual address mapping module, thereby realizing real-time sharing of data between multiple application threads of different application software modules.

[0013] The application software module can be run on a CPU platform.

[0014] The PCIE dual-address mapping module can run on an FPGA platform.

[0015] The shared space module can run on a DSP platform.

[0016] The communication interface between the CPU platform and the FPGA platform is a 4x PCIE interface, and the communication interface between the FPGA platform and the DSP platform is a 4x SRIO interface.

[0017] The specific steps of the dual-threaded parallel reading and writing shared space system are as follows:

[0018] Step 1: Application thread 1 on the CPU platform accesses PCIE decoder 1 on the FPGA platform by calling the PCIE driver; application thread 2 accesses PCIE decoder 2 on the FPGA platform by calling the PCIE driver;

[0019] Step 2: SRIO access arbitration mechanism: interprets the bus data of PCIE decoder 1 and PCIE decoder 2, then alternately accesses the SRIO IP core to perform read and write operations on the SRIO node on the DSP platform;

[0020] Step 3: The space is divided on the DSP platform. Application thread 1 can only write to the first address space of 0xD..., and application thread 2 can only write to the first address space of 0x8.... Application thread 1 and application thread 2 can read data in any space to ensure that the data will not be tampered with and that reading and writing do not interfere with each other.

[0021] (3) Beneficial effects

[0022] Compared with the existing technology, the present invention breaks the traditional point-to-point data communication mode. Through software-defined PCIE dual-address mapping and SRIO arbitration mechanism, a processor can independently read and write external shared space when running a dual-threaded application component. This solves the problem of mutual interference and access competition when dual threads communicate between heterogeneous platforms, ensuring that dual threads do not interfere with each other when communicating between heterogeneous platforms and that access time is controllable. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A system diagram showing dual-threaded parallel reading and writing of shared space. DETAILED DESCRIPTION

[0024] In order to make the purpose, content, and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below with reference to the accompanying drawings and examples.

[0025] In order to solve the above technical problems, the present invention provides a dual-threaded parallel reading and writing shared space system, the system comprising: an application software module, a PCIE dual address mapping module, and a shared space module;

[0026] The application software module includes: application thread 1, application thread 2, and PCIE driver. Application thread 1 and application thread 2 can independently call the PCIE driver.

[0027] The PCIE dual address mapping module includes: a PCIE IP core, an SRIO access arbitration mechanism, and an SRIO IP core; the PCIE IP core internally instantiates two completely independent PCIE decoders, address FIFOs, command FIFOs, write data FIFOs, and read data FIFOs to form two independent PCIE address spaces; the SRIO access arbitration mechanism determines the access order based on the address, data, and command information of the two independent PCIE address spaces to achieve a mapping relationship between the dual PCIE address spaces and the single SRIO address space; the SRIO IP core is used to implement access to the shared space module; wherein the two completely independent PCIE decoders are PCIE decoder 1 and PCIE decoder 2;

[0028] The shared space module includes two independent spaces opened up by underlying hardware logic, which are used by application thread 1 and application thread 2 of the application software module to read and write data respectively.

[0029] Among them, there is only one PCIE physical link between the application software module and the PCIE dual address mapping module. By instantiating two completely independent PCIE address spaces inside the PCIE IP core, dual application threads can read and write two completely independent PCIE address spaces in parallel through virtualized dual PCIE without interfering with each other.

[0030] Among them, there is only one SRIO physical path between the PCIE dual address mapping module and the shared space module. Through the SRIO access arbitration mechanism, the dual PCIE address spaces can access SRIO alternately, realizing the virtualization of the dual PCIE address space. After passing through SRIO, the two shared spaces are read and written without cross-talk, thereby ensuring the access time of the two application threads.

[0031] The system can be rapidly expanded and used, and multiple application software modules can simultaneously access a shared space module in combination with a PCIE dual address mapping module, thereby achieving real-time sharing of data between multiple application threads of different application software modules.

[0032] The application software module can be run on a CPU platform.

[0033] The PCIE dual-address mapping module can run on an FPGA platform.

[0034] The shared space module can run on a DSP platform.

[0035] The communication interface between the CPU platform and the FPGA platform is a 4x PCIE interface, and the communication interface between the FPGA platform and the DSP platform is a 4x SRIO interface.

[0036] The specific steps of the dual-threaded parallel reading and writing shared space system are as follows:

[0037] Step 1: Application thread 1 on the CPU platform accesses PCIE decoder 1 on the FPGA platform by calling the PCIE driver; application thread 2 accesses PCIE decoder 2 on the FPGA platform by calling the PCIE driver;

[0038] Step 2: SRIO access arbitration mechanism: interprets the bus data of PCIE decoder 1 and PCIE decoder 2, then alternately accesses the SRIO IP core to perform read and write operations on the SRIO node on the DSP platform;

[0039] Step 3: The space is divided on the DSP platform. Application thread 1 can only write to the first address space of 0xD..., and application thread 2 can only write to the first address space of 0x8.... Application thread 1 and application thread 2 can read data in any space to ensure that the data will not be tampered with and that reading and writing do not interfere with each other.

[0040] Example 1

[0041] In this embodiment, the application software module can run on the CPU platform, the PCIE dual address mapping module can run on the FPGA platform, and the shared space module can run on the DSP platform. The communication interface between the CPU and FPGA is a 4x PCIE interface, and the communication interface between the FPGA and DSP is a 4x SRIO interface. Specific steps: Application thread 1 on the CPU platform accesses PCIE decoder 1 on the FPGA platform by calling the PCIE driver; application thread 2 accesses PCIE decoder 2 on the FPGA platform by calling the PCIE driver; the SRIO access arbitration mechanism interprets the bus data of PCIE decoder 1 and PCIE decoder 2, and then alternately accesses the SRIO IP core to perform read and write operations on the SRIO node on the DSP platform; the space on the DSP platform is divided, and application thread 1 can only write to the first address space of 0xD..., and application thread 2 can only write to the first address space of 0x8.... Application thread 1 and application thread 2 can read data in any space, ensuring that the data will not be tampered with and that reads and writes do not interfere with each other.

[0042] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A dual-threaded parallel reading and writing shared space system, characterized in that: The system includes: an application software module, a PCIE dual address mapping module, and a shared space module; The application software module includes: application thread 1, application thread 2, and PCIE driver. Application thread 1 and application thread 2 can independently call the PCIE driver. The PCIE dual address mapping module includes: a PCIE IP core, an SRIO access arbitration mechanism, and an SRIO IP core; the PCIE IP core internally instantiates two completely independent PCIE decoders, address FIFOs, command FIFOs, write data FIFOs, and read data FIFOs to form two independent PCIE address spaces; the SRIO access arbitration mechanism determines the access order based on the address, data, and command information of the two independent PCIE address spaces to achieve a mapping relationship between the dual PCIE address spaces and the single SRIO address space; the SRIO IP core is used to implement access to the shared space module; wherein the two completely independent PCIE decoders are PCIE decoder 1 and PCIE decoder 2; The shared space module includes: two independent spaces opened up by the underlying hardware logic, which are used by application thread 1 and application thread 2 of the application software module to read and write data respectively.

2. The dual-threaded parallel reading and writing shared space system according to claim 1, characterized in that: There is only one PCIE physical link between the application software module and the PCIE dual address mapping module. By instantiating two completely independent PCIE address spaces inside the PCIEIP core, dual application threads can read and write two completely independent PCIE address spaces in parallel through virtualized dual PCIE without interfering with each other.

3. The dual-threaded parallel reading and writing shared space system according to claim 2, characterized in that: There is only one SRIO physical path between the PCIE dual address mapping module and the shared space module. Through the SRIO access arbitration mechanism, the dual PCIE address spaces can access SRIO alternately, realizing the virtualization of the dual PCIE address space. After passing through SRIO, the two shared spaces are read and written without cross-talk, thereby ensuring the access time of the two application threads.

4. The dual-threaded parallel reading and writing shared space system according to claim 3, characterized in that: The system can be rapidly expanded and used, and multiple application software modules can simultaneously access a shared space module in combination with the PCIE dual address mapping module, thereby realizing real-time sharing of data between multiple application threads of different application software modules.

5. The dual-threaded parallel reading and writing shared space system according to claim 4, characterized in that: The application software module can run on a CPU platform.

6. The dual-threaded parallel reading and writing shared space system according to claim 5, characterized in that: The PCIE dual-address mapping module can run on an FPGA platform.

7. The dual-threaded parallel reading and writing shared space system according to claim 6, characterized in that: The shared space module can run on a DSP platform.

8. The dual-threaded parallel reading and writing shared space system according to claim 7, characterized in that: The communication interface between the CPU platform and the FPGA platform is a 4x PCIE interface, and the communication interface between the FPGA platform and the DSP platform is a 4xSRIO interface.

9. The dual-threaded parallel reading and writing shared space system according to claim 8, characterized in that: The specific steps of the dual-threaded parallel reading and writing shared space system are as follows: Step 1: Application thread 1 on the CPU platform accesses PCIE decoder 1 on the FPGA platform by calling the PCIE driver; Application thread 2 accesses PCIE decoder 2 on the FPGA platform by calling the PCIE driver; Step 2: SRIO access arbitration mechanism: interprets the bus data of PCIE decoder 1 and PCIE decoder 2, then alternately accesses the SRIO IP core to perform read and write operations on the SRIO node on the DSP platform; Step 3: The space is divided on the DSP platform. Application thread 1 can only write to the first address space of 0xD..., and application thread 2 can only write to the first address space of 0x8.... Application thread 1 and application thread 2 can read data in any space to ensure that the data will not be tampered with and that reading and writing do not interfere with each other.

10. The dual-threaded parallel reading and writing shared space system according to claim 9, characterized in that: The system breaks the traditional point-to-point data communication mode and, through software-defined PCIE dual-address mapping and SRIO arbitration mechanisms, enables a processor to independently read and write external shared space when running a dual-threaded application component, solving the problem of mutual serial communication and access contention between dual threads when communicating between heterogeneous platforms.

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