Three-dimensional on-chip brain real-time closed-loop control system and method, storage medium and equipment

Abstract

The invention discloses a three-dimensional on-chip brain real-time closed-loop control system and method, a storage medium and equipment, and belongs to the technical field of on-chip brains.The three-dimensional on-chip brain real-time closed-loop control method mainly comprises the steps that neural data generated by a multi-channel electrophysiological system is tracked in real time based on a Watchdog file monitoring mechanism; adjusting the neural data in combination with a timestamp alignment mechanism to realize synchronization of the neural signal and the stimulation event; processing the neural data in combination with a triple annular buffer architecture and a self-adaptive time window partitioning strategy, and circularly storing the newest data; and dynamically adjusting stimulation parameters according to the neural data and the change of the external environment, and feeding back the adjusted stimulation parameters to the multi-channel electrophysiological system for a stimulation experiment. Through a closed-loop feedback mechanism, an intelligent buffer system and a multi-source data synchronous alignment technology, the technical defects of an existing open-loop system are overcome, and high-precision and low-delay three-dimensional on-chip brain dynamic interaction is achieved.

Description

Technical Field

[0001] The present invention relates to the field of brain-on-chip technology, and in particular to a three-dimensional brain-on-chip real-time closed-loop control system, method, storage medium and device. Background Art

[0002] The brain-computer interface on a chip is a technology that uses the coupling of an in vitro cultured brain and an electrode chip to form an on-chip brain, and realizes information interaction with the outside world through encoding and decoding technology and a stimulation feedback system. It is of great significance for exploring the fusion and interaction of the new generation of living and non-living things, and forming new applications in major national demand areas such as hybrid intelligence, brain-like computing, and medical rehabilitation.

[0003] In current neuroscience research, electrophysiological signal acquisition and stimulation control systems are core tools for exploring the functions and mechanisms of the nervous system. Typical multi-channel electrophysiological systems, such as the Intan RHS system, have become mainstream research equipment in this field due to their high-sensitivity amplifiers and multi-channel data acquisition capabilities. The 3D brain-on-chip (BOC), which mimics the three-dimensional structure of a real brain, holds significant value in neurobiology and brain-inspired computing research. Composed of neurons and glial cells distributed within a 500-600μm-thick extracellular matrix and hydrogel scaffold, its cellular morphology and density more closely resemble the structure of a real brain. Theoretically, it can more effectively simulate in vivo neuronal activity than planar BOCs, offering unique advantages in neurobiology and electrophysiology research. Stereoscopic neural signal acquisition devices can meet the stereoscopic signal acquisition needs of 3D BOCs composed of brain organoids. These devices are primarily classified into three categories: implantable rigid electrodes, grid electrodes, and shell electrodes. Combined with the Intan RHS system, they enable real-time analysis of 3D BOC discharge data and electrical stimulation control.

[0004] However, 3D brain-on-a-chip research based on the Intan RHS system currently only supports open-loop systems. Although it can achieve stimulation and signal acquisition of the brain-on-a-chip, it has obvious limitations:

[0005] 1. Lack of real-time feedback capability: The core problem of the open-loop system is the inability to dynamically adjust stimulation parameters based on real-time feedback, resulting in insufficient feedback capability and delayed dynamic parameter adjustment, making it unable to adapt to ever-changing task requirements.

[0006] 2. Data delay leads to error accumulation: The existing Intan RHS system relies on manual operation and offline data analysis, and cannot respond to feedback signals from external stimuli in real time. The processing delay is high (usually >100ms), which affects the experimental accuracy.

[0007] 3. Fragmented tool chain: Due to the lack of a unified interface, interdisciplinary researchers need to develop complex control logic on their own, which is inefficient. Summary of the Invention

[0008] The purpose of the present invention is to overcome the problems existing in the existing open-loop system and provide a three-dimensional brain-on-chip real-time closed-loop control system, method, storage medium and equipment. By constructing an external closed-loop system loop, the real-time neural data collection and processing can be accurately adjusted according to the activity state of the brain-on-chip and changes in the external environment. Stimulation parameters can be dynamically adjusted to adapt to the ever-changing task requirements.

[0009] The object of the present invention is achieved through the following technical solutions:

[0010] In a first aspect, a three-dimensional brain-on-chip real-time closed-loop control system is provided, comprising:

[0011] Neural data monitoring module, which is used to track the neural data generated by the multi-channel electrophysiological system in real time based on the Watchdog file monitoring mechanism;

[0012] A neural data synchronization module, configured to adjust the neural data in combination with a timestamp alignment mechanism to synchronize neural signals with stimulation events;

[0013] A neural data cache module is used to process the neural data by combining a triple ring buffer architecture with an adaptive time window blocking strategy and cyclically store the latest data;

[0014] A command control interface module is used to communicate with the multi-channel electrophysiological system based on the TCP / IP protocol, dynamically adjust the stimulation parameters according to the neural data and changes in the external environment, and feed the adjusted stimulation parameters back to the multi-channel electrophysiological system for stimulation experiments;

[0015] The experimental design and execution module provides a programmable interface that allows users to customize experimental paradigms.

[0016] In some embodiments, the real-time tracking of neural data generated by a multi-channel electrophysiological system based on a Watchdog file monitoring mechanism includes:

[0017] A dynamic classification engine based on file name semantics is used to perform differentiated processing on different types of neural data.

[0018] In some embodiments, the differential processing of different types of neural data includes:

[0019] For timestamp data, sequential positioning reading combined with type conversion time mode is adopted; for neural signal data, multi-file parallel reading combined with numerical scaling amp mode is adopted; for stimulation data, bit operation analysis combined with structured data extraction stim mode is adopted.

[0020] In some embodiments, adjusting the neural data in conjunction with a timestamp alignment mechanism includes:

[0021] Memory mapping optimization and global sample bus indexing are used to ensure the synchronization between different types of data in neural data; open addressing and linear detection strategies are used to establish mapping tables for neural signal data, stimulation data and timestamps respectively.

[0022] In some embodiments, adjusting the neural data in conjunction with a timestamp alignment mechanism further includes:

[0023] When alignment is abnormal, the exception handling protocol is triggered, including:

[0024] When a sample is missing from the timestamp file, a sample backtracking compensation mechanism is initiated;

[0025] When it is detected that the timestamp file is in reverse order, a global time base recalibration is triggered and the mapping table is updated;

[0026] When there is a timing discrepancy between stimulus and response, the event log is recorded and the stimulus output is suspended.

[0027] In some embodiments, the adaptive time window blocking strategy includes:

[0028] Set the reference time window and dynamically calculate the sample number threshold based on the sampling rate;

[0029] Adjust the size of the benchmark time window based on the system load rate and CPU utilization.

[0030] In some embodiments, the triple ring buffer architecture includes a data storage ring, a metadata index ring, and an exception handling ring, wherein the data storage ring adopts a batch forward strategy and automatically rolls back to the starting end of the ring when it crosses the boundary, the metadata index ring adopts a smooth catch-up strategy and triggers an accelerated catch-up protocol when the lag exceeds the limit, and the exception handling ring adopts periodic retracement to verify data integrity and perform exception marking and isolation.

[0031] In a second aspect, a three-dimensional brain-on-chip real-time closed-loop control method is provided, comprising:

[0032] Based on the Watchdog file monitoring mechanism, real-time tracking of neural data generated by multi-channel electrophysiological systems;

[0033] Adjusting the neural data in conjunction with a timestamp alignment mechanism to synchronize neural signals with stimulation events;

[0034] Combining a triple ring buffer architecture with an adaptive time window partitioning strategy to process the neural data and cyclically store the latest data;

[0035] The stimulation parameters are dynamically adjusted according to the neural data and changes in the external environment, and the adjusted stimulation parameters are fed back to the multi-channel electrophysiological system for stimulation experiments.

[0036] In a third aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the real-time closed-loop control method described in the second aspect is implemented.

[0037] In a fourth aspect, an electronic device is provided, comprising a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, and when the processor executes the computer instructions, the real-time closed-loop control method described in the second aspect is executed.

[0038] It should be further explained that the technical features corresponding to the above embodiments can be combined or replaced with each other to form a new technical solution if there is no conflict.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. The present invention forms a closed-loop feedback mechanism by tracking the neural data generated by a multi-channel electrophysiological system in real time, dynamically adjusting the stimulation parameters according to the neural data and changes in the external environment, and feeding the adjusted stimulation parameters back to the multi-channel electrophysiological system for stimulation experiments. This allows for dynamic compensation and optimization of the stimulation parameters to adapt to ever-changing task requirements. During three-dimensional brain-on-chip tasks, it allows for real-time encoding of environmental information into electrical stimulation, and real-time observation and evaluation of neuronal activity, allowing for deeper exploration of the dynamic response and learning mechanisms of the brain-on-chip. At the same time, it provides a new research paradigm and closed-loop system construction solution for other fields of neuroscience, brain-like computing, and medical rehabilitation.

[0041] 2. The present invention achieves high-precision, low-latency three-dimensional brain-on-chip dynamic interaction through an intelligent buffer system and multi-source data synchronization alignment technology. Specifically, the adaptive buffer control algorithm and the ring buffer architecture design significantly reduce the memory operation overhead by 90%, ensuring high reliability of data processing when performing experimental tasks.

[0042] 3. The present invention provides users with the function of communicating with multi-channel electrophysiological systems, realizing key operations such as remote parameter setting, experimental process control, and experimental data acquisition; provides a programmable interface to realize the automated control of customized processes, lowering the threshold for interdisciplinary research, and allows users to use the interface to send relevant instructions to control the progress of experiments in real time, thereby reducing errors caused by human operation, and making rapid adjustments based on real-time data to adapt to complex situations under closed-loop experiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a schematic diagram of closed-loop communication between a three-dimensional brain-on-chip real-time closed-loop control system and a multi-channel electrophysiological system according to an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of file lifecycle tracking according to an embodiment of the present invention;

[0045] Figure 3 This is a process of the system of the present invention obtaining IntanRHS system data in real time, as shown in an embodiment of the present invention;

[0046] Figure 4 This is an embodiment of the present invention showing the process of stimulus control by the system of the present invention. DETAILED DESCRIPTION

[0047] The technical solutions of the present invention are described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings herein can be arranged and designed in various different configurations. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0048] It should be noted that the defects existing in the solutions in the above-mentioned prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above-mentioned problems and the solutions proposed in the embodiments of this application below for the above-mentioned problems should be the contributions made by the inventor to this application in the process of invention and creation, and should not be understood as technical contents known to technical personnel in this field.

[0049] In response to the technical problems pointed out in the background technology, the embodiments provided by the present invention are as follows:

[0050] Reference Figure 1 In one exemplary embodiment, a three-dimensional brain-on-chip real-time closed-loop control system is provided, comprising:

[0051] Neural data monitoring module, which is used to track the neural data generated by the multi-channel electrophysiological system in real time based on the Watchdog file monitoring mechanism;

[0052] A neural data synchronization module, configured to adjust the neural data in combination with a timestamp alignment mechanism to synchronize neural signals with stimulation events;

[0053] A neural data cache module is used to process the neural data by combining a triple ring buffer architecture with an adaptive time window blocking strategy and cyclically store the latest data;

[0054] A command control interface module is used to communicate with the multi-channel electrophysiological system based on the TCP / IP protocol, dynamically adjust the stimulation parameters according to the neural data and changes in the external environment, and feed the adjusted stimulation parameters back to the multi-channel electrophysiological system for stimulation experiments;

[0055] The experimental design and execution module provides a programmable interface that allows users to customize experimental paradigms.

[0056] This implementation utilizes the IntanRHS multi-channel electrophysiology system as its core architecture, leveraging its stimulation and recording capabilities. External systems connect to designated ports on the Intan RHS system. While maintaining the control precision of the native Intan RHS interface, it also provides a high-level abstract interface, making it easier for researchers to design and execute complex experimental paradigms, including conditional stimulation and state querying, thus overcoming the limitations of the original system in experimental flexibility.

[0057] The implementation details of each module of this system are given below.

[0058] The neural data monitoring module ensures that the three-dimensional neural data collected from the Intan RHS system are accurately stored and synchronized. This system uses the Watchdog file monitoring mechanism to track in real time the data files generated by the Intan RHS system, such as the stimulation data file stim.dat, the timestamp file time.dat, and the amplifier data file amp.dat (for neural signals). The file monitoring component of the neural data monitoring module will instantly capture the creation events of these files. The design of the neural data monitoring module includes the ability to monitor new directories. When a new data subdirectory is created, the monitoring focus will automatically shift to the latest subdirectory. This ensures the continuity and integrity of data acquisition.

[0059] Furthermore, the neural data monitoring module implements a dynamic classification engine based on file name semantics to implement targeted enhancement design and perform differentiated processing on different types of neural data. It also proposes a classification-driven streaming data governance architecture to break through the indiscriminate processing bottleneck of traditional solutions. Specifically, it includes:

[0060] 1. Build a typing reading strategy manager: Build an automatic classification system based on naming conventions to achieve intelligent mapping of file name classification → processing strategy:

[0061]

[0062] The best processing paradigm is preset for different file types. For timestamp data, sequential positioning reading combined with type conversion time mode is used:

[0063] Processing engine: TimestampSyncHandler

[0064] Reading mode: Sequential positioning reading + type conversion time mode

[0065] Data characteristics: 32-bit integer (np.int32)

[0066] Positioning mechanism: Positioning based on the precise offset of the number of stored samples (self.stored_samples*4).

[0067] For neural signal data, multi-file parallel reading combined with numerical scaling amp mode is used:

[0068] Processing engine:NeuralSignalHandler

[0069] Reading mode: parallel reading of multiple files + numerical scaling amp mode

[0070] Data characteristics: 16-bit integer (np.int16)

[0071] Positioning mechanism: precise offset positioning based on the number of stored samples (self.stored_samples*2)

[0072] Data conversion: The raw integer value is multiplied by the amplifier scaling factor (self.d_scale) to convert it to physical units (such as voltage).

[0073] For stimulus data, bit operation parsing combined with structured data is used to extract the stim pattern:

[0074] Processing engine: StimulationHandler

[0075] Read mode: bit operation parsing + structured data extraction stim mode

[0076] Data characteristics: 16-bit unsigned integer (np.uint16), containing various status information

[0077] Positioning mechanism: precise offset positioning based on the number of stored samples (self.stored_samples*2)

[0078] Data conversion: Use bit operations to extract current amplitude, sign, and various status flags

[0079] - The lower 8 bits are used for current amplitude (0-255)

[0080] - The 9th bit (256) is used to determine the sign

[0081] - Bits 14-16 are used for status flags

[0082] 2. Build a file lifecycle tracker: define file status transition rules to ensure strict synchronization of processing logic with the Intan RHS system recording cycle, such as Figure 2 shown.

[0083] In terms of data synchronization, the system features an efficient timestamp alignment mechanism to ensure strict synchronization between amplifier data and corresponding stimulation data. The system adjusts the time alignment of data blocks based on the contents of the timestamp file time.dat, which is crucial for subsequent data analysis and real-time feedback. The neural data synchronization module uses memory mapping optimization and global sample bus indexing to ensure synchronization between different types of data in the neural data. Specifically, it includes the following:

[0084] 1. Memory mapping optimization and index structure design

[0085] Using operating system-level memory mapping technology, the physical storage space of the timestamp file (time.dat) is directly mapped to the virtual address space, bypassing the multiple copy processes of traditional file I / O and achieving zero-copy access with microsecond latency. The clock source directly uses the high-precision timestamp recorded in the time.dat file (generated by the built-in microsecond timer of the Intan RH S system). A global sample bus index across data sources is constructed to integrate and synchronize multiple data sources, including:

[0086] Sample number → timestamp mapping table: Each time timestamp data is read, the newly read sample number and timestamp correspondence is added to the hash table. Using open addressing and linear probing, a primary and secondary hash values are calculated for each sample number. When a conflict occurs, linear probing is used to find the next available location. A locality-sensitive hash function design maps similar sample numbers to similar hash buckets, reducing cache misses. Supports fast retrieval of corresponding timestamps by sample number in the neural signal file (amp.dat).

[0087] Timestamp → Sample Number Ordered Dictionary: Builds an index structure that maintains time order. The B+ tree portion is used for range queries, while the skip list portion provides fast single-point access. Implements an in-memory cache layer for hot time intervals (such as recently accessed experimental snippets) to reduce tree traversal overhead. Supports fast range queries and concurrent reads based on time ranges.

[0088] Stimulus command number to timestamp mapping table: When parsing the stimulation parameters and status bits in the stim-*.dat files, each stimulation event identifier is mapped to its corresponding timestamp. This table is implemented using a hash table with open addressing and linear probing, applying locality-sensitive hashing to reduce conflicts and enabling fast retrieval of the corresponding timestamp by sample number in the stimulation parameter file (stim.dat).

[0089] 2. Multi-source alignment core process

[0090] Input: Amp sample number N_amp; stimulation instruction number N_stim.

[0091] Alignment algorithm:

[0092] 1). Get the timestamp T_amp corresponding to N_amp through the time.dat index

[0093] 2) Get the timestamp T_stim corresponding to N_stim

[0094] 3). Calculate the absolute time difference ΔT = |T_amp - T_stim|

[0095] 4).ifΔT≤Δ_threshold (default 50μs):

[0096] Generate alignment packets.

[0097] else:

[0098] Trigger the exception handling protocol.

[0099] 3. Anomaly detection and processing system

[0100] 3.1. The anomaly type matrix is shown in Table 1.

[0101] Table 1. Exception types and handling strategies

[0102]

[0103] 3.2. Sample Backtracking Compensation Mechanism

[0104] Forward missing compensation: When time.dat sample missing is detected, it is calculated based on the timestamp of the previous valid sample + theoretical interval.

[0105] Backward redundancy check: For each processed sample, retain the timestamp copies of samples N-1, N, and N+1, and ensure consistency through three checks.

[0106] 3.3. Global Time Base Recalibration

[0107] 1) Confirmation of test points

[0108] -When a timestamp reversal issue is discovered, record the location where the issue occurred;

[0109] - Determine the last correct timestamp location and value.

[0110] 2) Reset the baseline

[0111] - Use the last correct timestamp as the new reference point;

[0112] - Reposition the read pointer of the time.dat file to this location.

[0113] 3) Reread and calibrate

[0114] - Re-read a time stamp sequentially starting from the calibration point;

[0115] - Enforce a monotonically increasing check on the timestamps of all subsequent new reads.

[0116] 4) Update the index

[0117] - Simply clear and rebuild the timestamp index of the affected part;

[0118] - Update the timestamp mapping between sample number and stimulation instruction number.

[0119] The specific implementation mechanism of the neural data cache module is as follows:

[0120] 1. Adaptive time window blocking mechanism:

[0121] Dynamically adjust the data block length based on the experimental scenario to achieve the best balance between processing efficiency and real-time performance:

[0122] Benchmark block rule: The default benchmark time window is 100ms (which can be adjusted according to actual conditions). The sample number threshold is dynamically calculated based on the sampling rate: Sample number threshold = sampling rate (Hz) × 0.1s × safety factor.

[0123] Flexible adjustment strategy:

[0124] Extension conditions: When the system load rate is less than 40%, the window is automatically extended to 200ms to improve throughput;

[0125] Contraction conditions: When CPU utilization is > 75%, the window is shortened to 50ms to reduce latency.

[0126] 2. Cross-source data block assembly

[0127] Establish a three-source data flow collaborative triggering mechanism to ensure data integrity:

[0128] Synchronization trigger condition: the number of available samples ≥ 1000 sample number threshold (timestamp / neural signal / stimulation data three channels).

[0129] 3. Data organization specifications within the block

[0130] A matrix storage structure is used to improve access efficiency, and each data block carries a CRC16 checksum for data integrity verification:

[0131]

[0132] 4. Innovative design of ring buffer architecture

[0133] 4.1. Multi-ring collaborative storage structure: Constructing triple logical ring areas to achieve physical isolation and logical unification:

[0134] ●Data storage ring:

[0135] A state storage area connected end to end to store complete data blocks.

[0136] Metadata index ring:

[0137] Records metadata such as block start time, sample range, and status flags.

[0138] ●Exception handling loop:

[0139] Save diagnostic information such as data verification anomalies and compensation records.

[0140] 4.2. Pointer control strategy, as shown in Table 2.

[0141] Table 2. Pointer control strategies

[0142]

[0143] 4.2.1. Write pointer technology implementation

[0144] Batch forward mechanism:

[0145] ●The write pointer moves in units of fixed-size data blocks each time

[0146] ● Update the write pointer position through atomic operations to ensure consistency in a multi-threaded environment ● Dynamically adjust the batch size based on the write rate (W_speed) in the dual-rate prediction model, and increase the batch size when writing at high speed

[0147] ●Maintain write block counter and update write rate statistics every 10 blocks

[0148] Out-of-bounds wrapping processing:

[0149] ● Maintain the total capacity and current used capacity counter of the ring buffer

[0150] ●Wrap-around is triggered when the write pointer position + the next data block size > the end of the loop

[0151] The wrap operation resets the write pointer to the beginning of the ring using an atomic instruction.

[0152] ●Record rollback events to the event log for easy subsequent analysis of buffer usage

[0153] 4.2.2. Read pointer technology implementation

[0154] Smooth pursuit strategy:

[0155] ●Adjust the read step size based on the imbalance coefficient to maintain a balance between read and write rates

[0156] ● Fixed step size (1 block / cycle) in normal mode, dynamic step size in catch-up mode ● S-curve function is used to smooth step size changes to prevent processing fluctuations caused by sudden changes in reading speed

[0157] Hysteresis overrun processing:

[0158] ●Monitor the read / write pointer gap and trigger accelerated catch-up when it exceeds the threshold (30%)

[0159] ●Temporarily increase the reading batch in acceleration mode until the safe distance is restored

[0160] ● Issue a warning if the limit is exceeded continuously and reduce the writing speed if necessary

[0161] 4.2.3. Check pointer technology to implement periodic retrace mechanism:

[0162] ● Checkpointers run independently at fixed intervals (500ms) to verify data integrity ● Block-level verification using the uint16_t crc field in each TimeBlock, prioritizing newly written data blocks to reduce overall verification overhead Abnormal marking and isolation:

[0163] ●When a data block that fails CRC check is found, a flag is added and recorded in the exception log ●The abnormal block is isolated to prevent the subsequent processing from using this data

[0164] ●Trigger the exception notification mechanism, allowing upper-layer applications to decide the processing strategy.

[0165] 5. Adaptive buffer control algorithm

[0166] 5.1. Dual-rate prediction model

[0167] ●Write rate (W_speed): Statistics on the average write interval of the last 10 data blocks ●Read rate (R_speed): Calculate the actual processing speed based on the feedback from the read module ●Imbalance calculation:

[0168] Unbalance coefficient = (W_speed - R_speed) / max(W_speed, R_speed)

[0169] 5.2. Pointer Control Strategy

[0170] Normal mode (|imbalance coefficient|<0.1):

[0171] The read pointer advances in fixed steps (1 block / cycle)

[0172] ●Catch-up mode (imbalance coefficient ≥ 0.1):

[0173] Dynamically adjust the catching-up step size: step size = basic step size × (1 + log2 (imbalance coefficient))

[0174] 5.3. Smooth state transition: Use an S-shaped curve to adjust the step change rate to avoid severe pointer jitter.

[0175] This system integrates a timing-driven dynamic blocking strategy, a triple ring buffer architecture, and an adaptive index tracking algorithm to ensure the continuity and accuracy of data flow under high-load conditions. The file monitoring module based on regularized naming rules realizes the classification processing of different data types (neural signals, timestamps, stimulation parameters), and cooperates with memory mapping acceleration and the global sample bus index structure to effectively solve the problem of synchronous alignment of multi-source data. The system significantly reduces 90% of memory operation overhead through an adaptive time window blocking mechanism (50-200ms dynamic adjustment) and a ring buffer data management strategy, and automatically adjusts the read and write rate balance through an imbalance coefficient dynamic feedback mechanism. The complete anomaly detection and self-healing system can identify and correct anomalies such as sample discontinuity and timestamp inversion, ensuring high reliability of data processing when performing experimental tasks, and providing stable and efficient technical support for on-chip brain-computer interface research.

[0176] Furthermore, the instruction control interface module provides users with the function of communicating with the Intan RHS system, realizing key operations such as remote parameter setting, experimental process control and experimental data acquisition, including connecting and disconnecting from the server (IntanRHS system), configuring stimulation and recording parameters, setting experimental files and parameters, querying and verifying. This module interacts directly with the Intan RHS system through the TCP / IP protocol to ensure the real-time transmission and execution of instructions. Specifically, the external system is connected to the designated port of the IntanRHS system. While maintaining the control accuracy of the native interface of Intan RHS, it provides a high-level abstract interface.

[0177] The experiment design and execution module allows users to use the above-mentioned command control interface module to send relevant instructions to control the progress of the experiment in real time. It is easier to design and execute complex experimental paradigms, including conditional stimulation, status query, etc., thereby reducing errors in human operation and making rapid adjustments based on real-time data to adapt to complex situations in closed-loop experiments.

[0178] The process of stimulus control in this system is as follows Figure 4 Before running an experiment, ensure the Intan RHS system is powered on and the stimulation / recording controller is enabled (Intan RHS offers four modes. This issue does not apply when connecting to a real device; the default is stimulation / recording controller). In the Intan RHS system, go to Network -> Remote TCP Control and connect to 127.0.0.1, port 5000. The status should be "Pending." This will initiate the connection and allow you to run the experiment.

[0179] The process of this system acquiring IntanRHS system data in real time is as follows Figure 3 As shown in the figure, data exchange is based on disk reads and writes, reading incremental data at a near-real-time rate (latency <50ms), ensuring synchronization of timestamps with amplifier samples and stimulation data to avoid cumulative delays. Using a ring buffer instead of a traditional queue optimizes data storage and access strategies, reducing additional latency caused by data migration while achieving high reliability in data reading and processing.

[0180] It should be noted that the parameters or values involved in the present invention are not to be interpreted as limitations on the present application and can be adaptively adjusted according to actual conditions.

[0181] In another exemplary embodiment, based on the same inventive concept as the system, a three-dimensional brain-on-chip real-time closed-loop control method is provided, comprising:

[0182] Based on the Watchdog file monitoring mechanism, real-time tracking of neural data generated by multi-channel electrophysiological systems;

[0183] Adjusting the neural data in conjunction with a timestamp alignment mechanism to synchronize neural signals with stimulation events;

[0184] Combining a triple ring buffer architecture with an adaptive time window partitioning strategy to process the neural data and cyclically store the latest data;

[0185] The stimulation parameters are dynamically adjusted according to the neural data and changes in the external environment, and the adjusted stimulation parameters are fed back to the multi-channel electrophysiological system for stimulation experiments.

[0186] The principles of each step in the method are the same as those of the corresponding modules of the system and will not be described in detail here.

[0187] In another exemplary embodiment, based on the same inventive concept as the method, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the three-dimensional brain-on-chip real-time closed-loop control method provided by the embodiment of the present invention is implemented. Based on this understanding, the technical solution of this embodiment, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0188] In another exemplary embodiment, based on the same inventive concept as the method, an electronic device is provided, including a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, and when the processor runs the computer instructions, it executes the three-dimensional brain-on-chip real-time closed-loop control method provided by an embodiment of the present invention.

[0189] The processor may be a single-core or multi-core central processing unit or a specific integrated circuit, or one or more integrated circuits configured to implement the present invention.

[0190] Embodiments of the subject matter and functional operations described in this specification may be implemented in: tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and their structural equivalents, or a combination of one or more thereof. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by a data processing apparatus or to control the operation of the data processing apparatus. Alternatively or in addition, the program instructions may be encoded on an artificially generated propagated signal, such as a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode and transmit information to a suitable receiver apparatus for execution by the data processing apparatus.

[0191] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform the corresponding functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0192] Processors suitable for executing computer programs include, for example, general-purpose and / or special-purpose microprocessors, or any other type of central processing unit. Typically, a central processing unit will receive instructions and data from a read-only memory and / or random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or the computer will be operably coupled to such a mass storage device to receive data from it or to transmit data to it, or both. However, a computer does not necessarily have such a device. In addition, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0193] It should be understood that each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the part of the module, program segment or code comprises one or more executable instructions for realizing the logical function of the provision. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the function or action of the provision, or can be implemented with a combination of dedicated hardware and computer instructions.

[0194] The above specific implementation methods are detailed descriptions of the present invention. It cannot be considered that the specific implementation methods of the present invention are limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, they can make several simple deductions and substitutions without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A three-dimensional brain-on-chip real-time closed-loop control system, characterized in that: include: Neural data monitoring module, which is used to track the neural data generated by the multi-channel electrophysiological system in real time based on the Watchdog file monitoring mechanism; A neural data synchronization module, configured to adjust the neural data in combination with a timestamp alignment mechanism to synchronize neural signals with stimulation events; A neural data cache module is used to process the neural data by combining a triple ring buffer architecture with an adaptive time window blocking strategy and cyclically store the latest data; A command control interface module is used to communicate with the multi-channel electrophysiological system based on the TCP / IP protocol, dynamically adjust the stimulation parameters according to the neural data and changes in the external environment, and feed the adjusted stimulation parameters back to the multi-channel electrophysiological system for stimulation experiments; The experimental design and execution module provides a programmable interface that allows users to customize experimental paradigms.

2. The three-dimensional brain-on-chip real-time closed-loop control system according to claim 1, characterized in that: The Watchdog file monitoring mechanism is used to track the neural data generated by the multi-channel electrophysiological system in real time, including: A dynamic classification engine based on file name semantics is used to perform differentiated processing on different types of neural data.

3. The three-dimensional brain-on-chip real-time closed-loop control system according to claim 2, characterized in that: The differentiated processing of different types of neural data includes: For timestamp data, sequential positioning reading combined with type conversion time mode is adopted; for neural signal data, multi-file parallel reading combined with numerical scaling amp mode is adopted; for stimulation data, bit operation analysis combined with structured data extraction stim mode is adopted.

4. The three-dimensional brain-on-chip real-time closed-loop control system according to claim 1, characterized in that: The adjusting the neural data by combining a timestamp alignment mechanism includes: Memory mapping optimization and global sample bus indexing are used to ensure the synchronization between different types of data in neural data; open addressing and linear detection strategies are used to establish mapping tables for neural signal data, stimulation data and timestamps respectively.

5. The three-dimensional brain-on-chip real-time closed-loop control system according to claim 4, characterized in that: The adjusting of the neural data in combination with the timestamp alignment mechanism further includes: When alignment is abnormal, the exception handling protocol is triggered, including: When a sample is missing from the timestamp file, a sample backtracking compensation mechanism is initiated; When it is detected that the timestamp file is in reverse order, a global time base recalibration is triggered and the mapping table is updated; When there is a timing discrepancy between stimulus and response, the event log is recorded and the stimulus output is suspended.

6. The three-dimensional brain-on-chip real-time closed-loop control system according to claim 1, characterized in that: The adaptive time window blocking strategy includes: Set the reference time window and dynamically calculate the sample number threshold based on the sampling rate; Adjust the size of the benchmark time window based on the system load rate and CPU utilization.

7. The three-dimensional brain-on-chip real-time closed-loop control system according to claim 1, characterized in that: The triple ring buffer architecture includes a data storage ring, a metadata index ring, and an exception handling ring. The data storage ring adopts a batch forward strategy and automatically rewinds to the starting end of the ring when it crosses the boundary. The metadata index ring adopts a smooth catch-up strategy and triggers an accelerated catch-up protocol when the lag exceeds the limit. The exception handling ring adopts a periodic retracement to verify data integrity and mark and isolate exceptions.

8. A three-dimensional brain-on-chip real-time closed-loop control method, characterized in that: include: Based on the Watchdog file monitoring mechanism, real-time tracking of neural data generated by multi-channel electrophysiological systems; Adjusting the neural data in conjunction with a timestamp alignment mechanism to synchronize neural signals with stimulation events; Combining a triple ring buffer architecture with an adaptive time window partitioning strategy to process the neural data and cyclically store the latest data; The stimulation parameters are dynamically adjusted according to the neural data and changes in the external environment, and the adjusted stimulation parameters are fed back to the multi-channel electrophysiological system for stimulation experiments.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the real-time closed-loop control method described in claim 8 is implemented.

10. An electronic device comprising a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, wherein: When the processor runs the computer instructions, the real-time closed-loop control method described in claim 8 is executed.

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