Three-dimensional on-chip brain real-time closed-loop control system, method, storage medium and device

Abstract

This invention discloses a real-time closed-loop control system, method, storage medium, and device for three-dimensional brain-on-a-chip, belonging to the field of brain-on-a-chip technology. It mainly includes: real-time tracking of neural data generated by a multi-channel electrophysiological system based on a Watchdog file monitoring mechanism; adjusting the neural data using a timestamp alignment mechanism to achieve synchronization between neural signals and stimulation events; processing the neural data using a triple-ring buffer architecture and an adaptive time window block strategy, and cyclically storing the latest data; dynamically adjusting stimulation parameters according to changes in the neural data and the external environment, and feeding the adjusted stimulation parameters back to the multi-channel electrophysiological system for stimulation experiments. This invention overcomes the technical shortcomings of existing open-loop systems through a closed-loop feedback mechanism, an intelligent buffer system, and multi-source data synchronization and alignment technology, achieving high-precision, low-latency dynamic interaction of a three-dimensional brain-on-a-chip.

Description

Technical Field

[0001] This invention relates to the field of brain-on-a-chip technology, and more particularly to a three-dimensional brain-on-a-chip real-time closed-loop control system, method, storage medium, and device. Background Technology

[0002] Brain-computer interfaces (BCIs) are technologies that use in vitro cultured brains coupled with electrode chips to form a brain-on-a-chip. Through encoding and decoding technologies and stimulation feedback systems, they enable interaction with the outside world. This technology is of great significance for exploring the integration and interaction between living and non-living entities in the next generation and for developing new applications in areas of major national needs such as hybrid intelligence, brain-like computing, and medical rehabilitation.

[0003] In current neuroscience research, electrophysiological signal acquisition and stimulation control systems are core tools for exploring the functions and mechanisms of the nervous system. Typical multi-channel electrophysiological systems (such as the Intan RHS system), with their high-sensitivity amplifiers and multi-channel data acquisition capabilities, have become mainstream research equipment in this field. Three-dimensional brain-on-chips, by simulating the three-dimensional structure of the real brain, are of significant value in neurobiology and brain-like computing research. They consist of an extracellular matrix and hydrogel scaffold with a thickness of 500μm-600μm, containing neurons and glial cells. Their cell morphology and density are more similar to the structure of the real brain, and theoretically, they can more effectively simulate the activity state of neurons in vivo than planar cultured brain-on-chips, giving them unique advantages in neurobiology and electrophysiology research. Three-dimensional neural signal acquisition devices can meet the acquisition needs of three-dimensional brain-on-chips composed of brain organoids. These devices are mainly divided into three categories: implantable rigid electrodes, mesh electrodes, and shell electrodes. Combined with the Intan RHS system, real-time analysis and electrical stimulation control of three-dimensional brain-on-chip discharge data can be achieved.

[0004] However, current research on three-dimensional brain slices based on the Intan RHS system only supports open-loop systems. Although it can stimulate and acquire signals from the brain slice, it has significant limitations:

[0005] 1. Lack of real-time feedback capability: The core problem of open-loop systems is that they cannot dynamically adjust stimulus parameters based on real-time feedback, resulting in insufficient feedback capability and lag in dynamic parameter adjustment, making them unable to adapt to constantly changing task requirements.

[0006] 2. Data delay leads to error accumulation: The existing Intan RHS system relies on manual operation and offline data analysis, and cannot respond to feedback signals from external stimuli in real time. The processing delay is high (usually >100ms), which affects the accuracy of experiments.

[0007] 3. Fragmented toolchain: The lack of a unified interface requires interdisciplinary researchers to develop complex control logic themselves, which is inefficient. Summary of the Invention

[0008] The purpose of this invention is to overcome the problems of existing open-loop systems and to provide a three-dimensional brain-on-a-chip real-time closed-loop control system, method, storage medium and device. By constructing an external closed-loop system circuit, the acquisition and processing of real-time neural data can accurately adjust the stimulation parameters dynamically according to the activity state of the brain-on-a-chip and changes in the external environment, thereby adapting to constantly changing task requirements.

[0009] The objective of this invention is achieved through the following technical solution:

[0010] Firstly, a three-dimensional brain-on-a-chip real-time closed-loop control system is provided, comprising:

[0011] The neural data monitoring module is used to track neural data generated by the multi-channel electrophysiological system in real time based on the Watchdog file monitoring mechanism.

[0012] The neural data synchronization module is used to adjust the neural data in conjunction with a timestamp alignment mechanism to achieve synchronization between neural signals and stimulus events;

[0013] The neural data caching module is used to process the neural data by combining a triple ring buffer architecture with an adaptive time window block strategy, and to cyclically store the latest data.

[0014] The instruction control interface module is used to communicate with the multi-channel electrophysiological system based on the TCP / IP protocol, dynamically adjust the stimulation parameters according to the neural data and changes in the external environment, and feed the adjusted stimulation parameters back to the multi-channel electrophysiological system for stimulation experiments.

[0015] The experiment design and execution module provides a programmable interface that allows users to customize experimental paradigms.

[0016] In some embodiments, the real-time tracking of neural data generated by the multi-channel electrophysiological system based on the Watchdog file monitoring mechanism includes:

[0017] A dynamic classification engine based on filename semantics performs differentiated processing on different types of data in neural data.

[0018] In some embodiments, the differential processing of different types of data in neural data includes:

[0019] For timestamp data, sequential positioning and reading combined with type conversion (time mode) are used; for neural signal data, multi-file parallel reading combined with numerical scaling (amp mode) is used; and for stimulus data, bit manipulation parsing combined with structured data extraction (stim mode) is used.

[0020] In some embodiments, adjusting the neural data using a timestamp alignment mechanism includes:

[0021] Memory mapping optimization and global sample bus indexing are employed to ensure synchronization between different types of data in neural data; in particular, open addressing and linear probing strategies are used to establish mapping tables for neural signal data, stimulus data and timestamps respectively.

[0022] In some embodiments, adjusting the neural data using a timestamp alignment mechanism further includes:

[0023] When an alignment error occurs, an exception handling protocol is triggered, which includes:

[0024] When a missing sample is detected in the timestamp file, the sample backtracking compensation mechanism is activated.

[0025] When a reversed timestamp file is detected, a global time base recalibration is triggered, and the mapping table is updated.

[0026] When there is a timing discrepancy between the stimulus and the response, record the event log and pause stimulus output.

[0027] In some embodiments, the adaptive time window segmentation strategy includes:

[0028] Set a baseline time window and dynamically calculate the sample number threshold based on the sampling rate;

[0029] Adjust the size of the baseline time window based on system load and CPU utilization.

[0030] In some embodiments, the triple ring buffer architecture includes a data storage ring, a metadata index ring, and an anomaly handling ring. The data storage ring adopts a batch forward strategy and automatically rolls back to the beginning of the ring when it goes out of bounds. The metadata index ring adopts a smooth catch-up strategy and triggers an acceleration catch-up protocol when the lag exceeds the limit. The anomaly handling ring adopts a periodic backscan to verify data integrity and performs anomaly marking and isolation.

[0031] Secondly, a three-dimensional brain-on-a-chip real-time closed-loop control method is provided, including:

[0032] Based on the Watchdog file monitoring mechanism, neural data generated by the multi-channel electrophysiological system is tracked in real time.

[0033] By combining the timestamp alignment mechanism with the neural data, the synchronization of neural signals and stimulus events can be achieved;

[0034] The neural data is processed by combining a triple ring buffer architecture with an adaptive time window block strategy, and the latest data is stored cyclically.

[0035] The stimulation parameters are dynamically adjusted based on the neural data and changes in the external environment, and the adjusted stimulation parameters are fed back to the multi-channel electrophysiological system for stimulation experiments.

[0036] Thirdly, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program, which, when executed by a processor, implements the real-time closed-loop control method described in the second aspect.

[0037] Fourthly, an electronic device is provided, including a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, and the processor executes the real-time closed-loop control method described in the second aspect when executing the computer instructions.

[0038] It should be further noted that the technical features corresponding to the above embodiments can be combined or substituted with each other to form new technical solutions without conflict.

[0039] Compared with the prior art, the beneficial effects of the present invention are:

[0040] 1. This invention tracks neural data generated by a multi-channel electrophysiological system in real time and dynamically adjusts stimulation parameters based on changes in this data and the external environment. The adjusted stimulation parameters are then fed back to the multi-channel electrophysiological system for stimulation experiments, forming a closed-loop feedback mechanism. This mechanism enables dynamic compensation and optimization of stimulation parameters, adapting to constantly changing task requirements. During three-dimensional brain-on-a-chip tasks, it allows for the real-time encoding of environmental information into electrical stimulation application and real-time observation and evaluation of neuronal activity, enabling a deeper exploration of the dynamic response and learning mechanisms of the brain-on-a-chip. Simultaneously, it provides a novel research paradigm and closed-loop system construction scheme for other fields such as neuroscience, brain-inspired computing, and medical rehabilitation.

[0041] 2. This invention achieves high-precision, low-latency three-dimensional brain-on-a-chip dynamic interaction through an intelligent buffer system and multi-source data synchronization and alignment technology. In particular, the adaptive buffer control algorithm and the circular buffer architecture design significantly reduce memory operation overhead by 90%, ensuring high reliability of data processing when performing experimental tasks.

[0042] 3. This invention provides users with the ability to communicate with a multi-channel electrophysiological system, enabling key operations such as remote parameter setting, experimental process control, and experimental data acquisition; it provides a programmable interface to automate custom processes, lowers the threshold for interdisciplinary research, allows users to send relevant instructions via the interface to control the experiment in real time, thereby reducing human error and enabling rapid adjustments based on real-time data to adapt to complex situations in closed-loop experiments. Attached Figure Description

[0043] Figure 1 This is a schematic diagram illustrating closed-loop communication between a three-dimensional brain-on-a-chip real-time closed-loop control system and a multi-channel electrophysiological system, as shown in an embodiment of the present invention.

[0044] Figure 2 This is a schematic diagram illustrating file lifecycle tracking as shown in an embodiment of the present invention;

[0045] Figure 3 This embodiment of the invention illustrates the process by which the system of the present invention acquires IntanRHS system data in real time.

[0046] Figure 4 The process of stimulation control of the system of the present invention is shown in the embodiment of the present invention. Detailed Implementation

[0047] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] It should be noted that the defects in the solutions in the prior art are all the results of the inventors' practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of this application in the following text should be the inventors' contributions to this application in the process of invention and creation, and should not be understood as technical content known to those skilled in the art.

[0049] In view of the technical problems pointed out in the background art, the present invention provides the following embodiments:

[0050] Reference Figure 1 In one exemplary embodiment, a three-dimensional brain-on-a-chip real-time closed-loop control system is provided, comprising:

[0051] The neural data monitoring module is used to track neural data generated by the multi-channel electrophysiological system in real time based on the Watchdog file monitoring mechanism.

[0052] The neural data synchronization module is used to adjust the neural data in conjunction with a timestamp alignment mechanism to achieve synchronization between neural signals and stimulus events;

[0053] The neural data caching module is used to process the neural data by combining a triple ring buffer architecture with an adaptive time window block strategy, and to cyclically store the latest data.

[0054] The instruction control interface module is used to communicate with the multi-channel electrophysiological system based on the TCP / IP protocol, dynamically adjust the stimulation parameters according to the neural data and changes in the external environment, and feed the adjusted stimulation parameters back to the multi-channel electrophysiological system for stimulation experiments.

[0055] The experiment design and execution module provides a programmable interface that allows users to customize experimental paradigms.

[0056] This embodiment is structured around the IntanRHS multichannel electrophysiological system, fully utilizing its stimulation and recording capabilities. An external system connects to a designated port of the Intan RHS system. While maintaining the precision of the native Intan RHS interface, it provides a high-level abstraction interface, making it easier for researchers to design and execute complex experimental paradigms, including conditioned stimulation and state queries, thereby overcoming the limitations of the original system in terms of experimental flexibility.

[0057] The implementation details of each module of this system are given below.

[0058] The neural data monitoring module ensures that 3D neural data acquired from the Intan RHS system is accurately stored and synchronized. This system utilizes a watchdog file monitoring mechanism to track data files generated by the Intan RHS system in real time, such as the stimulus data file stim.dat, the timestamp file time.dat, and the amplifier data file amp.dat (for neural signals). The file monitoring component of the neural data monitoring module captures the creation events of these files instantly. The neural data monitoring module is designed to monitor new directories; when a new data subdirectory is created, the monitoring focus automatically shifts to the latest subdirectory, ensuring the continuity and integrity of data acquisition.

[0059] Furthermore, the neural data monitoring module, based on a dynamic classification engine using filename semantics, implements targeted enhancement design to differentiate the processing of different types of data within the neural data. A classification-driven streaming data governance architecture is proposed, overcoming the bottleneck of indiscriminate processing in traditional solutions. Specifically, this includes:

[0060] 1. Build a classification-based reading strategy manager: Construct an automatic classification system based on naming conventions to achieve intelligent mapping between filename categories and processing strategies.

[0061]

[0062] Optimal processing paradigms are preset for different file types. For timestamp data, sequential positioning and reading combined with type conversion in time mode are used:

[0063] Processing engine: TimestampSyncHandler

[0064] Reading mode: Sequential positioning and reading + type conversion (time mode)

[0065] Data characteristics: 32-bit integer (np.int32)

[0066] Location mechanism: Based on the precise offset of the number of stored samples (self.stored_samples*4).

[0067] For neural signal data, a multi-file parallel reading combined with numerical scaling (AMP) mode is used:

[0068] Processing engine: NeuralSignalHandler

[0069] Reading mode: Multi-file parallel reading + numerical scaling amp mode

[0070] Data characteristics: 16-bit integer (np.int16)

[0071] Location mechanism: Based on the precise offset of the number of stored samples (self.stored_samples*2)

[0072] Data conversion: The original integer value is multiplied by the amplifier scaling factor (self.d_scale) and converted into physical units (such as voltage).

[0073] For stimulus data, a bit manipulation parsing combined with structured data extraction is used:

[0074] Processing engine: StimulationHandler

[0075] Reading mode: Bit operation parsing + structured data extraction (stim mode)

[0076] Data characteristics: 16-bit unsigned integer (np.uint16), containing various state information.

[0077] Location mechanism: Based on the precise offset of the number of stored samples (self.stored_samples*2)

[0078] Data conversion: Using bitwise operations to extract current amplitude, sign, and various status flags.

[0079] - The lower 8 bits are used for the current amplitude (0-255).

[0080] - The 9th bit (256) is used to determine the symbol.

[0081] - Bits 14-16 are used for status flags

[0082] 2. Build a file lifecycle tracker: Define file state transition rules to ensure strict synchronization between the processing logic and the Intan RHS system's recording cycle, such as... Figure 2 As shown.

[0083] Regarding data synchronization, the system employs an efficient timestamp alignment mechanism to ensure strict synchronization between amplifier data and corresponding stimulus data. The system adjusts the time alignment of data blocks based on the contents of the timestamp file time.dat, which is crucial for subsequent data analysis and real-time feedback. The neural data synchronization module utilizes memory mapping optimization and a global sample bus index to ensure synchronization between different types of data within the neural dataset. Specifically, this includes the following:

[0084] 1. Memory mapping optimization and index structure design

[0085] Employing operating system-level memory mapping technology, the physical storage space of the timestamp file (time.dat) is directly mapped to the virtual address space, bypassing the multiple copying processes of traditional file I / O and achieving zero-copy access with microsecond-level latency. The clock source directly uses the high-precision timestamps recorded in the time.dat file (generated by the Intan RH S system's built-in microsecond-level timer). A global sample bus index is constructed across data sources, integrating and synchronizing multiple data sources, including:

[0086] ● Sample Number → Timestamp Mapping Table: Each time timestamp data is read, the newly read sample number and its corresponding timestamp are added to the hash table. An open addressing and linear probing strategy is employed, calculating a primary and secondary hash value for each sample number. When a collision occurs, linear probing is used to find the next available location. A locality-sensitive hash function is used to map similar sample numbers to similar hash buckets, reducing cache misses. Fast retrieval of the corresponding timestamp using the sample number in the neural signal file (amp.dat) is supported.

[0087] ●Timestamp → Sample Number Ordered Dictionary: Constructs and maintains an index structure based on time order. The B+ tree part is used for range queries, and the skip list part provides fast single-point access. For hot time intervals (such as recently accessed experimental segments), a memory caching layer is implemented to reduce tree traversal overhead. Supports fast range queries and concurrent reads based on time ranges.

[0088] ● Stimulus Instruction Number → Timestamp Mapping Table: When parsing the stimulus parameters and status bit information in the stim-*.dat file, a mapping is established between the identifier of each stimulus event and its corresponding timestamp. This is also implemented using a hash table with open addressing and linear probing, applying locality-sensitive hashing to reduce collisions, and supporting fast retrieval of the corresponding timestamp via the sample number in the stimulus parameter file (stim.dat).

[0089] 2. Core Process of Multi-Source Alignment

[0090] Input: Amp sample number N_amp; stimulus instruction number N_stim.

[0091] Alignment algorithm:

[0092] 1) Obtain the timestamp T_amp corresponding to N_amp using the time.dat index.

[0093] 2) Obtain the timestamp T_stim corresponding to N_stim

[0094] 3) Calculate the absolute time difference ΔT = |T_amp - T_stim|

[0095] 4) if ΔT ≤ Δ_threshold (default 50μs):

[0096] Generate an aligned data packet.

[0097] else:

[0098] Trigger the exception handling protocol.

[0099] 3. Anomaly Detection and Handling System

[0100] 3.1. The exception type matrix is ​​shown in Table 1.

[0101] Table 1. Exception Types and Handling Strategies

[0102]

[0103] 3.2. Sample backtracking compensation mechanism

[0104] Forward missing data compensation: When a missing time.dat sample is detected, it is calculated based on the timestamp of the previous valid sample plus the theoretical interval.

[0105] Backward redundancy check: For each processed sample, retain N-1, N, and N+1 timestamp copies of the sample, and ensure consistency through three checks.

[0106] 3.3. Global Time Base Reload Calibration

[0107] 1) Confirmation of testing sites

[0108] - When a timestamp reversal issue is discovered, record the location where the issue occurred;

[0109] - Determine the last correct timestamp position and value.

[0110] 2) Reset the baseline

[0111] - Use the last correct timestamp as the new reference point;

[0112] - Reposition the read pointer of the time.dat file to this location.

[0113] 3) Reread and Correct

[0114] - Re-read timestamps sequentially starting from the calibration point;

[0115] - Force a monotonically increasing check on all subsequent timestamps read.

[0116] 4) Update the index

[0117] - Simply clear and rebuild the timestamp index of the affected portion;

[0118] - Update the timestamp mappings corresponding to the sample number and stimulus instruction number.

[0119] The specific implementation mechanism of the neural data caching module is as follows:

[0120] 1. Adaptive time window segmentation mechanism:

[0121] The data block duration is dynamically adjusted based on the experimental scenario to achieve the best balance between processing efficiency and real-time performance.

[0122] Baseline segmentation rule: The default base time window is 100ms (which can be adjusted according to actual conditions). The sample number threshold is dynamically calculated based on the sampling rate: Sample number threshold = Sampling rate (Hz) × 0.1s × Safety factor.

[0123] Flexible adjustment strategy:

[0124] Extended condition: When the system load rate is <40%, automatically extend the window to 200ms to improve throughput;

[0125] Shrinkage condition: When CPU utilization is >75%, shorten the window to 50ms to reduce latency.

[0126] 2. Cross-source data block assembly

[0127] Establish a three-source data flow collaborative triggering mechanism to ensure data integrity:

[0128] Synchronization trigger condition: Number of available samples ≥ 1000 (timestamp / neural signal / stimulation data three channels).

[0129] 3. Data organization standards within blocks

[0130] A matrix-based storage structure is used to improve access efficiency, and each data block carries a CRC16 checksum for data integrity verification.

[0131]

[0132] 4. Innovative design of ring-shaped buffer architecture

[0133] 4.1. Multi-ring collaborative storage structure: Constructing a triple logical ring region to achieve physical isolation and logical unity:

[0134] ●Data storage ring:

[0135] A contiguous storage area stores complete data blocks.

[0136] ●Metadata index ring:

[0137] Record metadata such as block start time, sample range, and status flags.

[0138] ●Exception handling loop:

[0139] Save diagnostic information such as data verification anomalies and compensation records.

[0140] 4.2. Pointer control strategy, as shown in Table 2.

[0141] Table 2. Pointer Control Strategy

[0142]

[0143] 4.2.1. Implementation of write pointer technique

[0144] Batch forwarding mechanism:

[0145] ●The write pointer moves in units of fixed-size data blocks at a time.

[0146] ● Update the write pointer position through atomic operations to ensure consistency in a multi-threaded environment. ● Dynamically adjust the batch size based on the write rate (W_speed) in the dual-rate prediction model, increasing the batch size during high-speed writes.

[0147] ● Maintain a write block counter and update write rate statistics every 10 blocks.

[0148] Out-of-bounds rollback handling:

[0149] ● Maintain counters for the total capacity and currently used capacity of the circular buffer.

[0150] ● A rollback is triggered when the write pointer position plus the next data block size exceeds the end of the loop.

[0151] ●The rollback operation resets the write pointer to the beginning of the loop using atomic instructions.

[0152] ● The rollback event is recorded in the event log for easy analysis of buffer usage later.

[0153] 4.2.2. Implementation of Read Pointer Technique

[0154] Smooth catch-up strategy:

[0155] ● Adjust the read step size according to the imbalance coefficient to maintain a balance between read and write speeds.

[0156] ● Fixed step size (1 block / cycle) in normal mode, dynamic step size in catch-up mode. ● S-curve function is used to smooth step size changes and prevent processing fluctuations caused by sudden changes in read speed.

[0157] Handling of delayed and excessive limits:

[0158] ● Monitor the gap between read and write pointers; trigger accelerated catching-up when it exceeds the threshold (30%).

[0159] ●In acceleration mode, the read batch size is temporarily increased until the safe distance is restored.

[0160] ● Issue a warning if write speed is continuously exceeded, and reduce write speed if necessary.

[0161] 4.2.3. Checking the pointer technique to implement a periodic retrace mechanism:

[0162] ● Check pointers run independently at fixed intervals (500ms) to verify data integrity. ● Utilize the uint16_t crc field in each TimeBlock for block-level verification, prioritizing newly written data blocks to reduce overall verification overhead. Anomaly marking and isolation:

[0163] ● When a data block with a failed CRC check is detected, add a flag and record it in the exception log. ● Isolate the exception block to prevent subsequent processing from using this data.

[0164] ● Triggering an exception notification mechanism allows upper-layer applications to determine handling strategies.

[0165] 5. Adaptive Buffer Control Algorithm

[0166] 5.1. Dual-rate prediction model

[0167] ● Write speed (W_speed): The average write interval of the most recent 10 data blocks. ● Read speed (R_speed): The actual processing speed calculated based on feedback from the read module. ● Imbalance calculation:

[0168] Imbalance coefficient = (W_speed - R_speed) / max(W_speed, R_speed)

[0169] 5.2. Pointer Control Strategy

[0170] ●Normal mode (|imbalance coefficient| < 0.1):

[0171] The read pointer advances in fixed steps (1 block / cycle).

[0172] ●Catch-up mode (imbalance coefficient ≥ 0.1):

[0173] Dynamically adjust the catching-up step size: Step size = base step size × (1 + log2 (imbalance coefficient))

[0174] 5.3. Smooth transition of state: Use an S-curve to adjust the step size change rate to avoid violent pointer jitter.

[0175] This system integrates a time-driven dynamic block partitioning strategy, a triple-ring buffer architecture, and an adaptive index tracking algorithm to ensure the continuity and accuracy of the data stream under high load conditions. A file monitoring module based on regularized naming rules enables the classification and processing of different data types (neural signals, timestamps, stimulation parameters), effectively solving the problem of multi-source data synchronization and alignment through memory mapping acceleration and a global sample bus index structure. The system significantly reduces memory operation overhead by 90% through an adaptive time window block partitioning mechanism (dynamically adjusted from 50-200ms) and a ring buffer data management strategy, and automatically adjusts the read / write rate balance through a dynamic feedback mechanism of imbalance coefficient. A comprehensive anomaly detection and self-healing system can identify and correct anomalies such as sample discontinuity and timestamp reversal, ensuring high reliability of data processing during experimental tasks and providing stable and efficient technical support for on-chip brain-computer interface research.

[0176] Furthermore, the command control interface module provides users with the ability to communicate with the Intan RHS system, enabling key operations such as remote parameter setting, experimental process control, and data acquisition. This includes connecting and disconnecting from the server (Intan RHS system), configuring stimulus and recording parameters, setting experimental files and parameters, and querying and verifying data. This module interacts directly with the Intan RHS system via the TCP / IP protocol, ensuring real-time transmission and execution of commands. Specifically, external systems connect to designated ports on the Intan RHS system. It provides a high-level abstraction interface while maintaining the control precision of the native Intan RHS interface.

[0177] The experiment design and execution module allows users to send relevant instructions through the aforementioned instruction control interface module to control the experiment in real time. This makes it easier to design and execute complex experimental paradigms, including conditional stimuli and state queries, thereby reducing human error and enabling rapid adjustments based on real-time data to adapt to complex situations in closed-loop experiments.

[0178] The process of stimulus control in this system is as follows: Figure 4 As shown, before performing the experiment, ensure that the IntanRHS system is running and the stimulus / recording controller is being used (Intan RHS offers four modes; this is not an issue during actual connection, as the default is the stimulus / recording controller). Connect to 127.0.0.1, port 5000 via Network -> Remote TCP Control in the IntanRHS system, and ensure the connection status shows "Pending". Then you can initiate the connection and perform the experiment.

[0179] The process by which this system acquires data from the IntanRHS system in real time is as follows: Figure 3 As shown, data interaction is based on disk read / write, reading incremental data at near real-time rates (latency <50ms) and ensuring the synchronization of timestamps with amplifier samples and stimulus data to avoid accumulated latency. A circular buffer is used instead of a traditional queue to optimize data storage and access strategies, reduce additional latency caused by data migration, and achieve high reliability in data reading and processing.

[0180] It should be noted that the parameters or values ​​involved in this invention are not intended to limit this application and can be adapted to the actual situation.

[0181] In another exemplary embodiment, based on the same inventive concept as the system, a three-dimensional brain-on-a-chip real-time closed-loop control method is provided, comprising:

[0182] Based on the Watchdog file monitoring mechanism, neural data generated by the multi-channel electrophysiological system is tracked in real time.

[0183] By combining the timestamp alignment mechanism with the neural data, the synchronization of neural signals and stimulus events can be achieved;

[0184] The neural data is processed by combining a triple ring buffer architecture with an adaptive time window block strategy, and the latest data is stored cyclically.

[0185] The stimulation parameters are dynamically adjusted based on the neural data and changes in the external environment, and the adjusted stimulation parameters are fed back to the multi-channel electrophysiological system for stimulation experiments.

[0186] The principles underlying each step of the method are the same as those of the corresponding modules in the system, and will not be elaborated upon here.

[0187] In another exemplary embodiment, based on the same inventive concept as the method, a computer-readable storage medium is provided. This computer-readable storage medium stores a computer program, which, when executed by a processor, implements the three-dimensional brain-on-a-chip real-time closed-loop control method provided in this embodiment of the invention. Based on this understanding, the technical solution of this embodiment, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0188] In another exemplary embodiment, based on the same inventive concept as the method, an electronic device is provided, including a memory and a processor. The memory stores computer instructions that can be executed on the processor. When the processor executes the computer instructions, it performs the three-dimensional brain-on-a-chip real-time closed-loop control method provided in the embodiments of the present invention.

[0189] The processor may be a single-core or multi-core central processing unit or a specific integrated circuit, or one or more integrated circuits configured to implement the present invention.

[0190] The embodiments of the subject matter and functional operation described in this specification can be implemented in: tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and their structural equivalents, or combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by a data processing device or for controlling the operation of a data processing device. Alternatively or additionally, the program instructions may be encoded on artificially generated propagation signals, such as machine-generated electrical, optical, or electromagnetic signals, which are generated to encode information and transmit it to a suitable receiving device for execution by the data processing device.

[0191] The processing and logic flow described in this specification can be executed by one or more programmable computers that execute one or more computer programs to perform corresponding functions by operating on input data and generating output. The processing and logic flow can also be executed by dedicated logic circuitry—such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), and the device can also be implemented as dedicated logic circuitry.

[0192] Suitable processors for executing computer programs include, for example, general-purpose and / or special-purpose microprocessors, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from read-only memory and / or random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as disks, magneto-optical disks, or optical disks, or the computer will be operatively coupled to such mass storage devices to receive data from or transfer data to them, or both. However, a computer is not required to have such devices. Furthermore, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0193] It should be understood that each block in a flowchart or block diagram can represent a module, segment, or portion of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the figures. For example, two consecutive blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0194] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A three-dimensional brain-on-a-chip real-time closed-loop control system, characterized in that, include: The neural data monitoring module is used to track neural data generated by the multi-channel electrophysiological system in real time based on the Watchdog file monitoring mechanism. The neural data synchronization module is used to adjust the neural data in conjunction with a timestamp alignment mechanism to achieve synchronization between neural signals and stimulus events; The neural data caching module is used to process the neural data by combining a triple ring buffer architecture with an adaptive time window block strategy, and to cyclically store the latest data. The triple ring buffer architecture includes a data storage ring, a metadata index ring, and an anomaly handling ring. The data storage ring adopts a batch forward strategy and automatically rolls back to the beginning of the ring when it goes out of bounds. The metadata index ring adopts a smooth catch-up strategy and triggers an acceleration catch-up protocol when the lag exceeds the limit. The anomaly handling ring uses periodic backscanning to verify data integrity and to mark and isolate anomalies. The instruction control interface module is used to communicate with the multi-channel electrophysiological system based on the TCP / IP protocol, dynamically adjust the stimulation parameters according to the neural data and changes in the external environment, and feed the adjusted stimulation parameters back to the multi-channel electrophysiological system for stimulation experiments. The experiment design and execution module provides a programmable interface that allows users to customize experimental paradigms.

2. The three-dimensional brain-on-a-chip real-time closed-loop control system according to claim 1, characterized in that, The Watchdog file monitoring mechanism, which tracks neural data generated by a multi-channel electrophysiological system in real time, includes: A dynamic classification engine based on filename semantics performs differentiated processing on different types of data in neural data.

3. The three-dimensional brain-on-a-chip real-time closed-loop control system according to claim 2, characterized in that, The differential processing of different types of data in neural data includes: For timestamp data, sequential positioning and reading combined with type conversion (time mode) are used; for neural signal data, multi-file parallel reading combined with numerical scaling (amp mode) is used; and for stimulus data, bit manipulation parsing combined with structured data extraction (stim mode) is used.

4. The three-dimensional brain-on-a-chip real-time closed-loop control system according to claim 1, characterized in that, The adjustment of the neural data using the timestamp alignment mechanism includes: Memory mapping optimization and global sample bus indexing are employed to ensure synchronization between different types of data in neural data; in particular, open addressing and linear probing strategies are used to establish mapping tables for neural signal data, stimulus data and timestamps respectively.

5. The three-dimensional brain-on-a-chip real-time closed-loop control system according to claim 4, characterized in that, The adjustment of the neural data using the timestamp alignment mechanism also includes: When an alignment error occurs, an exception handling protocol is triggered, which includes: When a missing sample is detected in the timestamp file, the sample backtracking compensation mechanism is activated. When a reversed timestamp file is detected, a global time base recalibration is triggered, and the mapping table is updated. When there is a timing discrepancy between the stimulus and the response, record the event log and pause stimulus output.

6. The three-dimensional brain-on-a-chip real-time closed-loop control system according to claim 1, characterized in that, The adaptive time window segmentation strategy includes: Set a baseline time window and dynamically calculate the sample number threshold based on the sampling rate; Adjust the size of the baseline time window based on system load and CPU utilization.

7. A real-time closed-loop control method for a three-dimensional brain-on-a-chip, characterized in that, include: Based on the Watchdog file monitoring mechanism, neural data generated by the multi-channel electrophysiological system is tracked in real time. By combining the timestamp alignment mechanism with the neural data, the synchronization of neural signals and stimulus events can be achieved; The neural data is processed by combining a triple-ring buffer architecture with an adaptive time window block strategy, and the latest data is stored cyclically. The triple-ring buffer architecture includes a data storage ring, a metadata index ring, and an anomaly handling ring. The data storage ring adopts a batch forward strategy and automatically rolls back to the beginning of the ring when it goes out of bounds. The metadata index ring adopts a smooth catch-up strategy and triggers an acceleration catch-up protocol when the lag exceeds the limit. The anomaly handling ring uses periodic backscanning to verify data integrity and performs anomaly marking and isolation. The stimulation parameters are dynamically adjusted based on the neural data and changes in the external environment, and the adjusted stimulation parameters are fed back to the multi-channel electrophysiological system for stimulation experiments.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the real-time closed-loop control method as described in claim 7.

9. An electronic device comprising a memory and a processor, wherein the memory stores computer instructions executable by the processor, characterized in that, The processor executes the real-time closed-loop control method as described in claim 7 when running computer instructions.

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