FPGA chip with ultra-high rate and data ultra-high rate acquisition processing method

Abstract

The application discloses a kind of super high speed FPGA chip and data super high speed acquisition processing method.The FPGA chip includes main control module, data processing module, first data transmission module and memory control module;Main control module includes 4 serial interfaces and data rearrangement unit, each serial interface is used to simultaneously receive the super high speed data output by ADC chip, obtains 4 512-bit data blocks, data rearrangement unit is used to decompose the 4 512-bit data blocks received by each serial interface into 256 8-bit data units;Data processing module is used for data processing to each data unit, first data transmission module is used to convert 256 8-bit data units into 320 8-bit data units, and 320 8-bit data units are transmitted to memory control module;Memory control module includes 4 DDR units, for writing, reading and storing 320 8-bit data units.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of signal acquisition, in particular to an FPGA chip with an ultra-high rate and a data ultra-high rate acquisition and processing method. BACKGROUND

[0002] With the rapid development of chip, material and other process technologies, the real-time analysis bandwidth and data sampling rate of modern broadband data acquisition equipment are continuously improved. The data acquisition system with high bandwidth and high sampling rate is widely used in the fields of ultra-wideband communication radio frequency signal measurement, high-speed serial bus protocol analysis (such as USB4.0, HDMI, DDR4) and optical communication module testing, and can capture and analyze key parameters such as high-speed clock signal jitter and bus signal jitter, and test the transmission quality of optical signals.

[0003] With the increase of the sampling rate, the data rate of ADC acquisition is significantly increased, and the high-speed communication interface between the ADC and the FPGA needs to support higher transmission rate, and at the same time, higher requirements are put forward for the real-time digital signal processing capability of the FPGA. When processing ultra-high rate data, the traditional method often faces problems such as data transmission bottleneck, insufficient real-time processing capability and complex cache management. SUMMARY

[0004] The main purpose of the application is to provide an FPGA chip with an ultra-high rate and a data ultra-high rate acquisition and processing method to realize the acquisition, processing and storage of 640Gbps ultra-high rate data.

[0005] To achieve the above purpose, the application provides an FPGA chip with an ultra-high rate, which comprises a main control module, a data processing module, a first data transmission module and a memory control module connected in sequence.

[0006] The main control module comprises four serial interfaces and a data rearrangement unit, each serial interface is used for receiving ultra-high rate data output by an ADC chip at the same time to obtain four 512-bit data blocks, and the data rearrangement unit is used for decomposing the four 512-bit data blocks received by each serial interface into 256 8-bit first data units.

[0007] The data processing module is used for data processing of each first data unit, the first data transmission module is used for converting 256 8-bit first data units into 320 8-bit second data units, and transmitting the 320 8-bit second data units to the memory control module.

[0008] The memory control module comprises four DDR chips, which are used for writing, reading out and storing 320 8-bit second data units.

[0009] Optionally, each of the serial interfaces is used to receive ultra-high-speed data and synchronization signals output by the ADC chip to obtain four 512-bit data blocks; wherein, the synchronization signal is used to synchronize and align the data blocks.

[0010] Optionally, the memory control module further includes a data writing unit and a data reading unit connected to each of the DDR chips; the data writing unit is used to receive 320 8-bit second data units, divide the 320 8-bit second data units into 4 data groups, and write each data group into each of the DDR chips; each of the DDR chips is used to store the data groups; the data reading unit is used to receive the data groups read from each of the DDR chips.

[0011] Optionally, the FPGA chip further includes a second data transmission module and a PCIe module. The second data transmission module is connected to the memory control module and the PCIe module, and the PCIe module is connected to a host computer. The second data transmission module is used to receive each data group output by the data readout unit, convert each data group into DAM format, and output it to the PCIe module. The PCIe module is used to upload each data group in DAM format to the host computer.

[0012] Optionally, the FPGA chip further includes a configuration module connected to the PCIe module; the PCIe module is also used to receive control commands and / or configuration parameters sent by the host computer, and send the control commands and / or configuration parameters to the configuration module; the configuration module is used to send the control commands and / or configuration parameters to the remaining corresponding modules.

[0013] Optionally, the FPGA chip further includes a first phase-locked loop module, which is connected to the PCIe module; the PCIe module is also used to output a first signal to the first phase-locked loop module; the first phase-locked loop module is used to receive the first signal and, when the first signal is high, to perform clock configuration initialization on the clock phase-locked loop chip.

[0014] Optionally, the FPGA chip further includes a second phase-locked loop module, which is connected to the first phase-locked loop module. The first phase-locked loop module is further configured to send a second signal to the second phase-locked loop module after clock configuration initialization of the first clock phase-locked loop chip. The second phase-locked loop module is configured to receive the second signal and perform clock configuration initialization of the clock multiplier chip when the second signal is high.

[0015] Optionally, the FPGA chip further comprises an ADC control module, the ADC control module being connected with the second phase-locked loop module and the master control module; the second phase-locked loop module is further configured to send a third signal to the ADC control module after clock configuration initialization of the clock multiplier chip; the ADC control module is configured to receive the third signal, and perform configuration initialization on the ADC chip and send a fourth signal to the master control module if the third signal is high; and the master control module is configured to receive the fourth signal and start working if the fourth signal is high.

[0016] In addition, to achieve the above object, the application further provides a data super-high-rate acquisition and processing method based on an FPGA chip, applied to the super-high-rate FPGA chip as described above, the method comprising: simultaneously receiving super-high-rate data output by an ADC chip to obtain four 512-bit data blocks, and decomposing the four 512-bit data blocks into 256 8-bit first data units; performing data processing on each of the first data units, and converting the 256 8-bit first data units into 320 8-bit second data units; and writing, reading out and storing the 320 8-bit second data units.

[0017] Optionally, the simultaneously receiving super-high-rate data output by the ADC chip to obtain four 512-bit data blocks comprises: receiving super-high-rate data and a synchronization signal output by the ADC chip to obtain four 512-bit data blocks; wherein the synchronization signal is used to synchronize and align each data block.

[0018] The super-high-rate FPGA chip of the application can make the four serial interfaces simultaneously acquire 640Gbps super-high-rate data to obtain four 512-bit data blocks by setting four serial interfaces in the master control module; and can decompose the four 512-bit data blocks received by each serial interface into 256 8-bit first data units by the data rearrangement unit, so as to facilitate subsequent data processing on each first data unit; can convert the 256 8-bit first data units into 320 8-bit second data units by the first data transmission module, and can make four DDR chips respectively store 80 8-bit second data units by setting four DDR chips in the memory control module, thereby realizing acquisition, processing and storage of 640Gbps super-high-rate data. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a structural schematic diagram of the super-high-rate FPGA chip of the embodiment of the application;

[0020] Figure 2 is a flowchart of the data super-high-rate acquisition and processing method of the embodiment of the application;

[0021] In the figure, 110, master module; 120, data processing module; 130, first data transmission module; 140, memory control module; 150, second data transmission module; 160, PCIe module; 170, configuration module; 180, first phase-locked loop module; 190, second phase-locked loop module; 200, ADC control module.

[0022] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0023] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely below with reference to the accompanying drawings in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0024] With the continuous progress of semiconductor process technology, chip design and material science, the performance of modern wideband data acquisition equipment has been significantly improved, especially in terms of real-time analysis bandwidth and data sampling rate. The progress of these technologies enables data acquisition systems to support higher bandwidth and sampling rate, thus meeting the increasingly complex signal measurement requirements. Ultra-wideband communication radio frequency signal measurement, high-speed serial bus protocol analysis and development and testing of optical communication modules, etc. all put forward higher requirements on the performance of data acquisition systems.

[0025] In the field of communication, wideband data acquisition equipment can capture and analyze the parameters of random and occasional signals, such as the jitter of high-speed clock signals and the jitter of high-speed bus signals. Accurate measurement of these parameters is crucial for the stability and performance optimization of communication systems. In addition, in terms of protocol analysis, signal analysis of high-speed serial buses (such as USB4.0, HDMI, DDR4, etc.) requires data acquisition systems to have extremely high sampling rate and real-time processing capability to ensure the integrity and accuracy of signals. In the development and testing of optical communication modules and optical transmission equipment, data acquisition systems also need to be able to test the transmission quality of optical signals to ensure the efficiency and reliability of optical communication systems.

[0026] With the continuous improvement of the sampling rate, the data rate collected by the analog-to-digital converter (ADC) also increases significantly. This leads to the need for a high-speed communication interface between the ADC and the field programmable gate array (FPGA) to support higher data transmission rates. At the same time, the digital signal processing capability within the FPGA chip also faces higher real-time requirements. Traditional data acquisition and processing methods often fail to meet the real-time and bandwidth requirements when processing ultra-high-rate data, especially in scenarios where the data rate reaches 640Gbps and above.

[0027] Existing FPGA chips often face the following challenges when processing ultra-high-rate data:

[0028] 1. Data transmission bottleneck: The interface bandwidth between the ADC chip and the FPGA chip is limited, making it difficult to support real-time transmission of ultra-high-rate data.

[0029] 2. Insufficient real-time processing capability: The digital signal processing module within the FPGA chip may experience performance bottlenecks when processing ultra-high-rate data, leading to data processing delays or loss.

[0030] 3. Complex cache management: Efficient design is required for cache management of ultra-high-rate data to ensure data continuity and integrity.

[0031] Based on this, the embodiments of the present application provide an ultra-high-rate FPGA chip and an ultra-high-rate data sampling processing method. By optimizing the functional modules of the FPGA chip, 640Gbps ultra-high-rate data output by the ADC chip can be received, cached, and processed, thereby meeting the needs of modern broadband data acquisition equipment for high bandwidth, high sampling rate, and real-time processing capability.

[0032] Figure 1 is a structural schematic diagram of the ultra-high-rate FPGA chip according to an embodiment of the present application. As shown in Figure 1 , the ultra-high-rate FPGA chip can include a main control module 110, a data processing module 120, a first data transmission module 130, and a memory control module 140 connected in sequence.

[0033] The host module 110 includes 4 serial interfaces and a data rearrangement unit, each serial interface is used to receive the super high rate data output by the ADC chip, and 4 512-bit data blocks are obtained, and the data rearrangement unit is used to decompose the 4 512-bit data blocks received by each serial interface into 256 8-bit first data units; the data processing module 120 is used to process the data of each first data unit, the first data transmission module 130 is used to convert the 256 8-bit first data units into 320 8-bit second data units, and transmit the 320 8-bit second data units to the memory control module 140; the memory control module 140 includes 4 DDR chips, and is used to write, read out and store the 320 8-bit second data units.

[0034] In the embodiment, the host module 110 is mainly used to realize the functions of receiving and preprocessing the super high rate data between the FPGA chip and the ADC chip. The host module 110 can include 4 serial interfaces and a data rearrangement unit.

[0035] Since the data rate output by the ADC chip is as high as 640 Gbps, in order to enable the FPGA chip to receive the super high rate data and ensure the transmission of the super high rate data, the serial interface can adopt the JESD204C high-speed serial interface standard. Because the JESD204C high-speed serial interface standard has a higher transmission rate, the JESD204C supports a transmission rate of up to 32 Gbps per channel; in addition, the link efficiency of the JESD204C is higher, and it introduces a 64b / 66b encoding scheme, which reduces the overhead and improves the effective data throughput compared with the 8b / 10b encoding of the JESD204B, so the JESD204C is more suitable for receiving data with a data rate of up to 640 Gbps.

[0036] It should be noted that the implementation codes of the 4 serial interfaces are the same, so the functions that the 4 serial interfaces can realize are also the same.

[0037] In addition, the 4 serial interfaces are respectively connected with serdes[7:0], serdes[15:8], serdes[23:16] and serdes[31:24] which are 4 serializers (serdes), and the 4 serializers can convert the parallel data output by the ADC chip into serial data, so as to be transmitted through the high-speed serial link.

[0038] In the embodiment, when the host module 110 starts working, the four serial interfaces simultaneously receive the super-high-speed data output by the ADC chip, and each serial interface outputs a 512-bit data block. Further, the four 512-bit data blocks are input to the data rearrangement unit, which converts the four 512-bit data blocks into 256 8-bit first data units and transmits the 256 8-bit first data units to the data processing module 120.

[0039] The specific implementation of the data rearrangement unit converting the four 512-bit data blocks into 256 8-bit first data units can be as follows: the four 512-bit data blocks are spliced into a 2048-bit continuous data block; the 2048-bit data block is segmented into 256 8-bit first data units; and finally, the 256 8-bit first data units are output in sequence.

[0040] In the embodiment, after receiving the 256 8-bit first data units output by the data rearrangement unit, the data processing module 120 can perform data processing on each first data unit. The data processing can include filtering, Fourier transform, modulation and demodulation, data compression, encryption and decryption, data packet processing, and the like. It should be noted that the implementation code configured in the data processing module 120 of the embodiment can be replaced according to different application scenarios to implement different data processing functions, as long as the input and output of the data processing module 120 are both 256 8-bit first data units. The specific implementation function and implementation code of the data processing module 120 are not limited here. As an example, for the application of receiving high-speed radar signals, the implementation code configured in the data processing module 120 can be a radar-related signal processing algorithm; for the application of high-speed oscilloscope, the implementation code configured in the data processing module 120 can be an oscilloscope-related signal processing algorithm.

[0041] Further, after the data processing module 120 performs data processing on the 256 8-bit first data units, it transmits the processed 256 8-bit first data units to the first data transmission module 130. The first data transmission module 130 can convert the 256 8-bit first data units into 320 8-bit second data units, and finally the first data transmission module 130 transmits the 320 8-bit second data units to the memory control module 140, so that the memory control module 140 performs real-time caching on the data.

[0042] It should be noted that the first data transmission module 130 in the embodiment converts the 256 8-bit first data units into 320 8-bit second data units, which is not a change in the data itself, but a conversion of the processing method due to the different data processing methods of the serial interface (JESD204C) and the DDR unit under its working clock domain. Specifically, under the working clock domain of JESD204C, 256 8-bit first data units are processed at the same time in one JESD204C clock cycle. However, under the working clock domain of the DDR unit, 320 8-bit second data units can be processed at the same time in one DDR clock cycle. Therefore, converting the 256 8-bit first data units into 320 8-bit second data units is only a conversion of the data processing method.

[0043] In the embodiment, when the memory control module 140 receives the 320 8-bit second data units, the 4 DDR chips configured by the memory control module 140 can be used to realize real-time caching of the 320 8-bit second data units.

[0044] Therefore, by setting 4 serial interfaces in the host module 110, the 4 serial interfaces can simultaneously collect 640 Gbps ultra-high rate data to obtain 4 512-bit data blocks. Then, the data rearrangement unit decomposes the 4 512-bit data blocks received by each serial interface into 256 8-bit first data units, so as to facilitate subsequent data processing of each first data unit. By using the first data transmission module 130 to convert the 256 8-bit first data units into 320 8-bit second data units and setting 4 DDR chips in the memory control module 140, the 4 DDR chips can respectively store 80 8-bit second data units. Therefore, the collection, processing and storage of 640 Gbps ultra-high rate data are realized.

[0045] In some embodiments, each serial interface is used to receive ultra-high rate data and a synchronization signal output by an ADC chip to obtain 4 512-bit data blocks. The synchronization signal is used to synchronize and align each data block.

[0046] Specifically, each serial interface receives the same sysref signal while receiving the ultra-high speed data output by the ADC chip to realize data synchronization between the serial interfaces and ensure that the ultra-high speed data received by the FPGA chip is synchronized and aligned. It should be noted that Figure 1 The refclk_1, refclk_2, refclk_3 and refclk_4 in the above formula are four homologous reference clocks.

[0047] In some embodiments, the memory control module 140 can further include a data writing unit and a data reading unit connected with each DDR unit. The data writing unit is configured to receive the 320 8-bit second data units, divide the 320 8-bit second data units into 4 data groups, and write each data group into each DDR unit respectively; each DDR unit is configured to store the data group; and the data reading unit is configured to receive the data group read from each DDR unit.

[0048] Specifically, the memory control module 140 is mainly used for writing, reading and caching the 320 8-bit second data units processed by the front-end. The data writing unit is connected with the first data transmission module 130, and can receive the 320 8-bit second data units sent by the first data transmission module 130 and cache the 320 8-bit second data units. Further, the data writing unit can divide the 320 8-bit second data units into 4 data groups, each of which contains 80 8-bit data; and the data writing unit can further transmit the 4 data groups to the 4 DDR units respectively, and the 4 DDR units can output the respective data groups to the corresponding DDR chips for storage. It can be understood that the data bit width of the DDR ipcore in the FPGA chip is limited, and a group of DDR chip set can only accept 80 bits. In order to realize the caching of 640 Gbps ultra-high speed data, 4 groups of DDR chip sets are needed to cache data.

[0049] It should be noted that the grouping process of the data writing unit on the 320 8-bit second data units can refer to the data conversion process in the foregoing embodiments, which will not be described here. In addition, the implementation codes of each DDR unit are the same, and thus the functions that can be realized are consistent.

[0050] Further, when it is necessary to read the ultra-high speed data from each DDR chip, the data reading unit can receive the 4 data groups read from each DDR chip; and after receiving the 4 data groups, the data reading unit can convert the 4 data groups into 8 8-bit second data units and transmit the 8 8-bit second data units to the next stage.

[0051] In some embodiments, the FPGA chip further includes a second data transmission module 150 and a PCIe module 160, the second data transmission module 150 is connected with the memory control module 140 and the PCIe module 160, and the PCIe module 160 is connected with the host computer. The second data transmission module 150 is configured to receive each data group output by the data reading unit, convert each data group into DAM format, and output each data group in DAM format to the PCIe module 160; and the PCIe module 160 is configured to upload each data group in DAM format to the host computer.

[0052] Specifically, the second data transmission module 150 can receive the 8 eight-bit second data units output by the data readout unit. After the second data transmission module 150 receives the 8 eight-bit second data units output by the data readout unit, the second data transmission module 150 can convert the 8 eight-bit second data units into a DMA (Direct Memory Access) data format. Converting each second data unit into a DMA format can facilitate efficient data transmission, simplify hardware interfaces, unify data formats, and meet protocol requirements.

[0053] After the second data transmission module 150 converts the 8 eight-bit second data units into a DMA data format, the second data transmission module 150 can send the converted data to the PCIe module 160. The PCIe module 160 can communicate with and establish a link with the host computer through an X8 PCIE interface, and can receive data from or send data to the host computer. After the PCIe module 160 receives the data output by the second data transmission module 150, the PCIe module 160 can upload the data to the host computer for subsequent processing by the host computer.

[0054] It should be noted that in the present embodiment, the host computer can be a personal computer (PC), an industrial control computer (industrial computer), an embedded system, a microcontroller unit (MCU), a special hardware, a cloud service, etc., and the host computer is not specifically limited herein.

[0055] In some embodiments, the FPGA chip further includes a configuration module 170 connected to the PCIe module 160. The PCIe module 160 is further configured to receive control instructions and / or configuration parameters sent by the host computer, and send the control instructions and / or configuration parameters to the configuration module 170. The configuration module 170 is configured to send the control instructions and / or configuration parameters to the remaining corresponding modules.

[0056] In the present embodiment, the configuration module 170 is connected to the PCIe module 160. When the PCIe module 160 receives all the control instructions and configuration parameters issued by the host computer, the PCIe module 160 can send the control instructions and configuration parameters to the configuration module 170. The configuration module 170 stores the register addresses of the functional modules in the FPGA chip, and can distribute the control instructions and configuration parameters to different functional modules through different register addresses.

[0057] Specifically, the host computer generates control instructions and configuration parameters through a software tool or a custom application. These instructions and parameters can be configuration settings for specific functional modules, start / stop commands, or other operation requests. The host computer sends these instructions and parameters to the PCIe module 160 in the FPGA through the PCIE interface. The PCIe module 160 receives all control instructions and configuration parameters issued from the host computer, and since PCIe supports high-bandwidth data transmission, this step can be completed efficiently. Further, the PCIe module 160 needs to parse the received data packets and extract specific control instructions and configuration parameters.

[0058] Once the PCIe module 160 successfully parses the data packet, it forwards the extracted control instructions and configuration parameters to the configuration module 170. The configuration module 170 can store a mapping table inside, which records the register addresses corresponding to each functional module. When the configuration module 170 receives control instructions and configuration parameters, the configuration module 170 looks up the corresponding register address according to the instruction content. Further, the configuration module 170 distributes the control instructions and configuration parameters to the corresponding functional modules through the found register address.

[0059] In some embodiments, the FPGA chip further comprises a first phase-locked loop module 180 connected with the PCIe module 160; the PCIe module 160 is further configured to output a first signal to the first phase-locked loop module 180; the first phase-locked loop module 180 is configured to receive the first signal and perform clock configuration initialization on the clock phase-locked loop chip when the first signal is at a high level.

[0060] When the data acquisition system is powered on, the FPGA chip in the data acquisition system is powered on, and the PCIe module 160 in the FPGA chip communicates and builds a link with the host computer through the X8 PCIE interface. After the link is built, the PCIe module 160 outputs a first signal to the configuration module 170, the second data transmission module 150, and the first phase-locked loop module 180 to simultaneously start the configuration module 170, the second data transmission module 150, and the first phase-locked loop module 180, realizing the transmission function of register control commands and DMA data.

[0061] Taking the first phase-locked loop module 180 as an example, the first phase-locked loop module 180 is in a reset state during the period when the first signal is at a low level, and waits for the PCIe module 160 and the host computer to successfully build a link and output a high-level first signal. When the first signal received by the first phase-locked loop module 180 is at a high level, the first phase-locked loop module 180 starts to work. At this time, the first phase-locked loop module 180 performs clock configuration initialization on the clock phase-locked loop chip on the hardware of the data acquisition system through the SPI interface.

[0062] It should be noted that the clock configuration initialization process is a configuration process of a register of a clock chip by the FPGA chip through the SPI interface. According to the register definition in the data manual, the register value can be configured according to the required output clock frequency, so that the clock chip finally outputs the required clock frequency.

[0063] The configuration module 170 and the second data transmission module 150 will start working after receiving the high-level first signal, to realize the transmission function of the register control command and the DMA data.

[0064] In some embodiments, the FPGA chip can further include a second phase-locked loop module 190 connected with the first phase-locked loop module 180; the first phase-locked loop module 180 is further configured to send a second signal to the second phase-locked loop module 190 after the clock configuration initialization of the first clock phase-locked loop chip; and the second phase-locked loop module 190 is configured to receive the second signal and perform clock configuration initialization on the clock frequency multiplication chip when the second signal is high.

[0065] In the embodiment, after the first phase-locked loop module 180 completes the clock configuration initialization of the clock phase-locked loop chip, the first phase-locked loop module 180 outputs a second signal to the second phase-locked loop module 190. Specifically, similarly, the second phase-locked loop module 190 is in a reset state before the first phase-locked loop module 180 completes the clock configuration initialization, and waits for the initialization of the first phase-locked loop module 180 to be completed.

[0066] When the first phase-locked loop module 180 completes the clock configuration initialization of the clock phase-locked loop chip, the first phase-locked loop module 180 outputs a high-level second signal to the second phase-locked loop module 190. When the second signal is pulled high, the second phase-locked loop module 190 starts working, and the second phase-locked loop module 190 performs clock configuration initialization on the clock frequency multiplication chip on the hardware of the data acquisition system through the SPI interface.

[0067] In some embodiments, the FPGA chip can further include an ADC control module 200 connected with the second phase-locked loop module 190 and the master control module 110. The second phase-locked loop module 190 is further configured to send a third signal to the ADC control module 200 after the clock configuration initialization of the clock frequency multiplication chip; the ADC control module 200 is configured to receive the third signal and perform configuration initialization on the ADC chip when the third signal is high, and send a fourth signal to the master control module 110; and the master control module 110 is configured to receive the fourth signal and start working when the fourth signal is high.

[0068] In the embodiment, the ADC control module 200 is in a reset state before the second phase-locked loop module 190 completes initialization of the clock frequency multiplication chip, and waits for the second phase-locked loop module 190 to complete initialization of the clock frequency multiplication chip.

[0069] After the second phase-locked loop module 190 completes initialization of the clock frequency multiplication chip, the second phase-locked loop module 190 sends a high-level third signal to the ADC control module 200. After the third signal is pulled high, the ADC control module 200 starts to work, and the ADC control module 200 configures and initializes the ADC chip on the data acquisition system hardware through the SPI interface.

[0070] It should be noted that the configuration and initialization of the second phase-locked loop module 190 is the same as that of the first phase-locked loop module 180, which will not be described here. In addition, the first phase-locked loop module 180 is mainly used to generate a plurality of synchronous low-frequency clocks, and specifically can generate four 312.5MHz clocks, and output the four 312.5MHz clocks to the refclk of the FPGA chip main control module 110; can also generate a 1-4, 100MHz clock and output it to the second phase-locked loop module 190, so that the second phase-locked loop module 190 serves as a reference clock; can also generate a 125MHz clock and output it to four DDR units, so that the DDR unit serves as a reference clock. The second phase-locked loop module 190 is mainly used to generate a high-frequency clock, and output the high-frequency clock to the ADC chip as a sampling driving clock.

[0071] Further, the main control module 110 is in a reset state before the ADC control module 200 completes configuration and initialization of the ADC chip, and waits for the ADC control module 200 to complete configuration and initialization of the ADC chip.

[0072] After the ADC control module 200 completes configuration and initialization of the ADC chip, the ADC control module 200 sends a high-level fourth signal to the main control module 110. After the fourth signal is pulled high, the main control module 110 starts to work.

[0073] Therefore, the FPGA chip of the embodiment can realize acquisition, reception, caching and processing of 640Gbps ultra-high-speed data.

[0074] On the basis of the above embodiment, the application further provides a data ultra-high-speed acquisition and processing method based on an FPGA chip.

[0075] Figure 2is a flowchart of a data super-high-rate acquisition processing method of an embodiment of the present application. The data super-high-rate acquisition processing method based on an FPGA chip can be implemented by the FPGA chip of the above embodiment. The data super-high-rate acquisition processing method based on the FPGA chip can include the following steps.

[0076] Step 210: simultaneously receiving super-high-rate data output by the ADC chip to obtain four 512-bit data blocks, and decomposing the four 512-bit data blocks into 256 first data units of 8 bits.

[0077] Step 220: performing data processing on each first data unit, and converting the 256 first data units of 8 bits into 320 second data units of 8 bits.

[0078] Step 230: writing, reading out and storing the 320 second data units of 8 bits.

[0079] In some embodiments, the step 210 of simultaneously receiving super-high-rate data output by the ADC chip to obtain four 512-bit data blocks includes: receiving super-high-rate data output by the ADC chip and a synchronization signal to obtain four 512-bit data blocks; wherein the synchronization signal is used to synchronize and align each data block.

[0080] It should be noted that details not disclosed in the data super-high-rate acquisition processing method based on the FPGA chip of the present embodiment can refer to details disclosed in the FPGA chip of the super-high-rate embodiment of the present specification, which will not be described here.

[0081] The device embodiments described above are only schematic, wherein the units illustrated as separate components can or can not be physically separate, and the components illustrated as units can or can not be physical units, i.e., can be located in one place or distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment. Those skilled in the art can understand and implement without creative labor.

[0082] From the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software and the necessary general hardware platform, or by hardware. Based on such understanding, the above technical solutions can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

Claims

1. An ultra-high rate FPGA chip, characterized by, The main control module, the data processing module, the first data transmission module and the memory control module are sequentially connected. The main control module comprises four serial interfaces and a data rearrangement unit, each serial interface is used for receiving super-high-rate data output by an ADC chip to obtain four 512-bit data blocks, and the data rearrangement unit is used for decomposing the four 512-bit data blocks received by each serial interface into 256 first data units of 8 bits. The data processing module is used for data processing of each first data unit, the first data transmission module is used for data recombination of 256 first data units of 8 bits to convert them into 320 second data units of 8 bits, and the 320 second data units of 8 bits are transmitted to the memory control module; wherein the data content of the first data unit is the same as that of the second data unit. The memory control module comprises four DDR chips, which are used for writing, reading and storing 320 second data units of 8 bits.

2. The ultra-high rate FPGA chip of claim 1, wherein, Each serial interface is used for receiving super-high-rate data output by an ADC chip and a synchronization signal to obtain four 512-bit data blocks. The synchronization signal is used for synchronizing and aligning each data block.

3. The ultra-high rate FPGA chip of claim 1, wherein, The memory control module further comprises a data writing unit and a data reading unit connected with each DDR chip. The data writing unit is used for receiving 320 second data units of 8 bits, dividing them into four data groups, and writing each data group into each DDR chip. Each DDR chip is used for storing a data group. The data reading unit is used for receiving data groups read from each DDR chip.

4. The ultra-high rate FPGA chip of claim 3, wherein, The FPGA chip further comprises a second data transmission module and a PCIe module, the second data transmission module is connected with the memory control module and the PCIe module, and the PCIe module is connected with a host computer. The second data transmission module is used for receiving each data group output by the data reading unit, converting each data group into a DAM format, and outputting the DAM-formatted data group to the PCIe module. The PCIe module is used for uploading each DAM-formatted data group to the host computer.

5. The ultra-high rate FPGA chip of claim 4, wherein, The FPGA chip further comprises a configuration module connected with the PCIe module. The PCIe module is further used for receiving a control instruction and / or a configuration parameter sent by the host computer, and sending the control instruction and / or the configuration parameter to the configuration module. The configuration module is used for sending the control instruction and / or the configuration parameter to the corresponding modules.

6. The ultra-high rate FPGA chip of claim 4, wherein, The FPGA chip further comprises a first phase-locked loop module connected with the PCIe module. The PCIe module is further used for outputting a first signal to the first phase-locked loop module. The first phase-locked loop module is used for receiving the first signal and performing clock configuration initialization on a clock phase-locked loop chip when the first signal is at a high level.

7. The ultra-high rate FPGA chip of claim 6, wherein, The FPGA chip further comprises a second phase-locked loop module, which is connected with the first phase-locked loop module; The first phase-locked loop module is further configured to send a second signal to the second phase-locked loop module after clock configuration initialization of the first clock phase-locked loop chip; The second phase-locked loop module is configured to receive the second signal and perform clock configuration initialization of the clock frequency multiplication chip when the second signal is at a high level.

8. The ultra-high rate FPGA chip of claim 7, wherein, The FPGA chip further comprises an ADC control module, which is connected with the second phase-locked loop module and the master control module; The second phase-locked loop module is further configured to send a third signal to the ADC control module after clock configuration initialization of the clock frequency multiplication chip; The ADC control module is configured to receive the third signal and perform configuration initialization of the ADC chip when the third signal is at a high level, and send a fourth signal to the master control module; The master control module is configured to receive the fourth signal and start working when the fourth signal is at a high level.

9. A data super-high-rate acquisition processing method based on an FPGA chip, characterized in that, The method is applied to the FPGA chip of any one of claims 1 to 8, and the method comprises: simultaneously receiving super-high-rate data output by the ADC chip to obtain four 512-bit data blocks, and decomposing the four 512-bit data blocks into 256 first data units of 8 bits; performing data processing on each of the first data units, and recombining and converting the 256 first data units of 8 bits into 320 second data units of 8 bits; wherein the data content of the first data units is the same as that of the second data units; writing, reading out and storing the 320 second data units of 8 bits.

10. The FPGA chip-based data super-high-speed acquisition processing method according to claim 9, characterized in that, The simultaneously receiving super-high-rate data output by the ADC chip to obtain four 512-bit data blocks comprises: receiving super-high-rate data output by the ADC chip and a synchronization signal to obtain four 512-bit data blocks; wherein the synchronization signal is used to synchronize and align each data block.

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