Layout automatic generation method and device and electronic equipment

Abstract

Embodiments of the present application provide a kind of layout automatic generation method, device and electronic equipment, belong to computer technical field.The method includes: in response to the input instruction of metal layer processing mode, the metal layer processing mode of original layout is acquired;Metal layer information in the original layout is acquired;Through the graphics processing statement, the metal layer information in the original layout is carried out graphics operation, and the region to be handled corresponding to the metal layer processing mode in the original layout is screened out;Through the graphics generation statement, the new layout matched with the metal layer processing mode is generated on the region to be handled.The embodiments of the present application realize the quick, automatic modification and regeneration of original layout by computer program language in combination with the metal layer processing mode of original layout input by user, and the efficiency of chip layout design is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a layout automatic generation method, a layout automatic generation device, an electronic device, a machine-readable storage medium and a computer program product. Background Art

[0002] The time required to move a chip from design to mass production is often significant. Therefore, integrating high-performance modules into products of varying specifications across diverse fields, and thus leveraging the intellectual property (IP) of chip design, can significantly shorten the chip design cycle and reduce the risk of designing each product from scratch. Different products utilize varying metal layers during the design process due to differences in design, device usage, and power consumption.

[0003] To adapt the same chip IP to products with different metal layers, the chip IP's metal layout design must be modified based on the product's metal requirements. For example, if a chip IP currently has a maximum of six metal layers (M6), and a new application requires an additional eight metal layers (M8), then a seventh (M7) and eighth (M8) metal layers, along with the corresponding vias, must be added. Modifying metal layers within the layout can be accomplished using existing layout design tools like Virtuoso or CalibreDrv, but this requires manual effort and is time-consuming. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a layout automatic generation method, a layout automatic generation device, an electronic device, a machine-readable storage medium and a computer program product to solve the defect that the metal layer can be modified in the layout through the existing layout design tools Virtuoso or CalibreDrv, but manual operation by technicians is required, which takes a lot of time.

[0005] To achieve the above objectives, an embodiment of the present invention provides a method for automatically generating a layout, comprising:

[0006] In response to an input instruction of a metal layer processing method, obtaining a metal layer processing method for an original layout;

[0007] Obtaining metal layer information in the original layout;

[0008] Performing graphic operations on the metal layer information in the original layout through graphic processing statements to filter out the area to be processed in the original layout that corresponds to the metal layer processing method;

[0009] A new layout matching the metal layer processing method is generated on the area to be processed through a graphic generation statement.

[0010] Optionally, the metal layer processing method includes generating a preset number of new metal layers on the original metal layer; the graphic processing statement includes a graphic selection statement, and the graphic processing statement is used to perform graphic operations on the metal layer information in the original layout to screen out the area to be processed in the original layout corresponding to the metal layer processing method, including:

[0011] Performing graphic operations on the metal layer information in the original layout through a graphic selection statement to filter out the original metal layer in the original layout;

[0012] The step of generating a new layout matching the metal layer processing method on the area to be processed by using a graphic generation statement includes:

[0013] A preset number of new metal layers are generated on the original metal layer through a graphic generation statement to generate the new layout.

[0014] Optionally, the metal layer processing method includes adding a preset number of new metal layers on the first designated area; the graphic processing statement includes a graphic logic operation statement, and the graphic processing statement is used to perform graphic operations on the metal layer information in the original layout to screen out the area to be processed in the original layout corresponding to the metal layer processing method, including:

[0015] Performing graphic operations on the metal layer information in the original layout by using graphic logic operation statements to filter out the first designated area in the original layout;

[0016] The step of generating a new layout corresponding to the metal layer processing method on the area to be processed by using a graphic generation statement includes:

[0017] A preset number of new metal layers are generated on the first designated area through a graphic generation statement to generate the new layout.

[0018] Optionally, the metal layer processing method includes not generating a new metal layer on at least one of the original metal layer having a width smaller than a preset width threshold, the second designated area, and the sensitive area; the graphic processing statement includes a graphic selection statement and / or a graphic logic operation statement;

[0019] The step of performing graphic operations on the metal layer information in the original layout by using graphic processing statements to filter out the area to be processed in the original layout corresponding to the metal layer processing method includes:

[0020] performing a graphic operation on the metal layer information in the original layout by using a graphic selection statement to filter out original metal layers smaller than a preset width threshold in the original layout; and / or performing a graphic operation on the metal layer information in the original layout by using a graphic logical operation statement to filter out at least one of the second designated region and the sensitive region in the original layout;

[0021] The graphic generation statement generates a new layout corresponding to the metal layer processing mode on the to-be-processed region, including:

[0022] The graphic generation statement does not generate a new metal layer on at least one of the original metal layer smaller than the preset width threshold, the second designated region and the sensitive region to generate the new layout.

[0023] Optionally, the sensitive region includes a capacitance region and / or a sensitive signal line region.

[0024] Optionally, the metal layer processing mode includes generating a new metal layer according to the metal layer quantity of another original metal layer on any one of the original metal layers of the two layers arranged in cross, and the graphic processing statement includes a graphic selection statement and a graphic logical operation statement.

[0025] The graphic processing statement performs a graphic operation on the metal layer information in the original layout to filter out a to-be-processed region in the original layout corresponding to the metal layer processing mode, including:

[0026] The graphic selection statement and the graphic logical operation statement perform a graphic operation on the metal layer information in the original layout to filter out original metal layers of two layers arranged in cross in the original layout.

[0027] The graphic generation statement generates a new layout corresponding to the metal layer processing mode on the to-be-processed region, including:

[0028] The graphic generation statement generates a new metal layer according to the metal layer quantity of another original metal layer on any one of the original metal layers of the two layers arranged in cross to generate the new layout.

[0029] In another aspect, the embodiment of the present application also provides a layout automatic generation device, including:

[0030] An instruction input module is configured to acquire a metal layer processing mode of an original layout in response to an input instruction of a metal layer processing mode.

[0031] A metal layer information acquisition module is configured to acquire metal layer information in the original layout.

[0032] an area screening module, configured to perform graphic operations on the metal layer information in the original layout through graphic processing statements, and screen out the area to be processed in the original layout corresponding to the metal layer processing method;

[0033] The layout generation module is used to generate a new layout matching the metal layer processing method on the area to be processed by using a graphic generation statement.

[0034] Optionally, the metal layer processing method includes generating a preset number of new metal layers on the original metal layer; the graphic processing statement includes a graphic selection statement, and the graphic processing statement is used to perform graphic operations on the metal layer information in the original layout to screen out the area to be processed in the original layout corresponding to the metal layer processing method, including:

[0035] Performing graphic operations on the metal layer information in the original layout through a graphic selection statement to filter out the original metal layer in the original layout;

[0036] The step of generating a new layout matching the metal layer processing method on the area to be processed by using a graphic generation statement includes:

[0037] A preset number of new metal layers are generated on the original metal layer through a graphic generation statement to generate the new layout.

[0038] Optionally, the metal layer processing method includes adding a preset number of new metal layers on the first designated area; the graphic processing statement includes a graphic logic operation statement, and the graphic processing statement is used to perform graphic operations on the metal layer information in the original layout to screen out the area to be processed in the original layout corresponding to the metal layer processing method, including:

[0039] Performing graphic operations on the metal layer information in the original layout by using graphic logic operation statements to filter out the first designated area in the original layout;

[0040] The step of generating a new layout corresponding to the metal layer processing method on the area to be processed by using a graphic generation statement includes:

[0041] A preset number of new metal layers are generated on the first designated area through a graphic generation statement to generate the new layout.

[0042] Optionally, the metal layer processing method includes not generating a new metal layer on at least one of the original metal layer having a width smaller than a preset width threshold, the second designated area, and the sensitive area; the graphic processing statement includes a graphic selection statement and / or a graphic logic operation statement;

[0043] The metal layer information in the original layout is subjected to a graphic operation by a graphic processing statement to screen out a to-be-processed region in the original layout corresponding to the metal layer processing mode, which comprises:

[0044] The metal layer information in the original layout is subjected to a graphic operation by a graphic selection statement to screen out an original metal layer smaller than a preset width threshold in the original layout; and / or, the metal layer information in the original layout is subjected to a graphic operation by a graphic logical operation statement to screen out at least one region of a second designated region and a sensitive region in the original layout;

[0045] The graphic generation statement generates a new layout corresponding to the metal layer processing mode on the to-be-processed region, which comprises:

[0046] The graphic generation statement does not generate a new metal layer on at least one region of the original metal layer smaller than the preset width threshold, the second designated region and the sensitive region to generate the new layout.

[0047] Optionally, the sensitive region comprises a capacitance region and / or a sensitive signal line region.

[0048] Optionally, the metal layer processing mode comprises generating a new metal layer on any one of the original metal layers of two layers arranged in cross according to the metal layer quantity of the other original metal layer; and the graphic processing statement comprises a graphic selection statement and a graphic logical operation statement.

[0049] The metal layer information in the original layout is subjected to a graphic operation by a graphic processing statement to screen out a to-be-processed region in the original layout corresponding to the metal layer processing mode, which comprises:

[0050] The metal layer information in the original layout is subjected to a graphic operation by a graphic selection statement and a graphic logical operation statement to screen out original metal layers of two layers arranged in cross in the original layout;

[0051] The graphic generation statement generates a new layout corresponding to the metal layer processing mode on the to-be-processed region, which comprises:

[0052] The graphic generation statement generates a new metal layer on any one of the original metal layers of two layers arranged in cross according to the metal layer quantity of the other original metal layer to generate the new layout.

[0053] In another aspect, the application further provides an electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the above-mentioned layout automatic generation method.

[0054] On the other hand, the present invention also provides a machine-readable storage medium having a computer program stored thereon, which implements the above-mentioned automatic layout generation method when executed by a processor.

[0055] On the other hand, the present invention also provides a computer program product, including a computer program, which implements the above-mentioned layout automatic generation method when executed by a processor.

[0056] Through the above technical solution, the embodiment of the present invention uses graphic processing statements to perform graphic operations on the metal layer information in the original layout, screening out the area to be processed in the original layout; and uses graphic generation statements to generate a new layout corresponding to the metal layer processing method on the area to be processed. Thus, the embodiment of the present invention uses a computer program language combined with the metal layer processing method input by the user to achieve rapid and automatic modification and regeneration of the original layout, greatly improving the efficiency of chip layout design.

[0057] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present invention, but do not constitute a limitation of the embodiments of the present invention. In the accompanying drawings:

[0059] Figure 1 This is one of the flow charts of the method for automatically generating a layout provided by the present invention;

[0060] Figure 2 is one of the schematic diagrams of the unmodified layout provided by the present invention;

[0061] Figure 3 It is one of the layouts generated by the layout automatic generation method provided by the present invention;

[0062] Figure 4 This is the second schematic diagram of the unmodified layout provided by the present invention;

[0063] Figure 5 This is the second layout generated by the layout automatic generation method provided by the present invention;

[0064] Figure 6 It is a structural diagram of the layout automatic generation device provided by the present invention;

[0065] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0066] The following describes the specific implementation of the embodiment of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the embodiment of the present invention and is not used to limit the embodiment of the present invention.

[0067] The following are technical terms that appear in the embodiments of the present invention:

[0068] Pin layer: Pin layer is usually used to represent the input and output pins of a chip or module. In the layout, the pin layer can clearly mark which parts are used for external connections.

[0069] Exclude Layer: Exclude layers are used to specify areas during layout where specific components or traces are prohibited. For example, certain areas may be unusable due to physical constraints (such as mechanical structure or other already placed components). During layout optimization, EDA tools avoid placing any elements within the areas specified by the exclude layer.

[0070] CAP layer: The CAP layer is typically used to indicate the layout of capacitors. In the layout, the CAP layer can clearly indicate the location and size of the capacitors, making it easier for engineers to perform layout and routing.

[0071] Method Example

[0072] Please refer to Figure 1 , an embodiment of the present invention provides a method for automatically generating a layout, comprising:

[0073] Step 100: In response to an input instruction of a metal layer processing method, obtain a metal layer processing method for an original layout.

[0074] A user inputs a metal layer processing method for the original layout on an electronic device through an input device (such as a keyboard, touch screen, etc.). The electronic device responds to the input instruction for the metal layer processing method and obtains the metal layer processing method for the original layout. The metal layer processing method for the original layout includes a metal layer addition method. Different metal addition methods can be provided, such as adding 7 new metal layers (M7) to 5 metal layers (M5), adding 8 new metal layers (M8) to 6 metal layers (M6), adding 7 metal layers to a metal layer with a width greater than or equal to a preset width threshold, adding 7 metal layers to a designated area, adding 7 metal layers to a via area, and generating a new metal layer on either of two original metal layers with different numbers of layers based on the number of metal layers of the other original metal layer (such as adding M6 to an area with M5 but no M6, or adding M5 to an area with M6 but no M5). Metal layer processing methods also include not adding metal layers to designated areas and not adding metal layers to sensitive areas.

[0075] Step 200: Obtain metal layer information in the original layout.

[0076] In this embodiment of the present invention, a script written in the Calibre language can be used to automatically modify the layout. Specifically, the metal layers in the layout need to be defined. First, the number of the required graphic layers is defined, including the number of the existing 5-layer metal layer or via or 6-layer metal layer, and the number of the upper metal layer to be added, that is, the number of the 7-layer metal layer or the 8-layer metal layer.

[0077] For example, the following code is used to define 5 metal layers and vias:

[0078] tvf::LAYERMAP 15 DATATYPEPE==0 5001

[0079] tvf::LAYER M5 5001

[0080] tvf::LAYERMAP 16 DATATYPE==0 5002

[0081] tvf::LAYER V5 5002

[0082] The embodiment of the present invention also needs to define some other layers that need to be used. For example, the metal pin layer is defined as the addin layer, so that even if the specified area does not have 5 metal layers or 6 metal layers (i.e., M5 / M6), 7 metal layers or 8 metal layers (i.e., M7 / M8) can be added; the metal exclude layer and CAP layer are defined, so that even if the specified area has M5 / M6, metal M7 / M8 will not be added.

[0083] For example, the definitions of addin layer, exclude layer and CAP layer are implemented through the following code:

[0084] tvf::LAYERMAP 140 DATATYPE==32 5015

[0085] tvf::LAYER M5_addin 5015

[0086] tvf::LAYERMAP 140 DATATYPE==20 5016

[0087] tvf::LAYER M5_exc 5016

[0088] tvf::LAYERMAP 62 DATATYPE==123 5017

[0089] tvf::LAYER CAP 5017

[0090] This embodiment of the present invention also requires defining TEXT layers to identify specific metals. The TEXT layer definition uses the tvf::TEXT LAYER layer to specify a layer as a text layer, the tvf::PORT LAYER TEXT layer to specify a layer as a port layer, and the tvf::SETLAYER statement to define the text layer's graphics for subsequent calculations.

[0091] For example, it can be achieved through the following code:

[0092] tvf::LAYERMAP 34 DATATYPE==20 5020

[0093] tvf::LAYER M5_TXT 5020

[0094] tvf::TEXT LAYER M5_TXT

[0095] tvf::PORT LAYER TEXT M5_TXT

[0096] tvf::SETLAYER M5_LBL ="EXPAND TEXT \"?\" M5_TXT BY 0.02 PRIMARY ONLY"

[0097] Therefore, the embodiment of the present invention can obtain the metal layer information in the original layout by obtaining the number of the metal layer in the original layout.

[0098] The present embodiment uses SET and VARIABLE to define various variables. For example, SET is used to define the metal option Beol_Stack, providing different metal options. SET is also used to define metal addition methods, providing different metal addition methods. For example, M5andM6 is defined as adding a 7th metal layer (M7) to a 5th metal layer (M5), and an 8th metal layer (M8) to a 6th metal layer (M6). M6_Only is defined as adding M7 and M8 to M6. SET is used to define the minimum width of metal growth. Metal that is greater than twice the minimum width will be added with 7 or 8th metal layers (M7 / M8). SET is used to define special signals. Add_Connect_Only defines that all metal on a signal line will only be added at intersections with vias, ensuring correct signal connections and avoiding the introduction of excessive parasitics. Not_Add defines that no metal will be added to all metal on a signal line, reducing parasitics. VARIABLE is used to define the path and PRIMARY of the original layout file. VARIABLE is also used to define the size, distance, and minimum enclosure parameters of the vias.

[0099] The above definition of each variable using SET and VARIABLE can be achieved through the following code:

[0100] set Beol_Stack 3P9M1T0F

[0101] set Add_temp M6_Only

[0102] / / M5andM6,M6_Only

[0103] VARIABLE metal_width_min 0.499

[0104] set Connect_only_signal Add_Connect_Only

[0105] set Not_add_signal Not_Add

[0106] VERBATIM {

[0107] LAYOUT PRIMARY "Top_name"

[0108] LAYOUT PATH "Top_name.gds"

[0109] LAYOUT SYSTEM GDSII

[0110] VARIABLE Vx_space0.12

[0111] VARIABLE Vx_size0.1

[0112] VARIABLE Vx_enclose-0.04

[0113] }

[0114] Step 300: Perform graphic operations on the metal layer information in the original layout through graphic processing statements to filter out the area to be processed in the original layout that corresponds to the metal layer processing method.

[0115] Graphics processing statements may include graphics selection statements, graphics logic operation statements, graphics association statements, etc. In an embodiment of the present invention, a SIZE statement (i.e., a graphics selection statement) may be used to zoom in and out and filter graphics. For example, a SIZE statement may be used to filter out metal layers whose metal layer width is greater than a preset width threshold to add an upper layer of metal; or a graphics logic operation statement may be used to implement graphics operations, such as an OR statement to implement a graphics OR operation, an AND statement to implement a graphics AND operation, and a NOT statement to implement a graphics NOT operation; in other embodiments, a COPY statement (graphic selection statement) may be used to implement hierarchical copying; an INTERACT statement (graphic association statement) may be used to implement the association between metal and vias; a CONNECT statement (graphic association statement) may be used to connect each layer of metal to the vias; and a NET AREARATIO (graphic association statement) may be used to implement the association between metal and TEXT. Please refer to the following sample script:

[0116] tvf::SETLAYER add_M5_exc="M5_exc OR CAP"

[0117] tvf::SETLAYER add_M5_other = "COPY M5_addin"

[0118] / / Part 1

[0119] tvf::SETLAYER add_M5_o = "SIZE ((M5 INTERACT V5) NOT add_M5_exc) BYmetal_width_min UNDEROVER"

[0120] add_M6_exc = "M6_exc OR CAP"

[0121] / / Part 2

[0122] VERBATIM"

[0123] CONNECT M1 M2 BY V1

[0124] CONNECT...

[0125] CONNECT M7 M8 BY V7

[0126] / / 部分3

[0127] tvf::SETLAYER add_M5_cross_o = NET AREA RATIO add_M5_o (add_M5_o WITHTEXT \"Add_Connect_Only\" M5_LBL)>0

[0128] tvf::SETLAYER add_M5_Not_Add_o = NET AREA RATIO add_M5_o (add_M5_oWITH TEXT \"Not_Add\" M5_LBL)>0

[0129] / / 部分4

[0130] tvf::SETLAYER add_cross_via_org = "(add_M5_cross_o AND add_M6_cross_o) INTERACT V5"

[0131] tvf::SETLAYER add_M5_o_new="(((add_M5_o NOT add_M5_cross_o) NOT add_M5_Not_Add_o) OR add_cross_via_org)"

[0132] / / 部分5

[0133] tvf::SETLAYER shape_M5_via = "add_M5_o_new OR add_M5_via_other"

[0134] tvf::SETLAYER shape_M5_metal="add_M5_o_new OR add_M5_other"

[0135] / / 部分6

[0136] In the above script, part 1 defines add_M5_exc as the area where no upper metal is added, including the CAP and M5_exc areas, and add_M5_other is defined as the specific upper metal area to be added. That is, part 1 performs graphic operations on the metal layer information in the original layout through graphic logic operation statements to filter out the area to be processed in the original layout. Part 2 uses combination statements to implement M5 graphic operations. The graphic must overlap with the via V5, and remove the add_M5_exc area and the metal with a width less than 2 times metal_width_min. That is, part 1 performs graphic operations on the metal layer information in the original layout through graphic selection statements and graphic logic operation statements to filter out the area to be processed in the original layout. Part 3 uses the CONNECT statement to connect each layer of metal to the via. Part 4 uses the NET AREA RATIO statement to define the metal graphics associated with the special signal TEXT. Part 5 is the selection of the M5 graphic, which is the operation of the graphics of Part 2 and Part 4. The signal line of Add_Connect_Only only adds the upper metal in the via area to ensure the connectivity of the signal, and the signal line of Not_Add does not add the upper metal. That is, Part 5 performs graphic operations on the metal layer information in the original layout through graphic logic operation statements to filter out the area to be processed in the original layout. In Part 6, the addition of the add_M5_other graphic realizes that the area without 5 or 6 metal layers can also add 7 or 8 metal layers. The final graphic is shape_M5_metal&shape_M5_via. Part 6 performs graphic operations on the metal layer information in the original layout through graphic logic operation statements to filter out the area to be processed in the original layout.

[0137] Step 400: Generate a new layout matching the metal layer processing method on the area to be processed by using a graphic generation statement.

[0138] The embodiment of the present invention also uses RULECHECK to define the metal layers and vias that need to be grown, and uses the DRCCHECK MAP statement to generate a new layout. Please refer to the following example script to generate a new layout through the graphic generation statement:

[0139] tvf::RULECHECK created_M7 {

[0140] tvf::@ M7

[0141] tvf::SETLAYER A="COPY shape_M5_metal"

[0142] tvf::OUTLAYER "COPY A"

[0143] }

[0144] / / 部分11

[0145] tvf::RULECHECK created_V6 {

[0146] tvf::@ V6

[0147] tvf::SETLAYER A=" COPY shape_M5_via"

[0148] tvf::SETLAYER B="size A by Vx_close"

[0149] tvf::SETLAYER C="RECTANGLES Vx_size Vx_space INSIDE OF LAYER B"

[0150] tvf::SETLAYER C1="SIZE(A NOT (SIZE C by Vx_space)) BY metal_width_minUNDEROVER"

[0151] tvf::SETLAYER via1="RECTANGLES Vx_size Vx_size Vx_space INSIDE OFLAYER (size C1 by Vx_enclose)"

[0152] tvf::SETLAYER C2="SIZE(C1 NOT ( SIZE vial by Vx_space )) BY metal_width_min UNDEROVER"

[0153] tvf::SETLAYER via2="RECTANGLES Vx_size Vx_size Vx_space INSIDE OFLAYER (size C2 by Vx_enclose)"

[0154] tvf::SETLAYER V="(C or vial) or via2"

[0155] tvf::OUTLAYER "COPY V"

[0156] }

[0157] / / 部分12

[0158] tvf::DRC CHECK MAP created_V6 153 0 create.gds APPEND_create MAXIMUMRESULTS ALL

[0159] tvf::DRC CHECK MAP created_M7 142 0 create.gds APPEND _create MAXIMUMRESULTS ALL.

[0160] tvf::DRC CHECK MAP created_V7 154 0 create.gds APPEND create MAXIMUMRESULTS ALL

[0161] tvf::DRC CHECK MAP created_M8 143 0 create.gds APPEND create MAXIMUMRESULTS ALL

[0162] / / Part 13

[0163] In the above script, part 11 defines the shape of the 7-layer metal layer as shape_M5_metal; part 12 defines the shape of the via area V6 as shape_M5_via; the definition of the via uses multiple RECTANGLES statements to achieve the integrity of the via; part 13 uses the DRC CHECK MAP statement to generate the final new layout.

[0164] Thus, the embodiment of the present invention uses graphic processing statements to perform graphic operations on the metal layer information in the original layout, screening out the area to be processed in the original layout; and uses graphic generation statements to generate a new layout corresponding to the metal layer processing method on the area to be processed. Thus, the embodiment of the present invention uses a computer program language combined with the metal layer processing method input by the user to achieve rapid and automatic modification and regeneration of the original layout, greatly improving the efficiency of chip layout design.

[0165] In other aspects of the embodiments of the present invention, the metal layer processing method includes generating a preset number of new metal layers on the original metal layer; the graphic processing statement includes a graphic selection statement, and the graphic processing statement is used to perform graphic operations on the metal layer information in the original layout to filter out the area to be processed corresponding to the metal layer processing method in the original layout, including: performing graphic operations on the metal layer information in the original layout through the graphic selection statement to filter out the original metal layer in the original layout; the graphic generation statement is used to generate a new layout matching the metal layer processing method on the area to be processed, including: generating a preset number of new metal layers on the original metal layer through the graphic generation statement to generate the new layout.

[0166] In a specific embodiment, generating a preset number of new metal layers on the original metal layer can be to add 7 new metal layers on the 5-layer metal layer. In other embodiments, there may be multiple original metal layers, such as 5 metal layers and 6 metal layers. Graphic operations are performed on the metal layer information in the original layout through graphic logic selection statements to filter out the original metal layers in the original layout, which can be specifically implemented by the following code: tvf::SETLAYER shape_M7 = "COPY M5". Among them, M7 represents the new metal layer, and M5 represents the 5-layer metal layer. Then the final new layout can be generated by the DRC CHECK MAP statement. The embodiment of the present invention uses the Calibre language to quickly implement the addition of layout metal layers, avoiding the manual addition of upper metal or vias, and greatly improving the efficiency of chip layout design.

[0167] In other aspects of the embodiments of the present invention, the metal layer processing method includes adding a preset number of new metal layers to a first designated area; the graphic processing statement includes a graphic logic operation statement, and the graphic processing statement is used to perform graphic operations on the metal layer information in the original layout to filter out the area to be processed corresponding to the metal layer processing method in the original layout, including: performing graphic operations on the metal layer information in the original layout through graphic logic operation statements to filter out the first designated area in the original layout; the graphic generation statement is used to generate a new layout corresponding to the metal layer processing method on the area to be processed, including: generating a preset number of new metal layers on the first designated area through the graphic generation statement to generate the new layout.

[0168] In a specific embodiment, if you want to set an additional area, you need to use the pin layer of the corresponding metal to select the area in the original Gds file. The first designated area can be selected in the original Gds file using the pin layer of the corresponding metal, that is, the first designated area is selected by M5_addin. Graphic operations are performed on the metal layer information in the original layout through graphic logic operation statements, and the first designated area in the original layout is screened out by the following code: tvf::SETLAYER shape_M7="M5 OR M5_addin". Then the final new layout can be generated through the DRC CHECK MAP statement. The embodiment of the present invention uses the Calibre language to quickly implement the addition of the metal layer in the first designated area of ​​the layout, avoiding the manual addition of upper metal or vias, and greatly improving the efficiency of chip layout design.

[0169] In other aspects of the embodiments of the present invention, the metal layer processing method includes not generating a new metal layer on at least one of the original metal layer, the second designated area, and the sensitive area that is smaller than a preset width threshold; the graphic processing statement includes a graphic selection statement and / or a graphic logic operation statement; the graphic processing statement performs graphic operations on the metal layer information in the original layout to filter out the area to be processed corresponding to the metal layer processing method in the original layout, including: performing graphic operations on the metal layer information in the original layout through a graphic selection statement to filter out the original metal layer smaller than the preset width threshold in the original layout; and / or performing graphic operations on the metal layer information in the original layout through a graphic logic operation statement to filter out the second designated area and at least one of the sensitive areas in the original layout; the graphic generation statement generates a new layout corresponding to the metal layer processing method on the area to be processed, including: not generating a new metal layer on at least one of the original metal layer, the second designated area, and the sensitive area that is smaller than the preset width threshold through a graphic generation statement to generate the new layout.

[0170] Specifically, not generating a new metal layer on an original metal layer that is smaller than a preset width threshold means that you want to generate an upper metal layer only on a wide metal layer, and not on a fine metal layer. The SIZE statement can be used to define metal_width_min as required to filter out the fine metal layer. Graphic operations are performed on the metal layer information in the original layout using a graphic selection statement to filter out the original metal layers in the original layout that are smaller than the preset width threshold. This is achieved using the following code: tvf::SETLAYER shape_M7 = "SIZE M5 BY metal_width_min UNDEROVER". If you want to set an area not to be added, you need to select the area using the Exclude layer of the corresponding metal in the original Gds, that is, select the second specified area using M5_exc. Graphic operations are performed on the metal layer information in the original layout using a graphic logic operation statement to filter out the capacitor area in the original layout. This is achieved using the following code: tvf::SETLAYER shape_M7 = "(M5 NOT M5_exc) OR M5_addin". If the sensitive area does not want to add upper metal, such as the sensitive signal line, the corresponding TEXT Not_Add can be added to the signal line. If the parasitic sensitive signal only wants to add metal in the via area to ensure connectivity, the corresponding TEXT Add_Connect_Only can be added to the trace. The sensitive area includes the capacitor area, or the sensitive signal line area, or the capacitor area and the sensitive signal line area. Taking the capacitor area as an example, the metal layer information in the original layout is graphically operated through graphic logic operation statements to filter out the capacitor area in the original layout, which is implemented by the following code: tvf::SETLAYER shape_M7="(M5 NOT CAP) OR M5_addin". Graphic selection statements and graphic logic operations are used to perform graphic operations on the metal layer information in the original layout, filtering out the original metal layer, the second designated area, and the sensitive area that is smaller than a preset width threshold. This is achieved using the following code: tvf::SETLAYER shape_M7="SIZE (((M5 NOT M5_exc) NOT CAP) OR M5_addin)BY metal_width_minUNDEROVER". The final new layout can then be generated using the DRC CHECK MAP statement. This embodiment of the present invention selects designated sensitive signal line areas without adding upper-layer metal or adds metal only in the via area to ensure connectivity.

[0171] For example, Figure 2 and Figure 3 For a specific example, Figure 2 For the original layout, Figure 3To generate a new layout of the upper metal, Figure 2 The vertical lines in the middle are 5 metal layers (M5), and the horizontal lines are 6 metal layers (M6). Figure 3 1 in the middle is a thin trace, which is smaller than the defined metal_width_min and does not require adding upper metal. Figure 3 Middle 2 is the parasitic sensitive area, where the Exclude area has been added and no upper metal is generated; Figure 3 3 in the middle is a parasitic sensitive trace, TEXT of Not_Add has been added, and no upper metal is generated; Figure 3 4 is an additional area. Figure 2 There is no M5 / M6, but the pin layer has been added. Figure 3 The upper metal is generated in the middle; Figure 3 Middle 5 is the CAP region, where no upper metal is generated; Figure 3 The number 6 in the middle represents the routing of the ordinary 5-layer metal layer and the 6-layer metal layer. The 7-layer metal layer (M7) is generated on the 5-layer metal layer, and the 8-layer metal layer (M8) is generated on the 6-layer metal layer.

[0172] The embodiment of the present invention uses the Calibre language to quickly increase the metal layer of the layout, avoiding the manual addition of upper metal or vias, and greatly improving the efficiency of chip layout design. The embodiment of the present invention uses the Calibre language to quickly increase the metal layer of the first specified area of ​​the layout, avoiding the manual addition of upper metal or vias, and greatly improving the efficiency of chip layout design. The embodiment of the present invention uses the Calibre language to quickly implement the original metal layer, the second specified area, and at least one of the sensitive areas in the layout that is smaller than a preset width threshold without adding a metal layer, meeting the needs of special processing in chip IP.

[0173] In other aspects of the embodiments of the present invention, the metal layer processing method includes generating a new metal layer on any one of the two numbers of original metal layers that are cross-set according to the number of metal layers of the other original metal layer; the graphic processing statement includes a graphic selection statement and a graphic logic operation statement; the graphic processing statement performs graphic operations on the metal layer information in the original layout to filter out the area to be processed corresponding to the metal layer processing method in the original layout, including: performing graphic operations on the metal layer information in the original layout through graphic selection statements and graphic logic operation statements to filter out the two numbers of original metal layers that are cross-set in the original layout; the graphic generation statement generates a new layout corresponding to the metal layer processing method on the area to be processed, including: generating a new metal layer on any one of the two numbers of original metal layers that are cross-set according to the number of metal layers of the other original metal layer through a graphic generation statement to generate the new layout.

[0174] In the embodiment of the present invention, when using the Calibre language to automatically add upper metal layers, if the module is not sensitive to parasitics but has high parasitic resistance requirements, the script can add additional metal to reduce parasitic resistance. Take the metal model of 5 metal layers and 6 metal layers (M5, M6) as an example, Figure 4 and Figure 5 As shown, the embodiment of the present invention makes Figure 4 Increased metal formation Figure 5 The graphics, in Figure 4 In the area where there are 5 metal layers but no 6 metal layers, 6 metal layers can be added; Figure 4 In the area where there are 6 metal layers but no 5 metal layers, 5 metal layers can be added to reduce the trace resistance. The following code is used to filter out the areas to be processed in the horizontal and vertical frames:

[0175] tvf::SETLAYER add_M5_IR = "SIZE (add_M5_o_new NOT (SIZE M6 BY 1)) BYmetal_width_min UNDEROVER'

[0176] tvf::SETLAYER add_M6_IR="SIZE (add_M6_o_new NOT (SIZE M5 BY 1)) BYmetal_width_min UNDEROVER'

[0177] tvf::SETLAYER shape_M5_metal = "((add_M5_o_new OR add_M5_IR) OR add_M6_IR) OR add_M5_other"

[0178] tvf::SETLAYER shape_M6_metal ="((add_M6_o_new OR add_M5_IR) OR add_M6_IR) OR add_M6_other"

[0179] The above code performs graphical operations on the metal layer information in the original layout through graphical selection statements and graphical logical operation statements, screening out the original metal layers with two intersecting layers in the original layout using SIZE and NOT statements. The final new layout can then be generated using DRC CHECK MAP statements. This embodiment of the present invention uses the Calibre language to add corresponding metal to the intersecting two metal layers in areas that are insensitive to parasitic capacitance, greatly improving metal utilization and reducing chip trace resistance.

[0180] In summary, the embodiment of the present invention uses the Calibre language to quickly add a new metal layer to the original metal layer or via area of ​​the layout. It runs very fast and does not require manual operation. A large-scale chip IP can be processed using this method in just a few minutes. If automatic metal replication and manual addition of vias are used, it often takes dozens of hours. The embodiment of the present invention greatly improves the efficiency of chip layout design. The embodiments of the present invention can also realize various customized requirements, such as not growing upper metal in parasitic capacitance sensitive areas, and adding additional upper metal in designated areas; setting the minimum growth metal layer width, and not growing upper metal for metals smaller than this width; not growing upper metal in areas where the capacitor is parasitic sensitive; specifying sensitive signal line areas, choosing not to generate upper metal or only adding metal at the vias to ensure connectivity; choosing different ways to grow upper metal according to the design of the layout. If there is a lot of existing top metal, all newly added metal can be selected to cover the existing top metal. If there is not much existing top metal and there is a lot of existing sub-top metal, the newly added metal can be selected to cross-cover the existing top two metal layers, which can greatly improve the utilization rate of the metal; in areas where parasitic capacitance is insensitive, additional corresponding metal is added to the two crossed metal layers, which greatly reduces the wiring resistance of the chip.

[0181] Device embodiment

[0182] Please refer to Figure 6 On the other hand, an embodiment of the present invention further provides a layout automatic generation device, comprising:

[0183] The instruction input module 601 is used to obtain the metal layer processing method for the original layout in response to the input instruction of the metal layer processing method;

[0184] A metal layer information acquisition module 602 is used to acquire metal layer information in the original layout;

[0185] The region screening module 603 is configured to perform graphic operations on the metal layer information in the original layout using graphic processing statements to screen out the to-be-processed region in the original layout that corresponds to the metal layer processing method;

[0186] The layout generation module 604 is used to generate a new layout matching the metal layer processing method on the area to be processed by using a graphic generation statement.

[0187] Optionally, the metal layer processing method includes generating a preset number of new metal layers on the original metal layer;

[0188] The metal layer processing method includes generating a preset number of new metal layers on the original metal layer; the graphic processing statement includes a graphic selection statement; and the graphic processing statement is used to perform graphic operations on the metal layer information in the original layout to screen out the area to be processed in the original layout corresponding to the metal layer processing method, including:

[0189] Performing graphic operations on the metal layer information in the original layout through a graphic selection statement to filter out the original metal layer in the original layout;

[0190] The step of generating a new layout matching the metal layer processing method on the area to be processed by using a graphic generation statement includes:

[0191] A preset number of new metal layers are generated on the original metal layer through a graphic generation statement to generate the new layout.

[0192] Optionally, the metal layer processing method includes adding a preset number of new metal layers on the first designated area; the graphic processing statement includes a graphic logic operation statement; and performing graphic operations on the metal layer information in the original layout using the graphic processing statement to screen out the area to be processed in the original layout corresponding to the metal layer processing method includes:

[0193] Performing graphic operations on the metal layer information in the original layout by using graphic logic operation statements to filter out the first designated area in the original layout;

[0194] The step of generating a new layout corresponding to the metal layer processing method on the area to be processed by using a graphic generation statement includes:

[0195] A preset number of new metal layers are generated on the first designated area through a graphic generation statement to generate the new layout.

[0196] Optionally, the metal layer processing method includes not generating a new metal layer on at least one of the original metal layer having a width smaller than a preset width threshold, the second designated area, and the sensitive area; the graphic processing statement includes a graphic selection statement and / or a graphic logic operation statement;

[0197] The step of performing graphic operations on the metal layer information in the original layout by using graphic processing statements to filter out the area to be processed in the original layout corresponding to the metal layer processing method includes:

[0198] Performing a graphic operation on the metal layer information in the original layout using a graphic selection statement to screen out the original metal layers in the original layout that are smaller than a preset width threshold; and / or performing a graphic operation on the metal layer information in the original layout using a graphic logic operation statement to screen out at least one of the second designated area and the sensitive area in the original layout;

[0199] The step of generating a new layout corresponding to the metal layer processing method on the area to be processed by using a graphic generation statement includes:

[0200] The new layout is generated by not generating a new metal layer on at least one of the original metal layer having a width smaller than a preset threshold, the second designated area, and the sensitive area through a graphic generation statement. Optionally, the sensitive area includes a capacitor area and / or a sensitive signal line area.

[0201] Optionally, the metal layer processing method includes generating a new metal layer on any one of two original metal layers having two numbers of layers arranged crosswise, according to the number of metal layers of the other original metal layer; the graphic processing statement includes a graphic selection statement and a graphic logic operation statement;

[0202] The step of performing graphic operations on the metal layer information in the original layout by using graphic processing statements to filter out the area to be processed in the original layout corresponding to the metal layer processing method includes:

[0203] Performing graphic operations on the metal layer information in the original layout by using graphic selection statements and graphic logic operation statements to screen out the original metal layers of two numbers of layers that are cross-set in the original layout;

[0204] The step of generating a new layout corresponding to the metal layer processing method on the area to be processed by using a graphic generation statement includes:

[0205] A new metal layer is generated on any one of the two original metal layers with two numbers of layers arranged crosswise according to the number of metal layers of the other original metal layer through a graphic generation statement to generate the new layout.

[0206] The automatic layout generation device includes a processor and a memory. The above-mentioned instruction input module 601, metal layer information acquisition module 602, area screening module 603 and layout generation module 604 are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize the corresponding functions.

[0207] The processor includes a kernel, which calls the corresponding program unit from the memory. There can be one or more kernels.

[0208] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0209] Figure 7 An example of a physical structure diagram of an electronic device is shown below. Figure 7 As shown, the electronic device may include: a processor 710, a communication interface 720, a memory 730, and a communication bus 740, wherein the processor 710, the communication interface 720, and the memory 730 communicate with each other via the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute a layout automatic generation method, which includes: obtaining a metal layer processing method for an original layout in response to an input instruction of a metal layer processing method; obtaining metal layer information in the original layout; performing graphic operations on the metal layer information in the original layout through graphic processing statements to filter out a to-be-processed area in the original layout corresponding to the metal layer processing method; and generating a new layout matching the metal layer processing method on the to-be-processed area through graphic generation statements.

[0210] Furthermore, the logic instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product, stored in a storage medium, includes instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0211] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a machine-readable storage medium. When the computer program is executed by a processor, the computer can execute a layout automatic generation method, which includes: obtaining the metal layer processing method for the original layout in response to an input instruction of the metal layer processing method; obtaining the metal layer information in the original layout; performing graphic operations on the metal layer information in the original layout through graphic processing statements, and screening out the area to be processed in the original layout corresponding to the metal layer processing method; and generating a new layout matching the metal layer processing method on the area to be processed through graphic generation statements.

[0212] On the other hand, the present invention also provides a machine-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute a layout automatic generation method, the method comprising: obtaining the metal layer processing method for the original layout in response to an input instruction of the metal layer processing method; obtaining the metal layer information in the original layout; performing graphic operations on the metal layer information in the original layout through graphic processing statements, and screening out the area to be processed in the original layout corresponding to the metal layer processing method; and generating a new layout matching the metal layer processing method on the area to be processed through graphic generation statements.

[0213] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0214] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0215] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for automatically generating a layout, characterized in that: include: In response to an input instruction of a metal layer processing method, obtaining a metal layer processing method for an original layout; Obtaining metal layer information in the original layout; Performing graphic operations on the metal layer information in the original layout through graphic processing statements to filter out the area to be processed in the original layout that corresponds to the metal layer processing method; Generate a new layout matching the metal layer processing method on the area to be processed by using a graphic generation statement; The metal layer processing method includes not generating a new metal layer on at least one of the original metal layer having a width smaller than a preset threshold, the second designated area, and the sensitive area; the graphic processing statement includes a graphic selection statement and / or a graphic logic operation statement; The step of performing graphic operations on the metal layer information in the original layout by using graphic processing statements to filter out the area to be processed in the original layout corresponding to the metal layer processing method includes: Performing a graphic operation on the metal layer information in the original layout using a graphic selection statement to screen out the original metal layers in the original layout that are smaller than a preset width threshold; and / or performing a graphic operation on the metal layer information in the original layout using a graphic logic operation statement to screen out at least one of the second designated area and the sensitive area in the original layout; The step of generating a new layout corresponding to the metal layer processing method on the area to be processed by using a graphic generation statement includes: Not generating a new metal layer on at least one of the original metal layer having a width smaller than a preset threshold, the second designated area, and the sensitive area through a graphic generation statement, so as to generate the new layout; Use Calibre language to write scripts to realize automatic modification of the layout; define all metals on the signal lines through Add_Connect_Only to add metal only at the intersections with vias; define all metals on the signal lines through Not_Add to not add metal; use SIZE statement to zoom in and out and filter the graphics; use OR statement to realize the OR operation of graphics, use AND statement to realize the AND operation of graphics, and use NOT statement to realize the NOT operation of graphics.

2. The method for automatically generating a layout according to claim 1, wherein: The graphic processing statement includes a graphic selection statement; the graphic processing statement performs graphic operations on the metal layer information in the original layout to screen out the area to be processed in the original layout corresponding to the metal layer processing method, including: Graphic operations are performed on the metal layer information in the original layout through graphic selection statements to filter out the original metal layers in the original layout.

3. The method for automatically generating a layout according to claim 2, wherein: The metal layer processing method includes generating a preset number of new metal layers on the original metal layer; and generating a new layout matching the metal layer processing method on the area to be processed by using a graphic generation statement, including: A preset number of new metal layers are generated on the original metal layer through a graphic generation statement to generate the new layout.

4. The method for automatically generating a layout according to claim 1, wherein: The metal layer processing method includes adding a preset number of new metal layers on a first designated area; the graphic processing statement includes a graphic logic operation statement; and performing graphic operations on the metal layer information in the original layout using the graphic processing statement to screen out the area to be processed in the original layout corresponding to the metal layer processing method includes: Performing graphic operations on the metal layer information in the original layout by using graphic logic operation statements to filter out the first designated area in the original layout; The step of generating a new layout corresponding to the metal layer processing method on the area to be processed by using a graphic generation statement includes: A preset number of new metal layers are generated on the first designated area through a graphic generation statement to generate the new layout.

5. The method for automatically generating a layout according to claim 1, wherein: The sensitive area includes a capacitor area and / or a sensitive signal line area.

6. The method for automatically generating a layout according to claim 1, wherein: The metal layer processing method includes generating a new metal layer on any one of two original metal layers having two numbers of layers arranged crosswise, according to the number of metal layers of the other original metal layer; the graphic processing statement includes a graphic selection statement and a graphic logical operation statement; The step of performing graphic operations on the metal layer information in the original layout by using graphic processing statements to filter out the area to be processed in the original layout corresponding to the metal layer processing method includes: Performing graphic operations on the metal layer information in the original layout by using graphic selection statements and graphic logic operation statements to screen out the original metal layers of two numbers of layers that are cross-set in the original layout; The step of generating a new layout corresponding to the metal layer processing method on the area to be processed by using a graphic generation statement includes: A new metal layer is generated on any one of the two original metal layers with two numbers of layers arranged crosswise according to the number of metal layers of the other original metal layer through a graphic generation statement to generate the new layout.

7. A layout automatic generation device, characterized in that: include: An instruction input module, configured to obtain a metal layer processing method for an original layout in response to an input instruction of a metal layer processing method; A metal layer information acquisition module, configured to acquire metal layer information in the original layout; an area screening module, configured to perform graphic operations on the metal layer information in the original layout through graphic processing statements, and screen out the area to be processed in the original layout corresponding to the metal layer processing method; A layout generation module, configured to generate a new layout matching the metal layer processing method on the area to be processed by using a graphic generation statement; The metal layer processing method includes not generating a new metal layer on at least one of the original metal layer having a width smaller than a preset threshold, the second designated area, and the sensitive area; the graphic processing statement includes a graphic selection statement and / or a graphic logic operation statement; The step of performing graphic operations on the metal layer information in the original layout by using graphic processing statements to filter out the area to be processed in the original layout corresponding to the metal layer processing method includes: Performing a graphic operation on the metal layer information in the original layout using a graphic selection statement to screen out the original metal layers in the original layout that are smaller than a preset width threshold; and / or performing a graphic operation on the metal layer information in the original layout using a graphic logic operation statement to screen out at least one of the second designated area and the sensitive area in the original layout; The step of generating a new layout corresponding to the metal layer processing method on the area to be processed by using a graphic generation statement includes: Not generating a new metal layer on at least one of the original metal layer having a width smaller than a preset threshold, the second designated area, and the sensitive area through a graphic generation statement, so as to generate the new layout; Use Calibre language to write scripts to realize automatic modification of the layout; define all metals on the signal lines through Add_Connect_Only to add metal only at the intersections with vias; define all metals on the signal lines through Not_Add to not add metal; use SIZE statement to zoom in and out and filter the graphics; use OR statement to realize the OR operation of graphics, use AND statement to realize the AND operation of graphics, and use NOT statement to realize the NOT operation of graphics.

8. The automatic layout generation device according to claim 7, characterized in that: The graphic processing statement includes a graphic selection statement; the graphic processing statement performs graphic operations on the metal layer information in the original layout to screen out the area to be processed in the original layout corresponding to the metal layer processing method, including: Graphic operations are performed on the metal layer information in the original layout through graphic selection statements to filter out the original metal layers in the original layout.

9. The automatic layout generation device according to claim 8, characterized in that: The metal layer processing method includes generating a preset number of new metal layers on the original metal layer; and generating a new layout matching the metal layer processing method on the area to be processed by using a graphic generation statement, including: A preset number of new metal layers are generated on the original metal layer through a graphic generation statement to generate the new layout.

10. The automatic layout generation device according to claim 7, characterized in that: The metal layer processing method includes adding a preset number of new metal layers on a first designated area; the graphic processing statement includes a graphic logic operation statement; and performing graphic operations on the metal layer information in the original layout using the graphic processing statement to screen out the area to be processed in the original layout corresponding to the metal layer processing method includes: Performing graphic operations on the metal layer information in the original layout by using graphic logic operation statements to filter out the first designated area in the original layout; The step of generating a new layout corresponding to the metal layer processing method on the area to be processed by using a graphic generation statement includes: A preset number of new metal layers are generated on the first designated area through a graphic generation statement to generate the new layout.

11. The automatic layout generation device according to claim 7, characterized in that: The sensitive area includes a capacitor area and / or a sensitive signal line area.

12. The automatic layout generation device according to claim 7, characterized in that: The metal layer processing method includes generating a new metal layer on any one of two original metal layers having two numbers of layers arranged crosswise, according to the number of metal layers of the other original metal layer; the graphic processing statement includes a graphic selection statement and a graphic logical operation statement; The step of performing graphic operations on the metal layer information in the original layout by using graphic processing statements to filter out the area to be processed in the original layout corresponding to the metal layer processing method includes: Performing graphic operations on the metal layer information in the original layout by using graphic selection statements and graphic logic operation statements to screen out the original metal layers of two numbers of layers that are cross-set in the original layout; The step of generating a new layout corresponding to the metal layer processing method on the area to be processed by using a graphic generation statement includes: A new metal layer is generated on any one of the two original metal layers with two numbers of layers arranged crosswise according to the number of metal layers of the other original metal layer through a graphic generation statement to generate the new layout.

13. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the layout automatic generation method according to any one of claims 1 to 6 is implemented.

14. A machine-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for automatically generating a layout according to any one of claims 1 to 6 is implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method for automatically generating a layout according to any one of claims 1 to 6 is implemented.

Images