High-energy-efficiency dynamic graph neural network acceleration method and hardware accelerator

Abstract

The invention relates to a high-energy-efficiency dynamic graph neural network acceleration method and a hardware accelerator. The method comprises the steps of dynamically tracking an original dependency chain based on a dynamic dependency chain generation algorithm; sequentially storing the active vertexes to a chained FIFO buffer area according to the dependency relationship among the active vertexes; pre-extracting a source vertex, a target vertex, a dependency chain and graph data features related to the dependency chain from the chain FIFO buffer area according to a dependency sequence, and storing the extracted features in a pre-fetching buffer area; scheduling the source vertex and the target vertex from the prefetch buffer area to an aggregation buffer area of an aggregation engine, and scheduling the state of the source vertex and the corresponding edge state to a second application buffer area of a second application engine, so that the aggregation engine and the second application engine execute state aggregation and edge calculation tasks in parallel; and scheduling an aggregation result of the aggregation engine and an edge calculation result of the second application engine to the first application engine for fusion calculation, and outputting a final state of the target vertex.

Description

Technical Field

[0001] The present invention relates to the field of graph data processing technology and the field of artificial intelligence chip technology, and in particular to a high-energy-efficiency dynamic graph neural network acceleration method and hardware accelerator. Background Art

[0002] With the advent of the big data era, graphs, as a data structure that can effectively express data relationships, have been widely used in many fields, including internet applications, data mining, and scientific computing. Currently, many important graph applications use graph neural networks (GNNs) to iteratively process graph data until convergence, such as path analysis, product recommendations, and social network analysis.

[0003] In GNNs, vertices follow a neighborhood aggregation scheme, communicating with neighboring vertices through multiple iterations of synchronous message passing. However, recent research has shown that GNNs require frequent global synchronization between layers during training, which severely impacts their performance. To address this issue, a more efficient graph neural network model, the Dynamic Graph Neural Network (DGNN), has emerged. Unlike traditional models, the state (i.e., feature vector) of each vertex in a DGNN is dynamically updated by aggregating and transforming the states of neighboring vertices until the entire process converges. Furthermore, the gradients and embeddings of the DGNN model have also been shown to have good convergence properties.

[0004] Although several software DGNN systems and hardware GNN accelerators have been proposed, these systems still suffer from excessive redundant computation and off-chip communication problems due to the following two reasons. First, in each iteration of the DGNN, active vertices processed by different cores will irregularly propagate their latest states to adjacent vertices along the dependency chain between them in a dynamic manner. As a result, most vertices may use outdated states of their adjacent vertices for state updates, which is often unnecessary. Second, because the state of a vertex is usually large and cannot be fully stored in the on-chip memory, it can only be sparsely scattered in the off-chip memory, which leads to serious irregular memory access problems during DGNN inference.

[0005] For example, CN113313243A discloses a method, apparatus, device, and storage medium for determining a neural network accelerator. The method includes: obtaining a neural network model set and an accelerator structure set, wherein the neural network model set includes at least one neural network model, and the accelerator structure set includes at least one accelerator structure; determining at least one neural network accelerator based on the neural network model set and the accelerator structure set, wherein any neural network accelerator is determined by at least one neural network model and one accelerator structure and is used to process data of a certain data type; determining design parameters for each neural network accelerator, and based on each design parameter, determining performance indicators for each neural network accelerator; and determining a target neural network accelerator from each neural network accelerator based on each performance indicator. However, the technical solution has the following drawbacks: it may lead to redundant calculations in graph scenarios because vertex state updates need to wait for global synchronization; the hardware architecture lacks a modular design for graph operations, and is less efficient when processing the aggregation and propagation of graph neural networks.

[0006] In addition, on the one hand, there are differences in understanding among those skilled in the art; on the other hand, the applicant studied a large number of documents and patents when making the present invention, but due to space limitations, not all details and contents are listed in detail. However, this does not mean that the present invention does not have the characteristics of these prior arts. On the contrary, the present invention already has all the characteristics of the prior art, and the applicant reserves the right to add relevant prior art to the background technology. Summary of the Invention

[0007] In response to the shortcomings of the existing technology, the present invention provides a high-energy-efficiency dynamic graph neural network acceleration method from a first aspect, the method comprising: taking an unvisited active vertex as a root vertex, and dynamically tracking the original dependency chain based on a dynamic dependency chain generation algorithm until all active vertices are visited; storing the active vertices in a chain FIFO buffer in the order of the dependencies between the active vertices, so that the processing order is consistent with the data propagation path; pre-extracting the source vertex, the target vertex, the dependency chain between the target vertex and its adjacent vertices, and the graph data features related to the dependency chain from the chain FIFO buffer in the order of the dependencies, and storing them in a prefetch buffer; scheduling the source vertex and the target vertex from the prefetch buffer to the aggregation buffer of the aggregation engine, and scheduling the state of the source vertex and its corresponding edge state to the second application buffer of the second application engine, so that the aggregation engine and the second application engine execute state aggregation and edge calculation tasks in parallel; scheduling the aggregation result of the aggregation engine and the edge calculation result of the second application engine to the first application engine for fusion calculation, and outputting the final state of the target vertex.

[0008] The present invention realizes normalized data access through chain perception, dynamically tracks the dependency chain between active vertices, and continuously processes them in the order of each active vertex on the chain, avoiding many redundant data accesses and processing related to vertex state updates, so that the graph vertex state can be efficiently propagated along the dependency chain, thereby effectively improving the convergence speed of iterative graph processing.

[0009] According to a preferred embodiment, the dynamic dependency chain generation algorithm includes: obtaining vertices from an active bit vector buffer or an intermediate queue buffer; obtaining the head and tail offsets of the active vertices from the vertex array of the graph structure buffer; obtaining the unvisited adjacent vertices of the active vertex from the adjacent vertex array of the graph structure buffer, and sending the adjacent vertices to the intermediate queue buffer and the chain FIFO buffer; updating the adjacent vertices marked as active in the active bit vector buffer to adjacent vertices in the inactive state to perform adjacent vertex selection.

[0010] The active bit vector determines whether a vertex needs to participate in the current iteration, eliminating the processing overhead of inactive vertices (such as converged vertices). Collaborative filtering between the intermediate queue buffer and the chained FIFO buffer ensures that only valid adjacent vertices are processed. The present invention marks active adjacent vertices as "inactive" in real time to prevent the same vertex from triggering repeated updates in a single iteration.

[0011] According to a preferred embodiment, the pre-extraction step includes: extracting source vertices from a chain FIFO buffer in dependency order; searching an edge array related to the source vertex, extracting all adjacent vertices of the source vertex, and forming a dependency chain in dependency order; extracting the source vertex state, target vertex state, and edge state of each edge in the dependency chain from an input feature buffer.

[0012] This prefetching strategy leverages spatial locality to centrally load the features of the vertices in the chain into an on-chip prefetch buffer, reducing the randomness of off-chip accesses. The prefetched data format is standardized (including source / destination vertex IDs and states), eliminating the need for subsequent first active compute unit 223 or second active compute unit 233 to parse the data (e.g., reducing data preprocessing time by 20%).

[0013] According to a preferred embodiment, the method also includes a chain-aware data caching strategy for managing vertex states in the input feature buffer; when requesting the state of a vertex, if the input feature buffer is not full, the vertex state is directly cached; if the input feature buffer is full, the priority of the vertex is calculated and the resident vertex with the lowest priority is replaced.

[0014] The chain-aware data caching strategy of the present invention effectively reduces unnecessary off-chip communication by preferentially caching the states of commonly used dependency chains in on-chip memory, achieves better data locality, breaks through the performance bottleneck caused by excessive data transmission overhead, and further promotes the effective use of hardware accelerators.

[0015] According to a preferred embodiment, the priority of a vertex is calculated as follows: Among them, P G represents the number of dependency chains in the graph, P G (v) represents the number of dependency chains containing vertex v, D v Represents the degree of vertex v.

[0016] The chain-aware data caching strategy dynamically manages the input feature buffer by quantifying vertex priorities Pri(v). In e-commerce recommendation scenarios, the status of high-frequency trading products (high) and popular users (high) are cached first, with a priority of 6-8 times that of ordinary nodes.

[0017] According to a preferred embodiment, the step of the aggregation engine performing state aggregation includes: preloading adjacent vertex state information generated by previous calculation into an aggregation buffer, and executing an aggregation operator to generate an aggregation result.

[0018] The aggregation engine preloads adjacent vertex states, allowing it to execute calculations directly without waiting for data to load. The aggregation buffer uses a multi-body bank structure, supporting simultaneous loading of multiple adjacent vertex states (e.g., loading the states of vertices B and C in parallel), improving aggregation throughput.

[0019] According to a preferred embodiment, the step of the second application engine executing the edge computing task includes: fusing the source vertex, target vertex state and edge attribute data, generating edge information transmission features and sending them to the first application engine.

[0020] The second application engine performs edge computations separately from vertex aggregation, making it suitable for scenarios where the number of edges far outnumbers the number of vertices (e.g., recommendation systems). The second application buffer stores edge state (e.g., weight coefficients) to avoid competing with vertex state for storage bandwidth.

[0021] According to a preferred embodiment, the steps of the operation task of the first application engine include: calculating the update state of the target vertex based on matrix-vector multiplication and nonlinear transformation; and sending the update state of the target vertex to the output buffer and the input feature buffer.

[0022] The fusion calculation of the first application engine takes into account the aggregation characteristics of adjacent vertices and edge transfer characteristics while ensuring the vertex status, avoiding the deviation caused by a single data source.

[0023] The present invention provides a high-energy-efficiency dynamic graph neural network hardware accelerator from a second aspect. The hardware accelerator includes a chain-driven traversal unit, a chain-driven processing unit, and an on-chip buffer. The chain-driven traversal unit is used to track the dependency chain of active vertices based on a dynamic dependency chain generation algorithm, and store the active vertices in a chain FIFO buffer in the order of the dependencies between the active vertices, so that the processing order is consistent with the data propagation path; and the source vertex, target vertex, dependency chain between the target vertex and its adjacent vertices, and graph data features related to the dependency chain pre-extracted from the chain FIFO buffer in the order of the dependencies, are stored in a prefetch buffer; the chain-driven processing unit is used to dispatch the source vertex and / or target vertex in the prefetch buffer to an aggregation engine, dispatch the source vertex state and edge state to a second application engine, realize parallel execution of aggregation and edge calculation, and pass the parallel execution results to the first application engine to generate the final state of the target vertex; the on-chip buffer includes a chain FIFO buffer, a prefetch buffer, and an input feature buffer, and the input feature buffer manages the vertex state through a chain-aware data caching strategy.

[0024] The present invention accelerates dynamic graph processing through a high-energy-efficiency dynamic graph neural network, and the technical effects are as follows: the hardware accelerator uses a chain FIFO buffer to dynamically maintain the dependency topology chain of active vertices, and performs sequentially aware pipelined preloading of vertex features on the dependency chain through a prefetch buffer, thereby achieving strict alignment of data access paths and processing orders, and effectively reducing redundant data memory access overhead; the parallel computing path of the aggregation engine and the second application engine is designed to form a pipelined processing link for vertex state aggregation, edge calculation, and final state generation, greatly improving data throughput efficiency; combined with the chain-aware data caching strategy of the input feature buffer, the propagation rate of vertex states along the dependency chain is accelerated, significantly reducing on-chip storage access energy consumption while ensuring calculation accuracy. The overall architecture achieves the coordinated optimization of computing resource utilization and storage access efficiency through a dependency-driven chain processing mechanism, and can achieve a 2.1-fold improvement in energy efficiency compared to traditional dynamic graph processing architectures.

[0025] According to a preferred embodiment, a chain-aware data caching strategy includes: when requesting vertex state, if the input feature buffer is not full, directly caching the vertex state; if the input feature buffer is full, calculating the vertex priority and replacing the resident vertex with the lowest priority. This chain-aware data caching strategy of the present invention effectively reduces unnecessary off-chip communication by prioritizing caching states on commonly used dependency chains in on-chip memory, achieving better data locality, overcoming performance bottlenecks caused by excessive data transmission overhead, and further promoting the effective utilization of hardware accelerators. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1This is a schematic diagram of the reasoning logic of the high-energy-efficiency dynamic graph neural network acceleration method provided by the present invention;

[0027] Figure 2 This is a schematic diagram of graph data and two dependency chains provided by the present invention;

[0028] Figure 3 This is a schematic diagram of the architecture of the high-energy-efficiency dynamic graph neural network hardware accelerator provided by the present invention;

[0029] Figure 4 1 is a flow chart of an embodiment of a high-energy-efficiency dynamic graph neural network acceleration method provided by the present invention;

[0030] Figure 5 It is a micro-architecture schematic diagram of the chain-driven traversal unit and the chain-driven processing unit provided by the present invention.

[0031] Reference Signs List

[0032] 1 00: Chain-driven traversal unit; 110: Tracking unit; 1 20: Prefetch unit; 1 21: Prefetch buffer; 130: Scheduling unit; 200: Chain-driven processing unit; 210: Aggregation engine; 211: Aggregation buffer; 220: First application engine; 221: First application buffer; 222: First application scheduler; 223: First active computation unit; 230: Second application engine; 231: Second application buffer; 232: Second application scheduler; 233: Second active computation unit; 250: Switch; 300: On-chip buffer; 310: Input feature buffer; 320: Graph structure buffer; 330: Chain FIFO buffer; 340: Intermediate queue buffer; 350: Weight matrix buffer; 360: Active bit vector buffer; 400: Control unit; 500: High bandwidth memory; 510: Output buffer. DETAILED DESCRIPTION

[0033] The following is a detailed description with reference to the accompanying drawings.

[0034] This invention explains some noun terms.

[0035] Chain perception: During dynamic graph neural network inference, the system dynamically tracks the dependency chains between graph vertices and optimizes data access and processing order based on these dependencies. In this design, the dependency chain serves as the core driver for vertex state updates. The system sequentially accesses and processes graph data according to the dependency chain, ensuring that each vertex's state update is based on the latest state of its neighboring vertices.

[0036] Active Vertex: In dynamic graph neural network inference, a vertex that needs to perform computation, propagate state, or receive updates. These vertices form the core processing unit of the dependency chain, driving the state update and propagation process.

[0037] Depth-first traversal: A graph traversal strategy that starts from a specified starting vertex (root vertex) and deeply explores along a single path until the end or there are no unvisited adjacent vertices. It then backtracks and continues traversing other paths until the traversal completion condition is met (all vertices are visited or a preset threshold is reached).

[0038] Dependency chain: The dependency path of vertex state updates in dynamic graph neural networks is composed of topological connection paths in the graph, and its vertex sequence strictly defines the temporal dependency of state propagation.

[0039] Edge Array: This is the fundamental data container for graph structures, storing the source and target vertex indices of all edges in an ordered list. Each edge is directly associated with a specific source and target vertex through its storage location, and an index map is used to provide a list of adjacent vertices for each vertex, enabling efficient adjacent edge retrieval.

[0040] Offset array: An index structure that works in conjunction with the edge array. By storing the start and end position indices (start_offset and end_offset) of each vertex's adjacent edge in the edge array, it enables fast location of vertex adjacent edges. This design leverages the principle of spatial locality, avoids the overhead of full graph traversal, and reduces the complexity of adjacency queries to O(1).

[0041] Adjacent Vertex Array: This array structure stores the connectivity relationships between adjacent vertices, using a storage format compatible with graph sparse representations. Each vertex's adjacent vertices are arranged in a pre-set order, allowing for quick access to all adjacent vertices and their associated edges for a target vertex.

[0042] Adjacent vertices: Vertices directly connected to the current vertex via edges. In graph neural networks, the state vectors of adjacent vertices will participate in the state update calculation of the current vertex, and the accuracy of their selection directly affects the effectiveness of the inference results.

[0043] Source Vertex ID: A unique identifier for the currently processed vertex. When a vertex is extracted from the chain FIFO buffer 330, its ID will be used as the source vertex ID to trigger the loading of adjacent edge data and state calculation for the vertex.

[0044] Target Vertex ID: A unique identifier for a vertex that is adjacent to the source vertex. During the dependency chain generation phase, the target vertex ID is used to identify the recipient of the state update propagation and constitutes the sequence of subsequent vertices in the dependency chain.

[0045] Vertex state: A data set that represents vertex features, including raw attribute data or multidimensional feature vectors transformed by a neural network. It serves as the core input parameter for message passing and state updates during the computation process.

[0046] Edge state: Feature data describing edge properties, including weight coefficients, type labels, and custom feature vectors. It participates in the information transfer calculation process between source and target vertices in graph neural networks.

[0047] Chain-driven: A mechanism that dynamically schedules computational tasks based on dependency chains. By tracking the dependency chain order of active vertices, it enforces state updates in topological dependency order, reducing redundant computation and invalid data access.

[0048] Aggregation engine 210 : a computing unit that performs aggregation of adjacent vertex states, supports aggregation operators such as sum, mean, and maximum, and outputs the aggregation results to the second application engine 230 .

[0049] The first application engine 220 is a computing unit dedicated to vertex state update, which generates a new state vector of the target vertex through matrix-vector multiplication and activation function transformation.

[0050] The second application engine 230 is a dedicated unit for processing edge-related calculations, fusing source vertex and target vertex states and edge attribute data, generating edge information transfer features and inputting them into the first application engine 220 .

[0051] Example 1

[0052] Current dynamic graph neural network (DGNN) systems and dedicated hardware accelerators face dual challenges in performance optimization. The core contradiction stems from the conflict between the dynamic computing paradigm and the inherent characteristics of graph data.

[0053] First, the dynamic state propagation mechanism triggers large-scale redundant computations. During the DGNN iteration process, multiple computing cores process active vertices in parallel. These vertices dynamically propagate their states to neighboring vertices through dynamic dependency chains. However, due to the lack of global synchronization and coordination between cores, the time windows for vertex updates vary significantly. After a vertex completes its state update, its neighboring vertices may still be performing computations based on the vertex's old state, causing the calculation results to deviate from the actual latest state. This "outdated state dependency" not only results in approximately 60% invalid update operations in a single iteration but also causes the cascading spread of incorrect states among multi-hop adjacent vertices. Experiments show that this type of redundant computation causes the system to waste 58%-72% of computing resources and incurs 22%-35% additional off-chip communication overhead.

[0054] Secondly, the high-dimensional nature of vertex state leads to a serious memory wall problem. The state of a single vertex in modern graph neural networks typically consists of hundreds to thousands of floating-point features, requiring storage that far exceeds the on-chip cache capacity, forcing the system to store most of the state data in off-chip DRAM. This design faces a fundamental contradiction in access patterns: the dynamic generation of dependency chains makes the vertex processing order highly irregular, while the physical characteristics of off-chip memory require continuous access to achieve ideal bandwidth. For example, when the system processes vertices A→D→B→C in the dependency chain order, the physical addresses of these vertices in DRAM may be distributed across non-contiguous banks, causing frequent bank conflicts and cache line thrashing. Actual data shows that this irregular access results in memory bandwidth utilization of less than 30%, while off-chip data movement consumes 64%-79% of the total system energy consumption.

[0055] The coupled effect of these two bottlenecks results in significant deficiencies in computational efficiency and energy efficiency in existing systems: redundant computations amplify unnecessary off-chip access requirements, while irregular storage accesses exacerbate idle computing resources. Benchmark tests show that these issues collectively cause the overall system energy efficiency to drop by approximately 3.8 times compared to the theoretical optimal value, becoming a key obstacle to the practical deployment of DGNNs in resource-constrained scenarios, such as edge computing devices.

[0056] To address the shortcomings of the prior art, this embodiment provides a high-energy-efficiency dynamic graph neural network acceleration method and hardware accelerator. The present invention may also provide a high-energy-efficiency dynamic graph neural network acceleration method and system. The present invention may also provide an electronic device equipped with the hardware accelerator of the present invention. The present invention may also provide a processor for executing the high-energy-efficiency dynamic graph neural network acceleration method of the present invention.

[0057] like Figure 3 As shown, the hardware accelerator includes a chain-driven traveler unit 100 (CDTU), a chain-driven processing unit 200 (CDPU), and an on-chip buffer 300. Preferably, the hardware accelerator is further configured with a control unit 400. Preferably, the hardware accelerator is also connected to a high-bandwidth memory 500 to form an output buffer 510.

[0058] The chain-driven traversal unit 100 can be implemented in hardware using a dedicated state machine (ASIC) or programmable logic (FPGA), with a built-in graph structure parsing engine responsible for dynamically generating dependency chains. For example, the chain-driven traversal unit 100 connects to the on-chip buffer 300 via a 512-bit wide AXI4-Stream bus, reading vertex offsets and adjacency table data in real time. The generated dependency sequence (including vertex IDs and timestamps) is written to the chain FIFO buffer 330 via a dynamic bit-width bridge.

[0059] The chain drive processing unit 200 adopts a multi-core vector processor array design, including an aggregation engine 210 (MAC array) and two application engines (vector ALU). Figure 3 As shown, the aggregation engine 210 is physically connected to the first application engine 220, and the first application engine 220 is physically connected to the second application engine 230. The aggregation engine 210 internally includes an aggregation buffer 211 and an aggregation scheduler. The first application engine 220 is provided with a first application buffer 221, a first application scheduler 222, and a first active calculation unit 223.

[0060] Preferably, the first application buffer 221 is used to store input data. The input data of the first application buffer 221 includes source vertex state, target vertex state, and edge state. The first application scheduler 222 is used to read data from the first application buffer 221 and assign tasks to the first active computing unit 223. The first active computing unit 223 inputs the calculation results into the first application buffer 221. The first application buffer 221 also transmits the calculation results to the aggregation engine 210, the second application engine 230, or the high bandwidth memory 500, completing data exchange.

[0061] Second application engine 230 includes a second application buffer 231, a second application scheduler 232, and a second active computation unit 233. A switch 250 is provided between first application engine 220 and second application engine 230. Second application buffer 231 stores the state of source vertices and edges for use by second application engine 230 when performing edge computations and vertex updates.

[0062] The second application buffer 231 receives and stores input data. The input data to the second application buffer 231 includes the initial state of the target vertex, aggregation results, and edge calculation results. The second application scheduler 232 reads the data in the second application buffer 231 and assigns tasks to the second active computing unit 233. The second active computing unit 233 calculates the final state of the target vertex and stores the result in the second application buffer 231. The second application buffer 231 transmits the calculation result to the first application engine 220 for storage in the high bandwidth memory 500 or later, completing the vertex update.

[0063] Preferably, the switch 250 is used to merge the first application engine 220 and the second application engine 230 into a single larger application engine.

[0064] The switch 250 realizes the merger of the first application engine 220 and the second application engine 230 by dynamically adjusting the data path, sharing computing resources and unifying task scheduling. In the merge mode, when the computing task is biased towards vertex update or does not require explicit edge calculation, the switch 250 reconfigures the data flow so that the first application buffer 221 and the second application buffer 231 share data storage, and allows the first active computing unit 223 to cooperate with the second active computing unit 233 to perform vertex calculations, thereby improving computing resource utilization and computing throughput. At the same time, the switch 250 allows the two application schedulers to work together to dynamically allocate computing tasks and ensure balanced computing load. Through the unified management of task scheduling by the switch 250, the switch 250 ensures that computing resources are fully utilized and avoids some of the first active computing units 223 or the second active computing units 233 from being idle. This mechanism ensures that when computing tasks change dynamically, computing throughput can be optimized, computing bottlenecks can be reduced, and the overall performance of dynamic graph neural network reasoning can be improved.

[0065] That is, for the DGNN variant without edge operations, the chain-driven processing unit 200 merges the first application engine 220 and the second application engine 230 into a single larger application engine through the control unit 400 and a dedicated hardware, namely the switch 250. This merger efficiently performs vertex operations, optimizes hardware resource utilization, and improves the efficiency of the first active computing unit 223 and the second active computing unit 233.

[0066] The chain-driven processing unit 200 interacts with the chain-driven FIFO buffer 330 through a duplex crossbar network, supports 8-way concurrent access to pre-fetch vertex features and edge weight data, and establishes a crossbar connection with the input feature buffer 310 (SRAM implementation) of the multi-body bank architecture to achieve fast loading and updating of 32-bit floating-point vector states.

[0067] Preferably, the control unit 400 adopts an independent microcontroller (MCU), which is interconnected with each chain-driven traversal unit 100 and the chain-driven processing unit 200 through a layered AMBA AXI bus to perform priority scheduling, DMA transmission and power domain management. Experiments have shown that it can improve task scheduling efficiency by 37% and reduce Crossbar network conflicts.

[0068] The control unit 400 is responsible for global task management, computing resource allocation, data flow control, and synchronization management. The control unit 400 coordinates the computing tasks of the first application engine 220, the second application engine 230, the aggregation engine 210, and the scheduling unit 130 to ensure efficient execution of the dynamic pipeline. The control unit 400 dynamically allocates computing resources, combines the switch 250 to optimize the merger of the first active computing unit 223 and the second active computing unit 233, and manages data in the input feature buffer 310 to improve memory access efficiency. The control unit 400 is also responsible for synchronizing computing tasks, avoiding data conflicts, and handling exceptions to ensure the stability and efficiency of dynamic graph neural network reasoning.

[0069] In terms of back-end storage expansion, the hardware accelerator is physically connected to the High Bandwidth Memory 500 (HBM) through a silicon interposer, using a 2.4Gbps / pin interface protocol that complies with the JEDEC HBM PHY standard. The design utilizes 2.5D integration technology to integrate the processing unit with the HBM stack at a 55μm bump pitch, achieving an interconnect density of 10,000 traces / mm. 2 Source Synchronous Clocking (SSC) is used to compensate for timing deviations, keeping clock jitter within ±15ps. High-Bandwidth Memory 500 (HBM), serving as the output buffer 510, offers 32GB of capacity (a 256x increase compared to a purely on-chip solution) and supports burst transfer mode to write back vertex states. Its interconnect bandwidth of ≥400GB / s and the processing unit's 32TOPS peak computational power create a 1:4 memory-to-computation ratio, effectively preventing data starvation.

[0070] The physical implementation utilizes a domain-specific energy efficiency optimization strategy: the chained FIFO buffer 330 operates at 0.9V and 800MHz, while the processing unit core operates at 1.2V / 1.5GHz, both independently controlled through dynamic voltage frequency scaling (DVFS). This architecture, through deep collaboration between silicon interposer interconnect and HBM, can meet the single-card inference requirements of million-vertex graphs while simultaneously increasing effective memory bandwidth utilization to over 78%.

[0071] The on-chip buffer 300 serves as the core storage component of the hardware accelerator. Its physical hardware can be static random access memory (SRAM) or a register file. The SRAM is constructed using six-transistor (6T) memory cells. A sense amplifier array enables high-precision detection of tiny voltage signals (approximately 200mV). Combined with a multi-bank architecture, the storage space is divided into 64 independent operation units, supporting fine-grained parallel access (such as simultaneous reading and writing of data from different banks). The register file uses fully custom routing to achieve a wide port configuration (for example, 32 read / 16 write ports), providing fast data access in extremely low latency scenarios (<1ns). Timing control circuitry, including a precharge clock tree and read / write timing generators, is integrated into the physical design to ensure sub-nanosecond timing margins. Voltage domain partitioning (1.0V power supply for the active area and 0.6V power supply for the sleep area) reduces static power consumption by over 40%.

[0072] In terms of connection architecture, the on-chip buffer 300 can be interconnected with the chain drive processing unit 200 through a 1,024-bit wide unidirectional bus (write direction) and a 512-bit wide bidirectional bus (read direction), using a source synchronous clock (SSC) to compensate for signal transmission delay differences, and the clock jitter is controlled within ±1.5 ps.

[0073] Preferably, in order to efficiently access data such as input features, graph structures, intermediate queues, weight matrices, and active bit vectors, the on-chip buffer 300 is set and divided into 6 areas: input feature buffer 310, graph structure buffer 320, chain FIFO buffer 330, intermediate queue buffer 340, weight matrix buffer 350, and active bit vector buffer 360.

[0074] Preferably, different buffer areas of the on-chip buffer 300, such as the chained FIFO buffer 330, can be implemented using independent memory banks. For example, the input feature buffer 310 can be constructed using multi-port SRAM, while the weight matrix buffer 350 can use a higher-density TCAM (Ternary Content-Addressable Memory). The memory cells in different areas are physically isolated in the layout, and dedicated data paths are implemented through metal layer routing.

[0075] For example, the chained FIFO buffer 330 includes a built-in ring pointer register and state machine circuitry to implement hardware-level first-in, first-out control logic (such as read / write pointer increment and full / empty flag generation). The active bit vector buffer 360 utilizes a configurable CAM (Content-Addressable Memory) structure and integrates parallel matching circuitry (such as a 64-bit XOR comparator array). The intermediate queue buffer 340 utilizes a row buffer acceleration circuit to support data prefetching in burst transfer mode.

[0076] The input feature buffer 310 is a memory area used to store the feature data of the vertices and edges in the graph. It saves information such as the state of each vertex and the state of the edge. These feature data will be read and used during the inference process.

[0077] The graph structure buffer 320 is a memory area that stores graph structured data. It typically includes vertex and edge information, such as vertex degrees, adjacency relationships, and edge weights. In the hardware accelerator, the graph structure buffer 320 stores a sparse representation of the graph, such as offset arrays and edge arrays, to provide data support for subsequent computations.

[0078] The chain FIFO buffer 330 is a chain FIFO buffer, which is a buffer for storing vertex information in a dependency chain. It follows a first-in-first-out order to ensure that the vertices in the dependency chain are processed in the correct order.

[0079] The intermediate queue buffer 340 is a cache area used to store pending vertices during graph neural network inference. It temporarily stores vertices that have not yet been fully processed, ensuring the sequential execution of computation tasks. Once a vertex's state is updated, it may be moved to the intermediate queue buffer 340 to await further computation or updates.

[0080] The weight matrix buffer 350 is used to store the weight parameters required for edge calculation, vertex calculation, and aggregation calculation, and exchanges data with the first application engine 220, the second application engine 230, and the aggregation engine 210 through the control unit 400. The weight matrix buffer 350 reads weight data from the high bandwidth memory 500 and provides weight support to the first application engine 220, the second application engine 230, and the aggregation engine 210 during the calculation process to ensure efficient execution of matrix calculations. Ultimately, the first application engine 220, the second application engine 230, and the aggregation engine 210 use these weights to calculate the new state and store the results in the first application buffer 221, the second application buffer 231, or the return storage system.

[0081] Active bit vector buffer 360 is used to store the "active" status of each vertex. Each vertex corresponds to an active bit, indicating whether the vertex is in the active state, that is, whether it needs to participate in the state update of the current iteration. If a vertex is in the active state, it means that its state needs to be updated, and its adjacent vertices may be affected.

[0082] Each buffer establishes a dedicated physical connection with the corresponding processing unit. Specifically, the input feature buffer 310 is connected to the aggregation engine 210 (MAC array) via a 512-bit wide H-Tree bus, and the wiring delay is balanced and controlled at ±5ps. The graph structure buffer 320 is directly connected to the chain-driven traversal unit 100 using through-silicon vias (TSVs) to realize a vertical transmission channel under the 3D stacking architecture. The weight matrix buffer 350 is interconnected with the vector ALUs of the two application engines via a bidirectional crossbar, supporting 8 concurrent access ports.

[0083] Preferably, the chain FIFO buffer 330 is directly connected to the chain-driven traversal unit 100 to store active vertices on the dependency chain and provide data to the prefetch unit 120 in sequence to support the acquisition of adjacent vertices and the generation of dependency chains. The intermediate queue buffer 340 is connected to the tracking unit 110 as a temporary storage unit for active vertices, and is used to cache vertices to be processed and provide data to the chain FIFO buffer 330 to ensure access in the order of the dependency chain. The weight matrix buffer 350 is interconnected to the first application engine 220 and the second application engine 230 via a bidirectional crossbar, providing weight data to the vector ALU to support the matrix operations required for edge calculation and vertex calculation. The active bit vector buffer 360 interacts directly with the tracking unit 110 to record the active state of the vertices in the graph, and cooperates with the chain-driven traversal unit 100 to update the state mark of the active vertex in the adjacent vertex selection phase to ensure state consistency and correct task scheduling during the calculation process.

[0084] The prefetch buffer 121 is a memory area that stores prefetched data and is used to temporarily save the state of each vertex and edge in the dependency chain. Each entry is stored in a specified format for fast access and subsequent processing, thereby reducing latency during the computation process.

[0085] Aggregation buffer 211 is a cache area for storing data required by aggregation engine 210. It saves the state information of source and target vertices, as well as the adjacency data related thereto, and provides necessary data support for subsequent aggregation calculations.

[0086] The application buffer is a memory area used to store data required for application engine calculations.

[0087] like Figure 3As shown, the chain drive traversal unit 100 includes a tracking unit 110 , a prefetch unit 120 and a scheduling unit 130 that perform data connection in sequence.

[0088] Preferably, the principle of the high energy efficiency dynamic graph neural network acceleration method performed by the hardware accelerator is as follows, and Figure 1 and Figure 5 shown.

[0089] S100: Taking the unvisited active vertex as the root vertex, the tracking unit 110 dynamically tracks the original dependency chain based on a dynamic dependency chain generation algorithm until all active vertices are visited. Preferably, the dynamic dependency chain generation algorithm can be a depth-first traversal algorithm.

[0090] The tracking unit 110 implements this process with four pipeline sub-steps, including four stages: obtaining vertices, obtaining head and tail offsets, obtaining adjacent vertices, and selecting adjacent vertices. Figure 5 shown.

[0091] Preferably, the steps of the dynamic dependency chain generation algorithm include:

[0092] S110 : The tracking unit 110 obtains vertices from the active bit vector buffer 360 or the intermediate queue buffer 340 .

[0093] S 11 1: During the vertex fetching phase, the tracking unit 110 first checks the intermediate queue buffer 340. If the intermediate queue buffer 340 is empty, the tracking unit 110 scans the active bit vector buffer 360 to find an active vertex.

[0094] S112: The tracking unit 110 immediately changes the flag of the vertex in the active bit vector buffer 360 to inactive to ensure the consistency of the vertex state. Then, the vertex is input into the chain FIFO buffer 330 for subsequent operations.

[0095] S 11 3: If the intermediate queue buffer 340 is not empty, the tracking unit 110 takes an active vertex from the intermediate queue buffer 340 and then performs step S111 to ensure that the correct order and dependency of the vertices are maintained.

[0096] S 1 20: Get the start and end offsets of the active vertices from the vertex array in the graph structure buffer 320 .

[0097] In the stage of obtaining the head and tail offsets, the tracking unit 110 first reads the offset information of each active vertex from the graph structure buffer 320. These offset information stores the connection relationship between each vertex and the adjacent vertices, including the position of all adjacent edges of the vertex in the edge array. The tracking unit 110 determines the first and last offsets (i.e., head and tail offsets) of each active vertex by searching the offset array. The head and tail offsets define the starting and ending positions of the adjacent edges of the vertex in the edge array. Using the head and tail offsets, the system can accurately and quickly access and process the adjacent edge data related to the current vertex, thereby accelerating the traversal and calculation process of the graph.

[0098] S130 : Obtain unvisited adjacent vertices of the active vertex from the adjacent vertex array of the graph structure buffer 320 , and send the adjacent vertices to the intermediate queue buffer 340 and the chain FIFO buffer 330 .

[0099] S 1 31 : In the adjacent vertex acquisition stage, the tracking unit 110 acquires adjacent vertices that are adjacent to the current active vertex and have not been visited yet from the adjacent vertex array in the graph structure buffer 320 .

[0100] S1 32: The tracking unit 110 sends these unvisited vertices to the intermediate queue buffer 340 and the chain FIFO buffer 330 for further processing. This ensures that all adjacent vertices that need to be updated are correctly stored and accessed and calculated in the order of the dependency chain.

[0101] S140: Update the adjacent vertices marked as active in the active bit vector buffer 360 to adjacent vertices in inactive state, so as to perform adjacent vertex selection.

[0102] The tracking unit 110 checks whether the adjacent vertices obtained during the Get Adjacent Vertices phase are marked as active in the active bit vector buffer 360. If these adjacent vertices are currently active, the tracking unit 110 immediately changes their flags in the active bit vector buffer 360 to inactive to ensure the consistency and correctness of the vertex state. This process helps avoid duplicate processing and state updates, ensuring that only vertices that need to be updated continue to participate in subsequent calculations.

[0103] By repeatedly executing the above four phases until all active vertices have been visited, tracking unit 110 ensures that the states of each active vertex and its adjacent vertices are updated in the correct order. The vertex access sequence in chained FIFO buffer 330 approximately reflects the dependency chain between vertex states. The core function of this process is to avoid unnecessary redundant computations by tracking and managing vertex state dependencies, while optimizing computation order and memory access, ensuring the efficiency and accuracy of the graph neural network inference process.

[0104] S200: storing active vertices in the chain FIFO buffer 330 in the order of dependencies between the active vertices, so that the processing order is consistent with the data propagation path.

[0105] In order to effectively pre-fetch the graph data on the dependency chain, the pre-fetch unit 120 operates using three pipeline sub-steps. The three stages are: extracting source vertices, generating dependency chains, and extracting features, such as Figure 5 shown.

[0106] S300: The prefetch unit 120 pre-extracts the source vertex, the target vertex, and the dependency chain between the target vertex and its adjacent vertices from the chained FIFO buffer 330 in dependency order. The prefetch unit 120 extracts graph data features related to the dependency chain. The prefetch unit 120 stores the source vertex, target vertex, dependency chain, and graph data features in the prefetch buffer 121. Through this pipeline approach, the prefetch unit 120 can efficiently manage and load graph data, reducing data latency during the computation process and thereby improving overall inference efficiency.

[0107] S310: The pre-fetch unit 120 extracts source vertices.

[0108] Source vertices are fetched from the chained FIFO buffer 330 in dependency order.

[0109] The prefetch unit 120 sequentially retrieves a vertex from the chained FIFO buffer 330, which is the source vertex. The data of the source vertex is the source vertex ID. In this way, the prefetch unit 120 can process active vertices in the graph one by one and, based on the dependencies between these vertices, generate the adjacent vertices and their associated data that need to be accessed later. By sequentially extracting vertices from the chained FIFO buffer 330, the prefetch unit 120 ensures that the order of the dependency chain is maintained, thereby efficiently preloading graph data.

[0110] S320: The pre-fetch unit 120 generates a dependency chain.

[0111] The pre-fetch unit 120 searches for an edge array associated with a source vertex, extracts all adjacent vertices of the source vertex, and forms a dependency chain in a dependency order.

[0112] In the dependency chain generation stage, the pre-fetch unit 120 obtains the information of the adjacent vertices of the current source vertex (ie, the target vertex ID) from the edge array stored in the graph structure buffer 320 to generate the dependency chain.

[0113] Specifically, prefetch unit 120 searches the edge array associated with a source vertex, extracts the IDs of all adjacent vertices to that source vertex, and forms a dependency chain in the order of dependencies. This dependency chain represents the sequence of state updates between the source vertex and its adjacent vertices, providing data support for subsequent feature extraction and computation. By generating a dependency chain, prefetch unit 120 can efficiently track and process dependencies between vertices, ensuring that the order in which graph data is preloaded meets computational requirements.

[0114] S330: The pre-fetch unit 120 extracts features.

[0115] The source vertex state, target vertex state, and edge state of each edge in the dependency chain are extracted from the input feature buffer 310 .

[0116] In the feature extraction stage, the pre-fetch unit 120 obtains the source vertex state, target vertex state, and edge state of each edge in the dependency chain from the input feature buffer 310 .

[0117] S340 : By searching for features of vertices and edges related to each edge, the pre-fetch unit 120 extracts the information and stores it in the pre-fetch buffer 121 .

[0118] Specifically, each prefetched entry is stored in the prefetch buffer 121 in the form of <source vertex ID, target vertex ID, source vertex state, target vertex state, edge state>. This data storage method ensures that in subsequent calculations, related vertex and edge features can be quickly accessed and used for calculation, thereby improving data access efficiency and computing performance.

[0119] In order to further reduce unnecessary off-chip communication, since off-chip communication of vertex states dominates the overall performance of DGNN inference, the present invention designs a chain-aware data caching strategy (CADC).

[0120] The input feature buffer 310 manages vertex states in the input feature buffer 310 based on a chain-aware data caching strategy.

[0121] When requesting the state of a vertex, ie, when the prefetch unit 120 requests the state of a vertex from the high bandwidth memory 500 , the current state of the input feature buffer 310 is first checked based on the chain-aware data caching strategy.

[0122] If the number of data entries in the current buffer has not reached the maximum capacity of the buffer, that is, if the input feature buffer 310 is not full, the input feature buffer 310 directly caches the vertex state.

[0123] If the input feature buffer 310 is full, the priority of the vertices is calculated based on the chain-aware data caching strategy and the lowest priority resident vertex in the input feature buffer 310 is replaced.

[0124] Specifically, after the priority of vertex v is calculated, the priority is compared with the priorities of the resident vertices currently residing in the input feature buffer 310 based on the chain-aware data caching strategy. If the priority Pri(v) of vertex v is greater than the priority Pri(v) of the smallest resident vertex, the resident vertex will be replaced with vertex v.

[0125] According to a preferred embodiment, the priority of a vertex is calculated as follows: Among them, P G represents the number of dependency chains in the graph, P G (v) represents the number of dependency chains containing vertex v, D v Represents the degree of vertex v.

[0126] The chain-aware data caching strategy of the present invention significantly reduces the need for off-chip storage access by storing the states of frequently accessed vertices in the graph in the on-chip buffer 300. Since high-degree vertices usually participate in more dependency chain propagations, their states are frequently updated during the reasoning process. The chain-aware data caching strategy implements on-chip caching for key vertices in the dependency chain, effectively reducing data transmission delays across storage levels and reducing communication bandwidth consumption. This design not only improves computing efficiency while ensuring reasoning accuracy, but also reduces system energy consumption, and exhibits significant performance advantages, especially when processing high-degree vertices and their complex dependency chains.

[0127] S400: Chain-driven dynamics processing.

[0128] The chain-driven processing unit 200 uses a dynamic pipeline to sequentially perform state aggregation, vertex operations, and edge operations for each vertex in the dependency chain, thereby updating the state of the vertex in the graph. This design allows the state update of each vertex to be performed in parallel without waiting for the update of other vertices, significantly improving the efficiency of the inference process. Through the chain-driven approach, the present invention can effectively reduce computational latency and fully utilize hardware resources, thereby achieving efficient dynamic graph neural network inference.

[0129] The chain-driven processing unit 200 implements a traditional systolic array architecture for multiply-accumulate computations, while the first active computation unit 223 manages the activation functions crucial for graph neural network inference. The aggregation scheduler of the aggregation engine 210 and the two application schedulers of the two application engines ensure smooth pipeline execution and distribute workloads to the aggregation engine 210 and the second application engine 230, respectively. They operate in a task-distributed aggregation mode similar to HyGCN to achieve workload balancing and task-level parallelism.

[0130] The dynamic processing steps of chain drive are described as follows.

[0131] S410: The scheduling unit 130 schedules the source vertex and the target vertex from the pre-fetch buffer 121 to the aggregation buffer 211 of the aggregation engine 210. This operation ensures that the aggregation engine 210 can obtain the state information of all adjacent vertices required for the current calculation, thereby performing effective state aggregation.

[0132] Preferably, when performing scheduling, the scheduling unit 130 reads data from the prefetch buffer 121 of the prefetch unit 120 and classifies the data based on the vertex role (source vertex or target vertex). Specifically, the scheduling unit 130 parses the vertex ID in the data packet and queries the active bit vector buffer 360 to confirm whether the vertex is in an active state.

[0133] Subsequently, the scheduling unit 130 stores the state of the source vertex and the state of the adjacent target vertex in the aggregation buffer 211 of the aggregation engine 210 according to the computational requirements of the vertex, ensuring that the aggregation engine 210 can efficiently perform the state aggregation operation. At the same time, the scheduling unit 130 dynamically adjusts the data transmission priority, giving priority to scheduling vertices in the critical path of the dependency chain, reducing the computational wait caused by data dependencies, and ultimately achieving efficient data flow control and task scheduling.

[0134] Specifically, when processing a target vertex, the scheduling unit 130 first extracts the target vertex's state from the prefetch buffer 121 and determines its scheduling priority based on its importance in the dependency chain. Subsequently, the scheduling unit 130 stores the target vertex's state in the aggregation buffer 211 of the aggregation engine 210 to perform state aggregation calculations and simultaneously transmits the relevant data to the second application engine 220 for edge calculations or vertex updates.

[0135] Preferably, the critical path refers to the sequence of vertices in the dependency chain that has the greatest impact on the execution order of computing tasks and the overall reasoning efficiency. In the dynamic graph neural network reasoning process, if the calculation of a vertex has not been completed, and the subsequent vertices it depends on need to wait for its results, the path where the vertex is located is considered to be the critical path. Preferably, after each vertex calculation is completed, the scheduling unit 130 re-evaluates the critical path. The process of the scheduling unit 130 determining the critical path includes: (1) the remaining calculation delay, that is, the sum of the estimated calculation time of the unfinished vertices in the calculation dependency chain; (2) the calculation of the data dependency depth, that is, the calculation of the longest path length from the template vertex to the final output node. If the product of the remaining calculation delay and the data dependency depth of a template vertex is the largest, the path where the target vertex is located is marked as the current critical path.

[0136] For target vertices on the critical path, the scheduling unit 130 prioritizes computing resources to ensure that their state updates are completed as quickly as possible, thereby reducing computational blockage and data dependency waits. After the computation is complete, the scheduling unit 130 stores the updated target vertex state in the second application buffer 230 or high-bandwidth memory 500 for subsequent inference processes, thereby optimizing the overall inference efficiency of the dynamic graph neural network.

[0137] Preferably, the scheduling unit 130 prioritizes vertices based on their importance in the dependency chain to optimize task scheduling and reduce computational latency caused by data dependencies. Critical path vertices have the highest scheduling priority because they directly impact the progress of subsequent computations and are therefore prioritized for scheduling to the aggregation buffer 211 for computation.

[0138] Normally active vertices are in the dependency chain but not on the current critical path. The computational progress of normal active vertices will affect some subsequent vertices, but their global impact on overall inference efficiency is lower than that of critical path vertices. The scheduling priority of normal active vertices is lower than that of critical path vertices. The conditions required for their scheduling include: (1) the computing resource utilization rate of the critical path vertex is lower than the threshold (e.g., <80%); (2) there are no higher priority tasks waiting to be executed to ensure the sequential execution of computing tasks.

[0139] A non-dependency chain active vertex is an active vertex that is not associated with any dependency chain. The computation results of a non-dependency chain active vertex only affect itself or a local subgraph and do not participate in the core data flow. The scheduling priority of a non-dependency chain active vertex is the lowest and is only scheduled when computing resources are sufficient to avoid affecting core tasks. The conditions required for scheduling a non-dependency chain active vertex include: (1) there are no critical path vertices or ordinary active vertices to be processed; (2) the computing resource idle rate is higher than the threshold (for example, >90%).

[0140] Through the above scheduling priority mechanism, the scheduling unit 130 can ensure the efficient execution of computing tasks and improve the overall performance of dynamic graph neural network reasoning. Preferably, in order to avoid pipeline congestion related to state aggregation operations, the present invention proposes a unique G-PE and A-PE design. Figure 3 As shown, each G-PE in aggregation engine 210 contains eight parallel aggregation modules. Each aggregation module is equipped with two input queues: the first input queue is used to store source vertex states, and the second input queue is used to store destination vertex states. Data is processed by adders and multiplexers, which determine whether to output the result directly or cache it as an intermediate value in the intermediate queue buffer 340.

[0141] Furthermore, the aggregation engine 210 employs feature-level parallelism to improve state aggregation efficiency. Each A-PE in the first application engine 220 and the second application engine 230 specializes in edge and vertex state update operations, including edge and vertex operations. It performs matrix-vector multiplication via a built-in matrix accumulation unit and supports nonlinear activation functions. When edge computation is not required, the two computation modules of the A-PE can be dynamically merged into a larger unit to optimize resource utilization.

[0142] According to a preferred embodiment, the step of performing state aggregation by the aggregation engine 210 includes: preloading adjacent vertex state information generated by previous calculation into the aggregation buffer 211, and executing an aggregation operator to generate an aggregation result.

[0143] S420: The scheduling unit 130 dispatches the source vertex state and its corresponding edge state to the second application buffer 231 of the second application engine 230, allowing the aggregation engine 210 and the second application engine 230 to perform state aggregation and edge computation tasks in parallel. This process provides the necessary data support for subsequent vertex operations (such as applying edge computation and state updates) and ensures smooth data flow between active computing units. Through the coordination of the scheduling unit 130, the entire graph neural network inference process can be executed efficiently.

[0144] According to a preferred embodiment, the step of the second application engine 230 executing the edge computing task includes: fusing the source vertex, target vertex states and edge attribute data, generating edge information transfer features and sending them to the first application engine 220 .

[0145] In the edge operation phase (edge computing task phase), the second application engine 230 calculates the state of each edge, typically using a neural network to transform the source vertex state, the target vertex state, and the attributes of the edge to generate a message.

[0146] The transformation formula is:

[0147]

[0148] Among them, f e represents the transformation function of the edge operation, and Represents the state of the source vertex and the target vertex respectively, Attr e Represents edge attributes. The goal of this stage is to combine vertex states with edge attributes to provide a basis for state propagation and aggregation.

[0149] In the state aggregation phase (fusion of source vertices), the aggregation engine 210 collects messages generated by edge operations from adjacent vertices, combines them, and uses them for state updates of target vertices.

[0150] Aggregation operations typically use simple mathematical operations such as sum, mean, or maximum:

[0151] Agg v =Aggregate({Message e |e∈N(v)}).

[0152] Among them, Agg v represents the aggregation result of the target vertex v, and N(v) is the set of neighbors of vertex v. This stage reduces the state dimension of adjacent vertices and provides a compact representation for the state update of the target vertex.

[0153] S430: dispatching the aggregation result of the aggregation engine 210 and the edge calculation result of the second application engine 230 to the first application engine 220 for fusion calculation, and outputting the final state of the target vertex.

[0154] According to a preferred embodiment, the steps of the operation task of the first application engine 220 include: calculating the update state of the target vertex based on matrix-vector multiplication and nonlinear transformation.

[0155] In the vertex operation phase, the target vertex generates a new state using its current state and the result obtained in the state aggregation phase.

[0156] Preferably, the formula completed by the first application engine 220 based on the neural network transformation is:

[0157]

[0158] Among them, f v Transformation functions representing vertex operations, Indicates the current state of the vertex, Agg v Represents the aggregation result of the target vertex v. The goal of the vertex operation is to combine the vertex history state and the neighbor history state to generate an updated vertex state.

[0159] With the support of dynamic pipelining, vertex state updates, adjacent vertex state aggregation, and edge operations can be performed simultaneously, maximizing parallelism and effectively improving computational efficiency. This dynamic processing reduces the waiting time for data transmission and computation, significantly improving the speed of the inference process.

[0160] S500 : The first application engine 220 sends the updated state of the target vertex to the output buffer 510 and the input feature buffer 310 .

[0161] In this way, the first application engine 220 is responsible for integrating the intermediate results of previous calculations and outputting the final state of each target vertex, ensuring the correctness and efficiency of the graph neural network reasoning process.

[0162] like Figure 1 As shown, the graph on the left includes vertices v0, v1, v2, and v3, and three edges between them. Edge A represents the edge from vertex v3 to vertex v2. Performing an edge operation on edge A generates message A. Edge B represents the edge from vertex v1 to vertex v0. Performing an edge operation on edge B generates message B. Edge C represents the edge from vertex v2 to vertex v0.

[0163] The tracking unit 110 accesses all active vertices and obtains the current state information of vertices v0, v1, v2, and v3 and the three edges between the vertices. The prefetch unit 120 pre-extracts the source vertex, the target vertex, and the dependency chain between the target vertex and its adjacent vertices in the order of dependency. That is, the prefetch unit 120 reads the current state information of vertex v3, generates message A, and transmits the current state information of vertex v3 to the target vertex v2 through edge A. The prefetch unit 120 reads the current state information of vertex v1, generates message B, and transmits the current state information of vertex v0 to the target vertex v0 through edge B. The prefetch unit 120 does not perform edge operations on edge C.

[0164] The scheduling unit 130 dispatches the information of the target vertex v0 and the target vertex v2 to the second application buffer 231 of the second application engine 230. The aggregation engine 210 performs a state aggregation operation on the target vertex v0 and the target vertex v2. The aggregation engine 210 performs a calculation based on the message A and the old state of the target vertex v2 to generate a new state for the target vertex v2. The aggregation engine 210 performs a calculation based on the message B and the old state of the target vertex v0 to generate a new state for the target vertex v2.

[0165] Second application engine 220 integrates a neural network model. During vertex and edge operations, it receives aggregated messages (e.g., message A or message B) or vertex states and generates new vertex states (e.g., the new state of target vertex v2) or new messages through the aforementioned vertex operation calculation process. Preferably, vertex operations are performed by a built-in neural network based on transformation functions.

[0166] As mentioned above, the processing path of vertex information is:

[0167] Edge A: Vertex v3 → Message A → Vertex v2 → State Aggregation → Vertex Operation → New State of Vertex v2.

[0168] Edge B: Vertex v1 → Message B → Vertex v0 → State Aggregation → Vertex Operation → New State of Vertex v0.

[0169] The present invention has the following advantages:

[0170] First, the convergence speed of iterative graph processing is fast: the present invention realizes normalized data access through chain perception, dynamically tracks the dependency chain between active vertices, and continuously processes them in the order of each active vertex on the chain, avoiding many redundant data accesses and processing related to vertex state updates, so that the graph vertex state can be efficiently propagated along the dependency chain, thereby effectively improving the convergence speed of iterative graph processing.

[0171] Second, the effective utilization rate of hardware accelerators is high: the present invention designs a chain-aware data caching strategy, which effectively reduces unnecessary off-chip communication by preferentially caching the states on the commonly used dependency chain in on-chip memory, obtains better data locality, breaks through the performance bottleneck caused by excessive data transmission overhead, and further promotes the effective utilization of hardware accelerators.

[0172] Example 2

[0173] This embodiment is a further improvement of embodiment 1, and repeated contents will not be repeated here.

[0174] Consider a graph where vertices represent users and edges represent relationships between users (e.g., friendships in a social network). The goal is to use the energy-efficient dynamic graph neural network acceleration method and hardware accelerator proposed in this paper to predict the activity level of each user and perform inference using the graph neural network.

[0175] like Figure 2 As shown, the vertex and edge data in the graph include:

[0176] Vertices: v0, v1, v2, v3, v4;

[0177] Edges: (v0, v1), (v1, v2), (v2, v3), (v2, v4).

[0178] Each vertex has an initial state (such as the user's activity level), and each edge has a weight (such as the strength of the friendship).

[0179] The process of the embodiment of the high energy efficiency dynamic graph neural network acceleration method of this embodiment is as follows Figure 4 shown.

[0180] S601: Get vertices.

[0181] Operation: Assuming that vertex v0 is an active vertex, the tracking unit 110 extracts vertex v0 from the chain FIFO buffer 330 as a source vertex.

[0182] Data transfer: The tracking unit 110 in the chain-driven traversal unit 100 extracts the state of the source vertex v0 from the active bit vector buffer 360 and marks it as inactive. Then, the source vertex v0 is sent to the chain FIFO buffer 330 for subsequent operations.

[0183] S602: Obtain the head and tail offsets.

[0184] Operation: The tracking unit 110 obtains the head and tail offsets of the source vertex v0, that is, the storage location of the adjacency relationship of the source vertex v0 in the graph structure buffer 320 (such as the edge array).

[0185] Data transmission: The tracking unit 110 determines that the adjacent vertex of the source vertex v0 is vertex v1 through the head and tail offsets, and extracts the relevant adjacent edge data from the graph structure buffer 320.

[0186] S603: Obtain adjacent vertices.

[0187] Operation: The tracking unit 110 obtains the adjacent vertex v1 of the source vertex v0 from the edge array.

[0188] Data transmission: The adjacent vertex v1 is stored by the tracking unit 110 into the intermediate queue buffer 340 and the chain FIFO buffer 330 for subsequent processing.

[0189] S604: Adjacent vertex selection.

[0190] Operation: The tracking unit 110 checks whether the adjacent vertex v1 is in an active state. If so, the tracking unit 110 marks the adjacent vertex v1 as inactive.

[0191] Data update: The tracking unit 110 updates the state of the adjacent vertex v1 to inactive to ensure the consistency of the vertex state.

[0192] S605: Prefetching image data.

[0193] Operation: The prefetch unit 120 sequentially performs the operations of extracting source vertices, generating dependency chains, and extracting features. First, the prefetch unit 120 obtains the source vertex v0 from the chain FIFO buffer 330 and then generates a dependency chain, where the source vertex v0 depends on the adjacent vertex v1.

[0194] Data transmission: The prefetch unit 120 extracts the states of the source vertex v0 and the adjacent vertex v1, as well as the states of the edges (such as the weights of the edges) from the input feature buffer 310, and stores these data in the prefetch buffer 121 in the format of <source vertex ID, target vertex ID, source vertex state, target vertex state, edge state>.

[0195] S606: Scheduling and calculation.

[0196] Operation: The scheduling unit 130 transmits the states of the source vertex v0 and the adjacent vertex v1 to the aggregation buffer 211 of the aggregation engine 210 , and transmits the state of the source vertex v0 and the state of the edge to the first application buffer 221 of the first application engine 220 .

[0197] Data transmission: The scheduling unit 130 ensures that data is delivered in the order of dependencies, ensuring smooth progress of aggregation operations and edge operations.

[0198] S607: Chain-driven dynamic processing.

[0199] Operation: The chain-driven processing unit 200 sequentially performs state aggregation, vertex operation, and edge operation for each target vertex.

[0200] State aggregation: The aggregation engine 210 aggregates the states of the source vertex v0 and the adjacent vertex v1 to generate an aggregation result of the adjacent vertex v1, ie, the target vertex v1.

[0201] Edge operation: The first application engine 220 performs edge calculation based on the states of the source vertex v0 and the target vertex v1 as well as the states of the edges.

[0202] Vertex operation: The second application engine 230 performs a state update operation on the target vertex v1 (eg, updating the state through a neural network).

[0203] Data transmission: The aggregation result of the aggregation engine 210 and the edge operation result of the second application engine 230 are transmitted to the first application engine 220 for final status update.

[0204] S608: Final state calculation.

[0205] Operation: After the aggregation engine 210 and the second application engine 230 complete their respective calculations, the calculation results are immediately sent by the aggregation engine 210 and the second application engine 230 to the first application engine 220 for final vertex state calculation.

[0206] Data transmission: After receiving the aggregation result and the edge operation result, the first application engine 220 performs a final state update on the target vertex v1, and transmits the updated state to the output buffer 510 and the input feature buffer 310 respectively for use in the next calculation.

[0207] The application of the present invention in predicting user activity in social networks significantly improves reasoning efficiency and performance. Through dependency chain tracking and dynamic pipeline processing, the present invention can efficiently manage dependencies between vertices, avoid redundant calculations, and accelerate state updates through parallel processing. At the same time, the present invention's efficient data prefetching mechanism and flexible task scheduling optimize data access and load distribution during the calculation process, ensuring maximum utilization of hardware resources. This enables the present invention to significantly improve computing efficiency while reducing latency when processing large-scale graph data, making it suitable for large-scale application scenarios such as social networks.

[0208] For example, the present invention describes the physical hardware modules of a high-energy-efficiency dynamic graph neural network hardware accelerator.

[0209] The chain-driven traversal unit 100 is a graph parsing state machine (ASIC). The chain-driven processing unit 200 is a multi-core vector processor array (DSP hard core cluster). The on-chip buffer 300 is a dual-port BRAM cache array.

[0210] Aggregation engine 210 is a MAC array (DSP hard core + BRAM). First application engine 220 is a vector ALU calculation module (FPGA programmable logic). Second application engine 230 is an edge state update module (FPGA programmable logic). Switch 250 is a crossbar interconnect module (Crossbar). High bandwidth memory 500 is an HBM memory controller (PHY hard core + GDDR6 interface).

[0211] The on-chip buffer 300 utilizes a heterogeneous storage architecture for energy-efficient data management. Its core modules include: a chained FIFO buffer 330 constructed from a hybrid of BRAM and URAM, implementing FIFO control of the dependency chain through a ring pointer register and a hardware state machine; an input feature buffer 310 employs a dual-port BRAM array and integrates a chain-aware data caching strategy, dynamically optimizing feature data retention based on vertex participation in the dependency chain; a graph structure buffer 320 stores vertex offsets and adjacency tables using high-density URAM modules, with built-in sparse coding compression circuitry increasing storage density by 1.8 times; and a weight matrix buffer 350 implements parallel matching queries of edge weights through TCAM, supporting a weight loading bandwidth of 256 GB / s. The prefetch buffer 121 is not a standalone module but is embedded within the BRAM array control logic of the input feature buffer 310. The hardware circuitry of prefetch buffer 121 shares the same physical area as the dual-port BRAM array. A dedicated prefetch channel couples the BRAM's address generator and data path, enabling seamless prefetch-store-compute integration. Prefetch buffer 121 is centrally scheduled by the chain-aware controller of input feature buffer 310, dynamically adjusting prefetch strategies (such as prefetch depth and data replacement rules) based on the priority of the vertex dependency chain.

[0212] The graph parsing state machine (ASIC) uses unvisited active vertices as its root vertex and uses a dynamic dependency chain generation algorithm (hardened into the ASIC's state transition logic) to trace the original dependency chain until all active vertices have been visited. The dependency chain is sequentially stored in a chained FIFO buffer 330 (a circular queue constructed from a hybrid of BRAM and URAM). Its hardware-level FIFO controller (integrated into the ASIC's pointer register bank) ensures that the processing order is strictly consistent with the data propagation path.

[0213] During the prefetch phase, prefetch buffer 121 (a dual-port BRAM array embedded in input feature buffer 310) receives source vertex, target vertex, adjacency dependency chain, and associated graph feature data from chained FIFO buffer 330 via a dedicated prefetch channel. Prefetch operations are dynamically scheduled by the chain-aware controller (implemented in FPGA programmable logic) in input feature buffer 310, adjusting the prefetch strategy based on dependency chain priorities.

[0214] When computing tasks are distributed, the DSP hard core cluster of the multi-core vector processor array 200 performs hardware scheduling:

[0215] The source / target vertices of the pre-fetch buffer 121 are pushed to the BRAM storage partition (aggregation buffer 211) of the MAC array, and the DSP hard core performs the weighted summation of neighborhood features; at the same time, the source vertex state and edge state are transmitted to the BRAM buffer of the edge state update module (implemented by FPGA programmable logic, serving as the second application engine 230) to complete edge operations such as gradient calculation.

[0216] The parallel computing results are converged to the first application engine 220 (vector ALU computing module, FPGA lookup table and DSP Slice construction) through the switch 250 (Crossbar interconnection module, FPGA high-speed wiring resource implementation), and nonlinear fusion calculations such as ReLU activation are completed in the FPGA logic, and finally the target vertex state is output to the high-bandwidth memory 500 (HBM PHY hard core + GDDR6 interface).

[0217] It should be noted that the above-mentioned specific embodiments are exemplary, and those skilled in the art can come up with various solutions inspired by the disclosure of the present invention, and these solutions also fall within the scope of the disclosure of the present invention and fall within the scope of protection of the present invention. Those skilled in the art should understand that the present invention specification and its drawings are illustrative and do not constitute a limitation on the claims. The scope of protection of the present invention is defined by the claims and their equivalents. The present invention specification contains multiple inventive concepts, such as "preferably" and "according to a preferred embodiment", which means that the corresponding paragraph discloses an independent concept, and the applicant reserves the right to file a divisional application based on each inventive concept.

Claims

1. A high-energy-efficiency dynamic graph neural network acceleration method, characterized in that: The method comprises: Taking the unvisited active vertices as root vertices, dynamically tracking the original dependency chain based on a dynamic dependency chain generation algorithm until all active vertices are visited; storing the active vertices in a chain FIFO buffer (330) according to the dependency order between the active vertices, so that the processing order is consistent with the data propagation path; Pre-extracting a source vertex, a target vertex, a dependency chain between the target vertex and its adjacent vertices, and graph data features related to the dependency chain from the chain FIFO buffer (330) in a dependency order, and storing them in a pre-fetch buffer (121); Dispatching the source vertex and the target vertex from the pre-fetch buffer (121) to the aggregation buffer (211) of the aggregation engine (210), and dispatching the state of the source vertex and the corresponding edge state to the second application buffer (231) of the second application engine (230), so that the aggregation engine (210) and the second application engine (230) execute the state aggregation and edge calculation tasks in parallel; The aggregation result of the aggregation engine (210) and the edge calculation result of the second application engine (230) are dispatched to the first application engine (220) for fusion calculation, and the final state of the target vertex is output.

2. The method according to claim 1, characterized in that The dynamic dependency chain generation algorithm includes: Get vertices from the active bit vector buffer (360) or the intermediate queue buffer (340); Get the first and last offsets of the active vertices from the vertex array in the graph structure buffer (320); Obtaining unvisited adjacent vertices of the active vertex from the adjacent vertex array of the graph structure buffer (320), and sending the adjacent vertices to the intermediate queue buffer (340) and the chained FIFO buffer (330); The adjacent vertices marked as active in the active bit vector buffer (360) are updated to adjacent vertices in inactive state to perform adjacent vertex selection.

3. The method according to claim 1 or 2, characterized in that The pre-extraction step includes: Extracting source vertices from the chained FIFO buffer (330) in dependency order; Searching for an edge array associated with the source vertex, extracting all adjacent vertices of the source vertex, and forming a dependency chain in the dependency order; The source vertex state, target vertex state and edge state of each edge in the dependency chain are extracted from the input feature buffer (310).

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises a chain-aware data caching strategy for managing vertex states in an input feature buffer (310), When requesting the state of a vertex, if the input feature buffer (310) is not full, the vertex state is directly cached; if the input feature buffer (310) is full, the priority of the vertex is calculated and the resident vertex with the lowest priority is replaced.

5. The method according to any one of claims 1 to 4, characterized in that The priority of the vertex is calculated as follows: Among them, P G represents the number of dependency chains in the graph, P G (v) represents the number of dependency chains containing vertex v, D v Represents the degree of vertex v.

6. The method according to any one of claims 1 to 5, characterized in that The steps of the aggregation engine (210) performing state aggregation include: The adjacent vertex state information generated by the previous calculation is preloaded into the aggregation buffer (211), and the aggregation operator is executed to generate the aggregation result.

7. The method according to any one of claims 1 to 6, characterized in that The steps of the second application engine (230) executing the edge computing task include: The source vertex and target vertex states are fused with edge attribute data to generate edge information transfer features and send them to the first application engine (220).

8. The method according to any one of claims 1 to 7, characterized in that The steps of the operation task of the first application engine (220) include: Based on matrix-vector multiplication and nonlinear transformation, the updated state of the target vertex is calculated; The updated state of the target vertex is sent to the output buffer (510) and the input feature buffer (310).

9. A high-energy-efficiency dynamic graph neural network hardware accelerator, characterized in that: The hardware accelerator includes: A chain-driven traversal unit (100) tracks dependency chains of active vertices based on a dynamic dependency chain generation algorithm, stores active vertices in a chain FIFO buffer (330) in the order of dependencies between the active vertices, so that the processing order is consistent with the data propagation path; and stores the source vertex, the target vertex, the dependency chain between the target vertex and its adjacent vertices, and graph data features related to the dependency chain pre-extracted from the chain FIFO buffer (330) in the order of dependencies in a pre-fetch buffer (121); The chain drive processing unit (200) dispatches the source vertex and / or target vertex of the pre-fetch buffer (121) to the aggregation engine (210), dispatches the source vertex state and edge state to the second application engine (230), realizes the parallel execution of aggregation and edge calculation, and transmits the parallel execution result to the first application engine (220) to generate the final state of the target vertex; An on-chip buffer (300) includes a chained FIFO buffer (330), a prefetch buffer (121), and an input feature buffer (310), wherein the input feature buffer manages vertex states through a chained perceptual data caching strategy.

10. The hardware accelerator according to claim 9, wherein: The chain-aware data caching strategy includes: When requesting the state of a vertex, if the input feature buffer (310) is not full, the vertex state is directly cached; if the input feature buffer (310) is full, the priority of the vertex is calculated and the resident vertex with the lowest priority is replaced.

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