Method for analyzing integrated circuit, non-transitory storage medium and detection device

Abstract

The present disclosure provides a method of analyzing an integrated circuit (IC), a non-transitory storage medium, and a detection device. The method includes acquiring a review scanning electron microscope (RSEM) image of the IC, and acquiring a voltage contrast electron beam image of the IC. The layout image is rendered from a layout file describing a layout of the IC. A transformation between spatial coordinates of an RSEM image of the IC and spatial coordinates of a voltage contrast electron beam image of the IC is determined using the layout image. A voltage contrast (VC) defect or other VC target pattern is identified in a voltage contrast electron beam image of the IC, and at least one region of interest (ROI) associated with the VC defect is positioned in an RSEM image of the IC using spatial transformation. The at least one ROI in the RSEM image of the IC is analyzed to generate information of a VC defect or other VC target pattern.

Description

Technical Field

[0001] The present invention relates to an analysis method for electronic circuits, and in particular to a method for analyzing integrated circuits, a non-transitory storage medium, and a detection device. Background Art

[0002] The following content involves semiconductor manufacturing technology, semiconductor quality control, semiconductor defect analysis, etc. Summary of the Invention

[0003] In one embodiment of the present disclosure, a method for analyzing an integrated circuit includes: obtaining a review scanning electron microscope image of the integrated circuit; obtaining a voltage contrast electron beam image of the integrated circuit; rendering the layout image based on a layout file describing the layout of the integrated circuit; using the layout image to determine a transformation between the spatial coordinates of the review scanning electron microscope image of the integrated circuit and the spatial coordinates of the voltage contrast electron beam image of the integrated circuit; identifying a voltage contrast target pattern in the voltage contrast electron beam image of the integrated circuit; using the spatial transformation to locate at least one region of interest associated with the voltage contrast target pattern in the review scanning electron microscope image of the integrated circuit; and analyzing at least one region of interest in the review scanning electron microscope image of the integrated circuit to generate defect information of the voltage contrast target pattern.

[0004] In one embodiment of the present disclosure, a non-transitory storage medium is configured to store instructions readable and executable by an electronic processor to perform a method for analyzing an integrated circuit based on a review scanning electron microscope image of the integrated circuit and a voltage contrast electron beam image of the integrated circuit. The method includes: using a layout image depicting a design base layout of the integrated circuit to determine a transformation between spatial coordinates of the review scanning electron microscope image of the integrated circuit and spatial coordinates of the voltage contrast electron beam image of the integrated circuit; identifying voltage contrast defects in the voltage contrast electron beam image of the integrated circuit; using the spatial transformation to locate multiple regions of interest associated with respective voltage contrast defects in the review scanning electron microscope image of the integrated circuit; and analyzing the multiple regions of interest in the review scanning electron microscope image of the integrated circuit to determine a root cause of the voltage contrast defect.

[0005] In one embodiment of the present disclosure, an inspection device for analyzing an integrated circuit includes a scanning electron microscope, a voltage contrast electron beam microscope, and an electronic processor. The scanning electron microscope acquires a review scanning electron microscope image related to the integrated circuit. The voltage contrast electron beam microscope acquires a voltage contrast electron beam image related to the integrated circuit. The electronic processor is programmed to perform a method. The method includes: using a layout image depicting a design base layout of the integrated circuit to determine a conversion between spatial coordinates of the review scanning electron microscope image of the integrated circuit and spatial coordinates of the voltage contrast electron beam image of the integrated circuit; identifying a voltage contrast target pattern in the voltage contrast electron beam image of the integrated circuit; using the layout image, locating multiple regions of interest associated with multiple voltage contrast target patterns in the review scanning electron microscope image of the integrated circuit; and analyzing the multiple regions of interest associated with each of the multiple voltage contrast target patterns in the review scanning electron microscope image of the integrated circuit to generate information about the voltage contrast target pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood when read in conjunction with the accompanying detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A wafer defect assessment system is schematically illustrated that employs a scanning electron microscope (SEM) configured to acquire review scanning electron microscope (RSEM) images and a voltage contrast electron beam inspection or imaging (VC-EBI) microscope.

[0008] Figure 2 A method for generating a transformation between the spatial coordinates of an RSEM image of an integrated circuit (IC) and the spatial coordinates of a voltage-contrast electron beam image of the IC is schematically illustrated.

[0009] Figure 3 A defect analysis method using RSEM images of ICs and Figure 2 The transforms generated by the method are used to analyze VC defects identified in voltage contrast electron beam images of ICs.

[0010] Figure 4 A non-limiting illustrative embodiment of a VC defect identifier in a wafer defect evaluation system is schematically illustrated. Figure 1 shown.

[0011] Figure 5A non-limiting illustrative embodiment of a customized algorithm for detecting VC defects due to metal gate protrusion is schematically illustrated.

[0012] Figure 6 A non-limiting illustrative embodiment of a RSEM image depicting a portion of an IC in which a VC defect is present and a region of interest of the VC defect is schematically illustrated.

[0013] Figure 7 A high energy (HE) RSEM image and a low energy (LE) RSEM image are schematically illustrated, and a root cause defect detected in the HE RSEM image is schematically indicated, the defect corresponding to a defect in the drain epitaxial layer.

[0014] Description of Reference Numerals

[0015] 10: VC-EBI system

[0016] 12: Voltage vs. Electron Beam Imaging

[0017] 14: VC Defect Identifier

[0018] 14c, 60, 62, 64, 66, 70, 72, 74, 76, 82, 84, 86, 90, 92, 94, 96, 98, 100, 102: Operation

[0019] 14a: General VC Defect Detection Algorithm

[0020] 14b: Customized VC defect detection algorithm

[0021] 16: Identified VC defects

[0022] 20: Re-examination of Scanning Electron Microscope (RSEM)

[0023] 22: RSEM imaging

[0024] 22LE: Low-energy (LE) RSEM imaging

[0025] 22HE: High Energy (HE) RSEM Imaging

[0026] 24: Defect Analyzer

[0027] 26: Arrow

[0028] 30: Secondary electron detector

[0029] 32: EDX detector

[0030] 40: Layout File

[0031] 42: Layout Image Rendering Engine

[0032] 44: Layout Image

[0033] 50: Server computer

[0034] 52: Electronic processor

[0035] 54: Display

[0036] 56: User Interface

[0037] 80: Conversion

[0038] 88: Position

[0039] C D :deviation

[0040] C MG : Boundary features

[0041] D RC : Image contrast

[0042] MD D : Drain Metallization

[0043] MD S : Source Metallization

[0044] MG: Gate Metallization

[0045] MG EX : Extrude

[0046] ROI1, ROI2, ROI3, ROI4: Region DETAILED DESCRIPTION

[0047] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, a first feature formed on or above a second feature may include an embodiment in which the first and second features are directly in contact, and may also include an embodiment in which an additional feature is formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0048] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to facilitate describing the relationship of one component or feature to another component or features as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0049] Reference Figure 1A voltage contrast electron beam inspection or imaging (VC-EBI) system 10 is provided. The VC-EBI system 10 may include a scanning electron microscope (SEM) or similar instrument having a vacuum enclosure, an electron beam source that directs an accelerated electron beam to an integrated circuit (IC) formed on a semiconductor wafer mounted on a stage (or otherwise disposed therein), the stage being connected to a voltage source for applying a stage bias to the IC (details not shown), and a secondary electron detector for measuring secondary electrons (SE) emitted by the IC in response to the applied electron beam. A voltage contrast electron beam image (i.e., VC-EBI image) 12 is acquired using the VC-EBI system 10 by moving the sample stage (or, additionally or alternatively, directing the electron beam) to scan the IC in two dimensions and acquiring a secondary electron signal as a function of scan position. VC-EBI imaging is a fast and effective method for identifying voltage contrast (VC) defects in ICs (or, more generally, VC target patterns in ICs, which can be defects or other features of interest in the IC that exhibit detectable voltage contrast) due to electrical shorts or opens in the IC. VC defects can lead to reduced yield. During VC-EBI imaging, a stage bias is applied to a semiconductor wafer (or other substrate) holding the IC, and the landing energy (LE) of the incident electron beam is the accelerating voltage of the electron beam minus the stage bias. Depending on the landing energy, the secondary electron yield can be greater than 1 (positive mode VC-EBI, meaning that on average each electron in the electron beam results in the emission of more than one secondary electron from the wafer surface), less than 1 (negative mode VC-EBI), or approximately equal to 1. In some non-limiting illustrative examples, the voltage contrast electron beam image 12 is acquired at a landing energy (LE1) of approximately 1 to achieve charge neutrality conditions, which can enhance sensitivity to defects. However, it is also contemplated to use other setups (e.g., positive mode or negative mode) to acquire voltage contrast electron beam images 12. VC-EBI imaging can preferably be performed at an early stage of the middle end of line (MEOL) or back end of line (BEOL), for example after the initial (e.g., M0) metallization has formed the metal gate (MG) and metallized contacts to the source and drain regions, and optionally further after the initial electrical interconnects have been formed.

[0050] VC-EBI imaging provides voltage contrast for various types of defects, such as those associated with or causing various types of electrical shunts, shorts, or open connections in an IC. For example, if a voltage-contrast electron beam image is acquired at LE1, a bright VC defect (i.e., an increased electron yield at the defect) may correspond to an electrical short, while a dark VC defect (i.e., a decreased electron yield at the defect) may correspond to an electrical open. Using a VC defect identifier 14, VC defects 16 are identified, for example, as bright-contrast or dark-contrast areas in the voltage-contrast electron beam image 12.

[0051] However, the contrast between light and dark observed VC defects provides only limited information about the root cause of the VC defect observed in the voltage contrast electron beam image 12, and it is difficult or impossible to determine the root cause of the VC defect from the voltage contrast electron beam image alone. To guide process improvements, it is necessary to determine the exact type of defect and the layer where the defect occurs. For example, an electrical short between the metal gate (MG) and the metal (MD) connected to the drain or source can be caused by various types of physical defects, such as metal gate extrusion or epitaxial damage at a specific layer. In addition, VC noise caused by localized charging can be mistakenly detected as a false VC defect. For some process layers, VC noise can mask true VC defects. Therefore, it is also desirable to distinguish VC noise from true VC defects as part of the defect classification analysis.

[0052] refer to Figure 1In embodiments disclosed herein, VC-EBI imaging performed using the VC-EBI system 10 is advantageously combined with a review scanning electron microscope (RSEM) 20. The RSEM 20 acquires RSEM images 22, which are analyzed by a defect analyzer 24 to provide defect information regarding VC defects (or, more generally, information regarding VC target patterns). The RSEM images 22 are scanning electron microscope images acquired using the RSEM 20, which is a scanning electron microscope operated with effective imaging parameters such that analysis of the RSEM images 22 provides sufficient defect information to better understand the source of the VC defects. In some embodiments, the defect analysis performed by the defect analyzer 24 is advantageously automated and can include information confirming the root cause of the VC defects observed in the voltage-contrast electron beam images 12. To facilitate defect analysis, the RSEM images 22 have a higher spatial resolution than the voltage-contrast electron beam images 12. Therefore, the defect analysis performed by the defect analyzer 24 on the RSEM images 22 can utilize the higher spatial resolution to locate the root cause of the VC defects (or other VC target patterns). For example, this can enable a root cause defect to be spatially localized at a specific location in a transistor or other IC component.

[0053] Due to the high resolution of the RSEM image 22, acquisition can be slow. Therefore, in some inspection workflow embodiments, a voltage contrast electron beam image 12 is first acquired, a VC target pattern (e.g., a VC defect in the illustrative embodiment) 16 is identified by the VC defect (or more generally, a VC target pattern) identifier 14, and then an RSEM image 22 is acquired in the vicinity of some or all of the identified VC defects 16. Figure 1 In FIG, the use of an identified VC defect 16 to guide RSEM imaging is schematically indicated by arrow 26, which indicates the input of the VC defect 16 (or its location in the voltage contrast electron beam image 12) to the RSEM 20. Figure 1, arrow 26 is shown with a dashed line to indicate that this is an optional aspect. In other approaches, RSEM 20 acquires RSEM image 22 of the entire area of the IC to be inspected, in which case such RSEM imaging based on the location of the VC defect is appropriately not employed.) This optional approach can improve the efficiency of the inspection workflow, particularly if the number of identified VC defects 16 is relatively small (or if only a subset of the identified VC defects 16 are further characterized by RSEM), because RSEM image 22 can be acquired only in the vicinity of the VC defect, rather than acquiring an RSEM image encompassing the entire IC (or an array of ICs fabricated on a semiconductor wafer). Therefore, it should be noted that while RSEM image 22 is generally referred to herein, RSEM image 22 may include multiple RSEM images, with different RSEM images acquired for different areas of the IC. RSEM image 22 may encompass the entire IC being inspected, or the entire array of ICs fabricated on a semiconductor wafer being inspected, or may encompass only a portion of the IC containing the VC defect.

[0054] In addition or alternatively, the RSEM image 22 may include multiple RSEM images acquired using different imaging parameters. As a non-limiting illustrative example, the RSEM image 22 may include two (or more) RSEM images acquired using electron beams with different accelerating voltages to acquire the RSEM images. As a specific non-limiting illustrative example, a low energy (LE) RSEM image may be acquired using an electron beam having a first accelerating voltage, and a high energy (HE) RSEM image may be acquired using an electron beam having a second accelerating voltage that is higher than the first accelerating voltage. The higher accelerating voltage of the HE RSEM image means that it probes deeper into the IC than the LE RSEM image; therefore, if a defect is detected in the HE RSEM image but not in the LE RSEM image (or, if the defect is detected more intensely in the HE RSEM image than in the LE RSEM image), it can be concluded that the root cause defect is in a buried layer that is probed (more intensely) by the HE RSEM image than by the LE RSEM image. Conversely, if a defect is detected in the LE RSEM image but not in the HE RSEM image (or, if the defect is detected more intensely in the LE RSEM image than in the HE RSEM image), it can be concluded that the root cause defect is at the surface or in a layer closer to the surface that the LE RSEM image detects (more intensely) than the HE RSEM image.

[0055] Taking the RSEM image 22 as another non-limiting illustrative example, which includes different RSEM images acquired using different imaging parameters, the RSEM image 22 may include: (1) an RSEM image acquired using at least one secondary electron (SE) detector 30, and (2) an energy-dispersive X-ray (EDX) image acquired using at least one EDX spectrometer 32, the technique being referred to as energy-dispersive X-ray (EDX) imaging. Figure 1 The optional use of EDX imaging is schematically indicated in FIG by using dashed lines to show an optional EDX spectrometer 32. Again, these are merely non-limiting illustrative examples, and the RSEM images 22 may be acquired using other types of SEM detectors, such as a backscattered electron (BSE) detector (not shown).

[0056] Defect analysis performed on RSEM images 22 by defect analyzer 24 can provide defect information about the VC defects identified by VC defect identifier 14, potentially including identifying the root cause of the VC defects. However, determining the root cause of VC defects by analyzing RSEM images is challenging for various reasons. Lower-resolution voltage-contrast electron beam images cannot precisely map VC defects to the coordinates of higher-resolution RSEM images 22. Furthermore, the root cause defect that caused the identified VC defect may be located at a distance from the VC defect. For example, a short between the metal gate (MG) and the metal drain contact (MD) may cause a VC defect that is observed at a distance from the root cause short.

[0057] Additionally, the root cause defect may be embedded in a buried layer of the IC and may not be easily visible in the RSEM image 22. The IC may have multiple process layers (e.g., one or more process layers corresponding to one or more dopant diffusion or implantation operations, a process layer corresponding to epitaxial deposition of transistor source and drain regions, and one or more metallization layers), and different physical defect types may exist on different process layers, which may result in electrical shorts or opens that are detected as VC defects.

[0058] Due to these difficulties, the root cause of VC defects may be misidentified or not found at all.

[0059] To solve these difficulties, Figure 1The inspection system further advantageously utilizes a layout file 40 describing the layout of the IC to be inspected. As non-limiting exemplary embodiments, the layout file 40 may be a Graphic Design System (GDS) layout file describing the layout of the IC to be inspected, an Open Artwork System Interchange Standard (OASIS) layout file describing the layout of the IC to be inspected, or an Electronic Design Interchange Format (EDIF) layout file describing the layout of the IC to be inspected. While reference is made to a layout file 40, it is contemplated that the layout file 40 may include multiple layout files, for example, for different layers of the IC, as non-limiting exemplary embodiments. A layout image rendering engine 42 renders a layout image 44 of the IC to be inspected from the layout-describing information contained in the layout file 40. As will be described later herein, the layout image 44 advantageously provides a common reference for determining the spatial coordinates of the RSEM image 22 of the IC and the spatial coordinates of the voltage-contrast electron beam image 12, thereby enabling rapid, automatic, and accurate mapping of the locations of identified VC defects to the coordinates of the RSEM image 22. Additionally, layout image 44 further advantageously provides a basis for identifying regions of interest (ROIs) for defect analysis by defect analyzer 24. For example, layout image 44 identifies locations where metal gate extrusion or epitaxial damage may be the root cause of an identified VC defect.

[0060] Figure 1 The detection system includes the VC-EBI system 10 and RSEM 20 as described above. The layout archive 40 is suitably stored in a database of an exemplary server computer 50 or other information technology (IT) system or storage. Figure 1In the embodiment of the present invention, the defect analyzer 24 is implemented by appropriately programming a computer or other electronic processor 52. More generally, a non-transitory storage medium (not shown, such as a hard disk, solid-state drive, electronic memory, and / or the like) stores instructions that are readable and executable by the computer or other electronic processor 50 to perform a method for inspecting an IC based on the RSEM image 22 of the IC and the voltage-contrast electron beam image 12 of the IC to be inspected. The method suitably includes VC defect recognition (or more generally, VC target pattern recognition) performed by the VC defect (or more generally, VC target pattern) identifier 14, layout image rendering performed by the layout image rendering engine 42, and defect analysis performed by the defect analyzer 24. It should also be noted that the voltage contrast electron beam image 12 of the IC may include the entire IC or only a portion of the IC, and similarly, the RSEM image 22 may include the entire IC or only a portion of the IC (the portion included in the RSEM image 22 may be different from the portion included in the voltage contrast electron beam image 12), and as previously described, the RSEM image 22 may also include RSEM images obtained using different imaging parameters (e.g., using electron beams with different accelerating voltages, using different detectors, such as the SE detector 30 and the EDX detector 32, and / or the like). Figure 1 As shown, the computer or other electronic processor 52 may include or be operatively connected to a display 54 on which a user interface 56 is presented for displaying defect data generated by the inspection system.

[0061] Reference Figure 1 And further refer to Figure 2 , shows a non-limiting illustrative embodiment of a method of processing a layout archive 40 , which is suitably implemented by the layout image rendering engine 42 and the defect analyzer 24 . Figure 2 The method includes an operation 60 of acquiring a voltage contrast electron beam image 12 using the VC-EBI system 10, and an operation 62 of acquiring an RSEM image 22 using the RSEM 20. As previously described, in some embodiments, operation 62 is guided by the location of the VC defect 16 identified in the voltage contrast electron beam image 12 (e.g., Figure 1 Operation 64 retrieves the layout file 40, and operation 66 executed by the layout image rendering engine 42 generates a layout image 44. The layout image 44 then needs to be spatially aligned with the voltage contrast electron beam image 12 and the RSEM image 22, respectively.

[0062] However, layout image 44 may differ substantially from these acquired voltage-contrast electron beam images 12 and RSEM images 22. While layout image 44 has image features corresponding to features of the design base layout of the IC to be inspected, voltage-contrast electron beam image 12 has image features corresponding to voltage contrast variations across the IC, and RSEM image 22 has image features corresponding to secondary electron yield variations across the IC. To improve the accuracy of spatial alignment with the voltage-contrast electron beam image, in operation 70, layout image 44 is processed to produce a VC-EBI feature layout image with a contrast closer to that of voltage-contrast electron beam image 12. Similarly, in operation 72, layout image 44 is processed to produce an RSEM feature layout image with a contrast closer to that of RSEM image 22. Operations 70 and 72 may employ various image processing techniques, such as dilation, thinning, or other Boolean operations, assigning dark or light image pixel intensities to different features in the layout (e.g., closer to the bright or dark contrast in voltage-contrast electron beam image 12, or closer to the grayscale intensity variations in RSEM image 22), and so forth. Operations 70 and 72 may also include pixel resampling to match the image resolution (ie, pixel size) of the voltage-contrast electron beam image 12 and the RSEM image 22, respectively.

[0063] In operation 74, a first spatial transformation is determined that spatially aligns the voltage-contrast electron beam image 12 of the IC with the VC-EBI feature layout image output from operation 70. In operation 76, a second spatial transformation is determined that spatially aligns the RSEM image 22 of the IC with the RSEM feature layout image output from operation 72. A transformation 80 is then derived from the first spatial transformation output from operation 74 and the second spatial transformation output from operation 76 between the spatial coordinates of the RSEM image 22 of the IC and the spatial coordinates of the voltage-contrast electron beam image 12 of the IC.

[0064] As a non-limiting example, operation 74 may determine a first transformation (T1) by performing a rigid or non-rigid spatial alignment between the voltage-contrast electron beam image 12 and the VC-EBI feature layout image output from operation 70. Thus, given the coordinate system CVC-EBI of the voltage-contrast electron beam image 12 and the reference layout image coordinate system CLayout of the layout image 44, the first transformation T1 may be expressed as:

[0065] T1(C VC-EBI )=C Layout (1)

[0066] Operation 76 may determine a second transformation (T2) by performing a rigid or non-rigid spatial alignment between the RSEM feature layout image output by operation 72 and the RSEM image 22. Thus, given the coordinate system CRSEM of the RSEM image 22 and the reference layout image coordinate system CLayout of the layout image 44, the second transformation T2 may be expressed as:

[0067] T2(C Layout )=C RSEM (2)

[0068] Transformation 80 may be a combination of transformation T1 and transformation T2 (e.g., transformation 80 may be a collection of transformations T1 and T2), and / or transformation 80 may be expressed as a combination or composite of transformation T1 and transformation T2, e.g.,

[0069] T(C VC-EBI , T1, T2)= T2(T1(C VC-EBI ))=C RSEM (3)

[0070] This is a transformation suitable for converting the VC defect location in the voltage-contrast electron beam image 12 to the coordinate system of the RSEM image 22. These are non-limiting illustrative examples only, and other representations of the transformation 80 may also be constructed.

[0071] Reference Figure 3 , describes a Figure 2 1 and 2. A non-limiting illustrative embodiment of a defect analysis method suitably implemented by the defect analyzer 24 of FIG. Figure 3 The method receives as input a voltage contrast electron beam image 12 which is obtained in operation 82 by Figure 1 The VC defect identifier 14 is processed by the voltage contrast electron beam image 12 to identify VC defects (or other VC target patterns) 16 in the voltage contrast electron beam image 12. Operation 82 identifies areas of the voltage contrast electron beam image 12 with significantly higher than average brightness as bright VC defects, or identifies areas of the voltage contrast electron beam image 12 with significantly lower than average brightness as dark VC defects. An empirically determined voltage contrast electron beam image intensity threshold value may be used, optionally in conjunction with pixel connectivity analysis, to identify bright VC defects in the voltage contrast electron beam image 12.

[0072] Reference Figure 1 and Figure 3 , and further reference Figure 4In some approaches, VC defect identification 82 is performed by the VC defect identifier 14 using one (or optionally multiple) general VC defect detection algorithms 14a implemented on the inspection device. However, the general VC defect (or more generally, VC target pattern) detection algorithm 14a may have limited sensitivity on challenging VC defects (such as embedded defects that induce VC). To improve defect identification, Figure 4 In a non-limiting illustrative embodiment, the voltage contrast electron beam image 12 acquired using the VC-EBI system 10 is also Figure 4 The parallel paths shown are processed with a customized VC defect (or more generally, VC target pattern) detection algorithm 14b. The customized VC defect detection algorithm 14b is constructed to detect a target type of VC defects. The target defect type for which the customized VC defect detection algorithm 14b is constructed can be a specific defect mechanism (e.g., gate metallization squeezed out, or damage to the epitaxial drain material, etc.), and / or the target defect type can be a target type specific to a specific integrated circuit (IC) design (e.g., the shape of a circuit feature in a specific IC), and / or the target defect type can be a target type specific to a given manufacturing technology, and / or so on. The customized VC defect detection algorithm 14b can be run, for example, as pluggable executable software on an additional central processing unit (CPU) in the imaging computer of the EBI tool, or can be run independently on an off-tool imaging computer connected to the tool via a high-speed electronic data network. Figure 4 In the illustrative example of FIG, a customized VC defect detection algorithm 14b includes an operation 14c for extracting image features that indicate the presence of a defect of interest (DOI) and then feeding the features to one or more decision rules or ML classifiers 14d to assess the likelihood of detectability. Identified VC defects 16 include VC defects identified by the general VC defect detection algorithm 14a and VC defects identified by a VC defect detection algorithm 14b configured to detect target-type VC defects.

[0073] Reference Figure 5 , an illustrative example of implementation of a customized VC defect detection algorithm 14b for VC defect detection is described. Figure 5A portion of a voltage contrast electron beam image of a transistor array region is schematically depicted, which includes a gate metallization MG, a drain metallization MDD, and a source metallization MDS. The gate metallization MG includes an extrusion MGEX. A customized VC defect detection algorithm 14b performs DOI image feature extraction 14c to determine the boundary or contour CMG of the gate metallization MG by a robust threshold algorithm that detects the transition from a bright MG to a dark background; then, an ML or rule-based classification 14d detects the extrusion MGEX as a deviation CD of the boundary feature CMG relative to its expected shape. That is, the classifier 14d analyzes the contour feature CMG and calculates or identifies the boundary extension CD (caused by the MG extrusion MGEX) relative to a reference MG profile (not shown; i.e., the expected MG profile of a defect-free gate metallization). It should be understood that although Figure 5 The illustrative example specifically for VC defect detection 14b is directed to detecting MG squeeze-out in an illustrative transistor array region, but more generally, Figure 4 The method can be applied to provide customized VC defect detection for additional and / or other target types of VC defects, such as damage to epitaxial drain material, etc. Suitable methods for constructing a customized VC defect detection algorithm 14b for a target type of defect include acquiring voltage-versus-e-beam images of devices with and without defects of the target defect type, determining computationally extractable image features (e.g., image contours, such as the illustrative MG boundary feature CMG, or image pixel patterns, etc.) that are significantly discriminatory between the presence and absence of defects of the target defect type, and training an ML classifier, or constructing suitable rules, for classifying input image features as exhibiting defects of the target defect type or as not exhibiting such defects. Such construction of the customized VC defect detection algorithm 14b can optionally utilize training voltage-versus-e-beam images of devices with and without defects of the target defect type, wherein the training voltage-versus-e-beam images are examples of a target IC layout, a target IC manufacturing technology, and / or the like, to facilitate tailoring the customized VC defect detection algorithm 14b to the specific IC layout and / or IC manufacturing technology, etc.

[0074] Refer again Figure 3 , Figure 3 The method also receives as input the RSEM image 22. Figure 1 As discussed, in some embodiments, for each VC defect, an RSEM image 22 is acquired in the vicinity of the defect, such as Figure 1 and Figure 3 As indicated by the arrow 26 shown in FIG. Figure 3 The method also receives a transformation 80 between the spatial coordinates of the RSEM image 22 and the spatial coordinates of the voltage contrast electron beam image 12, which is determined as previously described with reference to Figure 2described.

[0075] like Figure 3 As shown in operation 84 , each VC defect is analyzed in turn as follows: In operation 86 , the location of the VC defect in the spatial coordinates of the voltage-contrast electron beam image 12 is converted to the spatial coordinates of the RSEM image 22 using transformation 80 , thereby outputting the location 88 of the VC defect in the RSEM image 22 .

[0076] Reference Figure 3 And further refer to Figure 6 At least one region of interest (ROI) is identified for the evaluated VC in operation 90. Operation 90 utilizes knowledge of the IC layout and the mapping between the voltage-contrast electron beam image 12 and the RSEM image 22 provided by transformation 80. In other words, the VC defect is identified in the RSEM image 22 using the spatial transformation of operation 86, and in operation 90, each of a plurality of ROIs is found at a location associated with the VC defect 88 in the RSEM image 22 based on the layout image 44. An ROI found in the RSEM image 22 associated with a given VC defect is referred to herein as being associated with that VC defect.

[0077] To illustrate a non-limiting example of operation 90, Figure 6 A non-limiting exemplary embodiment of (at least a portion of) an RSEM image 22 is schematically illustrated, the RSEM image 22 depicting a portion of an IC including a portion of a transistor array having a metal gate MG and drain and source metallizations MDD and MDS. The drain metallization MDD and the source metallization MDS are typically formed as a single process layer, with the distinction between source and drain being a result of subsequent electrical connectivity provided by electrical connections formed during MEOL and / or BEOL processes. A bright VC defect is indicated at location 88 in the RSEM image 22. The VC defect is observed in the voltage contrast electron beam image 12, and the location 88 of the VC defect in the RSEM image 22 is indicated by Figure 3 The imaging operation 86 is determined.

[0078] Figure 6 Further illustrating four regions of interest ROI1, ROI2, ROI3, and ROI4 associated with the location 88 of the VC defect in the RSEM image 22, these regions are found in operation 90 by identifying locations in the RSEM image 22 that correspond to locations in the IC layout where the root cause defect may result as shown in FIG. Figure 1 The VC defect is shown at location 88 in RSEM image 22. The identification of the ROI in operation 90 utilizes the layout image 44 (or as previously referenced). Figure 2The corresponding RSEM feature layout image produced by operation 72 ) and a priori knowledge of the electrical connections of the IC (or the IC to be manufactured if IC inspection is performed before completing BEOL processing) and plausible root cause defects that may lead to the observed location 88 .

[0079] For example, focusing on Figure 6 In a non-limiting exemplary embodiment, the root cause defect at location 88 may be any of the following: (1) metal protrusion of the metal gate MG in region ROI1 causing a short circuit between the adjacent drain metallization MDD and gate MG regions; (2) damage to the epitaxial drain material causing a short circuit between region ROI1 and the adjacent gate MG region; (3) metal protrusion of the metal gate MG in region ROI2 causing a short circuit between the adjacent drain metallization MDD and gate MG regions; (4) damage to the epitaxial drain material causing a short circuit between region ROI2 and the adjacent gate MG region; (5) metal protrusion of the metal gate MG in region ROI3 causing a short circuit between the adjacent source metallization MDS and gate MG regions; (6) damage to the epitaxial source material causing a short circuit between region ROI3 and the adjacent gate MG region; (7) metal protrusion of the metal gate MG in region ROI4 causing a short circuit between the adjacent source metallization MDS and gate MG regions; or (8) damage to the epitaxial source material causing a short circuit between region ROI4 and the adjacent gate MG region.

[0080] Because any of these root cause defects can produce the VC defect observed in the voltage contrast electron beam image 12, it is difficult or impossible to determine which root cause defect caused the VC defect by analyzing the voltage contrast electron beam image alone. Figure 3 Operation 84 in the analysis analyzes the RSEM image 22 to provide defect information that, in some embodiments, is sufficient to isolate the root cause defect. Operation 90 identifies regions of interest ROI1, ROI2, ROI3, and ROI4 by utilizing transformation 86 (e.g., transformation T2 between the layout image 44 and the RSEM image 22) to locate features in the IC layout that may cause the observed luminance VC defect.

[0081] Again, Figure 6 is only a non-limiting example. In general, the number of ROIs identified in operation 90 may be one, two, three, four, five, or more. In addition, the range of the ROI may vary. Figure 6 For example, the region ROI1 may include a portion of the adjacent drain metallization MDD and / or a portion of the adjacent gate metallization MG, and the other ROIs (ie, the schematic regions ROI2, ROI3 and ROI4) are similar. Figure 6 A luminance VC defect is described in the example of , but a similar method can also be performed in the case of a black VC defect.

[0082] Furthermore, a particular ROI in the layout may correspond to ROIs of two (or more) RSEM images. For example, if the RSEM image 22 includes a low-energy (LE) RSEM image obtained using an electron beam with a relatively low accelerating voltage and a high-energy (HE) RSEM image obtained using an electron beam with a relatively high accelerating voltage, then each ROI (i.e., each lateral region) in the layout may have two RSEM ROIs: a LE RSEM image ROI and a HE RSEM image ROI.

[0083] As another non-limiting illustrative example of an ROI in a layout having two (or more) corresponding RSEM image ROIs, one RSEM image ROI may be located in an RSEM image acquired using a SE detector, while another RSEM image ROI may be located in an RSEM including an EDX image acquired using an EDX spectrometer.

[0084] Refocus Figure 3 In operation 92, one or more features are calculated for each ROI found in operation 90. These features may be image features (e.g., contrast metrics, brightness metrics, texture metrics, image gradient metrics, etc.) extracted from the corresponding ROI in the RSEM image 22. In some embodiments, the extracted features may be the ROI image bitmap itself. The features calculated for each ROI may optionally include one or more RSEM imaging parameters used when acquiring the RSEM image of the IC, such as electron beam acceleration energy (which is useful because it can indicate penetration depth and therefore whether image contrast is primarily due to surface or buried layers), RSEM image resolution (which may indicate whether small defects should be resolved in the ROI in the RSEM image), etc.

[0085] Operation 92 may also generate features for the ROI based on additional information. For example, if the VC defect to be analyzed is detected by a custom VC defect detection algorithm 14b built for the target type of defect (see Figure 4 and Figure 5 ), the additional feature calculated in operation 92 may be whether the VC defect is detected by the general VC defect detection algorithm 14a or by the customized VC defect detection algorithm 14b. Figure 3Schematically represented by dashed arrows 93, which feed information from VC defect identification 82 to feature computation 92. Thus, the features of the ROI in the RSEM image 22 may include a feature indicating whether the associated VC defect was identified by a defect detection algorithm 14b configured to detect the target type of VC defect. This additional feature may provide useful information for identifying the root cause of the associated VC defect because it incorporates information about the defect type obtained by the VC defect analyzer 14 from the voltage-contrast electron beam image 12 into the feature set. As a non-limiting illustrative example, returning to Figure 5 If the relevant VC defect is detected by the defect detection algorithm 14b constructed to detect VC defects due to MG protrusion, the feature indicating that the relevant VC defect is detected by the defect detection algorithm 14b is information tending to indicate that the ROI may exhibit MG protrusion.

[0086] In operation 94, the characteristics of each ROI are analyzed. The analysis may employ a formula or analytical method, or a machine learning (ML) model may be employed to analyze the ROI. In one illustrative example, operation 94 includes operation 96, in which each ROI is scored using an ML model, and the defect with the highest score is selected as the likely root cause defect location. For example, an ML model may be trained on manually labeled training ROI images of ICs manufactured using the same layout to distinguish between ROIs with and without root cause defects. In some embodiments, two (or more) ML models may be used to score each ROI. Figure 6 In the example, for example, region ROI1 might be scored using an ML model trained to detect root-cause defects in the form of gate protrusions and another ML model trained to detect root-cause defects in the form of epitaxial damage on the drain region epitaxial layer. If a lateral ROI in the layout has two (or more) corresponding RSEM image ROIs (e.g., an LE RSEM image ROI and an HE RSEM image ROI), the analysis can process the LE and HE RSEM images separately, together, or both. In operation 98, defect information for the VC defect is output.

[0087] The ML model used in operation 96 can be a random forest classifier, a convolutional neural network (CNN) classifier (such as ResNet or YoLo), another type of artificial neural network (ANN) classifier, or any other appropriately trained ML model. In the case of a CNN classifier, in some embodiments, the input can include the entire ROI image and optional metadata (e.g., beam acceleration energy). Using the trained ML model in operation 96 requires inputting one or more ROI features derived for the ROI to be analyzed into the ML algorithm and receiving a score for the ROI from the ML algorithm in response.

[0088] refer to Figure 7 ,describe Figure 3 Examples of operations 94, 96, and 98 in FIG. Figure 7 Shows the Figure 6 A high energy (HE) RSEM image 22HE and a low energy (LE) RSEM image 22LE of the same transistor array area are shown, and include identically depicted gate metallization MG, drain metallization MDD, and source metallization MDS. The low energy RSEM image 22LE was obtained using an electron beam having a first accelerating voltage, whereas the HE RSEM image 22HE was obtained using an electron beam having a second accelerating voltage higher than the first accelerating voltage. Typically, the higher energy electron beam used to obtain the HE RSEM image 22HE probes deeper into the IC than the lower energy electron beam used to obtain the LE RSEM image 22LE. Therefore, the HE RSEM image 22HE has image contrast corresponding to the buried layer(s) of the IC; whereas the LE RSEM image 22LE has image contrast corresponding to the surface or shallower buried layer(s) of the IC. In the present example, the source and drain epitaxy is formed first and therefore is deeper than the subsequent gate metallization MG. In Figure 7 In the example, it is assumed that the root cause defect is the epitaxial damage of the drain epitaxial layer adjacent to (or included in) the region ROI1 (e.g. Figure 6 As shown in FIG. 22A , the epitaxial damage produces a strong image contrast DRC in the HE RSEM image 22HE because the higher acceleration energy of the electron beam significantly penetrates the buried epitaxial layer. However, the epitaxial damage produces a weak or non-existent contrast in the LE RSEM image 22LE because the lower acceleration energy of the electron beam does not significantly penetrate the buried epitaxial layer. Therefore, by analyzing (and / or comparing) the region ROI1 in the HE RSEM image 22HE with the region ROI1 in the LE RSEM image 22LE, it is possible to distinguish whether the root cause defect is laterally located in the region ROI1 and whether the root cause defect is in the epitaxial layer or the metallization layer.

[0089] Although Figure 7An example is schematically shown in which a defect is located in a buried layer (e.g., an epitaxial layer) and is detected by analyzing the HE RSEM image 22HE. However, it should be understood that for surface defects (or shallowly buried defects), analyzing the LERSEM image 22LE may effectively detect the defect. For example, if the defect is a protrusion of the gate metal MG, it may show strong contrast in the LERSEM image 22LE but low (or non-existent) contrast in the HE RSEM image 22HE. In addition, although Figure 7 An example of acquiring and analyzing two RSEM images 22 with two different accelerating beam energies is depicted, but this can be extended to acquiring and analyzing RSEM images with three (or more) different accelerating beam energies to provide further in-depth analysis to isolate the root cause defect at different depths.

[0090] As mentioned earlier, Figure 3 The operation represented by operation 84 is performed for each VC defect identified in operation 82. In operation 100, the defect data generated by running operation 84 for each VC defect is accumulated (e.g., stored in an array or other suitable data structure). In optional operation 102, the accumulated defect data is analyzed to determine whether to continue wafer processing (if the defect data indicates that the defect count is sufficiently low and / or the defect type is acceptable) or whether the wafer should be scrapped (in which case the wafer can be further analyzed and / or the semiconductor processing workflow can be reviewed to determine why the semiconductor wafer has an unacceptable defect count / type). Therefore, operation 100 requires accumulating defect information by repeating operation 82 (identifying VC defects in the voltage-contrast electron beam image 12 of the IC), operations 86 and 90 (locating at least one ROI in the RSEM image associated with the VC defect), and operations 92, 94, and 98 (analyzing at least one ROI in the RSEM image of the IC associated with multiple VC defects). In some embodiments, operation 102 includes determining that the IC passes inspection based on the accumulated defect information, and in response to determining that the IC passes inspection, performing additional semiconductor manufacturing processing of the IC (eg, completing BEOL processing and optional packaging of the IC in a non-limiting example).

[0091] Figure 2 and Figure 3 The processing can be done by Figure 1 The processing may be performed by a computer or other electronic processor 52, by a server computer 50, or by a combination of these systems 50 and 52 (e.g., the server computer 50 may perform computationally complex processing, such as implementing the machine learning model for operation 96, while the computer or other electronic processor 52 may perform less computationally complex processing, such as operation 86). These are merely non-limiting illustrative examples of some suitable processing hardware configurations.

[0092] Some further embodiments are described below.

[0093] In one non-limiting illustrative embodiment, a method for analyzing an integrated circuit (IC) is disclosed. The method includes acquiring a review scanning electron microscope (RSEM) image of the IC, acquiring a voltage-contrast electron beam image of the IC, rendering the layout image from a layout file describing a layout of the IC, using the layout image to determine a transformation between spatial coordinates of the RSEM image of the IC and spatial coordinates of the voltage-contrast electron beam image of the IC, identifying a voltage-contrast (VC) target pattern in the voltage-contrast electron beam image of the IC, locating at least one region of interest (ROI) associated with the VC target pattern in the RSEM image of the IC using the spatial transformation, and analyzing the at least one ROI in the RSEM image of the IC to generate defect information for the VC target pattern.

[0094] In one embodiment, determining a transformation between spatial coordinates of a RSEM image of an IC and spatial coordinates of a voltage-contrast electron beam image of the IC includes: processing a layout image to generate an RSEM characteristic layout image; processing the layout image to generate a voltage-contrast electron beam image characteristic layout image; determining a first spatial transformation that spatially aligns the voltage-contrast electron beam image and the voltage-contrast electron beam image characteristic layout image; and determining a second spatial transformation that spatially aligns the RSEM image of the IC and the RSEM characteristic layout image. The transformation between the spatial coordinates of the RSEM image of the IC and the spatial coordinates of the voltage-contrast electron beam image of the IC is derived from the first spatial transformation and the second spatial transformation.

[0095] In one embodiment, analyzing at least one ROI in the RSEM image of the IC includes: deriving features of the at least one ROI in the RSEM image; and analyzing the derived features for the at least one ROI to generate defect information of the VC target pattern.

[0096] In one embodiment, the at least one ROI in the RSEM image includes multiple ROIs in the RSEM image, deriving features of the at least one ROI in the RSEM image includes deriving one or more ROI features for each of the multiple ROIs, and analyzing the features derived for the at least one ROI includes: scoring each ROI based on the one or more ROI features derived from analyzing the ROI; and generating defect information of the VC target pattern based on the highest-scoring ROI among the multiple ROIs and / or based on the ROI features of the highest-scoring ROI.

[0097] In one embodiment, the RSEM image includes a low-energy RSEM image obtained using an electron beam having a first accelerating voltage and a high-energy RSEM image obtained using an electron beam having a second accelerating voltage higher than the first accelerating voltage. The defect information includes layer information of a root cause defect corresponding to a VC target pattern, the root cause defect being determined based on whether a highest-scoring ROI among a plurality of ROIs is in the low-energy RSEM image or the high-energy RSEM image.

[0098] In one embodiment, using a spatial transformation to locate at least one ROI associated with a VC target pattern in an RSEM image of an IC includes: locating the VC target pattern in the RSEM image using the spatial transformation; and locating each of the multiple ROIs in the RSEM image associated with a position in the VC target pattern in the RSEM image based on the layout image.

[0099] In one embodiment, identifying a VC target pattern in a voltage-contrast electron beam image of an IC includes applying a VC target pattern detection algorithm to a target type constructed to detect the VC target pattern; and deriving a feature of at least one ROI in the RSEM image includes deriving a feature indicating whether the associated VC target pattern is recognized by the defect detection algorithm of the target type constructed to detect the VC target pattern.

[0100] In one embodiment, identifying a VC target pattern in a voltage-contrast electron beam image of an IC includes applying a general VC target pattern detection algorithm to the voltage-contrast electron beam image and applying the VC target pattern detection algorithm to a target type constructed for detecting the VC target pattern. The identified VC target pattern includes a plurality of VC target patterns identified by the general VC target pattern detection algorithm and a plurality of VC target patterns identified by a VC target pattern detection algorithm constructed for detecting the VC target pattern.

[0101] In one embodiment, the target type of the VC target pattern is a gate metal protrusion, and a VC target pattern detection algorithm constructed to detect the gate metal protrusion performs contour extraction to detect the contour of the gate metal and applies a classifier to the contour of the gate metal to detect the VC target pattern caused by the gate metal protrusion.

[0102] In one embodiment, the RSEM image includes a plurality of RSEM images, wherein the plurality of RSEM images include: an RSEM image acquired by a secondary electron detector; and an RSEM image including an energy dispersive X-ray image acquired by an energy dispersive X-ray spectrometer.

[0103] In one non-limiting illustrative embodiment, a non-transitory storage medium stores instructions readable and executable by an electronic processor to perform a method for analyzing an IC based on a RSEM image of the IC and a voltage-contrast electron beam image of the IC. The method includes determining a transformation between spatial coordinates of the RSEM image of the IC and the spatial coordinates of the voltage-contrast electron beam image of the IC using a layout image depicting a base layout of the IC design, identifying a VC defect in the voltage-contrast electron beam image of the IC, locating a region of interest (ROI) associated with the VC defect in the RSEM image of the IC using the spatial transformation, and analyzing the ROI in the RSEM image of the IC to determine a root cause of the VC defect.

[0104] In one embodiment, determining a transformation between spatial coordinates of a RSEM image of an IC and spatial coordinates of a voltage-contrast electron beam image of the IC includes: determining a first spatial transformation that spatially aligns the voltage-contrast electron beam image and the layout image; and determining a second spatial transformation that spatially aligns the RSEM image of the IC and the layout image. The transformation between the spatial coordinates of the RSEM image of the IC and the spatial coordinates of the voltage-contrast electron beam image of the IC is derived from the first spatial transformation and the second spatial transformation.

[0105] In one embodiment, analyzing multiple regions of interest in an RSEM image of an IC to determine the root cause of a voltage contrast defect includes: deriving one or more region of interest features for each region of interest in the RSEM image associated with the voltage contrast defect to be analyzed; scoring each region of interest associated with the voltage contrast defect to be analyzed by analyzing the one or more region of interest features derived from each region of interest; identifying the region of interest associated with the voltage contrast defect to be analyzed with the highest score based on the score; and determining the root cause of the voltage contrast defect to be analyzed based at least in part on the identification of the region of interest with the highest score.

[0106] In one embodiment, the RSEM image includes a low-energy RSEM image obtained using an electron beam having a first accelerating voltage and a high-energy RSEM image obtained using an electron beam having a second accelerating voltage higher than the first accelerating voltage. The root cause of the voltage contrast defect to be analyzed is determined at least in part based on whether the region of interest with the highest score is in the low-energy RSEM image or the high-energy RSEM image.

[0107] In one embodiment, scoring each region of interest associated with the voltage contrast defect to be analyzed includes inputting one or more region of interest features derived for the region of interest into a machine learning algorithm and, in response, receiving a score for the region of interest from the machine learning algorithm.

[0108] In one embodiment, locating the plurality of regions of interest in the RSEM image of the IC using spatial transformation includes, for each voltage contrast defect: locating the voltage contrast defect in the RSEM image using spatial transformation; and locating each region of interest in the RSEM image in association with a position of the voltage contrast defect in the RSEM image based on the layout image.

[0109] In one non-limiting illustrative embodiment, an apparatus for analyzing an IC is disclosed. The apparatus includes a scanning electron microscope configured to acquire a RSEM image of an associated IC; a voltage-contrast electron beam microscope configured to acquire a voltage-contrast electron beam image of an associated IC; and an electronic processor. The electronic processor is programmed to perform a method comprising: determining a transformation between spatial coordinates of an RSEM image of the IC and spatial coordinates of a voltage-contrast electron beam image of the IC using a layout image depicting a base layout of an IC design; identifying voltage-contrast (VC) target patterns in the voltage-contrast electron beam image of the IC; locating regions of interest (ROIs) associated with the VC target patterns in the RSEM image of the IC using the layout image; and analyzing the ROIs associated with each VC target pattern in the RSEM image of the IC to generate VC target pattern information.

[0110] In one embodiment, analyzing the multiple ROIs associated with each of the multiple VC target patterns in the RSEM image of the IC to generate information about the VC target pattern includes: deriving one or more ROI features for each ROI in the RSEM image associated with the VC target pattern; scoring each ROI associated with the VC target pattern by analyzing the one or more ROI features derived from each ROI; and identifying the ROI with the highest score.

[0111] In one embodiment, scoring each ROI associated with the VC target pattern includes inputting one or more ROI features derived for the ROI into a machine learning algorithm and responsively receiving a score for the ROI from the machine learning algorithm.

[0112] In one embodiment, the plurality of ROIs associated with the VC target pattern correspond to locations in an RSEM image of the IC, the locations in the RSEM image of the IC being correlated to locations of the VC target pattern in the RSEM image of the IC. The information about the VC target pattern includes a root cause of the VC target pattern determined at least in part based on the highest-scoring ROI.

[0113] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis to design or modify other processes and structures to achieve the same purposes and / or obtain the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for analyzing an integrated circuit, characterized in that: The method comprises: obtaining a re-inspection scanning electron microscope image of the integrated circuit; acquiring a voltage-contrast electron beam image of the integrated circuit; rendering a layout image based on a layout file describing a layout of the integrated circuit; using the layout image to determine a transformation between spatial coordinates of the review SEM image of the integrated circuit and spatial coordinates of a voltage-contrast electron beam image of the integrated circuit; identifying a voltage-contrast target pattern in a voltage-contrast electron beam image of the integrated circuit; using the spatial transformation to locate at least one region of interest associated with the voltage contrast target pattern in the review scanning electron microscope image of the integrated circuit; and The at least one region of interest in the review SEM image of the integrated circuit is analyzed to generate defect information of the voltage-versus-target pattern.

2. The method according to claim 1, characterized in that Determining a conversion between the spatial coordinates of the review SEM image of the integrated circuit and the spatial coordinates of the voltage-contrast electron beam image of the integrated circuit includes: processing the layout image to generate a review scanning electron microscope characteristic layout image; processing the layout image to generate a voltage-contrast electron beam image characteristic layout image; determining a first spatial transformation that spatially aligns the voltage-contrast electron beam image and the voltage-contrast electron beam image characteristic layout image; and determining a second spatial transformation that spatially aligns the reviewed SEM image and the reviewed SEM feature layout image of the integrated circuit; The transformation between the spatial coordinates of the review scanning electron microscope image of the integrated circuit and the spatial coordinates of the voltage-contrast electron beam image of the integrated circuit is derived from the first spatial transformation and the second spatial transformation.

3. The method according to claim 1, characterized in that Analyzing the at least one region of interest in the review scanning electron microscope image of the integrated circuit comprises: deriving characteristics of the at least one region of interest in the reviewed scanning electron microscope image; and The features derived for the at least one region of interest are analyzed to generate defect information for the voltage-versus-target pattern.

4. The method according to claim 3, characterized in that The at least one region of interest in the reviewed scanning electron microscope image includes a plurality of regions of interest in the reviewed scanning electron microscope image, deriving the feature of the at least one region of interest in the reviewed scanning electron microscope image includes deriving one or more region of interest features for each of the plurality of regions of interest, and analyzing the features derived for the at least one region of interest includes: scoring each region of interest by analyzing one or more region of interest features derived for the region of interest; and Defect information of the voltage-versus-target pattern is generated based on a highest-scoring ROI among the plurality of ROIs and / or based on ROI features of the highest-scoring ROI.

5. The method according to claim 4, characterized in that: The review SEM image includes a low-energy review SEM image obtained using an electron beam having a first accelerating voltage, and a high-energy review SEM image obtained using an electron beam having a second accelerating voltage higher than the first accelerating voltage, and The defect information includes layer information of a root cause defect corresponding to the voltage-versus-target pattern, the root cause defect being determined based on whether a highest-scoring region of interest among the plurality of regions of interest is in the low-energy review scanning electron microscope image or the high-energy review scanning electron microscope image.

6. A non-transient storage medium, characterized in that The non-transitory storage medium is configured to store instructions readable and executable by an electronic processor to perform a method for analyzing an integrated circuit based on a review scanning electron microscope image of the integrated circuit and a voltage contrast electron beam image of the integrated circuit, the method comprising: determining a transformation between spatial coordinates of the review SEM image of the integrated circuit and spatial coordinates of a voltage-contrast electron beam image of the integrated circuit using a layout image depicting a design basis layout of the integrated circuit; identifying voltage contrast defects in a voltage contrast electron beam image of the integrated circuit; using spatial transformation to locate a plurality of regions of interest associated with respective ones of the voltage contrast defects in the review scanning electron microscope image of the integrated circuit; and The plurality of regions of interest in the review SEM image of the integrated circuit are analyzed to determine a root cause of the voltage contrast defect.

7. The non-transitory storage medium according to claim 6, wherein: Determining the conversion between the spatial coordinates of the review SEM image of the integrated circuit and the spatial coordinates of the voltage-contrast electron beam image of the integrated circuit includes: determining a first spatial transformation that spatially aligns a voltage-contrast electron beam image with the layout image; and determining a second spatial transformation that spatially aligns the review SEM image and the layout image of the integrated circuit; The transformation between the spatial coordinates of the review SEM image of the integrated circuit and the spatial coordinates of the voltage-contrast electron beam image of the integrated circuit is derived from the first spatial transformation and the second spatial transformation.

8. The non-transitory storage medium according to claim 6, wherein: Analyzing the plurality of regions of interest in the review scanning electron microscope image of the integrated circuit to determine the root cause of the voltage contrast defect includes: deriving one or more region of interest features for each region of interest in the reviewed scanning electron microscope image associated with the voltage contrast defect to be analyzed; scoring each region of interest associated with the voltage contrast defect to be analyzed by analyzing one or more region of interest features derived from each region of interest; Based on the scores, identifying a highest scoring region of interest associated with a voltage contrast defect to be analyzed; and Based at least in part on the identification of the highest scoring region of interest, the root cause of the voltage contrast defect to be analyzed is determined.

9. The non-transitory storage medium according to claim 6, wherein: Locating the plurality of regions of interest in the review SEM image of the integrated circuit using the spatial transformation includes, for each voltage contrast defect: locating the voltage contrast defect in the review SEM image using the spatial transformation; and Each region of interest in the review SEM image is located relative to a location of the voltage contrast defect in the review SEM image based on the layout image.

10. A detection device for analyzing integrated circuits, characterized in that: The detection device comprises: a scanning electron microscope configured to obtain a review scanning electron microscope image associated with the integrated circuit; a voltage-contrast electron beam microscope configured to acquire the voltage-contrast electron beam image associated with the integrated circuit; and An electronic processor programmed to perform a method comprising: determining a transformation between spatial coordinates of the review SEM image of the integrated circuit and spatial coordinates of a voltage-contrast electron beam image of the integrated circuit using a layout image depicting a design basis layout of the integrated circuit; identifying a voltage-contrast target pattern in a voltage-contrast electron beam image of the integrated circuit; locating a plurality of regions of interest associated with a plurality of voltage contrast target patterns in the review scanning electron microscope image of the integrated circuit using the layout image; and The regions of interest associated with each of the voltage-versus-target patterns in the review SEM image of the integrated circuit are analyzed to generate information of the voltage-versus-target pattern.

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