Load control circuit and display panel

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a load control circuit and a display panel, and the load control circuit comprises a delay control module which is used for outputting a first control signal during power-on, and continuously outputting a second control signal after outputting the first control signal for a preset time length; the first control module is used for sending light-load display data or a power-on clock signal to the source electrode driving circuit and the grid electrode driving circuit under the action of the first control signal; the second control module is used for sending normal display data or a normal clock signal to the source electrode driving circuit or the grid electrode driving circuit under the action of the second control signal; therefore, the problem of startup abnormity caused by startup heavy load voltage drop is solved by providing light load display data during power-on or / and reducing the refresh frequency of the panel during power-on.

Description

Technical Field

[0001] The present disclosure belongs to the field of display drive technology, and particularly relates to a load control circuit and a display panel. Background Art

[0002] During the startup phase of an electronic product, each load module must switch from zero to full load in a very short period of time. This instantaneous load current surges dramatically, a phenomenon known as startup inrush current. According to the power equation P = UI, this sudden increase in load current (I) causes a significant drop in the supply voltage (U), resulting in a transient voltage drop.

[0003] Currently, when the display panel encounters a heavy-load display screen during startup, a large transient voltage drop will occur. The voltage drop may exceed the lower limit of the normal operating voltage, causing the core chip to trigger the undervoltage protection mechanism, resulting in abnormal phenomena such as startup failure.

[0004] Therefore, how to improve the abnormal phenomenon caused by heavy-load voltage drop during startup is an urgent problem to be solved. Summary of the Invention

[0005] The present application provides a load control circuit and a display panel, which solves the problem of abnormal startup caused by heavy load voltage drop when the power is turned on by providing light load display data and / or reducing the refresh frequency of the panel when power is turned on.

[0006] In a first aspect, an embodiment of the present application provides a load control circuit, which is applied to a display panel, wherein the display panel includes a timing controller, a source drive circuit, and a gate drive circuit. The load control circuit includes: a delay control module, which is used to output a first control signal when powered on, and continuously output a second control signal after outputting the first control signal for a preset time length; a first control module, wherein the control end of the first control module is connected to the output end of the delay control module, the first end of the first control module is connected to the output end of the timing controller, and the second end of the first control module is connected to the source drive circuit or the gate drive circuit. The first control module is used to send the light-load display data output by the timing controller to the display panel under the action of the first control signal. to the source drive circuit, or sends the power-on clock signal with a first clock frequency output by the timing controller to the gate drive circuit; a second control module, the control end of the second control module is connected to the output end of the delay control module, the first end of the second control module is connected to the output end of the timing controller, and the second end of the second control module is connected to the source drive circuit or the gate drive circuit, and the second control module is used to send the normal display data output by the timing controller to the source drive circuit or the normal clock signal with a second clock frequency output by the timing controller to the gate drive circuit under the action of the second control signal; wherein, the first clock frequency is less than the second clock frequency.

[0007] Optionally, the delay control module includes: a first resistor, wherein the first end of the first resistor is connected to the output end of the external power supply; a first capacitor, wherein the first end of the first capacitor is connected to the second end of the first resistor, and the second end of the first capacitor is grounded; a first transistor, wherein the control end of the first transistor is connected to the first end of the first capacitor; a second resistor, wherein the first end of the second resistor is grounded, and the second end of the second resistor is connected to the first end of the first transistor; a third resistor, wherein the first end of the third resistor is connected to the output end of the external power supply; a second transistor, wherein the control end of the second transistor is connected to the control end of the first transistor, the first end of the second transistor is connected to the second end of the third resistor, and the second end of the second transistor is connected to the second end of the first transistor; wherein the turn-on voltage of the first transistor is a low level, the turn-on voltage of the second transistor is a high level, and the second end of the first transistor or the second end of the second transistor is used as the output end of the delay control module.

[0008] Optionally, the delay control module includes: a differential amplifier, a first input terminal of the differential amplifier is connected to the reference voltage output terminal, and a second input terminal of the differential amplifier is connected to the power supply terminal of the timing controller, for amplifying the difference between the current power supply voltage on the power supply terminal of the timing controller and the reference voltage; a comparator, a first input terminal of the comparator is connected to the reference threshold terminal, and a second input terminal of the comparator is connected to the output terminal of the differential amplifier, for outputting the first control signal or the second control signal according to the comparison result between the voltage difference output by the differential amplifier and the reference threshold.

[0009] Optionally, the delay control module includes: an exclusive-OR gate, a first input terminal of the exclusive-OR gate is connected to the voltage output terminal at the first moment, a second input terminal of the exclusive-OR gate is connected to the voltage output terminal at the second moment, and the output terminal of the exclusive-OR gate serves as the output terminal of the delay control module; wherein, the voltage output terminal at the first moment is used to output the first power supply voltage of the power supply terminal of the timing controller at time t, and the voltage output terminal at the second moment is used to output the second power supply voltage of the power supply terminal of the timing controller at time t+N.

[0010] Optionally, the first control module includes a third transistor, the control end of the third transistor is connected to the output end of the delay control module, the first end of the third transistor is connected to the first output end of the timing controller, and the second end of the third transistor is connected to the source drive circuit or the gate drive circuit; the second control module includes a fourth transistor, the control end of the fourth transistor is connected to the output end of the delay control module, the first end of the fourth transistor is connected to the second output end of the timing controller, and the second end of the fourth transistor is connected to the source drive circuit or the gate drive circuit; wherein, the turn-on voltages of the third transistor and the fourth transistor are opposite.

[0011] Optionally, the first control module includes: an inverter, the input end of the inverter is connected to the output end of the delay control module, and is used to invert the output signal of the delay control module; a first AND gate, the first input end of the first AND gate is connected to the first output end of the timing controller, the second input end of the first AND gate is connected to the output end of the inverter, and the output end of the first AND gate is connected to the source drive circuit or the gate drive circuit, and is used to send the light-load display data or power-on clock signal output by the timing controller to the source drive circuit or the gate drive circuit respectively when a high level is received at the second input end.

[0012] Optionally, the second control module includes: a fifth transistor, the control end of the fifth transistor is connected to the output end of the delay control module, and the first end of the fifth transistor is connected to the enable end of the timing controller; a second AND gate, the first input end of the second AND gate is connected to the second end of the fifth transistor, the second input end of the second AND gate is connected to the output end of the timing controller, and the output end of the second AND gate is connected to the source drive circuit or the gate drive circuit; the second AND gate is used to send the normal display data or normal clock signal output by the timing controller to the source drive circuit or the gate drive circuit when a high level is received at the first input end.

[0013] Optionally, the display panel further includes M clock signal lines, wherein both ends of the 2m-1th clock signal line are respectively connected to the 2m-1th clock signal output end of the timing controller and the 2m-1th clock signal receiving end of the gate drive circuit; the load control circuit further includes: a plurality of control transistors, wherein the control end of the mth control transistor is connected to the output end of the delay control module, the first end of the mth control transistor is connected to the 2mth clock signal output end of the timing controller, and the second end of the mth control transistor is electrically connected to one end of the 2mth clock signal line; wherein the other end of the 2mth clock signal line is connected to the 2mth clock signal receiving end of the gate drive circuit;

[0014] Alternatively, the display panel further includes M clock signal lines, and both ends of the 2mth clock signal line are respectively connected to the 2mth clock signal output end of the timing controller and the 2mth clock signal receiving end of the gate drive circuit, and the load control circuit further includes: a plurality of control tubes, the control end of the mth control tube is connected to the output end of the delay control module, the first end of the mth control tube is connected to the 2m-1th clock signal output end of the timing controller, and the second end of the mth control tube is electrically connected to one end of the 2m-1th clock signal line; wherein, the other end of the 2m-1th clock signal line is connected to the 2m-1th clock signal receiving end of the gate drive circuit; wherein, M is an integer greater than 1.

[0015] Optionally, the load control circuit also includes: a sixth transistor, the control end of the sixth transistor is connected to the output end of the delay control module, and the first end of the sixth transistor is connected to the output end of the external power supply; a seventh transistor, the control end of the seventh transistor is connected to the control end of the sixth transistor, the first end of the seventh transistor is connected to the second end of the sixth transistor, and the second end of the seventh transistor is grounded; a first inductor, the first end of the first inductor is connected to the first end of the seventh transistor, and the second end of the first inductor is connected to the power supply end of the subsequent load; a second capacitor, the first end of the second capacitor is connected to the second end of the first inductor, and the second end of the second capacitor is grounded; wherein, the turn-on voltages of the sixth transistor and the seventh transistor are opposite.

[0016] In a second aspect, an embodiment of the present application provides a display panel comprising a display area and a non-display area, wherein the display area comprises a pixel array; the non-display area comprises a timing controller, a gate drive circuit, a source drive circuit and a load control circuit, and the load control circuit is electrically connected to the timing controller, the gate drive circuit and / or the source drive circuit respectively.

[0017] The technical solution provided by this application has at least the following beneficial effects:

[0018] The first control module in the present application sends the light-load display data output by the timing controller to the source drive circuit according to the first control signal output by the delay control module when powered on, so that the source drive circuit drives the pixels in the display panel to perform low-load display according to the light-load display data, or / and sends the low-frequency power-on clock signal output by the timing controller to the gate drive circuit, so that the gate drive circuit drives the scan lines in the display panel to open row by row according to the power-on clock signal, thereby reducing the refresh rate of the display panel, thereby avoiding the problem of a sharp increase in load current, thereby achieving normal power-on of the display panel; in addition, After powering on for a preset period of time, the second control module sends the normal display data output by the timing controller to the source drive circuit according to the second control signal output by the delay control module, so that the source drive circuit drives the pixels in the display panel for normal display according to the normal display data, or / and sends the normal clock signal output by the timing controller to the gate drive circuit, so that the gate drive circuit drives the pixels in the display panel for normal display according to the normal clock signal; therefore, the present application solves the problem of abnormal startup caused by heavy-load voltage drop when powering on by providing light-load display data when powering on or / and reducing the refresh frequency of the panel when powering on. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0020] Figure 1 Shown is a structural schematic diagram of the first load control circuit provided in an embodiment of the present application.

[0021] Figure 2 Shown is a structural schematic diagram of a second load control circuit provided in an embodiment of the present application.

[0022] Figure 3 Shown is a circuit diagram of a first load control circuit provided in an embodiment of the present application.

[0023] Figure 4 Shown is a circuit diagram of a second load control circuit provided in an embodiment of the present application.

[0024] Figure 5 Shown is a circuit diagram of a third load control circuit provided in an embodiment of the present application.

[0025] Figure 6 Shown is a circuit diagram of a fourth load control circuit provided in an embodiment of the present application.

[0026] Figure 7 Shown is a circuit diagram of the fifth load control circuit provided in an embodiment of the present application.

[0027] Figure 8 Shown is a schematic diagram of a clock signal provided in an embodiment of the present application.

[0028] Figure 9 Shown is a circuit diagram of the sixth load control circuit provided in an embodiment of the present application.

[0029] Description of reference numerals:

[0030] 100, load control circuit; 110, delay control module; 120, first control module; 130, second control module; 200, timing controller; 300, source drive circuit; 400, gate drive circuit; 500, clock signal line; 600, external power supply; 700, subsequent load;

[0031] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; Tc, control tube; R1, first resistor; R2, second resistor; R3, third resistor; C1, first capacitor; C2, second capacitor; L1, first inductor; U1, differential amplifier; U2, comparator; U3, XNOR gate; U4, inverter; U5, first AND gate; U6, second AND gate. DETAILED DESCRIPTION

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0033] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0034] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0035] In a first aspect, embodiments of the present application provide a load control circuit, specifically including the following embodiments:

[0036] Figure 1 FIG. 1 is a schematic diagram showing the structure of a first load control circuit provided in an embodiment of the present application; FIG. Figure 1 As shown, the load control circuit 100 includes a delay control module 110 for outputting a first control signal when powered on, and continuously outputting a second control signal after outputting the first control signal for a preset time period.

[0037] It should be noted that the load control circuit 100 of this embodiment can be applied to a display panel, which includes at least a timing controller and a source driver circuit; when the display panel is turned on, that is, when the load control circuit 100 is powered on, the delay control module 110 outputs a first control signal; after the delay control module 110 outputs the first control signal of a preset duration, it continuously outputs a second control signal; wherein, the first control signal and the second control signal have opposite phases, that is, when the first control signal is low, the second control signal is high; conversely, when the first control signal is high, the second control signal is low. In addition, the preset duration can be a fixed duration, for example, after the delay control module 110 outputs the first control signal of 1 second, it continuously outputs the second control signal; the preset duration can also be a duration obtained by dynamic detection based on a specific application scenario.

[0038] In this embodiment, the load control circuit 100 also includes a first control module 120, the control end of the first control module 120 is connected to the output end of the delay control module 110, the first end of the first control module 120 is connected to the first output end of the timing controller 200, and the second end of the first control module 120 is connected to the source drive circuit 300, and is used to send the light-load display data output by the timing controller 200 to the source drive circuit 300 under the action of the first control signal.

[0039] In this embodiment, the first control module 120 is used to receive the first control signal output by the delay control module 110, and is also used to send the light-load display data output by the timing controller 200 to the source drive circuit 300 under the action of the first control signal, so that the source drive circuit 300 drives the pixels in the display panel to perform low-load display according to the light-load display data; specifically, if the normal display data is a heavy-load screen when power is turned on, a large transient voltage drop will be generated, resulting in problems such as power-on failure or display abnormality; to this end, in this embodiment, through the first control signal output by the delay control module 110 when power is turned on, the first control module 120 sends the light-load display data output by the timing controller 200 to the source drive circuit 300, so that the source drive circuit 300 drives the pixels in the display panel to perform low-load display according to the light-load display data, that is: when the display panel displays light-load display data (i.e., low-load display data) when the power is turned on, there will be no problem of a sharp increase in load current, thereby achieving normal power-on of the display panel.

[0040] In this embodiment, the load control circuit 100 also includes a second control module 130, the control end of the second control module 130 is connected to the output end of the delay control module 110, the first end of the second control module 130 is connected to the second output end of the timing controller 200, and the second end of the second control module 130 is connected to the source drive circuit 300, and is used to send the normal display data output by the timing controller 200 to the source drive circuit 300 under the action of the second control signal.

[0041] It should be noted that after a certain period of power-on, the second control module 130, under the action of the second control signal output by the delay control module 110, sends the normal display data output by the timing controller 200 to the source driver circuit 300, so that the source driver circuit 300 drives the pixels in the display panel to display normally according to the normal display data.

[0042] It is worth noting that when the delay control module 110 outputs the first control signal, the second control module 130 does not operate; similarly, when the delay control module 110 outputs the second control signal, the first control module 120 does not operate.

[0043] In summary, it can be seen that the first control module 120 in the present application sends the light-load display data output by the timing controller 200 to the source drive circuit 300 according to the first control signal output by the delay control module 110 when power is turned on, so that the source drive circuit 300 drives the pixels in the display panel to perform low-load display according to the light-load display data, and the problem of a sharp increase in load current will not occur, thereby achieving normal startup of the display panel; after the preset power-on time, the second control module 130 sends the normal display data output by the timing controller 200 to the source drive circuit 300 according to the second control signal output by the delay control module 110, so that the source drive circuit 300 drives the pixels in the display panel to perform normal display according to the normal display data; therefore, the present application can solve the problem of abnormal startup caused by heavy-load voltage drop when power is turned on by providing light-load display data when power is turned on and restoring the input of normal display data after the power is stable.

[0044] Figure 2 FIG2 is a structural diagram of a second load control circuit provided in an embodiment of the present application; Figure 2 The embodiment shown is Figure 1 The difference lies in: the type of the output signal of the timing controller is different, and the loads connected to the second ends of the first control module and the second control module are different; Figure 2 As shown, the load control circuit 100 includes a delay control module 110 for outputting a first control signal when powered on, and continuously outputting a second control signal after outputting the first control signal for a preset time. The working principle of the load control circuit 100 provided in this embodiment is similar to that of the above embodiment ( Figure 1 The embodiment shown in FIG. 1 is the same as that shown in FIG. 1 , and will not be described in detail here.

[0045] In this embodiment, the load control circuit 100 also includes a first control module 120, the control end of the first control module 120 is connected to the output end of the delay control module 110, the first end of the first control module 120 is connected to the third output end of the timing controller 200, and the second end of the first control module 120 is connected to the gate drive circuit 400, and is used to send the power-on clock signal LX1 with a first clock frequency output by the timing controller 200 to the gate drive circuit 400 under the action of the first control signal, so that the gate drive circuit 400 drives the scan lines in the display panel to open row by row according to the power-on clock signal LX1.

[0046] In this embodiment, the first clock frequency is lower than the clock frequency during normal display, thereby achieving the purpose of reducing the refresh rate of the display panel; specifically, if the display data is a heavy-loaded screen when power is turned on, a large transient voltage drop will be generated, resulting in problems such as startup failure or display abnormality; to this end, this embodiment delays the first control signal output by the control module 110 when power is turned on, so that the first control module 120 sends the low-frequency power-on clock signal output by the timing controller 200 to the gate drive circuit 400, so that the gate drive circuit 400 drives the scan lines in the display panel to open row by row according to the power-on clock signal, thereby reducing the refresh rate of the display panel and avoiding the problem of a sharp increase in load current, thereby achieving normal startup of the display panel.

[0047] In this embodiment, the load control circuit 100 also includes a second control module 130, the control end of the second control module 130 is connected to the output end of the delay control module 110, the first end of the second control module 130 is connected to the fourth output end of the timing controller 200, and the second end of the second control module 130 is connected to the gate drive circuit 400, and is used to send the normal clock signal LX2 with the second clock frequency output by the timing controller 200 to the gate drive circuit 400 under the action of the second control signal.

[0048] It should be noted that the second clock frequency can be used as the clock frequency for normal display, that is, the second clock frequency is greater than the first clock frequency; after a certain period of power-on, the second control module 130, under the action of the second control signal output by the delay control module 110, sends the normal clock signal LX2 output by the timing controller 200 to the gate drive circuit 400, so that the gate drive circuit 400 drives the pixels in the display panel for normal display according to the normal clock signal.

[0049] In summary, it can be seen that the first control module 120 in the present application sends the low-frequency power-on clock signal output by the timing controller 200 to the gate drive circuit 400 according to the first control signal output by the delay control module 110 when powered on, so that the gate drive circuit 400 drives the scan lines in the display panel to open row by row according to the power-on clock signal, reduces the refresh rate of the display panel, avoids the problem of a sharp increase in load current, and thus realizes normal startup of the display panel; after the preset power-on time, the second control module 130 sends the normal clock signal output by the timing controller 200 to the gate drive circuit 400 according to the second control signal output by the delay control module 110, so that the gate drive circuit 400 drives the pixels in the display panel for normal display according to the normal clock signal; therefore, the present application can solve the problem of abnormal startup caused by overload voltage drop when the power is on by reducing the refresh frequency of the panel when powered on and restoring the normal refresh frequency after the power is stable.

[0050] Combine Figure 1 and Figure 2 It can be seen that the present application can set the load control circuit 100 between the timing controller 200 and the source drive circuit 300, and improve the problem of heavy-load voltage drop when the power is turned on by providing light-load display data when power is turned on; the present application can also set the load control circuit 100 between the timing controller 200 and the gate drive circuit 400, and improve the problem of heavy-load voltage drop when the power is turned on by reducing the panel refresh frequency when power is turned on; the present application can also set the load control circuit 100 between the timing controller 200 and the source drive circuit 300, and between the timing controller 200 and the gate drive circuit 400, so that the problem of heavy-load voltage drop when the power is turned on can be improved by providing light-load display data and reducing the refresh rate at the same time.

[0051] Figure 3 FIG. 1 is a circuit diagram of a first load control circuit provided in an embodiment of the present application; FIG. Figure 3 As shown, the delay control module 110 of this embodiment includes a first resistor R1, a first capacitor C1, a first transistor T1, a second resistor R2, a third resistor R3 and a second transistor T2; specifically, the first end of the first resistor R1 is connected to the output end of the external power supply; the first end of the first capacitor C1 is connected to the second end of the first resistor R1, and the second end of the first capacitor C1 is grounded; the control end of the first transistor T1 is connected to the first end of the first capacitor C1; the first end of the second resistor R2 is grounded, and the second end of the second resistor R2 is connected to the first end of the first transistor T1; the first end of the third resistor R3 is connected to the output end of the external power supply; the control end of the second transistor T2 is connected to the control end of the first transistor T1, the first end of the second transistor T2 is connected to the second end of the third resistor R3, and the second end of the second transistor T2 is connected to the second end of the first transistor T1.

[0052] In addition, the turn-on voltage of the first transistor T1 is a low level, which can be understood as the first transistor T1 being a P-type MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor), and the turn-on voltage of the second transistor T2 is a high level, which can be understood as the second transistor T2 being an N-type MOS transistor, and the second end of the second transistor T2 or the second end of the first transistor T1 is used as the output end of the delay control module 110.

[0053] It should be noted that the specific working principle of the delay control module 110 provided in this embodiment is as follows:

[0054] (1) Initial power-on period: The storage voltage on the first capacitor C1 is 0 V, that is, the gate voltage (i.e., the control terminal voltage) of the first transistor T1 and the gate voltage of the second transistor T2 are both equal to 0 V, then the first transistor T1 is turned on and the second transistor T2 is turned off, so that the first control signal output by the delay control module 110 is at a low level;

[0055] (2) Charging process: After power-on, the output voltage of the external power supply charges the first capacitor C1 through the first resistor R1, and the gate voltage of the first transistor T1 gradually increases. When the gate voltage increases to the turn-off voltage of the first transistor T1, the first transistor T1 is disconnected and the second transistor T2 is turned on, so that the second control signal output by the delay control module 110 is high.

[0056] In this embodiment, the delay time from a low level to a high level is mainly determined by the first resistor R1 and the first capacitor C1; therefore, the delay time (i.e., the preset duration) can be flexibly set by adjusting the parameter values of the first resistor R1 and the first capacitor C1; wherein, the second resistor R2 in this embodiment has a pull-down effect, causing the second end of the first transistor T1 to output a low level when the first transistor T1 is turned on; the third resistor R3 in this embodiment has a pull-up effect, causing the second end of the second transistor T2 to output a high level when the second transistor T2 is turned on.

[0057] It should also be noted that the external power supply has multiple output terminals, and the voltage output by each output terminal can be the same or different; Figure 3 As shown, the first end of the first resistor R1 is connected to the output terminal VDD1 of the external power supply, and the first end of the second resistor R2 is connected to the output terminal VDD2 of the external power supply; the output voltages of the output terminal VDD1 and the output terminal VDD2 can be the same or different; in addition, the first end of the first resistor R1 and the first end of the second resistor R2 can be connected to the same output terminal of the external power supply.

[0058] like Figure 3As shown, the first control module 120 of this embodiment includes a third transistor T3, the control end of the third transistor T3 is connected to the output end of the delay control module 110, the first end of the third transistor T3 is connected to the first output end of the timing controller 200, and the second end of the third transistor T3 is connected to the source drive circuit 300.

[0059] The second control module 130 of this embodiment includes a fourth transistor T4, the control end of the fourth transistor T4 is connected to the output end of the delay control module 110, the first end of the fourth transistor T4 is connected to the second output end of the timing controller 200, and the second end of the fourth transistor T4 is connected to the source driver circuit 300.

[0060] Here, the first output terminal of the timing controller 200 outputs the light-load display data D0 , and the second output terminal of the timing controller 200 outputs the normal display data. In addition, the turn-on voltages of the third transistor T3 and the fourth transistor T4 of this embodiment are opposite.

[0061] It should be noted that, in this embodiment, the third transistor T3 is a P-type MOS tube and the fourth transistor T4 is an N-type MOS tube. When the power is on, the first control signal output by the delay control module 110 is a low level, the third transistor T3 is turned on, and the fourth transistor T4 is turned off, so that the light-load display data D0 output by the first output end of the timing controller 200 is transmitted to the source driver circuit 300 through the turned-on third transistor T3; after the power-on preset time, the second control signal output by the delay control module 110 is a high level, the third transistor T3 is turned off, and the fourth transistor T4 is turned on, so that the second output end of the timing controller 200 is transmitted to the source driver circuit 300 through the turned-on fourth transistor T4. The normal display data D0 outputted from the output end is transmitted to the source driving circuit 300. Since the light-load display data can be a black screen or a low grayscale screen, the normal display screen is outputted after the power-on gradually stabilizes, which is equivalent to using a step to first raise the display screen to the first step and then from the first step to the second step, thereby dividing a process into two sections and reducing the instantaneous load. Furthermore, during the period when the delay control module outputs the first control signal, the light-load display data includes a plurality of display data, which are increased from low load to high load by inserting different screens or grayscale displays, thereby solving the problem of abnormal startup caused by heavy-load voltage drop and improving the stability of the startup screen.

[0062] In another embodiment, the first end of the third transistor T3 can also be connected to the third output end of the timing controller 200, and the second end of the third transistor T3 is connected to the gate drive circuit 400; the first end of the fourth transistor T4 can also be connected to the fourth output end of the timing controller 200, and the second end of the fourth transistor T4 is connected to the gate drive circuit 300. It should be noted that in this embodiment, the third output end of the timing controller outputs a power-on clock signal with a first clock frequency, and the fourth output end of the timing controller outputs a normal clock signal with a second clock frequency; the working principles of the third transistor T3 and the fourth transistor T4 in this embodiment are the same as those in the embodiment. Figure 3 The only difference is that the first end and the second end of each transistor are connected to different objects, which will not be described here.

[0063] Figure 4 FIG. 1 is a circuit diagram of a second load control circuit provided in an embodiment of the present application; Figure 4 and Figure 3 The difference lies in the specific structure of the delay control module 110; Figure 4 As shown, the delay control module 110 of this embodiment includes a differential amplifier U1 and a comparator U2; the first input terminal of the differential amplifier U1 is connected to the reference voltage output terminal, and the second input terminal of the differential amplifier U1 is connected to the power supply terminal of the timing controller 200, and is used to amplify the difference between the current power supply voltage Vin on the power supply terminal of the timing controller and the reference voltage Vref; the first input terminal of the comparator U2 is connected to the reference threshold terminal, and the second input terminal of the comparator U2 is connected to the output terminal of the differential amplifier U1, and is used to output a first control signal or a second control signal according to the comparison result between the voltage difference output by the differential amplifier U1 and the reference threshold Vth.

[0064] It should be noted that the reference voltage output terminal can be an output terminal of the timing controller, or an output terminal of an external power supply or an output terminal of another processor. The reference voltage Vref outputted by the reference voltage output terminal can be the normal supply voltage of the external power supply. In the initial power-on phase, if the current power supply voltage Vin is less than the reference voltage Vref due to a power-on load draw, the difference between the current power supply voltage and the reference voltage is amplified by the differential amplifier U1, and the voltage difference is then input into the comparator U2 for comparison with the reference threshold Vth. When the voltage difference is greater than the reference threshold, the comparator U2 outputs a first control signal. Conversely, when the voltage difference is less than or equal to the reference threshold, the comparator U2 outputs a second control signal. In this embodiment, the reference threshold can be set based on the amplification factor of the differential amplifier U1. In addition, the reference threshold terminal can be a voltage output terminal of the timing controller 200, or a triangle wave or square wave output terminal. Figure 4 The working principle of the third transistor T3 and the fourth transistor T4 is the same as Figure 2 The same, no longer repeated here.

[0065] Figure 5 FIG. 1 is a circuit diagram of a third load control circuit provided in an embodiment of the present application; Figure 5 and Figure 2 The difference lies in the specific structure of the delay control module 110; Figure 5 As shown, the delay control module 110 of this embodiment includes an XOR gate U3, a first input terminal of the XOR gate U3 is connected to the voltage output terminal at the first moment, a second input terminal of the XOR gate U3 is connected to the voltage output terminal at the second moment, and an output terminal of the XOR gate U3 serves as an output terminal of the delay control module 110.

[0066] In this embodiment, the first-time voltage output terminal is used to output the first power supply voltage Vt1 of the power supply terminal of the timing controller 200 at time t, and the second-time voltage output terminal is used to output the second power supply voltage Vt2 of the power supply terminal of the timing controller 200 at time t+N. The voltages at two adjacent times are compared by an exclusive-OR gate U3 to determine whether the current state is the startup phase or the stable phase. If Vt1 and Vt2 are different, it indicates that the voltage is unstable, i.e., the startup phase, and the exclusive-OR gate U3 outputs a low-level control signal. Conversely, if Vt1 and Vt2 are the same, it indicates that the voltage is stable, i.e., the stable phase, and the exclusive-OR gate U3 outputs a high-level control signal. Here, t varies with time, and N is a constant, such as 50ms or 100ms.

[0067] In one embodiment, the delay control module 110 may further include a timing chip, and the delay duration is controlled by setting a software program inside the timing chip.

[0068] In another embodiment, the delay control module 110 may further include a comparator, which determines whether the current state is the startup phase or the stable phase by comparing the voltages at two adjacent moments; Figure 5 The XNOR gate in is replaced by a voltage comparator. The specific output logic is the same and will not be described here.

[0069] Figure 6 FIG. 1 is a circuit diagram of a fourth load control circuit provided in an embodiment of the present application; Figure 6 and Figure 5 The difference is that the specific structures of the first control module 120 and the second control module 130 are different; Figure 6As shown, the first control module 120 of this embodiment includes an inverter U4 and a first AND gate U5, the input end of the inverter U4 is connected to the output end of the delay control module 110; the inverter U4 is used to invert the output signal of the delay control module 110; the first input end of the first AND gate U5 is connected to the first output end of the timing controller 200, the second input end of the first AND gate U5 is connected to the output end of the inverter U4, and the output end of the first AND gate U5 is connected to the source drive circuit 300 or the gate drive circuit 400; the first AND gate U5 is used to receive a high level at the second input end, and send the light-load display data or power-on clock signal output by the timing controller 200 to the source drive circuit 300 or the gate drive circuit 400 respectively.

[0070] It should be noted that the working principle of the first control module 120 of this embodiment is described in detail: when the delay control module 110 outputs a low level, it is inverted by the inverter U4 to obtain a high level; at this time, the second input end of the first AND gate U5 is a high level, and the first AND gate U5 outputs the light-load display data or power-on clock signal received at the first input end as an output signal; conversely, when the delay control module 110 outputs a high level, it is inverted by the inverter U4 to obtain a low level; at this time, the second input end of the first AND gate U5 is a low level, and the first AND gate U5 does not output any signal or outputs a low-level signal to the back end.

[0071] like Figure 6 As shown, the second control module 130 includes a fifth transistor T5 and a second AND gate U6, the control end of the fifth transistor T5 is connected to the output end of the delay control module 110, and the first end of the fifth transistor T5 is connected to the enable end of the timing controller 200; the first input end of the second AND gate U6 is connected to the second end of the fifth transistor T5, the second input end of the second AND gate U6 is connected to the output end of the timing controller 200, and the output end of the second AND gate U6 is connected to the source drive circuit 300 or the gate drive circuit 400; the second AND gate U6 is used to send the normal display data or normal clock signal output by the timing controller 200 to the source drive circuit 300 or the gate drive circuit 400 when a high level is received at the first input end.

[0072] The fifth transistor T5 of this embodiment is an N-type MOS transistor. The enable terminal of the timing controller 200 outputs a high level. The working principle of the second control module 130 is described in detail: when the delay control module 110 outputs a high level, the fifth transistor T5 is turned on; at this time, the first input terminal of the second AND gate U6 receives the high level output by the enable terminal of the timing controller 200, and the second AND gate U6 outputs the normal display data or normal clock signal received at the second input terminal as the output signal; conversely, when the delay control module 110 outputs a low level, the fifth transistor T5 is turned off; at this time, the first input terminal of the second AND gate U6 is in a low level or high-impedance state, and the second AND gate U6 does not output any signal or outputs a low-level signal to the back end.

[0073] Figure 7 FIG. 1 is a circuit diagram of a fifth load control circuit provided in an embodiment of the present application; Figure 7 is Figures 1 to 6 On the basis of adding multiple control tubes Tc, specifically: Figure 7 As shown, the display panel also includes M clock signal lines 500, and the two ends of the 2m-1th clock signal line 500 are respectively connected to the 2m-1th clock signal output end of the timing controller 200 and the 2m-1th clock signal receiving end of the gate drive circuit 400. The load control circuit also includes: multiple control tubes Tc, the control end of the mth control tube Tc is connected to the output end of the delay control module 110, the first end of the mth control tube Tc is connected to the 2mth clock signal output end of the timing controller 200, and the second end of the mth control tube Tc is electrically connected to one end of the 2mth clock signal line 500; wherein, the other end of the 2mth clock signal line 500 is connected to the 2mth clock signal receiving end of the gate drive circuit 400.

[0074] It is worth noting that, from the aforementioned embodiments, the circuit structure of the delay control module 110 of the present application includes at least three embodiments (i.e. Figure 3 、 Figure 4 and Figure 5 As shown), the first control module 120 includes at least two embodiments (ie Figure 5 and Figure 6 As shown) and the second control module 130 also includes at least two embodiments (ie Figure 5 and Figure 6 As shown), different embodiments of each module can be combined with each other, and the combination examples and drawings are not given here one by one; in addition, Figure 7 Only the delay control module 110 and the additional technical features are shown in the figure. For the sake of simplicity, the first control module 120 and the second control module 130 are not shown. However, in actual application, Figure 7 The illustrated embodiment shall include a first control module 120 and a second control module 130 .

[0075] Figures 1-6 The embodiment shown solves the problem of abnormal startup caused by heavy load voltage drop during startup by providing light load display data or / and reducing the refresh frequency of the panel during power-on. At the same time, the resolution during power-on can be reduced by using multiple control transistors Tc of this embodiment, further improving the problem of load extraction during startup. Specifically, taking the control transistors Tc as N-type MOS transistors as an example, when the delay control module 110 outputs the first control signal of low level during power-on, each control transistor Tc is turned off. At this time, the gate drive circuit 400 can only receive half of the clock signal, such as Figure 8 As shown, only the odd-numbered scan lines in the display panel can be turned on, thereby reducing the current draw of the display panel; after power-on stabilization, when the delay control module 110 outputs the second control signal of a high level, each control transistor Tc is turned on, and the gate drive circuit 400 can receive all clock signals and turn on all the scan lines in the display panel row by row.

[0076] In another embodiment, the display panel further includes M clock signal lines 500, where two ends of the 2m-th clock signal line 500 are respectively connected to the 2m-th clock signal output end of the timing controller 200 and the 2m-th clock signal receiving end of the gate driving circuit 400, and the load control circuit further includes: a plurality of control transistors Tc, where the control end of the m-th control transistor Tc is connected to the output end of the delay control module 110, a first end of the m-th control transistor Tc is connected to the 2m-1-th clock signal output end of the timing controller 200, and a second end of the m-th control transistor Tc is electrically connected to one end of the 2m-1-th clock signal line 500; wherein the other end of the 2m-1-th clock signal line 500 is connected to the 2m-1-th clock signal receiving end of the gate driving circuit 400; M is an integer greater than 1.

[0077] This embodiment and Figure 7 The difference shown is the difference between opening odd-numbered scan lines and even-numbered scan lines. The other working principles are the same and will not be described here. Indicates that M is divided by 2 and rounded down, which is equivalent to when M is an even number. When M is an odd number

[0078] Figure 8 FIG. 5 is a circuit diagram of a sixth load control circuit provided in an embodiment of the present application; Figure 8 Respectively Figures 1-6 The difference is: Figure 8 Based on other load control circuits 100 , the load control circuit 100 further includes a sixth transistor T6 , a seventh transistor T7 , a first inductor L1 , and a second capacitor C2 .

[0079] Specifically, the control end of the sixth transistor T6 is connected to the output end of the delay control module 110, and the first end of the sixth transistor T6 is connected to the output end of the external power supply 600; the control end of the seventh transistor T7 is connected to the control end of the sixth transistor T6, the first end of the seventh transistor T7 is connected to the second end of the sixth transistor T6, and the second end of the seventh transistor T7 is grounded; the first end of the first inductor L1 is connected to the first end of the seventh transistor T7, and the second end of the first inductor L1 is connected to the power supply end of the subsequent load 700; the first end of the second capacitor C2 is connected to the second end of the first inductor L1, and the second end of the second capacitor C2 is grounded; the turn-on voltages of the sixth transistor T6 and the seventh transistor T7 are opposite.

[0080] Here, taking the delay control module 110 including the differential amplifier U1 and the comparator U2 as an example, the working principle of the load control circuit 100 of this embodiment is described in detail:

[0081] (1) The voltage difference between the current power supply voltage Vin and the reference voltage Vref is compared by differential amplifier U1 and input into comparator U2. Comparator U2 compares the voltage difference with a triangular wave (i.e., a reference threshold) to determine the pulse width of the output signal and control the output voltage. Optionally, comparator U2 generates a voltage error signal by comparing the voltage error signal from the current power supply voltage and the reference voltage with a constant sawtooth ramp waveform. The ramp is started by a clock signal from an oscillator, and good noise tolerance performance is achieved with a fixed ramp amplitude. The voltage regulation is independent of the output current. The use of voltage mode requires a fixed, predictable switching frequency and is also useful when large output load changes may occur.

[0082] (2) The on and off of the sixth transistor T6 and the seventh transistor T7 are controlled by the output signal of the comparator U2. Specifically, if the current power supply voltage is less than the reference voltage, the delay control module 110 outputs a low level to turn on the sixth transistor T6, and charges the first inductor L1 and the second capacitor C2 through the output voltage of the external power supply 600, thereby raising the voltage on the power supply end of the subsequent load 700, so that the voltage is not pulled down when power is turned on or when the heavy load screen is switched; if the current power supply voltage is equal to or greater than the reference voltage, the delay control module 110 outputs a high level to turn on the seventh transistor T7, does not receive the output voltage of the external power supply 600, and discharges through the first inductor L1 and the second capacitor C2, thereby reducing the voltage on the power supply end of the subsequent load 700, so that the normal operating voltage is restored after the power is stabilized.

[0083] At the same time, the load control circuit 100 of this embodiment also adjusts the current display data or refresh rate through the first control module 120 and the second control module 130; therefore, this embodiment adjusts the size of the voltage received by the load end through the sixth transistor T6, the seventh transistor T7, the first inductor L1 and the second capacitor C2, and cooperates with the first control module 120 and the second control module 130 to adjust the current display data or refresh rate, which can further improve the problem of heavy-load voltage drop during startup and ensure the normal startup of the display panel.

[0084] It should also be noted that Figure 9 The post-stage load 700 in the embodiment may be a general term for a timing controller, a source driver circuit, a gate driver circuit and other modules.

[0085] In the second aspect, an embodiment of the present application provides a display panel including a display area and a non-display area, the display area including a pixel array; the non-display area including a timing controller, a gate drive circuit, a source drive circuit and a load control circuit, and the load control circuit is electrically connected to the timing controller, the gate drive circuit and the source drive circuit respectively.

[0086] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0087] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0088] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A load control circuit, characterized in that: Applied to a display panel, the display panel includes a timing controller, a source driver circuit, and a gate driver circuit, and the load control circuit includes: a delay control module, configured to output a first control signal upon power-up, and continuously output a second control signal after outputting the first control signal for a preset time period; a first control module, wherein a control end of the first control module is connected to an output end of the delay control module, a first end of the first control module is connected to an output end of the timing controller, and a second end of the first control module is connected to the source driver circuit or the gate driver circuit, and the first control module is configured to send the light-load display data output by the timing controller to the source driver circuit or send the power-on clock signal with a first clock frequency output by the timing controller to the gate driver circuit under the action of the first control signal; A second control module, wherein the control end of the second control module is connected to the output end of the delay control module, the first end of the second control module is connected to the output end of the timing controller, and the second end of the second control module is connected to the source drive circuit or the gate drive circuit. The second control module is used to send the normal display data output by the timing controller to the source drive circuit, or send the normal clock signal with a second clock frequency output by the timing controller to the gate drive circuit under the action of the second control signal; wherein the first clock frequency is less than the second clock frequency.

2. The load control circuit according to claim 1, wherein: The delay control module includes: a first resistor, wherein a first end of the first resistor is connected to an output end of an external power supply; a first capacitor, wherein a first end of the first capacitor is connected to the second end of the first resistor, and a second end of the first capacitor is grounded; a first transistor, wherein a control terminal of the first transistor is connected to a first terminal of the first capacitor; a second resistor, wherein a first end of the second resistor is grounded, and a second end of the second resistor is connected to the first end of the first transistor; a third resistor, a first end of the third resistor being connected to the output end of the external power supply; a second transistor, wherein a control terminal of the second transistor is connected to the control terminal of the first transistor, a first terminal of the second transistor is connected to the second terminal of the third resistor, and a second terminal of the second transistor is connected to the second terminal of the first transistor; The turn-on voltage of the first transistor is a low level, the turn-on voltage of the second transistor is a high level, and the second end of the first transistor or the second end of the second transistor is used as the output end of the delay control module.

3. The load control circuit according to claim 1, wherein: The delay control module includes: a differential amplifier, wherein a first input terminal of the differential amplifier is connected to the reference voltage output terminal, and a second input terminal of the differential amplifier is connected to the power supply terminal of the timing controller, and is used to amplify the difference between the current power supply voltage on the power supply terminal of the timing controller and the reference voltage; A comparator, wherein a first input terminal of the comparator is connected to a reference threshold terminal, and a second input terminal of the comparator is connected to the output terminal of the differential amplifier, and is used to output the first control signal or the second control signal based on a comparison result between a voltage difference output by the differential amplifier and a reference threshold.

4. The load control circuit according to claim 1, wherein: The delay control module includes: An XNOR gate, wherein a first input terminal of the XNOR gate is connected to the voltage output terminal at the first moment, a second input terminal of the XNOR gate is connected to the voltage output terminal at the second moment, and an output terminal of the XNOR gate serves as an output terminal of the delay control module; Among them, the first-time voltage output end is used to output the first power supply voltage of the power supply end of the timing controller at time t, and the second-time voltage output end is used to output the second power supply voltage of the power supply end of the timing controller at time t+N.

5. The load control circuit according to any one of claims 2 to 4, characterized in that: The first control module includes a third transistor, a control end of the third transistor is connected to the output end of the delay control module, a first end of the third transistor is connected to the first output end of the timing controller, and a second end of the third transistor is connected to the source drive circuit or the gate drive circuit; The second control module includes a fourth transistor, a control end of the fourth transistor is connected to the output end of the delay control module, a first end of the fourth transistor is connected to the second output end of the timing controller, and a second end of the fourth transistor is connected to the source drive circuit or the gate drive circuit; The turn-on voltages of the third transistor and the fourth transistor are opposite.

6. The load control circuit according to any one of claims 2 to 4, characterized in that: The first control module includes: an inverter, wherein an input end of the inverter is connected to an output end of the delay control module and is used to invert an output signal of the delay control module; A first AND gate, wherein the first input end of the first AND gate is connected to the first output end of the timing controller, the second input end of the first AND gate is connected to the output end of the inverter, and the output end of the first AND gate is connected to the source drive circuit or the gate drive circuit, and is used to send the light-load display data or power-on clock signal output by the timing controller to the source drive circuit or the gate drive circuit respectively when a high level is received at the second input end.

7. The load control circuit according to claim 6, wherein: The second control module includes: a fifth transistor, wherein a control terminal of the fifth transistor is connected to the output terminal of the delay control module, and a first terminal of the fifth transistor is connected to the enable terminal of the timing controller; A second AND gate, wherein the first input end of the second AND gate is connected to the second end of the fifth transistor, the second input end of the second AND gate is connected to the output end of the timing controller, and the output end of the second AND gate is connected to the source drive circuit or the gate drive circuit; the second AND gate is used to send the normal display data or normal clock signal output by the timing controller to the source drive circuit or the gate drive circuit when a high level is received at the first input end.

8. The load control circuit according to claim 1, wherein: The display panel further includes M clock signal lines, and two ends of the 2m-1th clock signal line are respectively connected to the 2m-1th clock signal output end of the timing controller and the 2m-1th clock signal receiving end of the gate drive circuit. The load control circuit further includes: a plurality of control tubes, wherein a control end of an mth control tube is connected to an output end of the delay control module, a first end of the mth control tube is connected to a 2mth clock signal output end of the timing controller, and a second end of the mth control tube is electrically connected to one end of a 2mth clock signal line; wherein the other end of the 2mth clock signal line is connected to a 2mth clock signal receiving end of the gate drive circuit; Alternatively, the display panel further includes M clock signal lines, two ends of the 2mth clock signal line are respectively connected to the 2mth clock signal output end of the timing controller and the 2mth clock signal receiving end of the gate drive circuit, and the load control circuit further includes: a plurality of control transistors, wherein a control end of an mth control transistor is connected to an output end of the delay control module, a first end of the mth control transistor is connected to a 2m-1th clock signal output end of the timing controller, and a second end of the mth control transistor is electrically connected to one end of a 2m-1th clock signal line; wherein the other end of the 2m-1th clock signal line is connected to a 2m-1th clock signal receiving end of the gate drive circuit; in, M is an integer greater than 1.

9. The load control circuit according to claim 1, wherein: The load control circuit further includes: a sixth transistor, wherein a control terminal of the sixth transistor is connected to the output terminal of the delay control module, and a first terminal of the sixth transistor is connected to the output terminal of the external power supply; a seventh transistor, wherein a control terminal of the seventh transistor is connected to the control terminal of the sixth transistor, a first terminal of the seventh transistor is connected to the second terminal of the sixth transistor, and a second terminal of the seventh transistor is grounded; a first inductor, wherein a first end of the first inductor is connected to the first end of the seventh transistor, and a second end of the first inductor is connected to a power supply end of the subsequent load; a second capacitor, wherein a first end of the second capacitor is connected to the second end of the first inductor, and a second end of the second capacitor is grounded; The turn-on voltages of the sixth transistor and the seventh transistor are opposite.

10. A display panel comprising a display area and a non-display area, characterized in that: The display area includes a pixel array; The non-display area includes a timing controller, a gate driving circuit, a source driving circuit and a load control circuit according to any one of claims 1 to 9, and the load control circuit is electrically connected to the timing controller, the gate driving circuit and the source driving circuit respectively.

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