Display driving device and method capable of controlling pixel brightness

Abstract

The invention relates to a display driving device and method capable of controlling pixel brightness. A display driving device according to one embodiment of the present disclosure may include: a pixel driving circuit connected to each of a plurality of LEDs forming at least one row and column, and driving the LEDs by connecting a PWM method; a control unit that determines a PWM duty ratio for indicating a light emission period of the LED during one frame interval; and a timing controller generating a first clock signal according to the PWM duty ratio and providing the first clock signal to the pixel driving circuit in rows or columns through the shift register. When the PWM duty ratio is changed, the time schedule controller can generate a second clock signal matched with the changed PWM duty ratio and selectively provide the first clock signal or the second clock signal to the pixel driving circuit.

Description

[0001] This application is a divisional application with the application date of December 4, 2023, application number 202380082740.1, and invention name “Display driving device and method capable of controlling pixel brightness”. Technical Field

[0002] The present invention relates to a display driving device and method capable of achieving fine brightness control using multiple clock signals. In addition, the present invention relates to a display driving device and method capable of achieving fine brightness control using virtual signals. Background Art

[0003] The present invention relates to a display driving device and method, and more particularly to a display driving device and method capable of flexibly controlling the change of pulse width modulation (PWM ON Duty) to adjust the light emitting time of a pixel.

[0004] A conventional display driving device includes a plurality of pixels, which are N pixels are arranged in a row. Each pixel can include one or more light-emitting elements, usually three (R, G, B). Each light-emitting element is called a sub-pixel.

[0005] Among various methods for controlling the driving of sub-pixels, there is a PWM control method that stores video data used to control the emission of sub-frames during a single frame in an internal memory and controls grayscale using a pulse width modulation (PWM) signal.

[0006] For pixels driven by PWM, image data is stored in the pixel memory during a specified time (pixel programming). Then, based on the image data stored in the pixel memory, the sub-pixels emit light during the light-emitting time (duty cycle) within one frame. At this time, the brightness of the sub-pixels is controlled by PWM. Figure 1 As shown in FIG, a gray clock signal for PWM control is input to a sub-pixel driving circuit. At this time, the number of gray clock signals MSB, MSB-1, MSB-2, ..., LSB is determined according to the number of bits of image data.

[0007] The brightness of the sub-pixel can be controlled by changing the light-emitting time, and the change of the light-emitting time can be controlled by adjusting the PWM duty cycle.

[0008] However, when the light emission time is changed to adjust the brightness of the sub-pixel, the output signal before the change is affected by the grayscale clock signal after the change due to the change of the grayscale clock signal, which may cause an error.

[0009] Furthermore, due to the limited number of drive signals, fine brightness adjustment is difficult when controlling pixel brightness using PWM. For example, the grayscale clock signal input to the subpixel drive circuit has a constant period. Therefore, when the grayscale clock signal is shifted in a constant manner according to the grayscale clock signal period, it is difficult to achieve fine brightness adjustment based on time intervals smaller than the grayscale clock signal period.

[0010] The above-mentioned background technology is technical information mastered by the inventor in order to derive the present invention or obtained in the process of deriving the present invention, and is not necessarily considered to be public knowledge disclosed to the general public before the submission of the present invention. Summary of the Invention

[0011] Technical Problems to be Solved by the Invention

[0012] The present invention aims to provide a display driving device and method that can realize fine brightness control by using multiple clock signals. In addition, the present invention aims to provide a display driving device that can realize fine brightness control by using virtual signals.

[0013] The problems to be solved by the present invention are not limited to the problems mentioned above. Other problems and advantages of the present invention not mentioned above can be understood through the following description and can be more clearly understood through the embodiments of the present invention. In addition, it can be understood that the problems to be solved and advantages of the present invention can be achieved by the means specified in the claims and their combinations.

[0014] Technical Solution

[0015] As a technical solution to the above-mentioned technical problem, one embodiment of the present disclosure provides a display driver device, comprising: a pixel driver circuit connected to each of a plurality of light-emitting diodes (LEDs) forming at least one row and column, and driving the LEDs via PWM; a control unit configured to determine a PWM duty cycle representing a light-emitting period of the LEDs within a frame interval; and a timing controller configured to generate a first clock signal based on the PWM duty cycle and provide the first clock signal to the pixel driver circuit in units of rows or columns via a shift register. When the PWM duty cycle changes, the timing controller generates a second clock signal matching the changed PWM duty cycle and selectively provides either the first clock signal or the second clock signal to the pixel driver circuit.

[0016] Another embodiment of the present disclosure may provide a display driving device, which includes: a pixel driving circuit, connected to each of a plurality of LEDs forming at least one row and column, and driving the LEDs through PWM; a scanning driving circuit, sequentially outputting a first signal to the LEDs arranged along a first direction among the LEDs connected to the pixel driving circuit; a data driving circuit, outputting a second signal to the LEDs arranged along a second direction among the LEDs connected to the pixel driving circuit; and the timing controller.

[0017] Another embodiment of the present disclosure may provide a method for controlling a display driver, the method comprising: receiving a first clock signal corresponding to a first frame interval and a second clock signal corresponding to a second frame interval continuous with the first frame interval; receiving a first selection signal; a first frame driving step of transmitting the first selection signal to a selection signal shift register corresponding to a first row of a plurality of LEDs, selecting the first clock signal based on the first selection signal, and transmitting the first clock signal to a clock signal shift register connected to the first row; sequentially performing the first frame driving step to an Nth row of the plurality of LEDs during the first frame interval; receiving a second selection signal; a second frame driving step of transmitting the second selection signal to a selection signal shift register corresponding to the first row, selecting the second clock signal based on the second selection signal, and transmitting the second clock signal to a clock signal shift register connected to the first row; and sequentially performing the second frame driving step to the Nth row during a second frame interval. At least one row where the first frame driving step and the second frame driving step overlap is driven only by the first clock signal.

[0018] In addition, other methods and systems for implementing the present invention, and a computer-readable recording medium storing a computer program for executing the method may also be provided.

[0019] Other aspects, features, and advantages in addition to those described above will become apparent from the following drawings, claims, and detailed description of the invention.

[0020] Beneficial effects

[0021] According to the above technical solution of the present disclosure, compared with the prior art, the present disclosure can control the brightness of the display panel more finely.

[0022] In addition, according to the technical solution of the present disclosure, optimal brightness adjustment can be achieved according to display quality or power consumption.

[0023] In addition, according to the technical solution of the present disclosure, it is possible to solve the output error of the shift register that may occur when controlling the brightness of the display panel.

[0024] In addition, according to the technical solution of the present disclosure, more subtle brightness adjustment can be achieved when controlling the brightness of the display panel.

[0025] The effects of the present invention are not limited to the above-mentioned contents, and those skilled in the art will clearly understand other effects not mentioned from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a driving circuit diagram of a sub-pixel according to the prior art.

[0027] Figure 2 is a block diagram schematically showing a configuration of a display driving apparatus according to one embodiment.

[0028] Figure 3 is a block diagram schematically illustrating a configuration of a display driving apparatus including a timing controller according to one embodiment.

[0029] Figure 4 is a block diagram schematically illustrating an example of a PWM clock signal output by a timing controller.

[0030] Figure 5 is a timing diagram showing another example of a PWM clock signal output by a timing controller when a single clock is used.

[0031] Figure 6 FIG. 1 is a timing diagram schematically illustrating a problem of a pulse signal output by a timing controller when a single clock is used.

[0032] Figure 7 is a block diagram schematically showing a configuration of a timing controller according to one embodiment.

[0033] Figure 8 FIG. 4 is a timing diagram showing an example of selecting a CLK signal by a timing controller according to an embodiment.

[0034] Figure 9 is a block diagram schematically illustrating a configuration of a timing controller including a multiplexer (MUX) according to one embodiment.

[0035] Figure 10 is a timing diagram showing an example of a PWM clock signal output by a timing controller according to an embodiment.

[0036] Figure 11 is a flowchart for explaining an example of a method for controlling a display driving device according to an embodiment.

[0037] Figure 12 FIG. 1 is a timing diagram schematically illustrating a problem of a PWM clock signal output by a timing controller that does not use a virtual signal.

[0038] Figure 13 FIG. 1 is a timing diagram schematically illustrating a PWM clock signal output by a timing controller according to an embodiment.

[0039] Figure 14 is a circuit diagram schematically showing a configuration of a timing controller according to one embodiment.

[0040] Figure 15 is a circuit diagram schematically illustrating a configuration of a timing controller that generates a virtual clock signal according to one embodiment.

[0041] Figure 16 is a flowchart for explaining an example of a method for controlling pixel brightness using a virtual signal according to an embodiment. DETAILED DESCRIPTION

[0042] A display driver device according to one embodiment of the present disclosure may include: a pixel driver circuit connected to each of a plurality of LEDs forming at least one row and column, and driving the LEDs using PWM; a control unit configured to determine a PWM duty cycle representing a light-emitting period of the LEDs during a frame interval; and a timing controller configured to generate a first clock signal based on the PWM duty cycle and provide the first clock signal to the pixel driver circuit in units of rows or columns via a shift register. When the PWM duty cycle changes, the timing controller may generate a second clock signal matching the changed PWM duty cycle and selectively provide the first clock signal or the second clock signal to the pixel driver circuit. Specific embodiments

[0044] The terms used in the examples are selected from widely used common terms whenever possible, but this may vary depending on the intentions of those skilled in the art, precedents, the emergence of new technologies, and other circumstances. Furthermore, in certain cases, there may be terms arbitrarily selected by the applicant; in such cases, their meanings will be detailed in the corresponding description. Therefore, the terms used in the specification should be defined based on the meanings attached to the terms and the entire specification, rather than simply by their names.

[0045] Throughout this specification, when a section is described as "including" a certain component, this does not exclude other components, but rather indicates that it may include other components, unless otherwise specified. Furthermore, terms such as "unit" and "module" described in this specification refer to a unit that handles at least one function or task, which may be implemented by hardware, software, or a combination of hardware and software. Furthermore, a "section" may be a hardware component (e.g., a processor or circuit) and / or a software component executed by a hardware component (e.g., a processor).

[0046] In addition, the terms including ordinal numbers such as "first" or "second" used in the specification may be used to describe various components, but the components should not be limited by the terms. The terms may be used to distinguish one component from another.

[0047] When it is mentioned that an element is “connected to” another element, it includes a case where the element is directly connected to the other element as well as a case where other elements are interposed.

[0048] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. However, the embodiments may be implemented in various forms and are not limited to the examples described herein.

[0049] Figure 2 is a block diagram schematically showing a configuration of a display driving apparatus according to one embodiment.

[0050] Reference Figure 2 According to one embodiment, a display driver device 101 may include a display panel 111, a scan driver circuit 130, a data driver circuit 140, and a control unit 150. Furthermore, the control unit 150 may include a timing controller (not shown), but is not limited thereto. For example, the display driver device 101 may include a display panel 111, a scan driver circuit 130, a data driver circuit 140, a control unit 150, and a timing controller (not shown).

[0051] The display panel 111 may include a plurality of pixels (PX). The plurality of pixels PX may be arranged in a matrix of m×n (m, n are natural numbers). However, the plurality of pixels may be arranged in various patterns, such as a zigzag pattern, according to embodiments.

[0052] The display panel 111 can be implemented as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic light emitting diode (OLED) display, an active-matrix organic light emitting diode (AMOLED) display, an electrochromic display (ECD), a digital micromirror device (DMD), an actuated mirror device (AMD), a grating light valve (GLV), a plasma display panel (PDP), an electroluminescent display (ELD), or a vacuum fluorescent display (VFD). Furthermore, the display panel 111 can be implemented as another type of flat panel display or flexible display. In this specification, an LED display panel is used as an example for description.

[0053] Each pixel PX may include one or more light-emitting elements. The light-emitting elements may be light-emitting diodes (LEDs). The light-emitting diodes may be micro-LEDs (Micro LEDs) with a size of 80 μm or less. A pixel PX may output various colors using multiple light-emitting elements of different colors. As an example, a pixel PX may include light-emitting elements consisting of red, green, and blue. As another example, if a white light-emitting element is also included, the white light-emitting element may replace any one of the red, green, and blue light-emitting elements. In embodiments where a pixel PX includes multiple light-emitting elements, each light-emitting element included in the pixel PX may be referred to as a "sub-pixel."

[0054] Each sub-pixel can store data related to the color brightness to be output during a video frame, i.e., grayscale. The size of the grayscale-related data can vary, and this specification uses 10 bits as an example. However, the display driver device 101 according to this specification is not limited to this example.

[0055] Each pixel PX may include a pixel driver circuit for driving the light-emitting element (i.e., sub-pixel) included in the pixel. The pixel driver circuit can drive the sub-pixel to turn on or off based on signals output by the scan driver circuit 130 and / or the data driver circuit 140. As an example, the pixel driver circuit may include at least one transistor, at least one capacitor, etc. The pixel driver circuit may be implemented on a semiconductor wafer and formed into a laminated structure with the light-emitting element for connection to the light-emitting element, or arranged on the side of the light-emitting element for connection to the light-emitting element, thereby controlling the light emission of the light-emitting element.

[0056] On the other hand, the display panel 111 may include one or more scan lines SL1 to SLm arranged along a first direction and one or more data lines DL1 to DLn arranged along a second direction. The first direction refers to the row direction or the column direction, and the second direction refers to the column direction or the row direction. As an example, the first direction may be the row direction, and the second direction may be the column direction. As another example, the first direction may be the column direction, and the second direction may be the row direction.

[0057] On the other hand, a pixel PX may be located at the intersection of one or more scan lines SL1-SLm and one or more data lines DL1-DLn. Each pixel PX may be connected to any scan line SLk and any data line DLk. One or more scan lines SL1-SLm may be connected to the scan driving circuit 130, and one or more data lines DL1-DLn may be connected to the data driving circuit 140.

[0058] The scan drive circuit 130 can output a signal (hereinafter referred to as a first signal) for driving one or more pixels connected to any one of one or more scan lines SL1 to SLm. Preferably, the scan drive circuit 130 can sequentially select one or more scan lines SL1 to SLm. For example, the pixels connected to the first scan line SL1 can be driven during a first scan drive period, and the pixels connected to the second scan line SL2 can be driven during a second scan drive period.

[0059] The data driving circuit 140 can output a signal related to grayscale (hereinafter referred to as a second signal) to each pixel through one or more data lines DL1 to DLn. Figure 2 As shown, one data line is connected to more than one pixel in the vertical direction, but a signal related to a gray scale can be input only to pixels connected to a scan line selected by the scan driving circuit 130 .

[0060] The control unit 150 can output control signals to execute the operations of the scan driver circuit 130 and the data driver circuit 140. The control unit 150 can output control signals corresponding to video data corresponding to one video frame to the scan driver circuit 130 or the data driver circuit 140. The control unit 150 can also determine the PWM duty cycle (PWM ON DUTY) that indicates the LED light-emitting period during one frame interval.

[0061] On the other hand, the scan driving circuit 130 and the data driving circuit 140 may include a processor, an application-specific integrated circuit (ASIC), other chipsets, logic circuits, registers, communication modems, data processing devices, etc. known in the technical field of the present invention to execute various control logics. In addition, when the control logic is implemented by software, the scan driving circuit 130 and the data driving circuit 140 may be implemented as a collection of program modules. In this case, the program modules may be stored in a memory device and executed by a processor. As an example, the scan driving circuit 130 may include at least one shift register. The shift register may correspond to Figure 3 In addition, the shift register may correspond to any one of the multiple shift registers 120_1, 120_2, ..., 120_k described below. Figure 9 The timing controller 120 or Figure 14 The timing controller 1120 is configured to:

[0062] A program may include code written in a computer language (e.g., C / C++, C#, JAVA, Python, or machine language). This code can be read by a computer's processor (CPU) through the computer's device interface, allowing the computer to read the program and execute the method implemented by the program. This code may include functional code related to functions that define the functions required to execute the method, as well as control code related to the execution process required for the computer processor to perform the functions in a specified sequence. Furthermore, this code may include code related to memory references, which indicates the location (address number) in the computer's internal or external memory where additional information or media required for the computer processor to execute the function should be referenced. Furthermore, when the computer's processor needs to communicate with any remote computer or server in order to execute the function, the code may also include communication-related code, such as how to use the computer's communication module to communicate with the remote computer or server, and what information or media should be sent and received during communication.

[0063] The storage medium that stores the program is not a medium that stores data for a short period of time, such as a register or cache memory. Instead, it is a medium that stores data semi-permanently and is readable by a device. Specifically, examples of storage media include, but are not limited to, ROM, RAM, CD-ROM, magnetic tape, floppy disks, and optical data storage devices. In other words, the program can be stored on various storage media on various computer-accessible servers or on various storage media on a user's computer. Furthermore, the storage medium can be distributed across computer systems connected via a network, storing computer-readable code in a distributed manner.

[0064] Figure 3 is a block diagram schematically illustrating a configuration of a display driving apparatus including a timing controller according to one embodiment.

[0065] Reference Figure 3 , the display driving device 100 may include a display panel 110 and a plurality of shift registers 120_1 , 120_2 , . . . , 120 — k.

[0066] For ease of explanation, Figure 3 , a plurality of shift registers 120_1, 120_2, ..., 120_k are shown, but are not limited thereto. In other words, the shift register may be one. Preferably, the number of shift registers may be one or the same as the number of lines of the display panel, and a PWM clock signal for controlling the PWM drive interval of the pixel may be provided to each line. Hereinafter, a device for generating or providing a PWM clock signal (including a shift register or a plurality of shift registers 120_1, 120_2, ..., 120_k) is defined as a timing controller 120. On the other hand, the timing controller 120 may include Figure 2 At least one of the scan driving circuit 130 or the data driving circuit 140.

[0067] On the other hand, as mentioned above, Figure 2 The scan driving circuit 130 may include at least one shift register. That is, Figure 2 The scan driving circuit 130 may correspond to Figure 3 Multiple shift registers 120_1, 120_2, ..., 120_k. Figure 3 Although not shown Figure 2 However, those skilled in the art can easily understand that the data driving circuit 140 and the control unit 150 are Figure 3 Zhongye and Figure 2 Therefore, the display driving device 100 and the display panel 110 correspond to Figure 2 The display driving device 101 and the display panel 111 are shown in FIG. Figure 2Duplicate description.

[0068] For example, the timing controller 120 may generate a first clock signal based on the PWM duty cycle and provide the first clock signal to the pixel driving circuit in rows or columns via a shift register. Furthermore, when the PWM duty cycle changes, the timing controller 120 generates a second clock signal that matches the changed PWM duty cycle and selectively provides the first clock signal or the second clock signal to the pixel driving circuit.

[0069] As another example, the timing controller 120 may generate a first clock signal based on the PWM duty cycle, and may generate a PWM clock signal based on the first clock signal via a shift register, and then provide the PWM clock signal to the pixel driving circuit on a row or column basis. Furthermore, when the PWM duty cycle changes, the timing controller 120 may generate a second clock signal that matches the changed PWM duty cycle, select either the first clock signal or the second clock signal, and then generate a PWM clock signal based on the selected clock signal, and provide the PWM clock signal to the pixel driving circuit.

[0070] As another example, the timing controller 120 may generate a first clock signal according to a PWM duty cycle, generate a virtual clock signal based on the first clock signal, and then control the brightness of the LED using the first clock signal and the virtual clock signal.

[0071] As another example, the timing controller 120 may generate a virtual clock signal by delaying the first clock signal by a predetermined time interval. The predetermined time interval may refer to the time by which the virtual clock signal is delayed relative to the first clock signal. When the virtual clock signal is generated by delaying the first clock signal by 1H-ΔT, the predetermined time interval may be 1H-ΔT.

[0072] As another example, the timing controller 120 may generate a PWM clock signal based on the clock signal, and may provide the PWM clock signal to the pixel driving circuit in units of rows or columns.

[0073] As another example, the timing controller 120 may generate a virtual signal based on the virtual clock signal, and the virtual signal may not be provided to the pixel driving circuit.

[0074] The timing controller 120 may output pulse signals to a plurality of pixel lines based on a prescribed period using pulse signals having widths and dummy signals to adjust the brightness of the display panel.

[0075] A pixel line refers to an electrical connection that connects pixels by inputting a PWM clock signal output by the timing controller 120. A pixel line can connect all pixels connected to the same row or column in parallel. As an example, when "m" is 533, the timing controller 120 may include 533 pixel lines.

[0076] Figure 4 is a block diagram schematically illustrating an example of a PWM clock signal output by a timing controller.

[0077] Reference Figure 4 , a timing diagram showing a timing controller using a single clock outputting a PWM clock signal to pixel lines in sequence can be identified. The timing controller may include a shift register. Specifically, the ST signal is a pulse signal related to PWM control, indicating the PWM duty cycle interval for LED light emission. The CLK signal is a signal input to multiple flip-flops or multiplexers (MUXs) within the timing controller. The PWM clock signal is output to the pixel lines, synchronized with the ST signal and the CLK signal cycle.

[0078] Check Figure 4 1 , the ST signal is input to the timing controller 120. At this time, the ST signal is shifted under the action of the CLK signal and is output to each pixel line in sequence.

[0079] Check Figure 4 The timing diagram on the right confirms that after the ST signal is input, it is shifted sequentially from the first row to the Nth row under the influence of the CLK signal, and is output as a PWM clock signal to each pixel line. The PWM clock signal at this time is characterized by being output to the pixel lines in the order in which the ST signal is shifted under the influence of the CLK signal. Therefore, each PWM clock signal for each line has a time difference determined by the CLK signal.

[0080] Figure 5 is a timing diagram showing another example of a PWM clock signal output by a timing controller when a single clock is used.

[0081] The Hsync signal indicates the timing of the signal moving through each line in the display. Figure 5 For example, assuming that the panel is simply composed of 4 row lines and the LED is driven with a PWM duty cycle of 100% representing the maximum brightness of the LED, an ST signal with a length four times the pulse period (1H) included in Hsync can be generated.

[0082] As an example, the CLK signal is a signal input to the MUX, and the ST signal input to the timing controller may be shifted corresponding to the CLK signal and output to the pixel line.

[0083] As another example, the CLK signal is input to multiple flip-flops within a shift register and consists of pulses with the same period as the Hsync signal. Therefore, the ST signal, input to the first flip-flop under the CLK signal, is synchronized with the Hsync signal's pulse period and then output from the next flip-flop.

[0084] As another example, the CLK signal is input to multiple flip-flops within a timing controller and consists of pulses with the same period as the Hsync signal. Therefore, the ST signal input to the first flip-flop under the CLK signal can be synchronized with the Hsync signal's pulse period and then output from the next flip-flop.

[0085] Figure 6 is a timing diagram schematically illustrating a problem of a pulse signal output by a timing controller when a single clock is used.

[0086] Reference Figure 6 Assuming that during the PWM drive time period of the first ST signal, a second ST signal is used in order to adjust the brightness by adjusting the PWM duty cycle (for example, adjusting the brightness to a PWM duty cycle of 75%) to drive the LED, it can be confirmed that there is a problem when the "ST" signal with a changed width is input into a timing controller using a single clock. Specifically, the width of the ST signal can be changed to change the drive, such as the brightness of the display. In this case, when the width of the ST signal is changed, the period of the CLK signal will also change. In this case, the changed period of the CLK signal can affect the entire circuit through the shift register. Therefore, there is a problem that, at the time point when the period of the CLK signal is changed, the pulse signal output to the Nth pixel line due to the ST signal before the width of the ST signal is changed is affected by the changed CLK signal, resulting in an output error.

[0087] As mentioned above, a timing controller using a single clock signal uses only one CLK signal. Therefore, the CLK signal that changes according to the width of the ST signal changes can affect the pulse signal based on the existing ST signal. This may cause errors such as signal flickering or shutoff.

[0088] Figure 7 is a block diagram schematically showing a configuration of a timing controller according to one embodiment.

[0089] Reference Figure 7, it can be confirmed that the configuration of the timing controller 120 includes a multiplexer (MUX) 124. Figure 7 1 , the multiplexer (MUX) 124 is shown to be included in the timing controller 120 , but may be included in the timing controller 120 and configured separately, but is not limited thereto.

[0090] On the other hand, although the multiplexer (MUX) 124 is shown as a configuration for selecting a clock signal, it can also be implemented by other configurations of the display driver device, but is not limited thereto. Therefore, the operation of the multiplexer (MUX) 124 described below can be implemented by the timing controller 120, the scan driver circuit 130, the data driver circuit 140, the control unit 150, or more devices.

[0091] First, the multiplexer (MUX) 124 included in the timing controller 120 selects a clock signal from the CLK1 and CLK2 signals. Specifically, when an ST signal with a specified width is initially input to the timing controller 120, each PWM clock signal is sequentially output to a pixel line according to the corresponding CLK1 signal. Furthermore, when an ST signal with a different width than the initial ST signal is input to the timing controller, each PWM clock signal is sequentially output to a pixel line according to the corresponding CLK2 signal.

[0092] Even if an ST signal of a different width is input to the shift register 121, a clock signal different from the original ST signal is used, so the CLK signal changed according to the ST signal with a changed width does not affect the pulse signal according to the existing ST signal. Figure 6 A problem in the timing controller is that, since only one CLK signal is used, the CLK signal changed according to the ST signal whose width has been changed affects the pulse signal according to the existing ST signal.

[0093] Meanwhile, multiplexer (MUX) 124 receives multiple clock signals from at least one clock input terminal and selects a single clock signal from these multiple clock signals. Using multiplexer (MUX) 124 allows the selection of a CLK signal that matches the PWM on-duty ratio applied to each line. Consequently, even when the light-emission duration is changed to adjust the brightness of a subpixel, the output signal prior to the change is not affected by the changed clock signal, preventing errors.

[0094] For example, the multiplexer (MUX) 124 receives two clock signals from two clock input terminals and selects one of the two clock signals. Specifically, the multiplexer (MUX) 124 receives the CLK 1 signal and the CLK 2 signal from the clock input terminals and selects one of the two clock signals.

[0095] On the other hand, the multiplexer (MUX) 124 may use a switch to receive inputs of a plurality of clock signals from at least one clock input terminal, and may select one clock signal therefrom.

[0096] Furthermore, the timing controller 120 may include: at least one flip-flop including an output terminal connected to the pixel driving circuit; and at least one multiplexer (MUX) 124 for selecting a clock signal input to a clock terminal of the at least one flip-flop. For example, the multiplexer (MUX) 124 receives multiple clock signals from at least one clock input terminal and selects one clock signal from the multiple clock signals to be input to the clock terminal of the at least one flip-flop. For another example, the multiplexer (MUX) 124 may use a switch to select one clock signal input to the clock terminal of the at least one flip-flop.

[0097] Figure 8 FIG. 4 is a timing diagram showing an example of selecting a CLK signal by a timing controller according to an embodiment.

[0098] Reference Figure 8 For example, when the width of the ST signal is determined to drive LEDs with a 100% PWM duty cycle, the period of the corresponding clock signal, CLK1, is determined to match the width of the ST signal and is shifted by 1H for each row line through the timing controller. Subsequently, when the width of the ST signal is changed to drive the LEDs by adjusting the PWM duty cycle to 75%, the period of the corresponding CLK signal is also adjusted, and the changed clock signal, CLK2, is input through the timing controller. To prevent output errors caused by the pulse signal output to the Nth pixel line based on the ST signal, which was previously driven at a 100% PWM duty cycle, being affected by the changed CLK2 signal, the existing CLK1 signal is input through a multiplexer (MUX) even when the CLK2 signal is input, allowing the shift register to select the appropriate CLK1 or CLK2 signal for the corresponding line.

[0099] Figure 9 is a block diagram schematically illustrating a configuration of a timing controller including a multiplexer (MUX) according to one embodiment.

[0100] The timing controller 120 includes a multiplexer (MUX), a selection signal shift register (SEL SHIFT), and a PWM signal shift register (PWMSHIFT). The PWM signal shift register can be a clock signal shift register. In addition, although Figure 9 Although not shown, the timing controller 120 may include a clock signal selection unit (not shown). The clock signal selection unit (not shown) outputs a selection signal (SEL signal) for selecting one clock signal from a plurality of clock signals based on driving information of the pixel driving circuit.

[0101] For ease of explanation, Figure 9 Two multiplexers (MUX) 124_1 and 124_2 are shown in FIG. 1 , but the circuit may be driven by one multiplexer (MUX) and is not limited thereto.

[0102] The SEL signal is a signal that selects a CLK signal from multiple CLK signals. The timing controller 120 can receive or generate the SEL signal and transmit the SEL signal to the multiplexer (MUX) via the SEL SHIFT. Furthermore, the multiplexers (MUX) 124_1 and 124_2 can select a CLK signal based on the SEL signal received from the SEL SHIFT and transmit it to the shift register. As an example, the SEL SHIFT can output a selection signal (SEL signal) to each pixel line unit based on the drive information of the pixel drive circuit. The selection signal (SEL signal) is used to select the first clock signal (CLK1 signal) or the second clock signal (CLK2 signal). Furthermore, the multiplexer (MUX) can output the first clock signal or the second clock signal based on the selection signal (SEL signal). The first clock signal and the second clock signal are characterized by operating independently of each other with respect to the pixel drive circuit.

[0103] Reference Figure 9SEL SHIFT 121_1 and 121_2 are shift registers that shift the SEL signal according to the clock cycle. The clock signal selection unit (not shown) transmits a selection signal (SEL signal) for selecting the first clock signal or the second clock signal to SEL SHIFT 121_1 based on the drive information of the pixel drive circuit. The SEL signal is a signal that selects one signal from the CLK1 signal and the CLK2 signal. As an example, by transmitting a signal consisting of 0 or 1 to the multiplexer (MUX), when the SEL signal is 1, the multiplexer (MUX) can transmit the CLK1 signal, and when the SEL signal is 0, the multiplexer (MUX) can transmit the CLK2 signal. SEL SHIFT 121_1 receives the SEL signal and the CLK SEL signal. The SEL signal is input to the SEL SHIFT and shifted, and then output to each pixel line unit in sequence. PWM SHIFT 122_1 and 122_2 are shift registers that shift the ST signal according to the clock cycle and output the ST signal for each pixel line. The CLK SEL signal is the clock signal for the SEL signal. As the ST signal shifts from PWM SHIFT 122_1 and 122_2 under the influence of the CLK signal, the SEL signal also shifts from SEL SHIFT 121_1 and 121_2 under the influence of the SEL CLK signal. This allows the same CLK signal to be selected for the same ST signal. Multiplexer (MUX) 124_1 receives the SEL signal from SEL SHIFT 121_1. Multiplexer (MUX) 124_1 receives the ST 1 and ST 2 signals, and also receives the CLK 1 and CLK 2 signals for the ST signals (ST 1 and ST 2). Multiplexer (MUX) 124_1 selects the CLK 1 signal and the ST 1 signal based on the received SEL signal and transmits them to PWM SHIFT 122_1. Multiplexer (MUX) 124_1 may use a switch to select the clock signal. For example, multiplexer (MUX) 124_1 receives a SEL signal consisting of 1 and turns on a switch to transmit the CLK 1 signal. PWM SHIFT 122_1 shifts the ST 1 signal and transmits it to the first line. Similarly, multiplexer (MUX) 124_2 receives the SEL signal and the CLK SEL signal from SEL SHIFT 121_2. The SEL signal received by multiplexer (MUX) 124_2 is a signal that has been shifted once by SEL SHIFT 121_1. The multiplexer (MUX) 124_2 receives the CLK 1 signal and the CLK 2 signal.Multiplexer (MUX) 124_2 selects either the CLK 1 signal or the CLK 2 signal based on the received SEL signal and transmits it to PWM SHIFT 122_2. Multiplexer (MUX) 124_2 selects the CLK 1 signal based on the SEL signal and transmits it to PWM SHIFT 122_2. PWM SHIFT 122_2 shifts the ST 1 signal based on the ST 1 signal received from PWM SHIFT 122_1 and the CLK 1 signal received from multiplexer (MUX) 124_2, and transmits it to the second line (2nd Line).

[0104] While the ST1 and CLK1 signals are being transmitted to each line through the shift register, SEL SHIFT 121_1 can serve as a select signal for the CLK2 signal and transmit the SEL signal to multiplexer (MUX) 124_1. Based on the received SEL signal, multiplexer (MUX) 124_1 selects the CLK2 signal as the clock signal and the ST2 signal as the ST signal, which it then transmits to PWM SHIFT 122_1. PWM SHIFT 122_1 shifts the ST2 signal and transmits it to the first line (1stLine). Similarly, multiplexer (MUX) 124_2 receives the SEL and CLKSEL signals from SEL SHIFT 121_2. The SEL signal can be a signal that has been shifted once by SEL SHIFT 121_1. Multiplexer (MUX) 124_2 receives both the CLK1 and CLK2 signals. Multiplexer (MUX) 124_2 selects either the CLK 1 signal or the CLK 2 signal based on the received SEL signal and transmits it to PWM SHIFT 122_2. Multiplexer (MUX) 124_2 selects the CLK 2 signal based on the SEL signal and transmits it to PWM SHIFT 122_2. PWM SHIFT 122_2 shifts the ST 2 signal based on the ST 2 signal received from PWM SHIFT 122_1 and the CLK 2 signal received from multiplexer (MUX) 124_2, and transmits it to the second line (2nd Line).

[0105] The SEL signal is shifted per pixel line by SEL SHIFT and input to the multiplexer (MUX). Therefore, while the ST 1 and CLK 1 signals are shifted per pixel line by PWM SHIFT, they are not affected by the ST 2 and CLK 2 signals caused by the SEL signal. In other words, while the ST 1 and CLK 1 signals are sequentially transmitted from the first pixel line to the Nth pixel line via the shift register, even if the ST 2 and CLK 2 signals are also transmitted to the first pixel line via the shift register, the already transmitted ST 1 and CLK 1 signals are not affected by the ST 2 and CLK 2 signals, thus preventing errors.

[0106] Therefore, a plurality of clock signals are used, and different clock signals are applied to the changed ST signals. Therefore, the changed clock signal does not affect the shift register driven by the clock signal before the change, and thus no error occurs.

[0107] exist Figure 9 1 and 2 are shown as being included in the timing controller 120, but they may be configured separately without being included in the timing controller 120 and are not limited thereto. Furthermore, although the multiplexers (MUX) 124_1 and 124_2 and the SEL SHIFTs 121_1 and 121_2 are shown as a configuration for selecting a clock signal, this may be implemented using other configurations of the display driver and is not limited thereto.

[0108] The operations of the clock signal selection unit (not shown), multiplexers (MUX) 124_1, 124_2, SEL shifts 121_1, 121_2, and PWM shifts 122_1, 122_2 may be implemented by a single device (e.g., a timing controller, a clock signal selection unit, a multiplexer (MUX), SEL shift, and PWM shift) or by multiple devices.

[0109] In addition, the timing controller 120 may include a pulse signal input terminal ST and a clock input terminal CLK.

[0110] Pulse signals related to PWM control and LED light emission timing are input to pulse signal input terminals ST 1 and ST 2. Pulse signals corresponding to the brightness of the display panel are input to pulse signal input terminals ST 1 and ST 2. Specifically, pulse signals having a width adjusted according to the brightness of the display panel can be input to pulse signal input terminals ST 1 and ST 2.

[0111] Clock input terminals CLK1 and CLK2 receive multiple clock signals input to multiplexers (MUX) 124_1 and 124_2 within the timing controller 120. There can be at least one clock input terminal CLK1 or CLK2. Clock signal input terminals CLK1 and CLK2 can receive multiple clock signals input to the clock terminals of multiplexers (MUX) 124_1 and 124_2.

[0112] Figure 10 is a timing diagram showing an example of a PWM clock signal output by a timing controller according to an embodiment.

[0113] Reference Figure 10 , used to adjust the "VSYNC" signal and image data (Image Data) recording interval synchronized between frames, the LED lighting interval according to the PWM clock signals PWM 1 and PWM 2 output by the timing controller, and the timing of the SEL signal that selects the clock CLK signal according to the PWM duty cycle of each VSYNC interval.

[0114] For ease of explanation, take the following embodiment as an example: in the first frame interval, the first PWM duty cycle corresponds to the PWM 1 setting, in the second frame interval, the second PWM duty cycle corresponds to the PWM 2 setting, in the third frame interval, the first PWM duty cycle corresponds to the PWM 1 setting again, and in the fourth frame interval, the second PWM duty cycle corresponds to the PWM 2 setting again.

[0115] Therefore, PWM1 is a PWM clock signal output by the timing controller based on the ST1 signal and the CLK1 signal. PWM2 is a PWM clock signal output by the timing controller based on the ST2 signal and the CLK2 signal. Each of PWM1 and PWM2 is represented by a trapezoidal shape to indicate that the output is shifted 1H sequentially from the first pixel line to the Nth pixel line, in units of pixel lines.

[0116] In PWM 1, the SEL signal is at a high level (High) and shifts from the first pixel line to the Nth pixel line, thereby selecting the CLK 1 signal. In PWM 2, the SEL signal is at a low level (Low), synchronized with the VSYNC interval, and shifts from the first pixel line to the Nth pixel line, thereby selecting the CLK 2 signal. At this time, when the PWM clock signal is being output from the first pixel line to the Nth pixel line via the first pixel line in PWM 1, even if the CLK 2 signal is selected and sent to the first pixel line in PWM 2, the CLK 1 signal of the Nth pixel line will not be affected by the CLK 2 signal due to the SEL signal already being at a high level (High). Similarly, in PWM 2, the SEL signal is at a low level (Low) and shifts from the first pixel line to the Nth pixel line, thereby selecting the CLK 2 signal. When the PWM clock signal is being output to the N-th pixel line via the first pixel line in PWM 2, even if the CLK 1 signal is selected to be transmitted to the first pixel line in the next PWM 1, the CLK 2 signal of the N-th pixel line will not be affected by the CLK 1 signal due to the SEL signal already being at a low level (Low).

[0117] Figure 11 is a flowchart for explaining an example of a method for controlling a display driving device according to an embodiment.

[0118] Reference Figure 11 , the timing controller selectively provides multiple clock signals to the pixel driving circuit. Regarding the content of the timing controller providing clock signals to the pixel driving circuit, the following is omitted Figures 2 to 10 The content described in the content is duplicate content.

[0119] In step 1001 , a timing controller receives a first clock signal corresponding to a first frame interval and a second clock signal corresponding to a second frame interval continuous with the first frame interval.

[0120] In step 1002, the timing controller receives a first selection signal. The first selection signal is a selection signal for selecting a first clock signal.

[0121] In step 1003, the timing controller transmits a first selection signal to a selection signal shift register corresponding to a first row of the plurality of LEDs, selects a first clock signal based on the first selection signal, and then transmits the first clock signal to a clock signal shift register connected to the first row. Step 1003 is designated as a first frame driving step.

[0122] In step 1004, the timing controller sequentially executes the first frame driving step to the Nth row of the plurality of LEDs during the first frame interval. The selection signal shift register sequentially shifts the first selection signal to the Nth row to transmit the first selection signal, and transmits the first clock signal to the clock signal shift register based on the sequentially transmitted first selection signal.

[0123] In step 1005, a second selection signal is received. The second selection signal is a selection signal for selecting the second clock signal.

[0124] In step 1006, the second selection signal is transmitted to the selection signal shift register corresponding to the first row, and the second clock signal is selected based on the second selection signal. The second clock signal is then transmitted to the clock signal shift register connected to the first row. Step 1006 is named the second frame driving step.

[0125] In step 1007, the second frame driving step is sequentially executed to the Nth row during the second frame interval. The selection signal shift register sequentially shifts the second selection signal to the Nth row to transmit the second selection signal, and transmits the second clock signal to the clock signal shift register based on the sequentially transmitted second selection signal. In the row where the first frame driving step and the second frame driving step overlap, it is characterized in that only the first clock signal is operated. The first frame driving step is driven based on the first selection signal, and the second frame driving step is driven based on the second selection signal. Even if the first frame driving step and the second frame driving step are driven simultaneously at the overlapping time, the first frame driving step is driven based on the first selection signal, and is therefore not affected by the second clock signal based on the second selection signal and is driven independently. In other words, when the second clock signal is received during the driving period based on the first clock signal, at least one row where the first frame driving step and the second frame driving step overlap can be operated by the first clock signal without being affected by the second clock signal based on the first selection signal.

[0126] According to one embodiment of the present invention, when receiving the second clock signal during driving based on the first clock signal, the pixel driving circuit is driven by the first clock signal based on the first selection signal and is not affected by the second clock signal.

[0127] Figure 12 FIG. 1 is a timing diagram schematically illustrating a problem of a PWM clock signal output by a timing controller that does not use a virtual signal.

[0128] Reference Figure 12, it can be confirmed that the problem occurs when the ST signal is input to the timing controller that does not use virtual signals. Specifically, when the width of the ST signal is changed, the brightness of the display and other driving changes can be made. According to the change of the ST signal, the period of the CLK signal is also changed. The changed period of the CLK signal is immediately applied to the entire circuit of the timing controller. At this time, the ST signal is shifted at a specified time interval based on the period of CLK, so there will be a problem that it will not shift at a fine time interval of ΔT. That is, when adjusting Figure 12 There is a limit to the fine time interval of the ΔT shown. If the timing controller without virtual signal is used, the ST signal is shifted and output based on the cycle of the CLK signal, which cannot be adjusted. Figure 12 The fine time interval of ΔT is limited, so there is a problem that the display brightness adjustment is limited.

[0129] Figure 13 FIG. 1 is a timing diagram schematically illustrating a PWM clock signal output by a timing controller according to an embodiment.

[0130] Reference Figure 13 It can be confirmed that the PWM clock signal is adjusted and output at a fine time interval of about ΔT.

[0131] The ST signal is shifted based on the CLK signal, resulting in a PWM clock signal that is sequentially output to multiple pixel lines. The CLK signal consists of a first clock signal and a dummy clock signal. The first clock signal has a period (1H) for controlling the sequential output to multiple pixel lines. The dummy clock signal is generated based on the first clock signal. As an example, the CLK signal consists of a first clock signal with a period of 1H and a dummy signal that delays the first clock signal by a time interval of approximately 1H-ΔT. The ST signal is generated by shifting the first dummy clock signal that constitutes the CLK signal. The dummy signal generated in this manner is not output to any pixel line. Furthermore, the ST signal, which has been shifted once by the first dummy clock signal, is shifted by the second first clock signal that constitutes the CLK signal to generate a PWM clock signal. That is, the ST signal is shifted once by the first clock signal and once again by the dummy clock signal, resulting in a total of two shifts to generate the PWM clock signal that is output to the first pixel line. The PWM clock signal generated by shifting the second first clock signal is adjusted to an on-time by a fourth dummy clock signal.

[0132] When a virtual clock signal is generated based on a first clock signal, the virtual clock signal is generated by delaying the first clock signal according to the desired on-time of the PWM clock signal. The virtual clock signal can be generated according to the desired on-time without being restricted by any time interval within the period (1H) of the first clock signal. The PWM clock signal adjusted to the desired on-time is output to the first (1st) pixel line. According to the present invention, by using a virtual signal, the PWM clock signal can be finely adjusted to a time interval of ΔT. Similarly, according to the same process as above, a second virtual signal is generated based on the second virtual clock signal. Furthermore, a PWM clock signal is generated using the third first clock signal, and the generated PWM clock signal is output to the second (2nd) pixel line. The on-time of the PWM clock signal output to the second (2nd) pixel line is adjusted by the fifth virtual clock signal.

[0133] As an example, the ST signal is input into the shift register, and the input ST signal is shifted in the first sub-flip flop in the shift register based on the virtual clock signal to generate a virtual signal. At this time, the generated virtual signal is not output to the pixel line. In addition, the main flip flop receives the ST signal that has been shifted once and shifts it based on the first clock signal to generate a PWM clock signal. The details will be discussed in detail. Figure 14 described in .

[0134] The virtual clock signal is generated based on the first clock signal. For example, the virtual clock signal can be generated by delaying the first clock signal by a predetermined time interval. For another example, the virtual clock signal can be generated by delaying the first clock signal by approximately 1H-ΔT, thereby shortening the on-time of the PWM clock signal by approximately ΔT.

[0135] The timing controller uses two shifts to output a PWM clock signal. Specifically, the timing controller does not output a dummy signal generated by one shift to the pixel line, but instead outputs a PWM clock signal generated by two shifts to the pixel line.

[0136] On the other hand, the PWM clock signal generated from the first clock signal constituting the CLK signal is output to the pixel line, but the dummy signal generated from the dummy clock signal constituting the CLK signal is not output to the pixel line.

[0137] According to an embodiment of the present invention, a virtual signal and a PWM clock signal are generated based on a clock signal (CLK signal), so that the PWM clock signal can adjust the on-time to finely adjust the brightness of the LED.

[0138] Figure 14 is a circuit diagram schematically showing a configuration of a timing controller according to one embodiment.

[0139] Reference Figure 14 The timing controller 1120 may include m first flip-flops 1121_1, 1121_2, ..., 1121_m and m second flip-flops 1122_1, 1122_2, ..., 1122_m connected to the m first flip-flops 1121_1, 1121_2, ..., 1121_m, respectively. The m first flip-flops and the m second flip-flops may be connected in series. Therefore, a signal output from a first flip-flop may be input to a second flip-flop located at the next position, and a signal output from a second flip-flop may be input to a first flip-flop located at the next position. Through the series connection of the m first flip-flops and the m second flip-flops, the signal is sequentially transmitted to the next flip-flop.

[0140] On the other hand, the first trigger receives the signal input first. However, unlike the example shown in the accompanying drawings of this specification, the signal can be first input to the first trigger shown at the top. That is, the input direction of the signal can be selected according to the designer, and the display driver 100, 101 according to this specification is not limited by the examples shown in this specification. As an example, the first trigger 1121_1 receives the input of the signal and generates a virtual signal by shifting the ST signal once. The virtual signal is not output to the pixel line. In addition, the ST signal that has been shifted once is input to the second trigger 1122_1, and then shifted again to generate a PWM clock signal. At this time, the generated PWM clock signal is output to the pixel line as the first PWM clock signal.

[0141] In addition, the timing controller 1120 may include a pulse signal input terminal ST and a clock input terminal CLK. The timing controller may include one shift register (not shown) or multiple shift registers (not shown). Each shift register (not shown) may include a pulse signal input terminal ST and a clock input terminal CLK.

[0142] A pulse signal of the LED light-emitting time related to PWM control is input to the pulse signal input terminal ST. A pulse signal corresponding to the brightness of the display panel is input to the pulse signal input terminal ST. Specifically, a pulse signal having a width adjusted according to the brightness adjustment of the display panel can be input to the pulse signal input terminal ST. The lengths of the pulse signals input into the pulse signal input terminal ST of each shift register can be different from each other. More specifically, the lengths of the pulse signals input into the pulse signal input terminals ST of adjacent shift registers can differ from each other by twice. The shift register corresponding to the most significant bit MSB in the grayscale data input to the pixel is called the first shift register, and the shift register corresponding to the second most significant bit is called the second shift register. At this time, the length of the pulse signal input into the pulse signal input terminal ST of the first shift register is twice the length of the pulse signal input into the pulse signal input terminal ST of the second shift register. For example, when the size of the grayscale data input to the pixel is 10 bits, the length of the pulse signal input to the pulse signal input terminal ST of the first shift register may be 512 times the length of the pulse signal input to the pulse signal input terminal ST of the tenth shift register corresponding to the least significant bit (LSB).

[0143] The clock signal input to the clock terminals of the m first flip-flops 1121_1, 1121_2, ..., 1121_m and the m second flip-flops 1122_1, 1122_2, ..., 1122_m is input to the clock input terminal CLK. As an example, a clock signal composed of the first clock signal and the dummy clock signal may be input.

[0144] On the other hand, the timing controller 1120 can generate a first clock signal based on the PWM duty cycle. Furthermore, the timing controller 1120 can generate a virtual clock signal based on the first clock signal. For example, the timing controller 1120 can include a clock generator 1123. The clock generator 1123 can generate the first clock signal based on the PWM duty cycle. Furthermore, the clock generator 1123 can generate a virtual clock signal based on the first clock signal.

[0145] Figure 15 is a circuit diagram schematically illustrating a configuration of a timing controller that generates a virtual clock signal according to one embodiment.

[0146] The timing controller may include Figure 15 As an example, the timing controller may include the circuit shown in FIG. Figure 15 The circuit shown is configured as a clock generation portion, but is not limited thereto.

[0147] Reference Figure 15, the timing controller receives the CLK signal. The timing controller may include a virtual clock signal DLY that generates a virtual clock signal by delaying the received CLK signal by a specified time interval. In addition, the timing controller may include an XOR gate or an OR gate for selectively outputting the virtual clock signal and the CLK signal. As an example, the timing controller receives a first clock signal according to the PWM duty cycle. In addition, the timing controller delays the first clock signal by a specified period through DLY to generate a virtual clock signal. The timing controller passes the first clock signal and the virtual clock signal through an XOR gate or an OR gate in sequence and outputs them through OUT. Therefore, the output clock signal is composed of the first clock signal and the virtual clock signal.

[0148] However, if Figure 15 The structure of the timing controller generating the virtual clock signal shown is only an example and is specified only to help understand the present invention. Therefore, the structure of the present invention generating the virtual clock signal is not affected by Figure 15 restrictions.

[0149] Figure 16 is a flowchart for explaining an example of a method for controlling the brightness of a pixel using a virtual signal according to an embodiment.

[0150] Reference Figure 16 , the timing controller uses the virtual signal to output a PWM clock signal to the pixel line to control the brightness of the pixel. The content about the timing controller generating the first clock signal and the virtual clock signal, generating the PWM clock signal and the virtual signal based on the first clock signal and the virtual clock signal, and providing the PWM clock signal to the pixel driving circuit will be omitted. Figures 2 to 15 The content described in the content is duplicate content.

[0151] In step 1601 , a timing controller generates a first clock signal based on a PWM duty cycle.

[0152] In step 1602, the timing controller generates a virtual clock signal based on the first clock signal. As an example, the timing controller generates the virtual clock signal by delaying the first clock signal by a predetermined time interval.

[0153] In step 1603 , the timing controller generates a PWM clock signal and a virtual signal based on the first clock signal and the virtual clock signal.

[0154] In step 1604, the timing controller provides a PWM clock signal to the pixel driving circuit. As an example, the timing controller provides a PWM clock signal to the pixel driving circuit, but does not provide a dummy signal to the pixel driving circuit.

[0155] Those skilled in the art of the present invention will appreciate that the present invention can be implemented in various forms without departing from the essential features described above. Therefore, the disclosed method should be considered in an illustrative rather than restrictive sense, and the scope of rights should be indicated by the claims rather than the above description, and should be interpreted as covering all differences within the scope of equivalents.

Claims

1. A display driving device, characterized in that: include: a pixel driving circuit connected to each of the plurality of light emitting diodes forming at least one row and column and driving the light emitting diodes by pulse width modulation; a control unit, determining a pulse width modulation duty cycle for representing a light emitting period of the light emitting diode within a frame interval; as well as A timing controller generates a first clock signal according to the pulse width modulation duty cycle, generates a virtual clock signal based on the first clock signal, and uses the first clock signal and the virtual clock signal to control the brightness of the light emitting diode.

2. The display driving device according to claim 1, wherein: The timing controller is configured as follows: The virtual clock signal is generated by delaying the first clock signal by a prescribed time interval.

3. The display driving device according to claim 1, wherein: The timing controller is configured as follows: generating a pulse width modulated clock signal based on the first clock signal and the virtual clock signal; The pulse width modulation clock signal is provided to the pixel driving circuit in units of rows or columns.

4. The display driving device according to claim 1, wherein: The timing controller is configured as follows: generating a virtual signal based on the first clock signal and the virtual clock signal; The dummy signal is not provided to the pixel driving circuit.

5. The display driving device according to claim 1, wherein: The timing controller includes: a plurality of first triggers, comprising output terminals connected to the pixel driving circuit; and At least one second trigger is connected between the first triggers.

6. The display driving device according to claim 5, wherein: The timing controller includes: a pulse signal input terminal, to which a pulse signal corresponding to the brightness of the light-emitting diode is input; and At least one clock input terminal, a clock signal composed of a first clock signal and a virtual clock signal is input to the at least one clock input terminal.

7. A display driving device, characterized in that: include: a pixel driving circuit connected to each of the plurality of light emitting diodes forming at least one row and column and driving the light emitting diodes by pulse width modulation; a scanning driving circuit, configured to sequentially output a first signal to the light-emitting diodes connected to the pixel driving circuit and arranged along a first direction; a data driving circuit, configured to output a second signal to the light-emitting diodes connected to the pixel driving circuit and arranged along a second direction; as well as A timing controller according to any one of claims 1 to 6.

8. A method for controlling the brightness of a light emitting diode using a virtual signal, characterized in that: include: generating a first clock signal based on a pulse width modulation duty cycle; a step of generating a virtual clock signal based on the first clock signal; generating a pulse width modulated clock signal and a virtual signal based on the first clock signal and the virtual clock signal; as well as The step of providing the pulse width modulated clock signal to the pixel driving circuit.

9. The method according to claim 8, characterized in that The step of generating a virtual clock signal comprises: The step of generating the virtual clock signal by delaying the first clock signal by a prescribed time interval.

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