Preparation method of TSV structure
By forming grooves with large opening widths in the silicon substrate and depositing a silicon oxide layer, the Cu diffusion problem caused by the loss of the silicon oxide protective layer on the sidewall of the TSV pore is solved, and the isolation reliability and device yield of the TSV structure are improved.
Patent Information
- Application Number
- CN202410172244.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-06
- Publication Date
- 2025-08-08
AI Technical Summary
During the preparation of existing TSV structures, the loss of the silicon oxide protective layer on the side walls of the TSV pores causes the metal Cu to diffuse into the silicon wafer, causing device failure.
A groove with a larger opening width is first formed in the silicon substrate, and then a silicon oxide layer is deposited in the groove. The TSV holes that penetrate the silicon oxide layer and the composite film layer are formed in one step to reveal the metal wiring, ensuring that the groove side walls are covered with a good silicon oxide layer and avoiding etching of the silicon oxide material at the bottom of the TSV hole.
Improves isolation reliability, prevents metal Cu from diffusing into the silicon substrate, and improves device yield.
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Figure CN120453227A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor manufacturing and relates to a method for preparing a TSV structure. Background Art
[0002] In the semiconductor industry, researchers have developed a series of advanced packaging technologies to achieve high-density electronic packaging, superior performance, and lower costs. Three-dimensional (3D) packaging technology, among others, offers excellent electrical performance and reliability, while enabling high packaging density. It is widely used in various high-speed circuits and miniaturized systems.
[0003] Through Silicon Via (TSV) technology is a technique for interconnecting stacked chips in three-dimensional integrated circuits. It achieves electrical interconnection between different chips by creating vertically interconnected TSV structures on silicon wafers. TSV technology maximizes chip stacking density in three dimensions, minimizes interconnect lines between chips, and minimizes overall dimensions. It also significantly improves chip speed and power consumption, making it one of the most compelling technologies in current electronic packaging.
[0004] like Figures 1 to 4 , which illustrates a schematic diagram of the structure presented in each step of preparing a TSV structure in the prior art, wherein the process steps for preparing a TSV structure include:
[0005] Thinning a silicon (Si) wafer 100;
[0006] A silicon oxide (SiO2) mask layer 400 is formed on the silicon wafer 100;
[0007] forming a photoresist (not shown) and performing photolithography and etching to pattern the silicon oxide mask layer 400;
[0008] Etching the silicon wafer 100 and the composite film layer 200 to form a TSV hole 500 exposing the metal wiring 300;
[0009] The photoresist is removed, and a silicon oxide protection layer 600 is deposited to cover the TSV hole 500;
[0010] Etching the silicon oxide protection layer 600 to expose the metal wiring 300;
[0011] A dielectric layer (not shown) and a TSV pillar (not shown) are formed in the TSV hole 500 .
[0012] However, during the entire process, when the silicon oxide protection layer 600 is etched to expose the metal wiring 300, while the silicon oxide protection layer 600 at the bottom of the TSV hole 500 is opened, the silicon oxide protection layer 600 on the sidewall of the TSV hole 500 is also etched away. Figure 3 T1 and Figure 4 In the embodiment of FIG. 5 , t2 is less than t1, and the loss of the silicon oxide protection layer 600 on the sidewall of the TSV hole 500 affects the isolation effect, causing the subsequent diffusion of metal copper (Cu) in the TSV column into the silicon wafer 100 and causing device failure.
[0013] Therefore, it is necessary to provide a method for preparing a TSV structure. Summary of the Invention
[0014] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for preparing a TSV structure, so as to solve the problem of device failure caused by the loss of the silicon oxide protection layer on the sidewall of the TSV hole in the prior art.
[0015] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a TSV structure, comprising the following steps:
[0016] Providing a semiconductor substrate, the semiconductor substrate comprising a stacked silicon substrate, a composite film layer and a rewiring layer;
[0017] thinning the silicon substrate;
[0018] patterning the silicon substrate to form a groove penetrating the silicon substrate to expose the composite film layer;
[0019] depositing a silicon oxide layer, wherein the silicon oxide layer covers the surface of the silicon substrate and fills the groove;
[0020] The silicon oxide layer is patterned to form a TSV hole in the groove that penetrates the silicon oxide layer and the composite film layer to expose the metal wiring in the redistribution layer.
[0021] Optionally, a central axis of the TSV hole coincides with a central axis of the groove.
[0022] Optionally, a difference between an opening width of the groove and an opening width of the TSV hole is 0.5-2 μm.
[0023] Optionally, the depth of the TSV hole is 10-20 μm, and the opening width of the TSV hole is 2-4 μm.
[0024] Optionally, the method for thinning the silicon substrate includes a CMP method, and the thickness of the silicon substrate after thinning is 5 to 15 μm.
[0025] Optionally, after depositing the silicon oxide layer, a step of polishing the silicon oxide layer by using a CMP method to planarize the silicon oxide layer is included.
[0026] Optionally, after planarization, the thickness of the silicon oxide layer on the surface of the silicon substrate is 0.5 to 1.5 μm.
[0027] Optionally, the method further includes depositing a dielectric layer and a TSV column in the TSV hole.
[0028] Optionally, the dielectric layer in the composite film layer includes one or a combination of a silicon oxide layer and a silicon nitride layer.
[0029] Optionally, after the TSV hole is formed, the thickness of the silicon oxide layer attached to the sidewall of the silicon substrate is greater than 0.3 μm.
[0030] As described above, the method for preparing the TSV structure of the present invention first forms a groove with a large opening width in the silicon substrate, and then deposits a silicon oxide layer in the groove. Thereafter, a TSV hole is formed by etching in a single step, which penetrates the silicon oxide layer and the composite film layer and exposes the metal wiring. This allows the sidewalls of the groove in the silicon substrate to have a well-covered silicon oxide layer, eliminating the need to etch the silicon oxide material at the bottom of the TSV hole. This can improve isolation reliability, prevent metal Cu from diffusing into the silicon substrate, and improve device yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figures 1 to 4 It shows a schematic diagram of the structure presented in each step when preparing a TSV structure in the prior art.
[0032] Figure 5 Shown is a process flow chart for preparing a TSV structure according to the present invention.
[0033] Figures 6-9 The figure shows a schematic structural diagram of each step in preparing a TSV structure according to the present invention.
[0034] Description of Reference Numerals
[0035] 100 silicon wafers
[0036] 200 composite film layer
[0037] 300 metal wiring
[0038] 400 silicon oxide mask layer
[0039] 500TSV holes
[0040] 600 silicon oxide protective layer
[0041] 110 silicon substrate
[0042] 210 composite film layer
[0043] 310 metal wiring
[0044] 410 groove
[0045] 510 silicon oxide layer
[0046] 610TSV hole DETAILED DESCRIPTION
[0047] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0048] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.
[0049] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "over," and the like may be used herein to describe the relationship of one element or feature to other elements or features illustrated in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
[0050] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.
[0051] See Figure 5 This embodiment provides a method for preparing a TSV structure, comprising the following steps:
[0052] S1: Providing a semiconductor substrate, wherein the semiconductor substrate comprises a stacked silicon substrate, a composite film layer, and a rewiring layer;
[0053] S2: thinning the silicon substrate;
[0054] S3: patterning the silicon substrate to form a groove penetrating the silicon substrate to expose the composite film layer;
[0055] S4: depositing a silicon oxide layer, wherein the silicon oxide layer covers the surface of the silicon substrate and fills the groove;
[0056] S5: patterning the silicon oxide layer to form a TSV hole in the groove that penetrates the silicon oxide layer and the composite film layer to expose the metal wiring in the redistribution layer.
[0057] The preparation method of the TSV structure of this embodiment is to first form the groove with a larger opening width in the silicon substrate, then deposit the silicon oxide layer in the groove, and then form the TSV hole that penetrates the silicon oxide layer and the composite film layer and exposes the metal wiring through a one-step etching process, so that the sidewall of the groove located in the silicon substrate can be well covered with the silicon oxide layer, and there is no need to etch the silicon oxide material at the bottom of the TSV hole, which can improve isolation reliability, prevent metal Cu from diffusing into the silicon substrate, and improve device yield.
[0058] The following instructions Figure 5 、 Figures 6 to 9 , further introduces the preparation method of the TSV structure.
[0059] First, see Figure 5 and Figure 6 , perform step S1 to provide a semiconductor substrate, wherein the semiconductor substrate includes a stacked silicon substrate 110, a composite film layer 210 and a rewiring layer.
[0060] Specifically, the size of the silicon substrate 110 may include, for example, 6 inches, 8 inches, or 12 inches, and the thickness of the silicon substrate 110 may be set as needed. The composite film layer 210 may include components for electrical connection, and the type, quantity, and distribution of the components may be set as needed. The rewiring layer includes metal wiring 310 for electrical connection and a dielectric layer. The number of layers, distribution, and material of the metal wiring 310, as well as the material of the dielectric layer, are not particularly limited.
[0061] The preparation of the semiconductor substrate may include bonding the composite film layer 210 and the redistribution layer, and the specific bonding method is not limited here.
[0062] As an example, the dielectric layer in the composite film layer 210 may include one or a combination of a silicon oxide layer and a silicon nitride layer.
[0063] Specifically, when the dielectric layer in the composite film layer 210 uses a silicon oxide layer and / or a silicon nitride layer, since the diffusion of copper (Cu) metal in silicon oxide and silicon nitride is low, the diffusion of Cu metal formed in subsequent processes can be effectively avoided, thereby achieving a good isolation and insulation effect.
[0064] The material of each film layer in the composite film layer 210 and the specific number of layers can be selected according to needs and are not overly limited here.
[0065] Next, see Figure 5 and Figure 6 , executing step S2 to thin the silicon substrate 110.
[0066] Specifically, in order to reduce the size of the device finally prepared, it is preferred to perform a thinning operation on the silicon substrate 110 in the semiconductor base, wherein the thinning process method may include, but is not limited to, chemical mechanical polishing (CMP), and may also include mechanical polishing, etc. In this embodiment, in order to improve the flatness of the silicon substrate 110 after polishing, it is preferred to use CMP for thinning.
[0067] The thickness of the thinned silicon substrate 110 may be 5 to 15 μm, such as 5 μm, 10 μm, 15 μm, etc., and may be set according to actual needs without any excessive limitation.
[0068] Next, see Figure 5 and Figure 7 , executing step S3 , patterning the silicon substrate 110 to form a groove 410 penetrating the silicon substrate 110 to expose the composite film layer 210 .
[0069] Specifically, a first photoresist (not shown) may be formed on the surface of the thinned silicon substrate 110, and then the first photoresist may be exposed and developed to pattern the first photoresist, and then the silicon substrate 110 may be etched to form the groove 410 that penetrates the silicon substrate 110 and exposes the composite film layer 210. Figure 7 , the opening width of the groove 410 is marked as D. The data on the opening width D of the groove 410, the opening morphology and the position distribution of the groove 410 can be set according to the requirements of the TSV structure to be finally prepared, and no excessive restrictions are made here.
[0070] Next, see Figure 5 and Figure 8 , executing step S4 , depositing a silicon oxide layer 510 , wherein the silicon oxide layer 510 covers the surface of the silicon substrate 110 and fills the groove 410 .
[0071] Specifically, the first photoresist in step S3 is first removed, and then the deposition process of the silicon oxide layer 510 is performed to form the silicon oxide layer 510 covering the surface of the silicon substrate 110 and filling the groove 410. The deposition method of the silicon oxide layer 510 can adopt an ALD deposition method, but is not limited to this.
[0072] Furthermore, after the silicon oxide layer 510 is deposited and formed, the silicon oxide layer 510 may be planarized. For example, the silicon oxide layer 510 may be polished using a CMP process to smooth the uneven surface of the silicon oxide layer 510. At the same time, a certain thickness of the silicon oxide layer 510 is reserved on the surface of the silicon substrate 110. The reserved silicon oxide layer 510 can be used as a top dielectric layer and an etching hard mask to facilitate the subsequent preparation of the TSV hole 610. The thickness of the reserved silicon oxide layer 510 may include, for example, 0.5 μm, 1.0 μm, 1.5 μm, etc.
[0073] Next, see Figure 5 and Figure 9 , executing step S5, patterning the silicon oxide layer 510, forming the TSV hole 610 in the groove 410, which penetrates the silicon oxide layer 510 and the composite film layer 210 to expose the metal wiring 310 in the redistribution layer.
[0074] Specifically, a second photoresist (not shown) may be formed on the surface of the planarized silicon oxide layer 510, and then the second photoresist may be exposed and developed to pattern the second photoresist. The silicon oxide layer 510 may then be etched to form the TSV hole 610 in the groove 410, which penetrates the silicon oxide layer 510 and the composite film layer 210 and exposes the metal wiring 310 in the redistribution layer. Figure 9 , the opening width of the TSV hole 610 is marked as d. The data on the opening width d of the TSV hole 610, the opening morphology and the position distribution of the TSV hole 610 can be set according to the requirements of the TSV structure to be finally prepared, and no excessive restrictions are made here.
[0075] Since the TSV hole 610 extends downward from the groove 410, the opening width d of the TSV hole 610 is smaller than the opening width D of the groove 410, and d<D. Therefore, when the TSV hole 610 is etched to form, the silicon oxide layer 510 attached to the sidewall of the silicon substrate 110 has good diffusion barrier properties for Cu material. Therefore, the silicon oxide layer 510 can serve as a protective layer for the silicon substrate 110, thereby improving isolation reliability, effectively preventing metal Cu from diffusing into the silicon substrate 110, and improving device yield.
[0076] As an example, the difference between the opening width D of the groove 410 and the opening width d of the TSV hole 610 may be 0.5-2 μm, such as 0.5 μm, 1 μm, 1.5 μm, 2 μm, etc.
[0077] It is preferred that the central axis of the TSV hole 610 coincides with the central axis of the groove 410 , so that the silicon oxide layer 510 is evenly distributed around the periphery of the TSV hole 610 , thereby further improving isolation reliability.
[0078] As an example, Figure 9 In the embodiment, after the TSV hole 610 is formed, the thickness T of the silicon oxide layer 510 attached to the side wall of the silicon substrate 110 is preferably greater than 0.3 μm. For example, the thickness T may be 0.5 μm, 0.8 μm, 1.0 μm, etc., to provide the silicon oxide layer 510 with a sufficient thickness, thereby effectively blocking the diffusion of metal Cu. There is no excessive restriction on the selection of the thickness T of the silicon oxide layer 510.
[0079] As an example, the depth of the formed TSV hole 610 can be 10 to 20 μm, such as 10 μm, 15 μm, 20 μm, etc., and the opening width d of the formed TSV hole 610 can be 2 to 4 μm, such as 2 μm, 3 μm, 4 μm, etc. There is no excessive restriction on the selection of the specific morphology and data of the TSV hole 610.
[0080] After completing step S5 , the second photoresist may be removed, a dielectric layer (not shown) may be deposited in the TSV hole 610 , and steps related to preparing TSV pillars (not shown) may be performed to ultimately form the TSV structure (not shown).
[0081] Among them, the dielectric layer may include a stack of layers such as a barrier layer, an adhesion layer and a metal seed layer, but is not limited thereto. The type and specific preparation method of the dielectric layer can be set as needed; the TSV column may be a Cu column prepared by electroplating, but the preparation method is not limited thereto.
[0082] In summary, the preparation method of the TSV structure of the present invention first forms a groove with a large opening width in the silicon substrate, and then deposits a silicon oxide layer in the groove. Thereafter, a TSV hole that penetrates the silicon oxide layer and the composite film layer and exposes the metal wiring is formed by a one-step etching, so that the sidewall of the groove located in the silicon substrate can have a well-covered silicon oxide layer, and there is no need to etch the silicon oxide material at the bottom of the TSV hole, which can improve the isolation reliability, prevent the diffusion of metal Cu into the silicon substrate, and improve the device yield.
[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A method for preparing a TSV structure, characterized in that: The following steps are involved: Providing a semiconductor substrate, the semiconductor substrate comprising a stacked silicon substrate, a composite film layer and a rewiring layer; thinning the silicon substrate; patterning the silicon substrate to form a groove penetrating the silicon substrate to expose the composite film layer; depositing a silicon oxide layer, wherein the silicon oxide layer covers the surface of the silicon substrate and fills the groove; The silicon oxide layer is patterned to form a TSV hole in the groove that penetrates the silicon oxide layer and the composite film layer to expose the metal wiring in the redistribution layer.
2. The method for preparing a TSV structure according to claim 1, wherein: A central axis of the TSV hole coincides with a central axis of the groove.
3. The method for preparing a TSV structure according to claim 1, wherein: The difference between the opening width of the groove and the opening width of the TSV hole is 0.5-2 μm.
4. The method for preparing a TSV structure according to claim 1, wherein: The depth of the TSV hole is 10-20 μm, and the opening width of the TSV hole is 2-4 μm.
5. The method for preparing a TSV structure according to claim 1, wherein: The method for thinning the silicon substrate includes a CMP method, and the thickness of the silicon substrate after thinning is 5 to 15 μm.
6. The method for preparing a TSV structure according to claim 1, wherein: After depositing the silicon oxide layer, a step of polishing the silicon oxide layer by using a CMP method to planarize the silicon oxide layer is included.
7. The method for preparing a TSV structure according to claim 6, wherein: After planarization, the thickness of the silicon oxide layer on the surface of the silicon substrate is 0.5 to 1.5 μm.
8. The method for preparing a TSV structure according to claim 1, wherein: The method also includes the step of depositing a dielectric layer and a TSV column in the TSV hole.
9. The method for preparing a TSV structure according to claim 1, wherein: The dielectric layer in the composite film layer includes one or a combination of a silicon oxide layer and a silicon nitride layer.
10. The method for preparing a TSV structure according to claim 1, wherein: After the TSV hole is formed, the thickness of the silicon oxide layer attached to the sidewall of the silicon substrate is greater than 0.3 μm.