Semiconductor package based on lead finger and manufacturing method thereof

Abstract

A semiconductor package based on lead fingers and a method of manufacturing the same are provided. The semiconductor package includes: a substrate; a plurality of first chips stacked on the substrate, each of the plurality of first chips being electrically connected to the substrate through a first bonding wire; a second chip disposed on the substrate and spaced apart from the plurality of first chips in a first direction parallel to an upper surface of the substrate, in which the second chip includes a dummy pad on an upper surface of the second chip and a lead finger on the dummy pad, and the lead finger is electrically connected to the substrate through a second bonding wire; the first plastic package body covers the first chips and the second chips on the substrate and exposes the upper surfaces of the lead fingers; the third chip is arranged on the upper surface of the first plastic package body and is electrically connected to the lead fingers through third bonding leads; and the second plastic package body covers the third chip on the first plastic package body.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor packaging, and in particular, to a lead-finger-based semiconductor package and a method for manufacturing the same. Background Art

[0002] In the related art, a multi-chip package can generally encapsulate multiple chips with different functions in one package. The current multi-chip package is composed of a semiconductor chip, a metal wire, a wafer bonding film, a molding compound, a substrate, etc. A wire bonding pad is provided on the semiconductor chip. In the related art, the interconnection between the semiconductor chip and the substrate is achieved based on the wire bonding technology, and the semiconductor chip and the circuit are molded using a molding compound to protect them from the influence of the external environment. External terminals (for example, solder balls) are provided on the surface of the substrate opposite to the surface on which the semiconductor chip is mounted, and the multi-chip package is finally soldered to the circuit board of the terminal product through the external terminals through the surface mounting (SMT) process, thereby achieving electrical connection between the semiconductor chip and the external components.

[0003] Generally, since sizes of semiconductor chips having various functions included in a multi-chip package are different from each other, reliability problems of the multi-chip package may be caused.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the technical background of the present disclosure and therefore the above information may contain information that does not form the prior art that is already known in this country to a person skilled in the art. Summary of the Invention

[0005] To solve the above problems, embodiments of the present disclosure disclose a lead finger-based semiconductor package and a method for manufacturing the semiconductor package, which can reduce voids in a plastic package and / or suppress warpage.

[0006] According to one aspect of the present disclosure, a semiconductor package is provided, comprising: a substrate; a plurality of first chips stacked on the substrate, each of the plurality of first chips being electrically connected to the substrate via a first bonding wire; a second chip arranged on the substrate and spaced apart from the plurality of first chips in a first direction parallel to an upper surface of the substrate, wherein the second chip comprises a dummy pad and a lead finger, the dummy pad being located on an upper surface of the second chip, the lead finger being located on the dummy pad, and the lead finger being electrically connected to the substrate via a second bonding wire; a first plastic package covering the plurality of first chips and the second chip on the substrate and exposing the upper surface of the lead finger; a third chip arranged on an upper surface of the first plastic package and electrically connected to the lead finger via a third bonding wire; and a second plastic package covering the third chip on the first plastic package.

[0007] Preferably, a first distance in the second direction between the upper surface of the lead finger and the upper surface of the substrate may be equal to or greater than a thickness of the first plastic package body in the second direction between the upper surface of the first plastic package body and the upper surface of the substrate.

[0008] Preferably, the lead finger may include at least one conductive connection member stacked in the second direction, and an upper surface of an uppermost conductive connection member among the at least one conductive connection member is exposed from the first plastic package body.

[0009] Preferably, each of the at least one conductive connection member may be a metal ball.

[0010] Preferably, the second bonding wire may be connected to a lowermost conductive connection among the at least one conductive connection.

[0011] Preferably, the second chip may be a circuit chip having electrical functions, and the second chip may be electrically connected to the substrate through a fourth bonding wire.

[0012] Preferably, the second chip may further include a function pad located on the upper surface of the second chip and spaced apart from the dummy pad in the first direction, wherein the fourth bonding wire is connected to the function pad and the substrate.

[0013] Preferably, the second chip may be a dummy chip without electrical function.

[0014] Preferably, the dummy pads and the lead fingers may be arranged in at least one column on the upper surface of the second chip.

[0015] Preferably, the thickness of the first plastic packaging body may be greater than the thickness of the second plastic packaging body in the second direction between the upper surface of the second plastic packaging body and the upper surface of the first plastic packaging body.

[0016] Preferably, the first plastic packaging body and the second plastic packaging body may be formed of different materials.

[0017] Preferably, the third chip may be provided in plurality and may be electrically connected to each other through the third bonding wires.

[0018] According to another aspect of the present disclosure, a method for manufacturing a semiconductor package is provided, comprising: providing a substrate; stacking a plurality of first chips on the substrate, and electrically connecting each of the plurality of first chips to the substrate via a first bonding wire; arranging a second chip on the substrate, the second chip being spaced apart from the plurality of first chips in a first direction parallel to the upper surface of the substrate, wherein the second chip includes a dummy pad located on the upper surface of the second chip; arranging lead fingers on the dummy pad, and electrically connecting the lead fingers to the substrate via a second bonding wire; performing a first molding process to form a first molding body, the first molding body covering the plurality of first chips and the second chip on the substrate and exposing the upper surfaces of the lead fingers; arranging a third chip on the upper surface of the first molding body, and electrically connecting the third chip to the lead fingers via a third bonding wire; and performing a second molding process to form a second molding body, the second molding body covering the third chip on the first molding body.

[0019] Preferably, a first distance between the upper surface of the lead finger and the upper surface of the substrate in the second direction may be equal to or greater than a thickness of the first plastic package body in the second direction between the upper surface of the first plastic package body and the upper surface of the substrate.

[0020] Preferably, the step of setting the lead finger may include: stacking at least one conductive connector in a second direction perpendicular to the upper surface of the substrate, and the step of performing the first molding process may include: exposing the upper surface of the uppermost conductive connector among the at least one conductive connector from the first molding body.

[0021] Preferably, each of the at least one conductive connection member may be a metal ball.

[0022] Preferably, the second bonding wire may be connected to a lowermost conductive connection among the at least one conductive connection, and the lowermost conductive connection may be disposed on the dummy pad.

[0023] Preferably, the second chip may be a circuit chip having electrical functions, and the step of providing the second chip may further include: electrically connecting the second chip to the substrate via a fourth bonding wire.

[0024] Preferably, the second chip may further include a function pad located on the upper surface of the second chip and spaced apart from the dummy pad in the first direction, wherein the fourth bonding wire is connected to the function pad and the substrate.

[0025] Preferably, the second chip may be a dummy chip without electrical function.

[0026] Preferably, the dummy pads and the lead fingers may be arranged in at least one column on the upper surface of the second chip.

[0027] Preferably, the thickness of the first plastic packaging body may be greater than the thickness of the second plastic packaging body in the second direction between the upper surface of the second plastic packaging body and the upper surface of the first plastic packaging body.

[0028] Preferably, the first plastic packaging body and the second plastic packaging body may be formed of different materials.

[0029] Preferably, the third chip may be provided in plurality and may be electrically connected to each other through the third bonding wires. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects of the present disclosure and their advantages will become clear by describing the embodiments of the present disclosure in detail below in conjunction with the accompanying drawings. In the accompanying drawings, the same reference numerals will always indicate the same elements.

[0031] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0032] Figure 2 is a cross-sectional view of a semiconductor package according to a comparative example.

[0033] Figure 3 is a flowchart of a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0034] Figure 4 、 Figure 5 、 Figure 6 and Figure 7 is a cross-sectional view of an intermediate stage in a method of manufacturing a semiconductor package according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Various embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings in which some embodiments are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0036] For ease of description, spatially relative terms such as "under," "beneath," "below," "above," and "above" may be used herein to describe the relationship of one element to other elements as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element previously described as "under" or "beneath" another element would then be oriented "above" the other element. Thus, the term "under" may encompass both the orientations of "above" and "under."

[0037] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0038] Reference Figure 1 The semiconductor package 1000 includes: a substrate SUB; a plurality of first chips 100 stacked on the substrate SUB, each of the plurality of first chips 100 being electrically connected to the substrate SUB via a first bonding wire 110; a second chip 200 disposed on the substrate SUB and spaced apart from the plurality of first chips 100 in a first direction D1 parallel to an upper surface of the substrate SUB, wherein the second chip 200 includes a dummy pad 220 and a lead finger 230 located on the dummy pad 220, and the dummy pad 220 is located at a position on the upper surface of the second chip 200, and the lead fingers 230 are electrically connected to the substrate SUB through the second bonding wires 210; a first plastic package 400, covering a plurality of first chips 100 and second chips 200 on the substrate SUB and exposing the upper surface of the lead fingers 230; a third chip 300, arranged on the upper surface of the first plastic package 400, and electrically connected to the lead fingers 230 through the third bonding wires 310; and a second plastic package 500, covering the third chip 300 on the first plastic package 400.

[0039] In one embodiment, the substrate SUB may be a printed circuit board. For example, the substrate SUB may include a multilayer wiring 600, a plurality of vias interconnecting the multilayer wiring 600, a pad PAD disposed on the upper surface of the substrate SUB, and an external connection terminal 700 disposed on the lower surface of the substrate SUB. In this case, the semiconductor package 1000 may be a system-in-package structure including a plurality of packaged chips and may be electrically connected to an external device through the external connection terminal 700.

[0040] The plurality of first chips 100 may be circuit chips having electrical functions, such as memory chips or logic chips. In one embodiment, the active surface of each of the plurality of first chips 100 may be arranged upward. The first bonding wires 110 may be connected to connection pads provided on the active surface of each first chip 100 and pads PAD provided on the substrate SUB, respectively, so that the first chips 100 can be electrically interconnected with the substrate SUB.

[0041] In one embodiment, a plurality of first chips 100 may be sequentially stacked on the substrate SUB along a second direction D2 perpendicular to the upper surface of the substrate SUB to form a first chip stack. A die attach film DAF may be provided between adjacent first chips 100. In one embodiment, the material of the first bonding wire 110 may be gold (Au), but the present disclosure is not limited thereto.

[0042] In one embodiment, the third chip 300 may be provided in plurality and may be electrically connected to each other via third bonding wires 310. For example, a plurality of third chips 100 may be sequentially stacked on the first plastic package 400 along a second direction D2 perpendicular to the upper surface of the substrate SUB to form a second chip stack. A die attach film DAF may also be provided between adjacent third chips 300. The third chip 300 may also be a circuit chip having an electrical function. However, the third chip 300 may have an electrical function different from that of the first chip 100.

[0043] In one embodiment, the first molding body 400 and the second molding body 500 can be formed from different materials. For example, the first molding body 400 can include epoxy resin (EMC). The second molding body 500 can be made of a material that is more rigid than EMC. In this case, since the second molding body 500 is disposed above the first molding body 400 and has greater rigidity, it can prevent the semiconductor package 1000 from warping. Furthermore, the first molding body 400 can be formed from a material with greater fluidity than the second molding body 500. This can reduce voids or pores caused by poor filling of the molding compound during the first molding process, thereby improving product yield.

[0044] In one embodiment, in the second direction D2, the thickness T1 of the first plastic package body 400 can be greater than the thickness T2 of the second plastic package body 500. Thickness T1 is the length between the upper surface of the first plastic package body 400 and the upper surface of the substrate SUB in the second direction D2. In this case, the number of third chips 300 can be less than the number of first chips 100, and the thickness of the second chip stack can be less than the thickness of the first chip stack.

[0045] In one embodiment, a first distance H1 between the upper surface of the lead finger 230 and the upper surface of the substrate SUB in the second direction D2 may be equal to or greater than a thickness T1 in the second direction D2 of the first mold package body 400. In this case, the third chip 300 may be electrically connected to the exposed upper surface of the lead finger 230 via the third bonding wire 310.

[0046] In one embodiment, the lead finger 230 may include at least one conductive connection 231, 232, and 233 stacked in a second direction D2 perpendicular to the upper surface of the substrate SUB. The upper surface of the uppermost conductive connection 233 among the at least one conductive connection 231, 232, and 233 may be exposed from the first plastic package 400. The lowermost third chip among the third chips 300 may be electrically connected to the exposed upper surface of the uppermost conductive connection 233 via a third bonding wire 310.

[0047] Conductive connections 231, 232, and 233 may be stacked on one another along the second direction D2 to form lead fingers 230. A second distance H2 in the second direction D2 between the exposed upper surface of lead finger 230 and the upper surface of second chip 200 may be equal to the sum of the heights of conductive connections 231, 232, and 233 in the second direction D2.

[0048] In one embodiment, each of at least one conductive connector 231, 232, and 233 may be a metal ball. For example, each of the conductive connectors 231, 232, and 233 may be a gold wire ball formed directly when forming the second bonding wire 210. For example, the material of the second bonding wire 210 may be Au, and the material of the gold wire ball may be the same as that of the second bonding wire 210. The second distance H2 may be equal to the sum of the diameters of each metal ball (e.g., the gold wire ball). In this case, the second bonding wire 210 may be connected to the lowest conductive connector 231 among the conductive connectors 231, 232, and 233, so that the third chip 300 can be electrically connected to the pad PAD on the substrate SUB via the third bonding wire 310, the lead finger 230, the dummy pad 220, and the second bonding wire 210.

[0049] In addition, a third distance H3 in the second direction D2 between the upper surface of the first plastic package body 400 and the upper surface of the uppermost first chip among the plurality of first chips 100 may be smaller than the second distance H2 in the second direction D2. In this case, the thickness of the second chip 200 in the second direction D2 may be smaller than the thickness of the first chip stack.

[0050] In one embodiment, the second chip 200 may be a circuit chip having electrical functions, and the second chip 200 may be electrically connected to the substrate SUB through fourth bonding wires 240 .

[0051] Specifically, the second chip 200 may further include a function pad 250 located on the upper surface of the second chip 200 and spaced apart from the dummy pad 220 in the first direction D1, wherein the fourth bonding wire 240 is connected to the function pad 250. In this case, a signal from an external device may be transmitted to the second chip 200 via the external connection terminal 700, the multi-layer wiring 600, the pad PAD, the fourth bonding wire 240, and the function pad 250, or the second chip 200 may send a signal to an external device via the function pad 250, the fourth bonding wire 240, the pad PAD, the multi-layer wiring 600, and the external connection terminal 700.

[0052] In another embodiment, Figure 1 Unlike the example shown, the second chip 200 may be a dummy chip that does not have electrical functions. In this case, the Figure 1 The fourth bonding wire 240 and the functional pad 250 are arranged on the upper surface of the second chip 200. The dummy pad 220 and the lead finger 230 can be arranged in at least one row along a third direction D3 perpendicular to both the first direction D1 and the second direction D2. Therefore, more connection points can be provided to the upper third chip 300, thereby increasing the integration density of the semiconductor package 1000.

[0053] Figure 2 is a cross-sectional view of a semiconductor package according to a comparative example.

[0054] Reference Figure 2 , the semiconductor package 2000 includes Figure 1 The first chip 100, the second chip 200, and the third chip 300 in the semiconductor package 1000 shown in FIG. The first chip 100A, the second chip 200A, and the third chip 300 correspond to each other. Furthermore, the semiconductor package 2000 further includes a first dummy chip 800 and a second dummy chip 900. The first dummy chip 800 may have the same thickness as the thickness of the second chip 200A in the second direction D2 and may be spaced apart from the second chip 200A along the first direction D1. The second dummy chip 900 may be stacked on the second chip 200A and the first dummy chip 800 so that the upper surface of the second dummy chip 900 is at the same height as the upper surface of the uppermost first chip among the plurality of first chips 100A stacked along the second direction D2. The third chip 300A may be provided in plurality and stacked on the uppermost first chip and the second dummy chip 900.

[0055] Typically, chips with different functions have different sizes. To package these chips of varying sizes within a single package, it is necessary to introduce some non-functional dummy chips or buffer chips, such as the first dummy chip 800 and the second dummy chip 900 in semiconductor package 2000, to compensate for the size differences between the different chips. This results in the presence of numerous tunnels within the package.

[0056] The structure of semiconductor package 2000 described above forms multiple tunnel structures. For example, tunnel structure V1 can be located between the sidewalls of the stacked first chips 100A and the sidewalls of the stacked second chip 200A and second dummy chip 900. Tunnel structure V2 can be located between the sidewalls of the spaced-apart first dummy chip 800 and second chip 200A. During the encapsulation process, the encapsulation compound can be difficult to completely fill these tunnel structures, resulting in voids within the tunnel structures, which can cause product reliability issues.

[0057] The semiconductor package structure according to an embodiment of the present disclosure may include a first plastic package 400 and a second plastic package 500 disposed on the first plastic package 400. The second chip 200 may be encapsulated in the first plastic package 400 and may have dummy pads 220 and lead fingers 230 disposed on its upper surface. The third chip 300, disposed above the second chip 200 and encapsulated in the second plastic package 500, may be electrically connected to the substrate SUB via the lead fingers 230. As a result, the aforementioned tunnel structure may be eliminated, and the formation of voids in the first plastic package 400 and the second plastic package 500 may be avoided. Therefore, the reliability of the semiconductor package may be improved.

[0058] Hereinafter, a method of manufacturing a semiconductor package according to an embodiment of the present disclosure will be described. Figure 3 is a flowchart of a method of manufacturing a semiconductor package according to an embodiment of the present disclosure. Figures 4 to 7 is a cross-sectional view of an intermediate stage in a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0059] exist Figures 3 to 7 The semiconductor package described in the Figure 1 The semiconductor package 1000 shown in FIG. Figure 3 and Figure 4 The method for manufacturing a semiconductor package includes: in step S1, providing a substrate SUB. For example, the substrate SUB may be a printed circuit board. The substrate SUB may include a multilayer wiring 600 and a plurality of vias.

[0060] In step S2, a plurality of first chips 100 are stacked on a substrate SUB, and each of the plurality of first chips 100 is electrically connected to the substrate SUB through a first bonding wire 110. Each of the plurality of first chips 100 may be a chip having electrical functions, such as a memory chip or a logic chip.

[0061] In step S3, a second chip 200 is disposed on a substrate SUB. The second chip 200 is spaced apart from the plurality of first chips 100 in a first direction D1 parallel to the upper surface of the substrate SUB. The second chip 200 includes a dummy pad 220 located on its upper surface. Here, the dummy pad 220 may be pre-added on the second chip 200 and may not be electrically connected to other pads of the second chip 200. In other words, the dummy pad 220 may serve only as a relay element electrically connecting the third chip 300 to the substrate SUB, and does not participate in or constitute a circuit pattern of the second chip 200.

[0062] In step S4 , lead fingers 230 are provided on the dummy pad 220 , and the lead fingers 230 are electrically connected to the substrate SUB through the second bonding wires 210 .

[0063] In one embodiment, step S4 of providing the lead fingers may include stacking at least one conductive connection 231, 232, and 233 along the second direction D2. Each of the conductive connections 231, 232, and 233 may be a metal ball, such as a gold wire ball. In this case, the second bonding wire 210 may be connected to the bottommost conductive connection 231 of the conductive connections 231, 232, and 233.

[0064] In one embodiment, the second chip 200 may be a circuit chip having electrical functions, and the step S3 of providing the second chip may further include: electrically connecting the second chip 200 to the substrate SUB via fourth bonding wires 240 .

[0065] Specifically, the second chip 200 may further include a function pad 250 on the upper surface of the second chip 200 and spaced apart from the dummy pad 230 in the first direction D1 , wherein the fourth bonding wire 240 is connected to the function pad 250 .

[0066] In another embodiment, the second chip 200 may be a dummy chip or a buffer chip having no electrical function. In this case, the functional pads and the fourth bonding wires may be omitted, and the dummy pads 220 and the lead fingers 230 may be arranged in at least one column on the upper surface of the second chip 200.

[0067] Reference Figure 3 and Figure 5In step S5 , a first molding process P1 is performed to form a first molding body 400 . The first molding body 400 covers the plurality of first chips 100 and second chips 200 on the substrate SUB and exposes the upper surfaces of the lead fingers 230 .

[0068] In one embodiment, step S5 of performing the first molding process may include exposing an upper surface of an uppermost conductive connection 233 among the at least one conductive connection 231, 232, and 233 from the first molding body 400. In this case, a first distance H1 in the second direction D2 between the exposed upper surface of the lead finger 230 and the upper surface of the substrate SUB may be equal to or greater than a thickness T1 of the first molding body 400 in the second direction D2.

[0069] For example, Figure 5 As shown, during the first molding process P1, the thickness T1 of the first molding body 400 in the second direction D2 can be formed to be equal to or slightly less than the height H1 of the upper surface of the lead finger 230 from the upper surface of the substrate SUB in the second direction D2. Thus, during the first molding process P1, the uppermost metal ball 233 of the lead finger 230 will be pushed into the release film at the bottom of the molding compound. Therefore, after the first molding process P1 is completed, the upper surface of the uppermost metal ball 233 can be directly exposed to the outside and serve as a lead finger in the subsequent wire bonding process.

[0070] Reference Figure 3 and Figure 6 In step S6, a third chip 300 may be provided on the upper surface of the first plastic package 400 and electrically connected to the lead fingers 230 via third bonding wires 310. In one embodiment, a plurality of third chips 300 may be provided and electrically connected to each other via third bonding wires 310.

[0071] Reference Figure 3 and Figure 7 In step S7, a second molding process P2 is performed to form a second molding body 500. The second molding body 500 covers the third chip 300 on the first molding body 400. In one embodiment, a thickness T1 of the first molding body 400 in the second direction D2 may be greater than a thickness T2 of the second molding body 500 in the second direction D2. The first molding body 400 and the second molding body 500 may be formed of different materials.

[0072] As a summary and review, according to the embodiments of the present disclosure, a first plastic package body and a second plastic package body stacked vertically can be formed through multiple plastic packaging processes. The dummy pads and lead fingers provided on the second chip can be encapsulated in the first plastic package body, and the third chip provided above the second chip can be encapsulated in the second plastic package body. The third chip can be electrically interconnected by wire bonding through the dummy pads and lead fingers instead of through molding vias (TMVs). Therefore, voids in the plastic package body can be avoided, the structure of the multi-chip package (MCP) can be simplified, and its reliability can be improved. In addition, the manufacturing method of the semiconductor package disclosed in the present disclosure can use traditional packaging processes and equipment, without the need for additional new processes or equipment, thereby saving production costs.

[0073] While embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A semiconductor package, comprising: substrate; a plurality of first chips stacked on the substrate, each of the plurality of first chips being electrically connected to the substrate via a first bonding wire; a second chip disposed on the substrate and spaced apart from the plurality of first chips in a first direction parallel to an upper surface of the substrate, wherein the second chip includes a dummy pad and a lead finger, the dummy pad being located on an upper surface of the second chip, the lead finger being located on the dummy pad, and the lead finger being electrically connected to the substrate through a second bonding wire; a first plastic package body, covering the plurality of first chips and the second chip on the substrate and exposing upper surfaces of the lead fingers; a third chip disposed on the upper surface of the first plastic package and electrically connected to the lead fingers through third bonding wires; and The second plastic packaging body covers the third chip on the first plastic packaging body.

2. The semiconductor package according to claim 1, wherein A first distance in a second direction between the upper surface of the lead finger and the upper surface of the substrate is equal to or greater than a thickness of the first plastic package body in the second direction between the upper surface of the first plastic package body and the upper surface of the substrate, and the second direction is perpendicular to the upper surface of the substrate.

3. The semiconductor package according to claim 2, wherein The lead finger includes at least one conductive connection member stacked in the second direction, and an upper surface of an uppermost conductive connection member among the at least one conductive connection member is exposed from the first plastic package body.

4. The semiconductor package according to claim 3, wherein Each of the at least one conductive connection is a metal ball.

5. The semiconductor package according to claim 3, wherein The second bonding wire is connected to a lowermost conductive connection of the at least one conductive connection, and Wherein, the lowermost conductive connecting member is arranged on the dummy pad.

6. The semiconductor package according to claim 2, wherein The thickness of the first plastic packaging body is greater than the thickness of the second plastic packaging body in the second direction between the upper surface of the second plastic packaging body and the upper surface of the first plastic packaging body.

7. A method for manufacturing a semiconductor package, comprising: providing a substrate; stacking a plurality of first chips on the substrate, and electrically connecting each of the plurality of first chips to the substrate through a first bonding wire; disposing a second chip on the substrate, the second chip being spaced apart from the plurality of first chips in a first direction parallel to an upper surface of the substrate, wherein the second chip includes a dummy pad located on an upper surface of the second chip; providing a lead finger on the dummy pad and electrically connecting the lead finger to the substrate through a second bonding wire; Performing a first molding process to form a first molding body, wherein the first molding body covers the plurality of first chips and the second chip on the substrate and exposes upper surfaces of the lead fingers; Disposing a third chip on the upper surface of the first plastic package body, and electrically connecting the third chip to the lead fingers through third bonding wires; and A second plastic packaging process is performed to form a second plastic packaging body, where the second plastic packaging body covers the third chip on the first plastic packaging body.

8. The method according to claim 7, wherein A first distance in a second direction between the upper surface of the lead finger and the upper surface of the substrate is equal to or greater than a thickness of the first plastic package body in the second direction between the upper surface of the first plastic package body and the upper surface of the substrate, and the second direction is perpendicular to the upper surface of the substrate.

9. The method according to claim 8, wherein The step of arranging the lead fingers includes: stacking at least one conductive connection member in the second direction, and The step of performing the first plastic packaging process includes: exposing the upper surface of the uppermost conductive connecting member among the at least one conductive connecting member from the first plastic packaging body.

10. The method according to claim 9, wherein Each of the at least one conductive connection is a metal ball.

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