Buck converter capable of quickly responding to output voltage switching

Abstract

The invention relates to the technical field of power management integrated circuits, and discloses a Buck converter capable of quickly responding to output voltage switching. The converter comprises a Buck control module, a BUCK driving module, a power tube, an auxiliary charging low dropout linear regulator and an auxiliary discharging low dropout linear regulator. Wherein the target output value of the auxiliary charging low-dropout linear regulator is lower than the target output value of the Buck converter by a first deviation value, and the target output value of the auxiliary discharging low-dropout linear regulator is higher than the target output value of the Buck converter by a second deviation value; when the reference voltage rises, the auxiliary charging low dropout linear regulator injects large current to accelerate the rise of the output voltage; when the reference voltage drops, the auxiliary discharge low dropout linear regulator absorbs large current to accelerate the drop of the output voltage. On the premise that the overall efficiency of the Buck converter is not affected, the switching speed and the transient response capability of the output voltage are remarkably improved, and the Buck converter is suitable for application scenes where voltage domains need to be frequently and rapidly switched.

Description

Technical Field

[0001] The present application relates to the field of power management circuits, and in particular to switching power supply control technology. Background Art

[0002] With the advancement of mobile communication technology, the integration and functional complexity of RF transceiver chips continue to increase. The RF amplifier is a key functional module in RF transceiver chips, and its supply voltage must be rapidly switched according to different operating modes. For example, in the GSM standard, the RF amplifier requires a higher supply voltage to achieve better power efficiency; in the WCDMA standard, a lower supply voltage is required to achieve better linearity. Therefore, the power management circuit that powers the RF amplifier must be able to rapidly switch the output voltage.

[0003] Buck converters are currently widely used in RF amplifier power supply circuits due to their high conversion efficiency. However, traditional buck converters suffer from slow response speeds. This is because the output of the buck converter is connected to an external inductor, L0, and the current in the inductor cannot change suddenly. When the output voltage needs to be increased rapidly, even if the loop compensator quickly increases the PWM duty cycle, the output voltage's rise rate will be limited due to the limited rise rate of the inductor current. Similarly, when the output voltage needs to be reduced rapidly, the rate of decrease of the inductor current also limits the output voltage's fall rate.

[0004] This slow response can lead to the following issues when switching operating modes: when switching from low voltage to high voltage, the slow voltage rise can cause insufficient output power in the RF amplifier during the transition; when switching from high voltage to low voltage, the slow voltage fall can cause poor linearity in the RF amplifier during the transition. These issues can affect the overall performance of the RF transceiver chip.

[0005] Therefore, how to improve the switching speed of the output voltage while maintaining the high efficiency characteristics of the Buck converter is a technical problem that needs to be solved urgently. Summary of the Invention

[0006] The purpose of this application is to provide a Buck converter that quickly responds to output voltage switching to solve the problems raised in the above background technology.

[0007] The present application discloses a Buck converter with fast response output voltage switching, comprising:

[0008] Buck control module, used to monitor the output voltage of the Buck converter, output pulse width modulation signal, and generate bias current and reference voltage;

[0009] A buck driver module and a power tube, wherein the input end of the buck driver module is connected to the pulse width modulation signal, and the output end outputs the driving signal; the power tube includes an upper P-type power tube and a lower N-type power tube, wherein the source of the P-type power tube is connected to the off-chip input power supply voltage, the gate is connected to the driving signal, the drain is short-circuited with the drain of the N-type power tube and output to the outside of the chip, the source of the N-type power tube is connected to the ground terminal of the chip, and the gate is connected to the driving signal;

[0010] an auxiliary charging low-dropout linear regulator, wherein the power terminal is connected to the analog power voltage, the ground terminal is connected to the analog ground, the input terminals are connected to the first reference voltage, the fourth bias current, and the first bias current, respectively, the trim control terminal is connected to the first mismatch adjustment signal, and the output terminal is connected to the output voltage;

[0011] an auxiliary discharge low-dropout linear regulator, wherein the power supply terminal is connected to the analog power supply voltage, the ground terminal is connected to the analog ground, the input terminals are respectively connected to the first reference voltage, the fifth bias current, the second bias current, and the third bias current, the trimming control terminal is connected to the second mismatch adjustment signal, and the output terminal is connected to the output voltage;

[0012] Off-chip inductors and load capacitors are used to stabilize the output voltage.

[0013] In a preferred embodiment, the target output value of the auxiliary charging low-voltage dropout linear regulator is lower than the target output value of the Buck converter by a first deviation value. When the reference voltage rises rapidly, the Buck converter gradually increases the output voltage through pulse width modulation signal control. At the same time, the auxiliary charging low-voltage dropout linear regulator responds quickly and injects current into the output terminal to make the output voltage rise rapidly. When the output voltage reaches the preset output voltage of the auxiliary charging low-voltage dropout linear regulator, the auxiliary charging low-voltage dropout linear regulator loop is automatically closed.

[0014] The target output value of the auxiliary discharge low-voltage dropout linear regulator is higher than the target output value of the Buck converter by a second deviation value. When the reference voltage drops rapidly, the Buck converter gradually reduces the output voltage through pulse width modulation signal control. At the same time, the auxiliary discharge low-voltage dropout linear regulator responds quickly, draws current from the output end to make the output voltage drop rapidly. When the output voltage reaches the preset output voltage of the auxiliary discharge low-voltage dropout linear regulator, the auxiliary discharge low-voltage dropout linear regulator loop is automatically closed, so that the auxiliary charge low-voltage dropout linear regulator and the auxiliary discharge low-voltage dropout linear regulator only work briefly when the reference voltage switches between rising and falling rapidly. After the switching is completed, the auxiliary charge low-voltage dropout linear regulator and the auxiliary discharge low-voltage dropout linear regulator are in the off state, which does not affect the overall efficiency of the Buck converter.

[0015] In a preferred embodiment, the Buck control module includes:

[0016] a first level converter and a second level converter, wherein the input end of the first level converter is connected to the first digital mismatch adjustment signal and the output end thereof outputs the first mismatch adjustment signal; the input end of the second level converter is connected to the second digital mismatch adjustment signal and the output end thereof outputs the second mismatch adjustment signal;

[0017] A low-pass filter, whose input terminal is connected to the reference voltage and outputs a first reference voltage after filtering out its high-frequency noise;

[0018] A loop compensator, wherein a reference voltage input terminal thereof is connected to a first reference voltage, a feedback input terminal thereof is connected to an output voltage, and an output loop compensator output signal is output;

[0019] A PWM generator, whose input terminal is connected to the loop compensator output signal and outputs a pulse width modulation signal;

[0020] The bias current generator has an input terminal connected to the first reference voltage and an output terminal outputting a first bias current, a second bias current, a third bias current, a fourth bias current and a fifth bias current.

[0021] In a preferred example, the auxiliary charging low-voltage dropout linear regulator also includes a first amplifier, whose power supply terminal is connected to the analog power supply voltage, the ground terminal is connected to the analog ground, the non-inverting input terminal is connected to the first reference voltage, the reverse input terminal is connected to the first feedback voltage, and the output terminal outputs the first amplifier output voltage.

[0022] In a preferred embodiment, the auxiliary charging low voltage drop linear regulator further includes:

[0023] a first output current limiting module, wherein a power supply terminal is connected to the analog power supply voltage, a ground terminal is connected to the analog ground, an input terminal is connected to the fourth bias current, and an output terminal is connected to the first amplifier output voltage;

[0024] a first N-type transistor, a first P-type transistor, and a second P-type transistor, wherein the source of the first N-type transistor is connected to the analog ground, the gate is connected to the first amplifier output voltage, and the drain is connected to the drain of the first P-type transistor to form a first current mirror connection point voltage; the drain and gate of the first P-type transistor are short-circuited, and the source is connected to the analog power supply voltage; the source of the second P-type transistor is connected to the analog power supply voltage, the gate is short-circuited to the gate of the first P-type transistor, and the drain is connected to the output voltage;

[0025] The first voltage divider feedback module has an input terminal connected to the output voltage, a bias current terminal connected to the first bias current, a trimming control terminal connected to the first mismatch adjustment signal, and a ground terminal connected to the analog ground.

[0026] In a preferred embodiment, the first voltage division feedback module further includes:

[0027] A first resistor group includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor;

[0028] a first capacitor;

[0029] A first group of N-type switching transistors includes a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, and a sixth N-type transistor;

[0030] a first decoder;

[0031] The second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, and the seventh resistor are connected in series in sequence. One end of the second resistor is connected to the output voltage, and a voltage signal between the other end and the third resistor in series serves as the first feedback voltage. The first capacitor and the first resistor are connected in series between the output voltage and the first feedback voltage. The voltage signal between the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, and the seventh resistor in series is connected to the sources of the third N-type transistor, the fourth N-type transistor, the fifth N-type transistor, and the sixth N-type transistor, respectively. The drains of the third N-type transistor, the fourth N-type transistor, the fifth N-type transistor, and the sixth N-type transistor are short-circuited together and connected to the first bias current. The input end of the first decoder is connected to the first mismatch adjustment signal, and the output end outputs a first set of switch control signals, including a first switch control signal, a second switch control signal, a third switch control signal, and a fourth switch control signal, and is connected to the gates of the third N-type transistor, the fourth N-type transistor, the fifth N-type transistor, and the sixth N-type transistor in sequence.

[0032] In a preferred embodiment, the auxiliary discharge low voltage dropout linear regulator further includes:

[0033] a second amplifier, having a power supply terminal connected to the analog power supply voltage, a ground terminal connected to the analog ground, an inverting input terminal connected to the first reference voltage, a non-inverting input terminal connected to the second feedback voltage, and an output terminal outputting the second amplifier output voltage;

[0034] a second output current limiting module, wherein a power supply terminal is connected to the analog power supply voltage, a ground terminal is connected to the analog ground, an input terminal is connected to the fifth bias current, and an output terminal is connected to the second amplifier output voltage;

[0035] a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a third P-type transistor, a fourth P-type transistor, and an eighth resistor, wherein the source of the seventh N-type transistor is connected to the analog ground, the gate is connected to the second amplifier output voltage, and the drain is connected to the drain of the third P-type transistor to form a second current mirror connection point voltage; the drain and gate of the third P-type transistor are short-circuited, and the source is connected to the analog power supply voltage; the source of the fourth P-type transistor is connected to the analog power supply voltage, the gate is short-circuited to the gate of the third P-type transistor, and the drain is connected to the gate and drain of the eighth N-type transistor to form a third current mirror connection point voltage; the source of the eighth N-type transistor is connected to the analog ground, the gate and drain are short-circuited to the third current mirror connection point voltage and connected to the gate of the ninth N-type transistor; the drain of the ninth N-type transistor is connected to the output voltage and one end of the eighth resistor; the other end of the eighth resistor is connected to the third bias current;

[0036] The second voltage divider feedback module has an input terminal connected to the output voltage, a bias current terminal connected to the second bias current, a trimming control terminal connected to the second mismatch adjustment signal, and a ground terminal connected to the analog ground.

[0037] In a preferred embodiment, the second voltage division feedback module further includes:

[0038] a second group of resistors, including a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor;

[0039] a second capacitor and a third capacitor;

[0040] a second group of N-type switching transistors, including a tenth N-type transistor, an eleventh N-type transistor, a twelfth N-type transistor, and a thirteenth N-type transistor;

[0041] a second decoder;

[0042] The tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, the fourteenth resistor, and the fifteenth resistor are connected in series in sequence; one end of the tenth resistor is connected to the analog ground, and a voltage signal between the other end and the series connection of the eleventh resistor serves as the second feedback voltage; the second capacitor and the ninth resistor are connected in series between the output voltage and the second feedback voltage; the voltage signal between the tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, and the series connection of the fourteenth resistor is connected to the sources of the tenth N-type transistor, the eleventh N-type transistor, the twelfth N-type transistor, and the thirteenth N-type transistor, respectively; the drains of the tenth N-type transistor, the eleventh N-type transistor, the twelfth N-type transistor, and the thirteenth N-type transistor are short-circuited together and connected to the second bias current; the input end of the second decoder is connected to the second mismatch adjustment signal, and the output end outputs a second set of switch control signals, including a fifth switch control signal, a sixth switch control signal, a seventh switch control signal, and an eighth switch control signal, and is connected to the gates of the tenth N-type transistor, the eleventh N-type transistor, the twelfth N-type transistor, and the thirteenth N-type transistor in sequence.

[0043] This application achieves the following technical effects by introducing an auxiliary charging low-voltage dropout linear regulator and an auxiliary discharging low-voltage dropout linear regulator on the basis of a traditional Buck converter:

[0044] First, it enables rapid output voltage switching and improves the circuit's transient response. In a traditional buck converter, when the reference voltage suddenly rises (falls), the loop compensator's output signal rises (falls), the pulse-width modulation signal's duty cycle increases (decreases), the power transistor's on-time increases (shortens), and the current in the external inductor rises (falls). Because the current in the external inductor cannot change suddenly, the output voltage cannot rise (fall) quickly, making it unsuitable for applications requiring rapid output voltage switching. By introducing an auxiliary charging low-dropout linear regulator (LDO) and an auxiliary discharging LDO, when the reference voltage suddenly rises, the output of the auxiliary charging LDO bypasses the external inductor. Therefore, the internal loop of the auxiliary charging LDO further activates the second P-type transistor, injecting a large current into the output terminal to increase the output voltage, significantly improving the output voltage's rise speed. When the reference voltage drops suddenly, the output of the auxiliary discharge low-voltage dropout linear regulator does not pass through the off-chip inductor, so the internal loop of the auxiliary discharge low-voltage dropout linear regulator will further turn on the ninth N-type transistor, drawing a large current from the output end to drop the output voltage, greatly increasing the output voltage drop speed.

[0045] Second, it will not affect the overall efficiency of the Buck converter. By adjusting the first mismatch adjustment signal and the second mismatch adjustment signal, the target output value of the auxiliary charging low-voltage dropout linear regulator is lower than the target output value of the Buck converter by a first deviation value, while the target output value of the auxiliary discharging low-voltage dropout linear regulator is higher than the target output value of the Buck converter by a second deviation value. Therefore, the auxiliary charging low-voltage dropout linear regulator and the auxiliary discharging low-voltage dropout linear regulator only work briefly when the reference voltage is rapidly rising and falling, respectively. After the switching is completed, the auxiliary charging low-voltage dropout linear regulator and the auxiliary discharging low-voltage dropout linear regulator are in the off state, which will not affect the overall efficiency of the Buck converter.

[0046] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be considered as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 1 is a schematic diagram of the overall structure of a Buck converter with fast response output voltage switching according to an embodiment of the present application.

[0048] Figure 2 This is a structural diagram of the prior art in which a compensation module is added to the constant on-time control.

[0049] Figure 3 It is a structural diagram of a selectable design scheme for reference voltage in the prior art.

[0050] Figure 4 4 is a schematic structural diagram of a Buck control module of a Buck converter with fast response output voltage switching according to an embodiment of the present application.

[0051] Figure 51 is a circuit diagram of an auxiliary charging low-dropout linear regulator of a Buck converter with fast response output voltage switching according to an embodiment of the present application.

[0052] Figure 6 1 is a circuit structure diagram of a first voltage divider feedback module of a Buck converter that quickly responds to output voltage switching according to an embodiment of the present application.

[0053] Figure 7 : is a waveform diagram of the working state of the auxiliary charging low-dropout linear regulator of the Buck converter with fast response output voltage switching according to an embodiment of the present application, wherein Figure 7 (a) shows the output voltage waveform when there is no auxiliary charging low-dropout linear regulator. Figure 7 (b) shows the output voltage waveform when assisted by an auxiliary charging low-dropout linear regulator.

[0054] Figure 8 1 is a circuit diagram of an auxiliary discharge low-dropout linear regulator of a Buck converter with fast response output voltage switching according to an embodiment of the present application.

[0055] Figure 9 1 is a circuit structure diagram of a second voltage divider feedback module of a Buck converter that quickly responds to output voltage switching according to an embodiment of the present application.

[0056] Figure 10 : is a waveform diagram of the working state of the auxiliary discharge low-dropout linear regulator of the Buck converter with fast response output voltage switching according to an embodiment of the present application, wherein Figure 10 (a) shows the output voltage waveform when there is no auxiliary discharge low voltage dropout linear regulator. Figure 10 (b) shows the output voltage waveform when assisted by an auxiliary discharge low-dropout linear regulator. DETAILED DESCRIPTION

[0057] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0058] Description of some concepts:

[0059] Buck converter (hereinafter referred to as "BUCK"): A type of switching power supply that converts a higher input DC voltage into a lower, stable output DC voltage by periodically turning on and off the switching tube.

[0060] Pulse Width Modulation (PWM): A technique for modulating the duty cycle of a pulse signal. In a Buck converter, it is used to control the on-time ratio of the switch, thereby regulating the output voltage.

[0061] Low-dropout (LDO) linear regulator: A linear regulator with a small input-output voltage difference, enabling fast voltage regulation but relatively low efficiency. The auxiliary charging LDO1 and auxiliary discharging LDO2 in this application both fall into this category.

[0062] Constant on-time control (COT): A control method that stabilizes the output voltage by fixing the on-time of the switch tube.

[0063] P-type metal oxide semiconductor field effect transistor (PMOS) and N-type metal oxide semiconductor field effect transistor (NMOS): two complementary field effect transistors that are the basic components of the circuit. The first P-type power transistor (PMOS0) and the first N-type power transistor (NMOS0) are the main switching transistors of the Buck converter.

[0064] External inductor L0: A key component in the Buck converter output filter circuit. Together with the load capacitor CL, it forms an LC filter network to filter out switching ripple.

[0065] The first mismatch adjustment signal offset1_tune<1:0> and the second mismatch adjustment signal offset2_tune<1:0> are used to adjust the deviation of the expected output voltages of the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharging low-dropout linear regulator LDO2 relative to the output voltage of the buck converter. In this specification, the "first mismatch adjustment signal offset1_tune<1:0>" and "second mismatch adjustment signal offset2_tune<1:0>" are sometimes referred to as "2-bit mismatch adjustment signal offset1_tune<1:0>" and "2-bit mismatch adjustment signal offset2_tune<1:0>."

[0066] The following is a summary of some of the innovative features of this application:

[0067] In summary, this application creatively proposes a unique technical solution for applications where the RF amplifier in an RF transceiver module needs to rapidly switch voltage domains to adapt to different operating modes. Two auxiliary low-dropout (LDO) regulators (LDO1, an auxiliary charging LDO, and LDO2, an auxiliary discharging LDO) are cleverly introduced into the traditional Buck converter architecture. Through a carefully designed mismatch adjustment mechanism, these regulators operate effectively only during voltage switching transients. Specifically, a first mismatch adjustment signal, offset1_tune<1:0>, controls the target output value of the auxiliary charging LDO1 to be lower than the target output value of the Buck converter by a first offset value, Voffset1. A second mismatch adjustment signal, offset2_tune<1:0>, controls the target output value of the auxiliary discharging LDO2 to be higher than the target output value of the Buck converter by a second offset value, Voffset2. This allows these two auxiliary LDOs to overcome the dynamic response limitations of traditional Buck converters, which are limited by the current continuity of the off-chip inductor L0, without affecting the steady-state efficiency of the Buck converter. When the reference voltage Vref rises rapidly, the auxiliary charging low-voltage difference linear regulator LDO1 injects a large current through the second P-type transistor PMOS12; when the reference voltage Vref drops rapidly, the auxiliary discharging low-voltage difference linear regulator LDO2 absorbs a large current through the ninth N-type transistor NMOS23. This collaborative working mechanism based on a preset deviation value not only solves the problems of slow response speed and large fluctuation of the output voltage Vout in the traditional Buck converter when the load suddenly changes or the output voltage Vout needs to be quickly switched, but also ensures that the system can smoothly transition to a high-efficiency steady-state working state after a rapid response through the automatic adjustment characteristics of the first voltage divider feedback module (13) and the second voltage divider feedback module (23), reflecting the uniqueness of the technical concept and the outstanding technical effect of the present application.

[0068] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0069] In the specification of this application, in order to make the article more clear and concise, some technical features are represented by English letter codes. It should be clarified that the technical features represented by letter codes in this application are exactly the same as the technical features represented by the corresponding Chinese names plus letter codes. For example, "BUCK" and "Buck converter" refer to the same technical feature, "PWM" and "Pulse Width Modulation PWM" refer to the same technical feature, and other similar technical features represented by English letter codes are also equivalent to the technical features represented by their corresponding Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented by letter codes only as the same as the technical features represented by their corresponding Chinese names plus letter codes. The technical features with English letter codes involved include but are not limited to:

[0070] Buck converter;

[0071] Pulse Width Modulation (PWM);

[0072] Low dropout linear regulator LDO;

[0073] Auxiliary charging low voltage dropout linear regulator LDO1;

[0074] Auxiliary discharge low voltage dropout linear regulator LDO2;

[0075] Output voltage Vout;

[0076] Reference voltage Vref;

[0077] a first reference voltage Vref1;

[0078] A first feedback voltage Vfb1;

[0079] A second feedback voltage Vfb2;

[0080] Input power supply voltage Vin;

[0081] Constant on-time control COT;

[0082] Analog power supply voltage VDD;

[0083] Analog ground VSS;

[0084] The first amplifier outputs a voltage Vg1;

[0085] The second amplifier outputs a voltage Vg2;

[0086] The voltage of the first current mirror connection point Vbp1;

[0087] The second current mirror connection point voltage Vbn2;

[0088] A first offset value Voffset1;

[0089] A second offset value Voffset2;

[0090] The first low-dropout linear regulator outputs an expected value Vout_LDO1;

[0091] The second low-dropout linear regulator outputs an expected value Vout_LDO2;

[0092] a first bias current Ibn1;

[0093] a second bias current Ibn2;

[0094] A third bias current Ibn10u;

[0095] a fourth bias current Ibp1;

[0096] a fifth bias current Ibp2;

[0097] P-type metal oxide semiconductor field effect transistor PMOS;

[0098] N-type metal oxide semiconductor field effect transistor NMOS;

[0099] The first P-type power tube PMOS0;

[0100] The first N-type power tube NMOS0;

[0101] A first driving signal HS;

[0102] A second driving signal LS;

[0103] A first amplifier AMP1;

[0104] A second amplifier AMP2;

[0105] Off-chip inductor L0;

[0106] Load capacitance CL;

[0107] Loop compensator output signal Verr;

[0108] First mismatch adjustment signal offset1_tune<1:0>;

[0109] The second mismatch adjustment signal offset2_tune<1:0>;

[0110] A first set of switch control signals SC11-SC14;

[0111] A second set of switch control signals SC21-SC24;

[0112] The first set of resistors R10-R16;

[0113] The second set of resistors R20-R28;

[0114] A first capacitor C10;

[0115] a second capacitor C20;

[0116] a third capacitor C21;

[0117] A first group of transistors NMOS11, PMOS11, PMOS12;

[0118] A second group of transistors NMOS21-23, PMOS21-22;

[0119] The first group of NMOS switch tubes SMN11-14;

[0120] The second group of NMOS switch tubes SMN21-24.

[0121] Furthermore, the same reference numerals are used throughout the drawings to denote the same elements or structures, wherein:

[0122] 11: First output current limiting module;

[0123] 21: Second output current limiting module;

[0124] 13: First voltage divider feedback module;

[0125] 23: Second voltage divider feedback module;

[0126] 12: first decoder;

[0127] 22: Second decoder.

[0128] To enhance clarity and conciseness in this specification, the same technical features may be referred to using different Chinese expressions in different contexts. For example, "Low Dropout Linear Regulator LDO" and "LDO Regulator" refer to the same technical feature. For ease of description and to avoid repetition, the specification uses different expressions for the same technical feature, such as letter codes, English abbreviations, and Chinese names.

[0129] It should be noted that, although the same technical features may be described in different ways throughout the specification, as long as the letter codes or English abbreviations are the same, they refer to the same technical features. The correspondence between the different designations can be determined based on the specific descriptions and drawings in the specification. Based on the contents of the specification, those skilled in the art will clearly understand the technical features designated by the same letter codes or English abbreviations without difficulty in understanding the invention.

[0130] In this specification, to maintain simplicity, the same technical feature will be referred to as "Chinese name + English code" when it first appears, and may be referred to as just the English code when it appears subsequently. These different forms of expression refer to the same technical feature.

[0131] To enhance clarity and conciseness in this specification, the same technical features may be referred to using different Chinese expressions in different contexts. For example, "Low Dropout Linear Regulator LDO" and "LDO Regulator" refer to the same technical feature. For ease of description and to avoid repetition, the specification uses different expressions for the same technical feature, such as letter codes, English abbreviations, and Chinese names.

[0132] It should be noted that, although the same technical features may be described in different ways throughout the specification, as long as the letter codes or English abbreviations are the same, they refer to the same technical features. The correspondence between the different designations can be determined based on the specific descriptions and drawings in the specification. Based on the contents of the specification, those skilled in the art will clearly understand the technical features designated by the same letter codes or English abbreviations without difficulty in understanding the invention.

[0133] The first embodiment of the present application relates to a Buck converter that quickly responds to output voltage switching, such as Figure 1 , Figures 4 to 6 ,as well as Figure 8 and Figure 9 As shown, including:

[0134] Buck control module, used to monitor the output voltage Vout of the Buck converter, output pulse width modulation PWM signal, and generate bias current and reference voltage Vref;

[0135] A buck driver module and a power transistor, wherein the input end of the buck driver module is connected to the pulse width modulation (PWM) signal, and the output end outputs drive signals HS and LS; the power transistor includes an upper P-type power transistor PMOS0 and a lower N-type power transistor NMOS0, wherein the source of the P-type power transistor PMOS0 is connected to the off-chip input power supply voltage Vin, the gate is connected to the drive signal HS, the drain is short-circuited with the drain of the N-type power transistor NMOS0 and output to the outside of the chip, the source of the N-type power transistor NMOS0 is connected to the ground terminal of the chip, and the gate is connected to the drive signal LS;

[0136] an auxiliary charging low-dropout linear regulator LDO1, having a power terminal connected to the analog power voltage VDD, a ground terminal connected to the analog ground VSS, an input terminal connected to the first reference voltage Vref1, the fourth bias current Ibp1, and the first bias current Ibn1, respectively, a trim control terminal connected to the first mismatch adjustment signal offset1_tune<1:0>, and an output terminal connected to the output voltage Vout;

[0137] an auxiliary discharge low-dropout linear regulator LDO2, having a power supply terminal connected to the analog power supply voltage VDD, a ground terminal connected to the analog ground VSS, input terminals connected to the first reference voltage Vref1, the fifth bias current Ibp2, the second bias current Ibn2, and the third bias current Ibn10u, respectively, a trim control terminal connected to the second mismatch adjustment signal offset2_tune<1:0>, and an output terminal connected to the output voltage Vout;

[0138] Optionally, the target output value of the auxiliary charging low-voltage dropout linear regulator LDO1 is lower than the target output value of the Buck converter by a first offset value Voffset1. When the reference voltage Vref rises rapidly, the Buck converter gradually increases the output voltage Vout through pulse width modulation PWM signal control. At the same time, the auxiliary charging low-voltage dropout linear regulator LDO1 responds quickly and injects current into the output end to make the output voltage Vout rise rapidly. When the output voltage Vout reaches the preset output voltage of the auxiliary charging low-voltage dropout linear regulator LDO1, the auxiliary charging low-voltage dropout linear regulator LDO1 loop is automatically closed.

[0139] The target output value of the auxiliary discharge low-voltage dropout linear regulator LDO2 is higher than the target output value of the Buck converter by a second offset value Voffset2. When the reference voltage Vref drops rapidly, the Buck converter gradually reduces the output voltage Vout through pulse width modulation (PWM) signal control. At the same time, the auxiliary discharge low-voltage dropout linear regulator LDO2 responds quickly, draws current from the output end to make the output voltage Vout drop rapidly. When the output voltage Vout reaches the preset output voltage of the auxiliary discharge low-voltage dropout linear regulator LDO2, the auxiliary discharge low-voltage dropout linear regulator LDO2 loop is automatically closed, so that the auxiliary charge low-voltage dropout linear regulator LDO1 and the auxiliary discharge low-voltage dropout linear regulator LDO2 only work briefly when the reference voltage Vref switches between rising and falling rapidly. After the switching is completed, the auxiliary charge low-voltage dropout linear regulator LDO1 and the auxiliary discharge low-voltage dropout linear regulator LDO2 are in the off state, which does not affect the overall efficiency of the Buck converter.

[0140] Optionally, the Buck control module includes:

[0141] a first level shifter and a second level shifter, wherein the first level shifter has an input terminal connected to a first digital mismatch adjustment signal offset1_tune_dig<1:0> and an output terminal outputting the first mismatch adjustment signal offset1_tune<1:0>; and the second level shifter has an input terminal connected to a second digital mismatch adjustment signal offset2_tune_dig<1:0> and an output terminal outputting the second mismatch adjustment signal offset2_tune<1:0>;

[0142] A low-pass filter, whose input terminal is connected to the reference voltage Vref, and outputs a first reference voltage Vref1 after filtering out its high-frequency noise;

[0143] A loop compensator, wherein a reference voltage input terminal thereof is connected to a first reference voltage Vref1 , a feedback input terminal thereof is connected to an output voltage Vout, and an output loop compensator output signal Verr is output;

[0144] A PWM generator, whose input terminal is connected to the loop compensator output signal Verr, outputs a pulse width modulation PWM signal;

[0145] The bias current generator has an input terminal connected to the first reference voltage Vref1 and an output terminal outputting a first bias current Ibn1, a second bias current Ibn2, a third bias current Ibn10u, a fourth bias current Ibp1 and a fifth bias current Ibp2.

[0146] Optionally, the auxiliary charging low-voltage difference linear regulator LDO1 also includes a first amplifier AMP1, whose power supply terminal is connected to the analog power supply voltage VDD, the ground terminal is connected to the analog ground VSS, the non-inverting input terminal is connected to the first reference voltage Vref1, the reverse input terminal is connected to the first feedback voltage Vfb1, and the output terminal outputs the first amplifier output voltage Vg1.

[0147] Optionally, the auxiliary charging low-dropout linear regulator LDO1 further includes:

[0148] a first output current limiting module 11 , whose power terminal is connected to the analog power supply voltage VDD, the ground terminal is connected to the analog ground VSS, the input terminal is connected to the fourth bias current Ibp1 , and the output terminal is connected to the first amplifier output voltage Vg1 ;

[0149] a first N-type transistor NMOS11, a first P-type transistor PMOS11, and a second P-type transistor PMOS12, wherein the source of the first N-type transistor NMOS11 is connected to the analog ground VSS, the gate is connected to the first amplifier output voltage Vg1, and the drain is connected to the drain of the first P-type transistor PMOS11 to form a first current mirror connection point voltage Vbp1; the drain and gate of the first P-type transistor PMOS11 are short-circuited, and the source is connected to the analog power supply voltage VDD; the source of the second P-type transistor PMOS12 is connected to the analog power supply voltage VDD, the gate is short-circuited to the gate of the first P-type transistor PMOS11, and the drain is connected to the output voltage Vout;

[0150] The first voltage-dividing feedback module 13 has an input terminal connected to the output voltage Vout, a bias current terminal connected to the first bias current Ibn1 , a trimming control terminal connected to the first mismatch adjustment signal offset1_tune<1:0>, and a ground terminal connected to the analog ground VSS.

[0151] Optionally, the first voltage division feedback module 13 further includes:

[0152] A first resistor group includes a first resistor R10, a second resistor R11, a third resistor R12, a fourth resistor R13, a fifth resistor R14, a sixth resistor R15, and a seventh resistor R16;

[0153] A first capacitor C10;

[0154] A first group of N-type switching transistors includes a third N-type transistor SMN11, a fourth N-type transistor SWN12, a fifth N-type transistor SWN13 and a sixth N-type transistor SWN14;

[0155] A first decoder 12;

[0156] The second resistor R11, the third resistor R12, the fourth resistor R13, the fifth resistor R14, the sixth resistor R15 and the seventh resistor R16 are connected in series in sequence, one end of the second resistor R11 is connected to the output voltage Vout, and the voltage signal between the other end and the third resistor R12 in series is used as the first feedback voltage Vfb1, the first capacitor C10 and the first resistor R10 in series are connected between the output voltage Vout and the first feedback voltage Vfb1, and the voltage signal between the third resistor R12, the fourth resistor R13, the fifth resistor R14, the sixth resistor R15 and the seventh resistor R16 in series is respectively connected to the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13 and the first N-type transistor SMN14. The source of the sixth N-type transistor SWN14, the drains of the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13 and the sixth N-type transistor SWN14 are short-circuited together and connected to the first bias current Ibn1, the input end of the first decoder 12 is connected to the first mismatch adjustment signal offset1_tune<1:0>, and the output end outputs a first group of switch control signals, including a first switch control signal SC11, a second switch control signal SC12, a third switch control signal SC13 and a fourth switch control signal SC14, and is sequentially connected to the gates of the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13 and the sixth N-type transistor SWN14.

[0157] Optionally, the auxiliary discharge low-dropout linear regulator LDO2 further includes:

[0158] a second amplifier AMP2, having a power supply terminal connected to the analog power supply voltage VDD, a ground terminal connected to the analog ground VSS, an inverting input terminal connected to the first reference voltage Vref1, a non-inverting input terminal connected to the second feedback voltage Vfb2, and an output terminal outputting a second amplifier output voltage Vg2;

[0159] a second output current limiting module 21 , whose power terminal is connected to the analog power supply voltage VDD, the ground terminal is connected to the analog ground VSS, the input terminal is connected to the fifth bias current Ibp2 , and the output terminal is connected to the second amplifier output voltage Vg2 ;

[0160] a seventh N-type transistor NMOS21, an eighth N-type transistor NMOS22, a ninth N-type transistor NMOS23, a third P-type transistor PMOS21, and a fourth P-type transistor PMOS22, and an eighth resistor R28, wherein the source of the seventh N-type transistor NMOS21 is connected to the analog ground VSS, the gate is connected to the second amplifier output voltage Vg2, and the drain is connected to the drain of the third P-type transistor PMOS21 to form a second current mirror connection point voltage Vbp2; the drain and gate of the third P-type transistor PMOS21 are short-circuited, and the source is connected to the analog power supply voltage VDD; the source of the fourth P-type transistor PMOS22 is connected The analog power supply voltage VDD, the gate of the third P-type transistor PMOS21 is short-circuited, and the drain is connected to the gate and drain of the eighth N-type transistor NMOS22 to form a third current mirror connection point voltage Vbn2; the source of the eighth N-type transistor NMOS22 is connected to the analog ground VSS, the gate and drain are short-circuited to form the third current mirror connection point voltage Vbn2 and connected to the gate of the ninth N-type transistor NMOS23; the drain of the ninth N-type transistor NMOS23 is connected to the output voltage Vout and one end of the eighth resistor R28; the other end of the eighth resistor R28 is connected to the third bias current Ibn10u;

[0161] The second voltage-dividing feedback module 23 has an input terminal connected to the output voltage Vout, a bias current terminal connected to the second bias current Ibn2, a trim control terminal connected to the second mismatch adjustment signal offset2_tune<1:0>, and a ground terminal connected to the analog ground VSS.

[0162] Optionally, the second voltage division feedback module 23 further includes:

[0163] a second resistor group including a ninth resistor R20, a tenth resistor R21, an eleventh resistor R22, a twelfth resistor R23, a thirteenth resistor R24, a fourteenth resistor R25, and a fifteenth resistor R26;

[0164] A second capacitor C20 and a third capacitor C21;

[0165] A second group of N-type switching transistors includes a tenth N-type transistor SMN21, an eleventh N-type transistor SWN22, a twelfth N-type transistor SWN23, and a thirteenth N-type transistor SWN24;

[0166] A second decoder 22;

[0167] The tenth resistor R21, the eleventh resistor R22, the twelfth resistor R23, the thirteenth resistor R24, the fourteenth resistor R25 and the fifteenth resistor R26 are connected in series in sequence, one end of the tenth resistor R21 is connected to the analog ground VSS, and the voltage signal between the other end and the eleventh resistor R22 in series is used as the second feedback voltage Vfb2, the second capacitor C20 and the ninth resistor R20 in series are connected between the output voltage Vout and the second feedback voltage Vfb2, and the voltage signal between the tenth resistor R21, the eleventh resistor R22, the twelfth resistor R23, the thirteenth resistor R24 and the fourteenth resistor R25 in series is respectively connected to the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23 and the source of the thirteenth N-type transistor SWN24, the drains of the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23 and the thirteenth N-type transistor SWN24 are short-circuited together and connected to the second bias current Ibn2, the input end of the second decoder 22 is connected to the second mismatch adjustment signal offset2_tune<1:0>, and the output end outputs a second group of switch control signals, including a fifth switch control signal SC21, a sixth switch control signal SC22, a seventh switch control signal SC23 and an eighth switch control signal SC24, and is sequentially connected to the gates of the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23 and the thirteenth N-type transistor SWN24.

[0168] In order to make the technical solution of this application clearer, Figures 1 to 9 The preferred embodiments of the present application are described in detail, but it should be understood that the described embodiments are only illustrative rather than restrictive.

[0169] Figure 1 This is a schematic diagram of the structure of the Buck converter that quickly responds to output voltage switching in this application, hereinafter referred to as the "Buck converter". Figure 1 As shown, the Buck converter includes a Buck control module, a Buck driver module, a power tube, an auxiliary charging low-voltage dropout linear regulator referred to as "auxiliary charging LDO1" or "LDO1" and an auxiliary discharging low-voltage dropout linear regulator referred to as "auxiliary discharging LDO2" or "LDO2", as well as an off-chip inductor L0 and a load capacitor CL.

[0170] Specifically, the Buck control module is used to monitor the output voltage Vout of the Buck converter, output a pulse width modulation signal, i.e., a PWM signal, and generate a bias current and a reference voltage Vref; the input end of the Buck drive module is connected to the PWM signal, and the output end outputs drive signals, i.e., HS and LS; the power tube includes an upper P-type power tube PMOS0 and a lower N-type power tube NMOS0, wherein the source of PMOS0 is connected to the off-chip input power supply voltage Vin, the gate is connected to the drive signal HS, the drain is short-circuited with the drain of NMOS0 and output to the outside of the chip, the source of NMOS0 is connected to the ground terminal of the chip, and the gate is connected to the drive signal LS.

[0171] Auxiliary charging LDO1 has a power terminal connected to the analog power supply voltage VDD, a ground terminal connected to the analog ground VSS, an input terminal connected to the first reference voltage Vref1 and bias currents Ibp1 and Ibn1 respectively, a trim control terminal connected to the 2-bit mismatch adjustment signal offset1_tune<1:0>, and an output terminal connected to the output voltage Vout. Auxiliary charging LDO1 is used to assist the Buck converter in rapidly increasing the output voltage.

[0172] Auxiliary discharge LDO2 has a power supply terminal connected to the analog power supply voltage VDD, a ground terminal connected to the analog ground VSS, input terminals connected to the first reference voltage Vref1 and bias currents Ibp2, Ibn2, and Ibn10u, a trim control terminal connected to the 2-bit mismatch adjustment signal offset2_tune<1:0>, and an output terminal connected to the output voltage Vout. The auxiliary discharge LDO2 is used to assist the Buck converter in rapidly decreasing the output voltage.

[0173] The off-chip inductor L0 and load capacitor CL are used to stabilize the output voltage Vout.

[0174] When the output voltage Vout needs to rise rapidly, the Buck converter gradually increases the output voltage through PWM signal control. Meanwhile, auxiliary charging LDO1 responds quickly, replenishing the output current and reducing the voltage rise time. When the output voltage Vout needs to drop rapidly, auxiliary discharging LDO2 quickly absorbs the excess current, lowering the output voltage. Meanwhile, the Buck converter gradually decreases the output voltage through PWM signal control. The coordinated operation of auxiliary charging LDO1 and auxiliary discharging LDO2 enables rapid switching of the Buck converter's output voltage, improving the circuit's dynamic response capability.

[0175] Figure 2 This is a schematic diagram of the structure in which a compensation module is added to the existing constant on-time control COT. Figure 2As shown in the figure, this structure is a Buck converter with fast dynamic response. By adding a compensation module to the COT, the dynamic response performance is improved. Although this design improves the transient response of the Buck converter, it cannot meet the requirement of rapid output voltage switching when the reference voltage switches rapidly. The figure shows the circuit structure of an existing Buck converter with COT control, which includes the input power supply Vin, driver Driver, switching transistor, inductor L, load capacitor CO, sense resistor network, and control loop circuit. This structure achieves output voltage regulation through duty cycle control, but due to the continuity limitation of the inductor current, its response speed is slow when the output voltage needs to switch rapidly, and it cannot meet the fast voltage switching requirements of high-performance power supply systems.

[0176] Figure 3 This is a schematic diagram of the structure of the existing reference voltage selectable design scheme. Figure 3 As shown, this structure is a voltage-mode buck converter that uses a reference voltage selection circuit and a threshold control circuit to switch the reference voltage. The figure shows the input power supply Vin, a high-side switching transistor (P-type), a low-side switching transistor (N-type), an inductor L, an output capacitor CL, a load current Iload, load resistors RFB1 and RFB2, and the control circuit. The control circuit includes a COT control circuit, a ramp generator, a reference voltage selection circuit, and a voltage controller. This design accelerates duty cycle changes and improves transient performance through the reference voltage selection circuit and threshold control circuit, but it still cannot meet the requirements for fast output voltage switching. Although this existing structure can achieve reference voltage selection, its response speed is still slow when fast output voltage switching is required due to the continuous nature of the inductor current.

[0177] Figure 4 This is a schematic diagram of the structure of the Buck control module of this application. Figure 4As shown, the Buck control module includes a level converter, a low-pass filter, a loop compensator, a PWM generator, and a bias current generator. Among them, the level converter is used to convert the signal in the digital voltage domain into the required analog voltage domain signal. Its input end is connected to two groups of 2-bit digital mismatch adjustment signals offset1_tune_dig<1:0> and offset2_tune_dig<1:0>, and its output end outputs 2-bit mismatch adjustment signals offset1_tune<1:0> and offset2_tune<1:0>; the low-pass filter is used to filter out the high-frequency noise on the reference voltage Vref. Its input end is connected to the reference voltage Vref, and after filtering out its high-frequency noise, it outputs the first reference voltage Vref1; the loop compensator can offset the high-frequency noise by adding poles and zeros to the loop. It eliminates the phase lag or lead caused by the LC filter and improves the DC gain of the Buck system to enhance the system's ability to adjust to input voltage changes and load changes. Its reference voltage input is connected to the first reference voltage Vref1, the feedback input is connected to the output voltage Vout, and the output is the loop compensator output signal Verr; the PWM generator is used to generate a PWM signal, its input is connected to the loop compensator output signal Verr, and it outputs a PWM signal; the bias current generator is used to generate various bias currents required by other modules, its input is connected to the first reference voltage Vref1, and it outputs bias currents Ibn1, Ibn2, Ibn10u, Ibp1 and Ibp2.

[0178] Figure 5 This is the circuit structure diagram of the auxiliary charging LDO1 of this application. Figure 5As shown, the auxiliary charging LDO 1 includes a first amplifier AMP1, a first output current limiting module 11, transistors NMOS 11, PMOS 11, PMOS 12, and a first voltage divider feedback module 13. AMP1 is used to amplify the difference between the first feedback voltage Vfb1 and the first reference voltage Vref1, output a first amplifier output voltage Vg1, and regulate the output voltage Vout through the negative feedback loop of the auxiliary charging LDO 1. Its power supply terminal is connected to the analog power supply VDD, the ground terminal is connected to the analog ground VSS, the non-inverting input terminal is connected to the first reference voltage Vref1, the inverting input terminal is connected to the first feedback voltage Vfb1, and the output terminal outputs the first amplifier output voltage Vg1. The first output current limiting module 11 is used to limit the gate voltage Vg1 of the NMOS 11, so that the voltage difference Vgs between the gate and source of the NMOS 11 is limited to a desired range. Its power supply terminal is connected to the analog power supply VDD, the ground terminal is connected to the analog ground VSS, the input terminal is connected to the bias current Ibp1, and the output terminal is connected to the first amplifier output voltage Vg1; the source of the transistor NMOS11 is connected to the analog ground VSS, the gate is connected to the first amplifier output voltage Vg1, and the drain is connected to the drain of the transistor PMOS11 to form the first current mirror connection point voltage Vbp1; the drain and gate of the transistor PMOS11 are short-circuited, and the source is connected to the analog power supply VDD; the source of the transistor PMOS12 is connected to the analog power supply VDD, the gate is short-circuited to the gate of the transistor PMOS11, and the drain is connected to the output voltage Vout; the first voltage divider feedback module 13, its input terminal is connected to the output voltage Vout, the bias current terminal is connected to the bias current Ibn1, the trimming control terminal is connected to the 2-bit mismatch adjustment signal offset1_tune<1:0>, and the ground terminal is connected to the analog ground VSS.

[0179] Figure 6 This is the circuit structure diagram of the first voltage divider feedback module 13 of the present application. Figure 6As shown, the first voltage divider feedback module 13 includes resistors R10-R16, a capacitor C10, NMOS switches SMN11, SWN12, SWN13, and SWN14, and a first decoder 12. The resistors R11-R16 are connected in series in sequence. One end of the resistor R11 is connected to the output voltage Vout, and the voltage signal between the other end and the resistor R12 in series serves as the first feedback voltage Vfb1. A capacitor C10 and a resistor R10 in series are connected between the output voltage Vout and the first feedback voltage Vfb1. The voltage signal between the resistors R12-R16 in series is connected to the sources of the NMOS switches SMN11-SWN14, respectively. The drains of these NMOS switches are short-circuited together and connected to the bias current Ibn1. The input of the first decoder 12 is connected to the 2-bit mismatch adjustment signal offset1_tune<1:0>, and the output outputs four sets of switch control signals SC11-SC14, which are connected to the gates of the NMOS switches SMN11-SWN14 in sequence. The voltage divider resistor feedback module adjusts the mismatch adjustment signal offset1_tune<1:0> to inject current Ibn1 into the series resistors with different polarities, thereby causing the LDO output voltage to deviate from the Buck target voltage.

[0180] Figure 7 This is the waveform diagram of the auxiliary charging LDO1 in this application. Figure 7 As shown, Figure 7 (a) is the waveform when the reference voltage Vref is switched from low to high without auxiliary LDO assistance. Figure 7 (b) is the waveform when Vref switches from low to high with the assistance of auxiliary LDO. It can be clearly seen from the waveform that with the assistance of auxiliary charging LDO1, when the reference voltage Vref switches from low to high, the output voltage Vout can rise to the target value faster. Figure 7 In (b), the ILDO1 signal indicates that the auxiliary charging LDO1 is activated during the rise of the reference voltage Vref, providing additional current to accelerate the rise of the output voltage Vout, significantly shortening the voltage rise time. Figure 7 In (a), due to the lack of support from the auxiliary LDO, the output voltage Vout rises more slowly and takes longer to reach a stable state.

[0181] Figure 8 This is the circuit structure diagram of the auxiliary discharge LDO2 of this application. Figure 8As shown, the auxiliary discharge LDO 2 includes a second amplifier AMP2, a second output current limiting module 21, transistors NMOS21, NMOS22, NMOS23, PMOS21, and PMOS22, a resistor R28, and a second voltage divider feedback module 23. AMP2 is used to amplify the difference between the feedback voltage Vfb2 and the first reference voltage Vref1 and output a signal Vg2. AMP2 also regulates the output voltage Vout through the negative feedback loop of the auxiliary discharge LDO 2. Its power supply terminal is connected to the analog power supply VDD, its ground terminal is connected to the analog ground VSS, its inverting input terminal is connected to the first reference voltage Vref1, its non-inverting input terminal is connected to the feedback voltage Vfb2, and its output terminal outputs the voltage Vg2. The second output current limiting module 21 is used to limit the gate voltage Vg2 of the NMOS 21, so that the voltage difference Vgs between the gate and source of the NMOS 21 is limited to a desired range. Its power supply terminal is connected to the analog power supply VDD, its ground terminal is connected to the analog ground VSS, its input terminal is connected to the bias current Ibp2, and its output terminal is connected to the voltage Vg2. The source of transistor NMOS21 is connected to analog ground VSS, the gate is connected to voltage Vg2, and the drain is connected to the drain of transistor PMOS21 to form a second current mirror connection point voltage Vbp2; the drain and gate of transistor PMOS21 are short-circuited, and the source is connected to analog power supply VDD; the source of transistor PMOS22 is connected to analog power supply VDD, the gate is short-circuited to the gate of transistor PMOS21, and the drain is connected to the gate and drain of transistor NMOS22 to form a third current mirror connection point voltage Vbn2; the source of transistor NMOS22 is connected to analog power supply VDD, the gate is short-circuited to the gate of transistor PMOS21, and the drain is connected to the gate and drain of transistor NMOS22 to form a third current mirror connection point voltage Vbn2; The gate and drain are short-circuited to Vbn2 and connected to the gate of transistor NMOS23; the drain of transistor NMOS23 is connected to the output voltage Vout and one end of resistor R28; the other end of resistor R28 is connected to the bias current Ibn10u; the second voltage divider feedback module 23 has its input end connected to the output voltage Vout, the bias current end connected to the bias current Ibn2, the trim control end connected to the 2-bit mismatch adjustment signal offset2_tune<1:0>, and the ground end connected to the analog ground VSS.

[0182] Figure 9 This is the circuit structure diagram of the second voltage divider feedback module 23 of the present application. Figure 9As shown, the second voltage divider feedback module 23 includes resistors R20-R26, capacitors C20 and C21, NMOS switches SMN21, SWN22, SWN23, and SWN24, and a second decoder 22. Resistors R21-R26 are connected in series in sequence. One end of resistor R21 is connected to the power ground VSS, and the voltage signal between the other end and the resistor R22 in series serves as the feedback signal Vfb2. Capacitor C20 and resistor R20 are connected in series between the output voltage Vout and the feedback signal Vfb2 voltage. The voltage signal between the series resistors R21-R25 is connected to the sources of the NMOS switches SMN21-SWN24, respectively. The drains of these NMOS switches are short-circuited together and connected to the bias current Ibn2. The input of the second decoder 22 is connected to the 2-bit mismatch adjustment signal offset2_tune<1:0>, and the output outputs four sets of switch control signals SC21-SC24, which are connected in sequence to the gates of the NMOS switches SMN21-SWN24. The voltage divider resistor feedback module adjusts the mismatch adjustment signal offset2_tune<1:0> to draw current Ibn2 from the series resistors with different polarities, thereby causing a deviation between the LDO expected output voltage and the Buck target voltage.

[0183] Figure 10 This is the waveform diagram of the auxiliary discharge LDO2 in this application when it is working. Figure 10 As shown, Figure 10 (a) is the waveform when the reference voltage Vref switches from high to low without auxiliary LDO assistance. Figure 10 (b) is the waveform when Vref switches from high to low with the assistance of auxiliary LDO. It can be clearly seen from the waveform that with the assistance of auxiliary discharge LDO2, when the reference voltage Vref switches from high to low, the output voltage Vout can drop to the target value faster. Figure 10 In (b), the ILDO2 signal indicates that the auxiliary discharge LDO2 is activated during the reference voltage Vref drop period, which accelerates the drop process of the output voltage Vout by absorbing excess current, significantly shortening the voltage drop time. Figure 10 In (a), due to the lack of support from the auxiliary LDO, the output voltage Vout decreases more slowly and takes longer to reach a stable state.

[0184] Working principle:

[0185] The Buck converter of the present application that can quickly respond to output voltage switching includes the following main functional modules: a Buck control module, which is used to monitor the output voltage Vout state and generate a PWM signal to adjust the duty cycle of the power tube to ensure that the output voltage Vout is stable at the expected value, and at the same time provide a reference voltage Vref and a bias current for other modules; a Buck drive module, which converts the PWM signal to the drive voltage domain, and at the same time improves the driving capability of the signal to drive the power tube; an auxiliary charging low-voltage difference linear regulator LDO1, when the output voltage needs to be quickly increased, the Buck converter gradually increases the output voltage through PWM control, and at the same time the auxiliary charging low-voltage difference linear regulator LDO1 responds quickly, supplements the output current, and reduces the voltage rise time; an auxiliary discharge low-voltage difference linear regulator LDO2, when the output voltage needs to be quickly reduced, the auxiliary discharge low-voltage difference linear regulator LDO2 quickly absorbs excess current, reduces the output voltage, and at the same time the Buck converter gradually reduces the output voltage through PWM control.

[0186] Buck control module such as Figure 4 As shown, the system includes a level converter, a low-pass filter, a loop compensator, a PWM generator, and a bias current generator. The level converter converts the digital voltage domain signal into the required analog voltage domain signal. The low-pass filter filters out high-frequency noise on the reference voltage Vref and outputs the first reference voltage Vref1. The loop compensator adds poles and zeros to the loop to offset the phase lag or lead caused by the LC filter. It also increases the DC gain of the Buck system to enhance the system's ability to adjust to input voltage and load changes, ensuring that the output voltage remains stable under various operating conditions. The PWM generator generates PWM signals. The bias current generator produces the various bias currents required by other modules.

[0187] The working steps of the auxiliary charging low-dropout linear regulator LDO1 are as follows:

[0188] Step 1: When the Buck converter is just started or the Buck converter has been started but the output voltage needs to be increased to a higher level, the output voltage Vout is at a low level. At this time, the Buck converter gradually increases the output voltage through PWM control. At the same time, the first voltage divider feedback module 13 of the auxiliary charging low-dropout linear regulator LDO1 samples the output voltage Vout and outputs a first feedback voltage Vfb1. At this time, the first feedback voltage Vfb1 is less than the first reference voltage Vref1. After passing through the first amplifier AMP1, the first amplifier output voltage Vg1 is increased, and the current of the transistor NMOS11 increases, so that the pull-up current of the output electrode transistor PMOS12 is synchronously increased to supplement the output current and reduce the voltage rise time.

[0189] Step 2: After the output voltage Vout reaches the preset output voltage of the auxiliary charging low-dropout linear regulator LDO1, due to the continuous operation of the Buck system, the output voltage Vout will continue to rise towards the preset output voltage of the Buck converter. At this time, the first feedback voltage Vfb1 sampled by the first voltage divider feedback module 13 gradually becomes greater than the first reference voltage Vref1. After passing through the first amplifier AMP1, the first amplifier output voltage Vg1 gradually decreases, the current of the transistor NMOS11 gradually decreases, and the pull-up current of the output transistor PMOS12 decreases synchronously. When the first feedback voltage Vfb1 is greater than the first reference voltage Vref1 by a certain value, the first amplifier output voltage Vg1 drops to a limit, and the transistors NMOS11 and PMOS12 are all turned off, so that the loop of the auxiliary charging low-dropout linear regulator LDO1 is completely disconnected from the Buck system, thereby not affecting the overall efficiency of the Buck converter.

[0190] The working steps of the auxiliary discharge low-dropout linear regulator LDO2 are as follows:

[0191] Step 1: When the Buck input reference voltage is switched from high to low and the output voltage needs to be reduced to a lower level, the output voltage Vout is still at a high level. At this time, the Buck converter gradually reduces the output voltage through PWM control. At the same time, the second voltage divider feedback module 23 of the auxiliary discharge low-dropout linear regulator LDO2 samples the output voltage Vout and outputs a second feedback voltage Vfb2. At this time, the second feedback voltage Vfb2 is greater than the first reference voltage Vref1. After passing through the second amplifier AMP2, the second amplifier output voltage Vg2 is increased, and the current of the transistor NMOS21 increases, so that the pull-down current of the output electrode transistor NMOS23 is synchronously increased to absorb a large current from the output end, thereby reducing the voltage fall time.

[0192] Step 2: After the output voltage Vout reaches the preset output voltage of the auxiliary discharge low-dropout linear regulator LDO2, due to the continuous operation of the Buck system, the output voltage Vout will continue to drop toward the preset output voltage of the Buck converter. At this time, the second feedback voltage Vfb2 sampled by the second voltage divider feedback module 23 gradually becomes less than the first reference voltage Vref1. After passing through the second amplifier AMP2, the second amplifier output voltage Vg2 gradually decreases, the current of the transistor NMOS21 gradually decreases, and the pull-down current of the output transistor NMOS23 decreases synchronously. When the second feedback voltage Vfb2 is less than a certain value of the first reference voltage Vref1, the second amplifier output voltage Vg2 drops to a limit, and the transistors NMOS21 and NMOS23 are all turned off, so that the loop of the auxiliary discharge low-dropout linear regulator LDO2 is completely disconnected from the Buck system, thereby not affecting the overall efficiency of the Buck converter.

[0193] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0194] This example proposes a fast-response buck converter with output voltage switching, including:

[0195] Buck control module, used to monitor the output voltage Vout of the Buck converter, output pulse width modulation PWM signal, and generate bias current and reference voltage Vref;

[0196] Buck driver modules and power transistors are used to enhance the driving capability of pulse width modulation (PWM) signals and output corresponding driving voltages to drive the power transistors.

[0197] Auxiliary charging low-dropout linear regulator LDO1 is used to assist the Buck converter in quickly increasing the output voltage;

[0198] Auxiliary discharge low-dropout linear regulator LDO2, used to assist the Buck converter in rapidly decreasing the output voltage;

[0199] The off-chip inductor L0 and load capacitor CL are used to stabilize the output voltage Vout.

[0200] Preferably, the Buck control module includes: a first level converter and a second level converter, wherein the input end of the first level converter is connected to the first digital mismatch adjustment signal offset1_tune_dig<1:0>, and the output end outputs the first mismatch adjustment signal offset1_tune<1:0>; the input end of the second level converter is connected to the second digital mismatch adjustment signal offset2_tune_dig<1:0>, and the output end outputs the second mismatch adjustment signal offset2_tune<1:0>; a low-pass filter, whose input end is connected to the reference voltage Vref, and After filtering out its high-frequency noise, it outputs a first reference voltage Vref1; a loop compensator, whose reference voltage input terminal is connected to the first reference voltage Vref1, whose feedback input terminal is connected to the output voltage Vout, and which outputs a loop compensator output signal Verr; a PWM generator, whose input terminal is connected to the loop compensator output signal Verr, and which outputs a pulse width modulation PWM signal; a bias current generator, whose input terminal is connected to the first reference voltage Vref1, and whose output terminal outputs a first bias current Ibn1, a second bias current Ibn2, a third bias current Ibn10u, a fourth bias current Ibp1, and a fifth bias current Ibp2.

[0201] Preferably, the input end of the BUCK driver module is connected to the pulse width modulation PWM signal, and the output end outputs the drive signals HS and LS; the power tube includes an upper P-type power tube PMOS0 and a lower N-type power tube NMOS0, wherein the source of the P-type power tube PMOS0 is connected to the off-chip input power supply voltage Vin, the gate is connected to the drive signal HS, the drain is short-circuited with the drain of the N-type power tube NMOS0 and output to the outside of the chip, the source of the N-type power tube NMOS0 is connected to the ground terminal of the chip, and the gate is connected to the drive signal LS.

[0202] Preferably, the auxiliary charging low-voltage difference linear regulator LDO1 has a power supply end connected to the analog power supply voltage VDD, a ground end connected to the analog ground VSS, an input end connected to the first reference voltage Vref1, the fourth bias current Ibp1 and the first bias current Ibn1 respectively, a trimming control end connected to the first mismatch adjustment signal offset1_tune<1:0>, and an output end connected to the output voltage Vout.

[0203] Preferably, the auxiliary charging low-voltage difference linear regulator LDO1 also includes a first amplifier AMP1, whose power supply terminal is connected to the analog power supply voltage VDD, the ground terminal is connected to the analog ground VSS, the non-inverting input terminal is connected to the first reference voltage Vref1, the reverse input terminal is connected to the first feedback voltage Vfb1, and the output terminal outputs the first amplifier output voltage Vg1.

[0204] Preferably, the auxiliary charging low voltage difference linear regulator LDO1 also includes: a first output current limiting module 11, whose power supply end is connected to the analog power supply voltage VDD, the ground end is connected to the analog ground VSS, the input end is connected to the fourth bias current Ibp1, and the output end is connected to the first amplifier output voltage Vg1.

[0205] Preferably, the auxiliary charging low-dropout linear regulator LDO1 further includes a first N-type transistor NMOS11, a first P-type transistor PMOS11, and a second P-type transistor PMOS12, wherein the source of the first N-type transistor NMOS11 is connected to the analog ground VSS, the gate is connected to the first amplifier output voltage Vg1, and the drain is connected to the drain of the first P-type transistor PMOS11 to form a first current mirror connection point voltage Vbp1; the drain and gate of the first P-type transistor PMOS11 are short-circuited, and the source is connected to the analog power supply voltage VDD; the source of the second P-type transistor PMOS12 is connected to the analog power supply voltage VDD, the gate is short-circuited to the gate of the first P-type transistor PMOS11, and the drain is connected to the output voltage Vout; a first voltage divider feedback module 13, whose input terminal is connected to the output voltage Vout, the bias current terminal is connected to the first bias current Ibn1, the trim control terminal is connected to the first mismatch adjustment signal offset1_tune<1:0>, and the ground terminal is connected to the analog ground VSS.

[0206] Preferably, the first voltage divider feedback module 13 is used to adjust the first offset value Voffset1 between the expected output voltage of the auxiliary charging low-dropout linear regulator LDO1 and the output voltage of the Buck converter. Its input end is connected to the output voltage Vout, the bias current end is connected to the first bias current Ibn1, the trimming control end is connected to the first mismatch adjustment signal offset1_tune<1:0>, the ground end is connected to the analog ground VSS, and the output end outputs the first feedback voltage Vfb1.

[0207] Preferably, the first voltage divider feedback module 13 further includes: a first group of resistors, including a first resistor R10, a second resistor R11, a third resistor R12, a fourth resistor R13, a fifth resistor R14, a sixth resistor R15 and a seventh resistor R16; a first capacitor C10; a first group of N-type switch tubes, including a third N-type transistor SMN11, a fourth N-type transistor SWN12, a fifth N-type transistor SWN13 and a sixth N-type transistor SWN14; a first decoder 12; wherein the second resistor R11, the third resistor R12, the fourth resistor R13, the fifth resistor R14, the sixth resistor R15 and the seventh resistor R16 are connected in series in sequence, one end of the second resistor R11 is connected to the output voltage Vout, and the voltage signal between the other end and the third resistor R12 in series is used as the first feedback voltage Vfb1, and the first capacitor C10 and the first resistor R10 connected in series are connected between the output voltage Vout and the first feedback voltage Vfb1 voltage, the third resistor R12, the fourth resistor R 13. A voltage signal between the fifth resistor R14, the sixth resistor R15, and the seventh resistor R16 connected in series is respectively connected to the sources of the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13, and the sixth N-type transistor SWN14. The drains of the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13, and the sixth N-type transistor SWN14 are short-circuited together and connected to the first bias current Ibn1. An input end of the first decoder 12 is connected to the first mismatch adjustment signal offset1_tune<1:0>, and an output end outputs a first set of switch control signals, including a first switch control signal SC11, a second switch control signal SC12, a third switch control signal SC13, and a fourth switch control signal SC14, and is sequentially connected to the gates of the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13, and the sixth N-type transistor SWN14.

[0208] The first voltage divider feedback module 13 is used to adjust the output expected value Vout_LDO1 of the auxiliary charging low-dropout linear regulator LDO1. Assuming that the first mismatch adjustment signal offset1_tune<1:0>=0b00, after being decoded by the first decoder 12, the first switch control signal SC11 is pulled high, and the third N-type transistor SMN11 is turned on. At this time, the relationship between the output expected value Vout_LDO1 of the auxiliary charging low-dropout linear regulator LDO1 and the first feedback voltage Vfb1 is derived as follows:

[0209] V out_ldo1 =(R 11 +R 12 +R 13 +R14 +R 15 +R 16 )×Vfb1 / (R 12 +R 13 +R 14 +R 15 +R 16 )-Ibn1*R 11 *(R 13 +R 14 +R 15 +R 16 ) / (R 12 +R 13 +R 14 +R 15 +R 16 )(1)

[0210] Set the resistor divider so that the output voltage Vout of the Buck converter satisfies the formula: V out =(R 11 +R 12 +R 13 +R 14 +R 15 +R 16 )Vref / (R 12 +R 13 +R 14 +R 15 +R 16 )(2)

[0211] When the auxiliary charging low-dropout linear regulator LDO1 works normally, because Vfb1 = Vref, we have:

[0212] V out_ldo1 =V out -Ibn1*R 11 *(R 13 +R 14 +R 15 +R 16 ) / (R 12 +R 13 +R 14 +R 15 +R 16 )(3)

[0213] Among them, V out_ldo1 Indicates the preset output voltage value of the auxiliary charging low-voltage dropout linear regulator, that is, the target output voltage that the auxiliary charging low-voltage dropout linear regulator stabilizes when working.

[0214] Then V offset1 =Ibn1*R 11 *(R 13 +R 14 +R15 +R 16 ) / (R 12 +R 13 +R 14 +R 15 +R 16 )(4)

[0215] Among them, V offset1 represents a first deviation value, that is, a voltage difference between the target output voltage of the auxiliary charging low-dropout linear regulator and the target output voltage of the Buck converter.

[0216] Preferably, the auxiliary discharge low-voltage dropout linear regulator LDO2 has a power supply end connected to the analog power supply voltage VDD, a ground end connected to the analog ground VSS, an input end connected to the first reference voltage Vref1, the fifth bias current Ibp2, the second bias current Ibn2 and the third bias current Ibn10u respectively, a trimming control end connected to the second mismatch adjustment signal offset2_tune<1:0>, and an output end connected to the output voltage Vout.

[0217] Preferably, the auxiliary discharge low-voltage dropout linear regulator LDO2 also includes: a second amplifier AMP2, whose power supply terminal is connected to the analog power supply voltage VDD, the ground terminal is connected to the analog ground VSS, the inverting input terminal is connected to the first reference voltage Vref1, the non-inverting input terminal is connected to the second feedback voltage Vfb2, and the output terminal outputs the second amplifier output voltage Vg2.

[0218] Preferably, the auxiliary discharge low-voltage difference linear regulator LDO2 also includes a second output current limiting module 21, whose power end is connected to the analog power supply voltage VDD, the ground end is connected to the analog ground VSS, the input end is connected to the fifth bias current Ibp2, and the output end is connected to the second amplifier output voltage Vg2.

[0219] Preferably, the auxiliary discharge low-voltage dropout linear regulator LDO2 further includes a seventh N-type transistor NMOS21, an eighth N-type transistor NMOS22, a ninth N-type transistor NMOS23, a third P-type transistor PMOS21 and a fourth P-type transistor PMOS22, and an eighth resistor R28, wherein the source of the seventh N-type transistor NMOS21 is connected to the analog ground VSS, the gate is connected to the second amplifier output voltage Vg2, and the drain is connected to the drain of the third P-type transistor PMOS21 to form a second current mirror connection point voltage Vbp2; the drain and gate of the third P-type transistor PMOS21 are short-circuited, and the source is connected to the analog power supply voltage VDD; the source of the fourth P-type transistor PMOS22 is connected to the analog power supply voltage VDD, and the gate is short-circuited to the gate of the third P-type transistor PMOS21. The drain is connected to the gate and drain of the eighth N-type transistor NMOS22 to form a third current mirror connection point voltage Vbn2; the source of the eighth N-type transistor NMOS22 is connected to the analog ground VSS, the gate and drain are short-circuited to form the third current mirror connection point voltage Vbn2 and connected to the gate of the ninth N-type transistor NMOS23; the drain of the ninth N-type transistor NMOS23 is connected to the output voltage Vout and one end of the eighth resistor R28; the other end of the eighth resistor R28 is connected to the third bias current Ibn10u; a second voltage divider feedback module 23, whose input end is connected to the output voltage Vout, the bias current end is connected to the second bias current Ibn2, the trim control end is connected to the second mismatch adjustment signal offset2_tune<1:0>, and the ground end is connected to the analog ground VSS.

[0220] Preferably, the second voltage divider feedback module 23 is used to adjust the second offset value Voffset2 between the expected output voltage of the auxiliary discharge low-dropout linear regulator LDO2 and the output voltage of the Buck converter. Its input end is connected to the output voltage Vout, the bias current end is connected to the second bias current Ibn2, the trimming control end is connected to the second mismatch adjustment signal offset2_tune<1:0>, the ground end is connected to the analog ground VSS, and the output end outputs the second feedback voltage Vfb2.

[0221] Preferably, the second voltage divider feedback module 23 further includes: a second group of resistors, including a ninth resistor R20, a tenth resistor R21, an eleventh resistor R22, a twelfth resistor R23, a thirteenth resistor R24, a fourteenth resistor R25, and a fifteenth resistor R26; a second capacitor C20 and a third capacitor C21; a second group of N-type switching transistors, including a tenth N-type transistor SMN21, an eleventh N-type transistor SWN22, a twelfth N-type transistor SWN23, and a thirteenth N-type transistor SWN24; a second decoder 22; wherein the The tenth resistor R21, the eleventh resistor R22, the twelfth resistor R23, the thirteenth resistor R24, the fourteenth resistor R25 and the fifteenth resistor R26 are connected in series in sequence, one end of the tenth resistor R21 is connected to the analog ground VSS, and the voltage signal between the other end and the eleventh resistor R22 in series is used as the second feedback voltage Vfb2, and the second capacitor C20 and the ninth resistor R20 are connected in series between the output voltage Vout and the second feedback voltage Vfb2. The voltage signal between the first resistor R22, the twelfth resistor R23, the thirteenth resistor R24 and the fourteenth resistor R25 connected in series is respectively connected to the sources of the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23 and the thirteenth N-type transistor SWN24, and the drains of the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23 and the thirteenth N-type transistor SWN24 are short-circuited together and connected to the second bias current Ibn2, the input end of the second decoder 22 is connected to the second mismatch adjustment signal offset2_tune<1:0>, and the output end outputs a second set of switch control signals, including a fifth switch control signal SC21, a sixth switch control signal SC22, a seventh switch control signal SC23 and an eighth switch control signal SC24, and is sequentially connected to the gates of the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23 and the thirteenth N-type transistor SWN24.

[0222] The second voltage-dividing feedback module 23 is used to adjust the expected output value Vout_LDO2 of the auxiliary discharge low-dropout linear regulator LDO2. Assuming that the second mismatch adjustment signal offset2_tune<1:0>=0b00, after being decoded by the second decoder 22, the fifth switch control signal SC21 is pulled high, the tenth N-type transistor SMN21 is turned on, and the other switches are turned off. At this time, the relationship between the expected output value Vout_LDO2 of the auxiliary discharge low-dropout linear regulator LDO2 and the second feedback voltage Vfb2 is derived as follows:

[0223] V out_ldo2 =(R 21+R 22 +R 23 +R 24 +R 25 +R 26 )×Vfb2 / (R 21 )-Ibn2*(R 23 +R 24 +R 25 +R 26 ) (5)

[0224] Set the resistor value so that the output voltage Vout of the Buck converter satisfies the formula:

[0225] V out =(R 21 +R 22 +R 23 +R 24 +R 25 +R 26 )Vref / (R 21 ) (6)

[0226] When the auxiliary discharge low-dropout linear regulator LDO2 works normally, because Vfb2 = Vref, we have:

[0227] V out_ldo2 =V out -Ibn2*(R 23 +R 24 +R 25 +R 26 ) (7)

[0228] Then V offset2 =Ibn2*(R 23 +R 24 +R 25 +R 26 ) (8)

[0229] More specifically, the Buck converter of the present application that can quickly respond to output voltage switching includes the following main functional modules: a Buck control module, which is used to monitor the output voltage Vout state of the Buck converter and generate a pulse width modulation PWM signal to adjust the duty cycle of the power tube to ensure that the output voltage Vout is stable at the expected value, and at the same time provide a reference voltage Vref and a bias current for other modules; a BUCK drive module, which converts the PWM signal into a driving voltage domain and improves the driving capability of the signal to drive the power tube; an auxiliary charging low-voltage difference linear regulator LDO1, when the output voltage needs to be quickly increased, the Buck converter gradually increases the output voltage Vout through PWM signal control, and at the same time the auxiliary charging low-voltage difference linear regulator LDO1 responds quickly, supplements the output current, and reduces the voltage rise time; an auxiliary discharge low-voltage difference linear regulator LDO2, when the output voltage needs to be quickly reduced, the auxiliary discharge low-voltage difference linear regulator LDO2 quickly absorbs excess current, reduces the output voltage Vout, and at the same time the Buck converter gradually reduces the output voltage Vout through PWM signal control.

[0230] Buck control module such as Figure 4 As shown, the system includes a level converter, a low-pass filter, a loop compensator, a PWM generator, and a bias current generator. The level converter converts the digital voltage domain signal into the required analog voltage domain signal. The low-pass filter filters out high-frequency noise on the reference voltage Vref and outputs the first reference voltage Vref1. The loop compensator adds poles and zeros to the loop to offset the phase lag or lead caused by the LC filter. It also increases the DC gain of the Buck system to enhance the system's ability to adjust to input voltage and load changes, ensuring that the output voltage remains stable under various operating conditions. The PWM generator generates a pulse-width modulated (PWM) signal. The bias current generator generates the various bias currents required by other modules.

[0231] The BUCK driver module converts the PWM signal into two sets of signals with a certain dead time. This ensures that there is a non-overlapping time period between the high-side power transistor PMOS0 and the low-side power transistor NMOS0. That is, the time period during which both power transistors are in the off state at a certain moment, thereby preventing direct conduction between the upper and lower transistors. At the same time, the signal driving capability is improved, and the output drive signals HS and LS that can drive the power transistors are output.

[0232] Auxiliary charging low voltage drop linear regulator LDO1 Figure 5As shown, it includes a first amplifier AMP1, a first output current limiting module 11, transistors NMOS11, PMOS11, PMOS12 and a first voltage divider feedback module 13. The first amplifier AMP1 is used to amplify the difference between the first feedback voltage Vfb1 and the first reference voltage Vref1, and output the first amplifier output voltage Vg1, and adjust the output voltage Vout through the negative feedback loop of the auxiliary charging low-voltage dropout linear regulator LDO1. The difference between the first feedback voltage Vfb1 and the first reference voltage Vref1 gradually decreases, so that the output voltage Vout is finally stabilized at an expected value; the first output current limiting module 11 is used to limit the gate voltage Vg1 of the first N-type transistor NMOS11, so that the voltage difference Vgs between the gate and the source of the first N-type transistor NMOS11 is limited to a desired range. According to the characteristics of the saturation region transistor, when Vgs is limited, its current is also limited. Then, through the mirroring effect of the current mirror of the first P-type transistor PMOS11 and the second P-type transistor PMOS12 according to a preset ratio, the pull-up current at the output end of the auxiliary charging low-voltage dropout linear regulator LDO1 can be limited to within the expected value; the first voltage divider feedback module 13 is as follows: Figure 6 As shown, the output voltage of the auxiliary charging low-voltage dropout linear regulator LDO1 is sampled according to a certain ratio to obtain a voltage Vfb1 and fed back to the inverting input terminal of the first amplifier AMP1. At the same time, by adjusting the first mismatch adjustment signal offset1_tune<1:0> to inject current Ibn1 into the series resistors with different poles, the output voltage of the auxiliary charging low-voltage dropout linear regulator LDO1 can be caused to deviate from the target voltage of the Buck converter.

[0233] The working steps of the auxiliary charging low-dropout linear regulator LDO1 are as follows:

[0234] Step 1: When the Buck converter is just started or the Buck converter has been started but the output voltage needs to be increased to a higher level, the output voltage Vout is at a low level. At this time, the Buck converter gradually increases the output voltage Vout through PWM signal control. At the same time, the first voltage divider feedback module 13 of the auxiliary charging low-dropout linear regulator LDO1 samples the output voltage Vout and outputs the first feedback voltage Vfb1. At this time, the first feedback voltage Vfb1 is less than the first reference voltage Vref1. After passing through the first amplifier AMP1, the first amplifier output voltage Vg1 is increased, and the current of the first N-type transistor NMOS11 increases, so that the pull-up current of the second P-type transistor PMOS12 is synchronously increased to supplement the output current and reduce the voltage rise time. The waveform is as follows Figure 7 As shown, Figure 7 (a) is the waveform when the reference voltage Vref is switched from low to high without the assistance of the auxiliary charging low-dropout linear regulator LDO1. Figure 7(b) is the waveform when the reference voltage Vref is switched from low to high with the assistance of the auxiliary charging low-dropout linear regulator LDO1.

[0235] Step 2: After the output voltage Vout reaches the preset output voltage of the auxiliary charging low-dropout linear regulator LDO1, due to the continuous operation of the Buck converter, the output voltage Vout will continue to rise toward the preset output voltage of the Buck converter. At this time, the first feedback voltage Vfb1 sampled by the first voltage divider feedback module 13 gradually becomes greater than the first reference voltage Vref1. After passing through the first amplifier AMP1, the first amplifier output voltage Vg1 gradually decreases, the current of the first N-type transistor NMOS11 gradually decreases, and the pull-up current of the second P-type transistor PMOS12 decreases synchronously. When the first feedback voltage Vfb1 is greater than the first reference voltage Vref1 by a certain value, the first amplifier output voltage Vg1 drops to a limit, and the first N-type transistor NMOS11 and the second P-type transistor PMOS12 are all turned off, so that the loop of the auxiliary charging low-dropout linear regulator LDO1 is completely disconnected from the Buck system, thereby not affecting the overall efficiency of the Buck converter.

[0236] Auxiliary discharge low voltage dropout linear regulator LDO2 Figure 8 As shown, it includes a second amplifier AMP2, a second output current limiting module 21, transistors NMOS21, NMOS22, NMOS23, PMOS21, PMOS22, an eighth resistor R28 and a second voltage divider feedback module 23. The second amplifier AMP2 is used to amplify the difference between the second feedback voltage Vfb2 and the first reference voltage Vref1, and output the second amplifier output voltage Vg2, and adjust the output voltage Vout through the negative feedback loop of the auxiliary discharge low-voltage dropout linear regulator LDO2. The difference between the second feedback voltage Vfb2 and the first reference voltage Vref1 gradually decreases, so that the output voltage Vout is finally stabilized at an expected value; the second output current limiting module 21 is used to limit the gate voltage Vg2 of the seventh N-type transistor NMOS21, so that the voltage difference Vgs between the gate and the source of the seventh N-type transistor NMOS21 is limited to a desired range, and the current mirror composed of the third P-type transistor PMOS21, the fourth P-type transistor PMOS22, the eighth N-type transistor NMOS22, and the ninth N-type transistor NMOS23 can be used to limit the output pull-down current of the auxiliary discharge low-voltage dropout linear regulator LDO2 to within the expected value through the mirror effect of the preset ratio; the second voltage divider feedback module 23 is as follows: Figure 9As shown, the output voltage of the auxiliary discharge low-dropout linear regulator LDO2 is sampled according to a certain ratio to obtain a second feedback voltage Vfb2 and fed back to the inverting input terminal of the second amplifier AMP2. At the same time, by adjusting the second mismatch adjustment signal offset2_tune<1:0> to draw current Ibn2 from the series resistors with different poles, the output of the auxiliary discharge low-dropout linear regulator LDO2 can be deviated from the target voltage of the Buck converter.

[0237] The working steps of the auxiliary discharge low-dropout linear regulator LDO2 are as follows:

[0238] Step 1: When the input reference voltage Vref of the Buck converter is cut from high to low and the output voltage Vout needs to be reduced to a lower level, the output voltage Vout is still at a high level. At this time, the Buck converter gradually reduces the output voltage Vout through PWM signal control. At the same time, the second voltage divider feedback module 23 of the auxiliary discharge low-dropout linear regulator LDO2 samples the output voltage Vout and outputs the second feedback voltage Vfb2. At this time, the second feedback voltage Vfb2 is greater than the first reference voltage Vref1. After passing through the second amplifier AMP2, the second amplifier output voltage Vg2 is increased, and the current of the seventh N-type transistor NMOS21 increases, so that the pull-down current of the ninth N-type transistor NMOS23 is synchronously increased to draw a large current from the output end and reduce the voltage drop time. The waveform is as follows Figure 10 As shown, Figure 10 (a) is the waveform when the reference voltage Vref is switched from high to low without the assistance of the auxiliary discharge low-dropout linear regulator LDO2. Figure 10 (b) is the waveform when the reference voltage Vref is switched from high to low with the assistance of the auxiliary discharge low-dropout linear regulator LDO2.

[0239] Step 2: After the output voltage Vout reaches the preset output voltage of the auxiliary discharge low-dropout linear regulator LDO2, due to the continued operation of the Buck converter, the output voltage Vout will continue to decrease toward the preset output voltage of the Buck converter. At this time, the second feedback voltage Vfb2 sampled by the second voltage divider feedback module 23 gradually becomes less than the first reference voltage Vref1. After passing through the second amplifier AMP2, the second amplifier output voltage Vg2 gradually decreases, the current of the seventh N-type transistor NMOS21 gradually decreases, and the pull-down current of the ninth N-type transistor NMOS23 decreases synchronously. When the second feedback voltage Vfb2 is less than a certain value of the first reference voltage Vref1, the second amplifier output voltage Vg2 drops to a limit, and the seventh N-type transistor NMOS21 and the ninth N-type transistor NMOS23 are both turned off, so that the loop of the auxiliary discharge low-dropout linear regulator LDO2 is completely disconnected from the Buck system, thereby not affecting the overall efficiency of the Buck converter.

[0240] Compared with the prior art, the present invention has the following advantages:

[0241] Beneficial effect 1: The output voltage can be switched quickly and the transient response capability of the circuit is improved.

[0242] In a traditional Buck converter, when the reference voltage Vref suddenly rises (falls), the output signal Verr of the loop compensator will rise (fall), the duty cycle of the pulse width modulation (PWM) signal will increase (decrease), the on-time of the power tube will be prolonged (shortened), and the current in the external inductor L0 will rise (fall). Since the current in the external inductor L0 cannot change suddenly, the output voltage Vout cannot rise (fall) quickly. This makes it unsuitable for applications that require fast output voltage switching.

[0243] By introducing the auxiliary charging low-voltage dropout linear regulator LDO1 and the auxiliary discharging low-voltage dropout linear regulator LDO2, when the reference voltage Vref suddenly rises, the output of the auxiliary charging low-voltage dropout linear regulator LDO1 does not pass through the external inductor L0. Therefore, the internal loop of the auxiliary charging low-voltage dropout linear regulator LDO1 further activates the second P-type transistor PMOS12, injecting a large current into the output terminal to increase the output voltage Vout, greatly improving the rise rate of the output voltage Vout. When the reference voltage Vref suddenly drops, the output of the auxiliary discharging low-voltage dropout linear regulator LDO2 does not pass through the external inductor L0. Therefore, the internal loop of the auxiliary discharging low-voltage dropout linear regulator LDO2 further activates the ninth N-type transistor NMOS23, drawing a large current from the output terminal to reduce the output voltage Vout, greatly improving the drop rate of the output voltage Vout.

[0244] Beneficial effect 2: It does not affect the overall efficiency of the Buck converter.

[0245] By adjusting the first mismatch adjustment signal offset1_tune<1:0> and the second mismatch adjustment signal offset2_tune<1:0>, the target output value of the auxiliary charging low-voltage dropout linear regulator LDO1 is lower than the target output value of the Buck converter by a first offset value Voffset1, while the target output value of the auxiliary discharging low-voltage dropout linear regulator LDO2 is higher than the target output value of the Buck converter by a second offset value Voffset2. Therefore, the auxiliary charging low-voltage dropout linear regulator LDO1 and the auxiliary discharging low-voltage dropout linear regulator LDO2 only work briefly when the reference voltage Vref switches rapidly between rising and falling. After the switching is completed, the auxiliary charging low-voltage dropout linear regulator LDO1 and the auxiliary discharging low-voltage dropout linear regulator LDO2 are in the off state, which will not affect the overall efficiency of the Buck converter.

[0246] The above embodiments have the following technical effects:

[0247] First, it enables rapid output voltage switching and improves the circuit's transient response capability. In a traditional buck converter, when the reference voltage Vref suddenly rises (falls), the loop compensator's output signal Verr rises (falls), the duty cycle of the pulse-width modulation (PWM) signal increases (decreases), the power transistor's on-time increases (shortens), and the current in the external inductor L0 increases (falls). Because the current in the external inductor L0 cannot change suddenly, the output voltage Vout cannot rise (fall) quickly, making it unsuitable for applications requiring rapid output voltage switching. By introducing the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharging low-dropout linear regulator LDO2, when the reference voltage Vref suddenly rises, the output of the auxiliary charging low-dropout linear regulator LDO1 does not pass through the external inductor L0. Therefore, the internal loop of the auxiliary charging low-dropout linear regulator LDO1 further turns on the second P-type transistor PMOS12, injecting a large current into the output terminal to increase the output voltage Vout, significantly improving the rise speed of the output voltage Vout. When the reference voltage Vref drops suddenly, the output of the auxiliary discharge low-dropout linear regulator LDO2 does not pass through the off-chip inductor L0. Therefore, the internal loop of the auxiliary discharge low-dropout linear regulator LDO2 will further turn on the ninth N-type transistor NMOS23, drawing a large current from the output terminal to reduce the output voltage Vout, thereby greatly increasing the falling speed of the output voltage Vout.

[0248] Second, it does not affect the overall efficiency of the Buck converter. By adjusting the first mismatch adjustment signal offset1_tune<1:0> and the second mismatch adjustment signal offset2_tune<1:0>, the target output value of the auxiliary charging low-dropout linear regulator LDO1 is lower than the target output value of the Buck converter by a first offset value Voffset1, while the target output value of the auxiliary discharging low-dropout linear regulator LDO2 is higher than the target output value of the Buck converter by a second offset value Voffset2. Therefore, the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharging low-dropout linear regulator LDO2 only operate briefly when the reference voltage Vref rapidly rises and falls, respectively. After the switching is completed, the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharging low-dropout linear regulator LDO2 are in the off state, which does not affect the overall efficiency of the Buck converter.

[0249] It should be noted that in the application documents of this application, relational terms such as first and second are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise," "include," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or device. Without further restriction, an element defined by the phrase "comprising a" does not exclude the presence of other identical elements in the process, method, article, or device comprising the element. In the application documents of this application, if it is mentioned that an action is performed according to a certain element, it means that the action is performed at least according to that element, including two situations: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "multiple," and "multiple" include "two," "twice," "two kinds," and "more than two," "more than two times," and "more than two kinds."

[0250] All documents mentioned in this application are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art may make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A Buck converter with fast response output voltage switching, characterized in that: include: Buck control module, used to monitor the output voltage of the Buck converter, output pulse width modulation signal, and generate bias current and reference voltage; A buck driver module and a power tube, wherein the input end of the buck driver module is connected to the pulse width modulation signal, and the output end outputs the driving signal; the power tube includes an upper P-type power tube and a lower N-type power tube, wherein the source of the P-type power tube is connected to the off-chip input power supply voltage, the gate is connected to the driving signal, the drain is short-circuited with the drain of the N-type power tube and output to the outside of the chip, the source of the N-type power tube is connected to the ground terminal of the chip, and the gate is connected to the driving signal; an auxiliary charging low-dropout linear regulator, wherein the power terminal is connected to the analog power voltage, the ground terminal is connected to the analog ground, the input terminals are connected to the first reference voltage, the fourth bias current, and the first bias current, respectively, the trim control terminal is connected to the first mismatch adjustment signal, and the output terminal is connected to the output voltage; an auxiliary discharge low-dropout linear regulator, wherein the power supply terminal is connected to the analog power supply voltage, the ground terminal is connected to the analog ground, the input terminals are respectively connected to the first reference voltage, the fifth bias current, the second bias current, and the third bias current, the trimming control terminal is connected to the second mismatch adjustment signal, and the output terminal is connected to the output voltage; Off-chip inductors and load capacitors are used to stabilize the output voltage.

2. The Buck converter according to claim 1, wherein: The target output value of the auxiliary charging low-voltage dropout linear regulator is lower than the target output value of the Buck converter by a first deviation value. When the reference voltage rises rapidly, the Buck converter gradually increases the output voltage through pulse width modulation signal control. At the same time, the auxiliary charging low-voltage dropout linear regulator responds quickly and injects current into the output terminal to make the output voltage rise rapidly. When the output voltage reaches the preset output voltage of the auxiliary charging low-voltage dropout linear regulator, the auxiliary charging low-voltage dropout linear regulator loop is automatically closed. The target output value of the auxiliary discharge low-voltage dropout linear regulator is higher than the target output value of the Buck converter by a second deviation value. When the reference voltage drops rapidly, the Buck converter gradually reduces the output voltage through pulse width modulation signal control. At the same time, the auxiliary discharge low-voltage dropout linear regulator responds quickly, draws current from the output end to make the output voltage drop rapidly. When the output voltage reaches the preset output voltage of the auxiliary discharge low-voltage dropout linear regulator, the auxiliary discharge low-voltage dropout linear regulator loop is automatically closed, so that the auxiliary charge low-voltage dropout linear regulator and the auxiliary discharge low-voltage dropout linear regulator only work briefly when the reference voltage switches between rising and falling rapidly. After the switching is completed, the auxiliary charge low-voltage dropout linear regulator and the auxiliary discharge low-voltage dropout linear regulator are in the off state, which does not affect the overall efficiency of the Buck converter.

3. The Buck converter according to claim 1, wherein: The Buck control module includes: a first level converter and a second level converter, wherein the input end of the first level converter is connected to the first digital mismatch adjustment signal and the output end thereof outputs the first mismatch adjustment signal; the input end of the second level converter is connected to the second digital mismatch adjustment signal and the output end thereof outputs the second mismatch adjustment signal; A low-pass filter, whose input terminal is connected to the reference voltage and outputs a first reference voltage after filtering out its high-frequency noise; A loop compensator, wherein a reference voltage input terminal thereof is connected to a first reference voltage, a feedback input terminal thereof is connected to an output voltage, and an output loop compensator output signal is output; A PWM generator, whose input terminal is connected to the loop compensator output signal and outputs a pulse width modulation signal; The bias current generator has an input terminal connected to the first reference voltage and an output terminal outputting a first bias current, a second bias current, a third bias current, a fourth bias current and a fifth bias current.

4. The Buck converter according to claim 1, wherein: The auxiliary charging low voltage difference linear regulator also includes a first amplifier, whose power supply terminal is connected to the analog power supply voltage, the ground terminal is connected to the analog ground, the non-inverting input terminal is connected to the first reference voltage, the reverse input terminal is connected to the first feedback voltage, and the output terminal outputs the first amplifier output voltage.

5. The Buck converter according to claim 4, wherein: The auxiliary charging low voltage drop linear regulator further includes: a first output current limiting module, wherein a power supply terminal is connected to the analog power supply voltage, a ground terminal is connected to the analog ground, an input terminal is connected to the fourth bias current, and an output terminal is connected to the first amplifier output voltage; a first N-type transistor, a first P-type transistor, and a second P-type transistor, wherein the source of the first N-type transistor is connected to the analog ground, the gate is connected to the first amplifier output voltage, and the drain is connected to the drain of the first P-type transistor to form a first current mirror connection point voltage; the drain and gate of the first P-type transistor are short-circuited, and the source is connected to the analog power supply voltage; the source of the second P-type transistor is connected to the analog power supply voltage, the gate is short-circuited to the gate of the first P-type transistor, and the drain is connected to the output voltage; The first voltage divider feedback module has an input terminal connected to the output voltage, a bias current terminal connected to the first bias current, a trimming control terminal connected to the first mismatch adjustment signal, and a ground terminal connected to the analog ground.

6. The Buck converter according to claim 5, wherein: The first voltage division feedback module further includes: A first resistor group includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; a first capacitor; A first group of N-type switching transistors includes a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, and a sixth N-type transistor; a first decoder; The second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, and the seventh resistor are connected in series in sequence. One end of the second resistor is connected to the output voltage, and a voltage signal between the other end and the third resistor in series serves as the first feedback voltage. The first capacitor and the first resistor are connected in series between the output voltage and the first feedback voltage. The voltage signal between the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, and the seventh resistor in series is connected to the sources of the third N-type transistor, the fourth N-type transistor, the fifth N-type transistor, and the sixth N-type transistor, respectively. The drains of the third N-type transistor, the fourth N-type transistor, the fifth N-type transistor, and the sixth N-type transistor are short-circuited together and connected to the first bias current. The input end of the first decoder is connected to the first mismatch adjustment signal, and the output end outputs a first set of switch control signals, including a first switch control signal, a second switch control signal, a third switch control signal, and a fourth switch control signal, and is connected to the gates of the third N-type transistor, the fourth N-type transistor, the fifth N-type transistor, and the sixth N-type transistor in sequence.

7. The Buck converter according to claim 1, wherein: The auxiliary discharge low voltage drop linear regulator further includes: a second amplifier, having a power supply terminal connected to the analog power supply voltage, a ground terminal connected to the analog ground, an inverting input terminal connected to the first reference voltage, a non-inverting input terminal connected to the second feedback voltage, and an output terminal outputting the second amplifier output voltage; a second output current limiting module, wherein a power supply terminal is connected to the analog power supply voltage, a ground terminal is connected to the analog ground, an input terminal is connected to the fifth bias current, and an output terminal is connected to the second amplifier output voltage; a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a third P-type transistor, a fourth P-type transistor, and an eighth resistor, wherein the source of the seventh N-type transistor is connected to the analog ground, the gate is connected to the second amplifier output voltage, and the drain is connected to the drain of the third P-type transistor to form a second current mirror connection point voltage; the drain and gate of the third P-type transistor are short-circuited, and the source is connected to the analog power supply voltage; the source of the fourth P-type transistor is connected to the analog power supply voltage, the gate is short-circuited to the gate of the third P-type transistor, and the drain is connected to the gate and drain of the eighth N-type transistor to form a third current mirror connection point voltage; the source of the eighth N-type transistor is connected to the analog ground, the gate and drain are short-circuited to the third current mirror connection point voltage and connected to the gate of the ninth N-type transistor; the drain of the ninth N-type transistor is connected to the output voltage and one end of the eighth resistor; the other end of the eighth resistor is connected to the third bias current; The second voltage divider feedback module has an input terminal connected to the output voltage, a bias current terminal connected to the second bias current, a trimming control terminal connected to the second mismatch adjustment signal, and a ground terminal connected to the analog ground.

8. The Buck converter according to claim 7, wherein: The second voltage division feedback module further includes: a second group of resistors, including a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor; a second capacitor and a third capacitor; a second group of N-type switching transistors, including a tenth N-type transistor, an eleventh N-type transistor, a twelfth N-type transistor, and a thirteenth N-type transistor; a second decoder; The tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, the fourteenth resistor, and the fifteenth resistor are connected in series in sequence; one end of the tenth resistor is connected to the analog ground, and a voltage signal between the other end and the series connection of the eleventh resistor serves as the second feedback voltage; the second capacitor and the ninth resistor are connected in series between the output voltage and the second feedback voltage; the voltage signal between the tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor, and the series connection of the fourteenth resistor is connected to the sources of the tenth N-type transistor, the eleventh N-type transistor, the twelfth N-type transistor, and the thirteenth N-type transistor, respectively; the drains of the tenth N-type transistor, the eleventh N-type transistor, the twelfth N-type transistor, and the thirteenth N-type transistor are short-circuited together and connected to the second bias current; the input end of the second decoder is connected to the second mismatch adjustment signal, and the output end outputs a second set of switch control signals, including a fifth switch control signal, a sixth switch control signal, a seventh switch control signal, and an eighth switch control signal, and is connected to the gates of the tenth N-type transistor, the eleventh N-type transistor, the twelfth N-type transistor, and the thirteenth N-type transistor in sequence.

Images