Method for enhancing precision of locking detection circuit of digital dynamic link library (DLL)
By multiplexing the delay unit of the CNC delay line in the lock detection circuit and generating the second control code, the accuracy reduction problem caused by the PVT changes in the traditional lock detection circuit is solved, and higher detection accuracy and circuit simplification are achieved.
Patent Information
- Application Number
- CN202510513911.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2025-08-08
AI Technical Summary
The delay time of traditional lock detection circuits is susceptible to process, voltage and temperature changes, resulting in a decrease in detection accuracy.
The delay unit of the CNC delay line is multiplexed in the lock detection circuit, and the number of delay units is determined by generating the second control code, ensuring that the delay time is bound to the clock cycle and changes independently from the PVT.
The accuracy of the lock detection circuit is improved, the impact of PVT changes on the delay time is reduced, the circuit structure is simplified, and the circuit is adapted to different input clock frequencies.
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Figure CN120454716A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of on-chip circuits, and in particular to a method for enhancing the accuracy of a lock detection circuit of a digital DLL. Background Art
[0002] Delay-locked loops (DLLs) are widely used in modern microprocessor and system-on-chip designs, such as dynamic random access memory (DRAM) interfaces and clock generation and distribution circuits. The core function of an analog DLL is to output an analog voltage to ensure that the total delay time of the delay unit is equal to one reference clock cycle. In an analog DLL, a charge pump (CP) converts the phase error signal (typically UP / DOWN pulses) output by a phase detector (PD) into an analog current or voltage, which is used to control the delay time of a voltage-controlled delay line (VCDL). The VCDL control voltage is adjusted by charging and discharging operations to align (lock) the phase of the feedback clock (CKFB) with the reference clock (CKREF). A lock detection circuit monitors the phase difference between the feedback clock and the reference clock in real time to ensure that they are within the allowable range (i.e., locked). However, traditional lock detection circuits use independent delay circuits, and their delay time fluctuates significantly due to variations in process, voltage, and temperature. Summary of the Invention
[0003] In order to solve the problems existing in the prior art, the embodiments of the present application provide a method for enhancing the accuracy of the lock detection circuit of a digital DLL, a digital delay phase-locked loop, a master-slave digital delay phase-locked loop system, and an integrated circuit chip. The method can improve the detection accuracy of lock detection.
[0004] In a first aspect, an embodiment of the present application provides a method for enhancing the accuracy of a lock detection circuit of a digital DLL, comprising: multiplexing delay units in a digitally controlled delay line in a lock detection circuit; determining a second control code for the lock detection circuit based on a first control code of the digitally controlled delay line, wherein the first control code is used to represent the number of delay units turned on in the digitally controlled delay line, and the second control code is used to represent the number of delay units turned on in the lock detection circuit; the second control code is the product of the first control code and a preset coefficient; and determining the number of delay units in the lock detection circuit based on the second control code.
[0005] In some possible implementations, the value range of the preset coefficient is 1 / 2 n, where n is a positive integer.
[0006] In some possible implementations, the second control code of the lock detection circuit is determined based on the first control code of the digitally controlled delay line, specifically by: shifting the first control code right by n bits, or intercepting the highest mn bits of the binary representation of the first control code, where m is the bit width of the first control code, m>n, and m and n are both positive integers.
[0007] In some possible implementations, the lock detection circuit includes a smaller number of delay unit stages than the digitally controlled delay line.
[0008] In some possible implementations, the delay unit is a buffer or a lattice delay unit.
[0009] In some possible implementations, the method further includes: comparing a phase difference between a reference clock and a feedback clock; and determining that the delay-locked loop is in a locked state when an absolute value of the phase difference does not exceed the delay time.
[0010] In some possible implementations, determining that the delay locked loop is in a locked state further includes: the phase difference does not exceed the delay time Td in N consecutive clock cycles.
[0011] In a second aspect, an embodiment of the present application provides a digital delay phase-locked loop that implements lock detection based on the method described in any one of the first aspects.
[0012] In a third aspect, an embodiment of the present application provides a master-slave digital delay phase-locked loop system, comprising: a master delay phase-locked loop, which adopts the fully digital delay phase-locked loop as described in the second aspect; and at least one slave delay phase-locked loop, whose digitally controlled delay line is configured by the first control code of the master delay phase-locked loop.
[0013] In a fourth aspect, an embodiment of the present application provides an integrated circuit chip, which integrates the digital delay locked loop described in the second aspect or the master-slave digital delay locked loop system described in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0015] Figure 1 This is a basic structural diagram of a digital DLL with a master-slave structure provided by an embodiment of the present application;
[0016] Figure 2 This is a schematic diagram of a traditional implementation of a lock detection circuit provided in an embodiment of the present application;
[0017] Figure 3 This is a voltage change timing diagram of a lock detection circuit provided in an embodiment of the present application;
[0018] Figure 4 1 is a circuit diagram for enhancing the accuracy of a lock detection circuit of an ADDLL provided by an embodiment of the present application;
[0019] Figure 5 1 is a flow chart of a method for enhancing the accuracy of the lock detection circuit of ADDLL provided in an embodiment of the present application. DETAILED DESCRIPTION
[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.
[0021] The term "and / or" as used herein describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. The symbol " / " as used herein indicates that the related objects are in an "or" relationship, for example, A / B means either A or B.
[0022] The terms "first" and "second" in this specification and claims are used to distinguish different objects rather than to describe a specific order of objects. For example, "first response message" and "second response message" are used to distinguish different response messages rather than to describe a specific order of response messages.
[0023] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0024] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.
[0025] To facilitate understanding of the embodiments of the present application, further explanation will be given below with reference to specific embodiments in conjunction with the accompanying drawings. The embodiments do not constitute a limitation on the embodiments of the present invention.
[0026] Although traditional analog DLLs have the characteristics of low jitter and small static phase difference, as the feature size of CMOS devices continues to shrink, digital DLLs (all-digital delay-locked loop, ADDLL) are now more widely used. Digital DLLs can output a digital code to make the total delay time of the delay unit equal to one reference clock cycle. Compared with traditional analog DLLs, digital DLLs are insensitive to environmental changes and are more suitable for the design of low-voltage, low-power modern microprocessors and system-on-chips. For example, Figure 1 FIG. 1 shows a basic structural diagram of a digital DLL with a master-slave structure provided by an embodiment of the present application. Figure 1As shown, a digital DLL typically consists of a master DLL (MDLL) with several slave DLLs (SDLLs). The MDLL uses its phase detector (PD) to determine the phase relationship between the feedback clock (CKFB) and the input reference clock (CKREF). It then adjusts the loop counter to ensure that the delay between the feedback clock and the input reference clock is exactly one clock cycle. The reference clock (CKREF) is the input reference clock for the DLL, providing a stable frequency and phase reference. It typically comes from the system's master clock (such as a crystal oscillator or PLL output). The feedback clock (CKFB) is the output clock of the DLL, adjusted by a digitally controlled delay line (DCDL), and fed back to the phase detection circuit. The goal is to achieve phase alignment (lock) between CKFB and CKREF by adjusting the delay. The MDLL detects the phase difference between the reference clock (CKREF) and the feedback clock (CKFB) and generates a control code. The MDLL must be precisely phase-locked; otherwise, the slave DLLs will fail. Locking refers to the DLL adjusting the delay line (digitally controlled delay line, DCDL) to align the phase of the feedback clock (CKFB) with the reference clock (CKREF). The DCDL monitors the phase difference between CKFB and CKREF in real time to ensure it is within an acceptable range (e.g., ±200 ps, depending on the frequency of the reference clock). If it is within this range, the DLL is considered locked; if it is not, the DLL is not locked. The SDLL obtains the n-bit code value output by the MDLL counter and then selects outputs with different phases to generate the final output clock. In a digital DLL, a digitally controlled delay line (DCDL) typically consists of multiple basic delay modules connected in series, replacing the voltage-controlled delay line (VCDL) to achieve the delay function. A digital control module (DCTRL) replaces the charge pump (CP) in analog DLLs to complete the closed-loop control. In a digital DLL, the DCTRL replaces the charge pump (CP) in a traditional analog DLL. It generates digital control signals (such as increasing or decreasing the code value) based on phase detection results, adjusts the delay of the digitally controlled delay line (DCDL), and ensures phase synchronization between the feedback clock (CKFB) and the reference clock (CKREF).
[0027] Digitally controlled delay lines (DCDLs) can be implemented in a variety of ways, including by cascading buffers or by cascading other delay subunits, such as lattice delay units (LDUs). Regardless of the method used, the total delay time of the DCDL is calculated according to the following formula:
[0028] T_delay=Tunit_delay*code
[0029] Where Tunit_delay is the delay of the first-level delay subunit, and code refers to the number of delay subunits enabled. When the code value is appropriate, T_delay = T_clk_period, and the total delay time equals one reference clock period, the loop is stable, and the DLL is locked.
[0030] For example, Figure 2 FIG2 shows a conventional implementation of a lock detection circuit (Lock Detector, LKD) provided in an embodiment of the present application. Figure 3 This is a timing diagram of voltage changes in a lock detection circuit provided by an embodiment of the present application. Figure 2 and Figure 3 , Figure 2 The Delay shown in is a delay module, and the delay time is (time delay, Td). Figure 3 When the delay between the input reference clock (CKREF) and the feedback clock (CKFB) is within ±Td, the output OUT of the lock detection circuit becomes 1, indicating that the DLL is locked (OUT can also pass through a counter, and when OUT is 1 for N consecutive cycles, the DLL lock signal is output as 1).
[0031] Traditional lock detection circuits (LKDs) use an independent delay circuit for the delay module. This problem arises from the fact that the time delay (Td) varies with PVT. For example, a typical Td of 200ps might rise to 130ps in the best case and 300ps in the worst case. This wide variation can reduce the accuracy of the lock detection circuit under different conditions.
[0032] In view of this, the embodiment of the present application provides a method for enhancing the accuracy of the lock detection circuit of ADDLL by multiplexing the delay unit of DCDL and dynamically generating Td by utilizing the relationship when MDLL is locked, so as to decouple Td from PVT to improve the detection accuracy. Figure 4 FIG. 1 shows a circuit diagram of enhancing the accuracy of the lock detection circuit of ADDLL provided by an embodiment of the present application. Figure 4 As shown, in the digitally controlled delay line DCDL, multiple delay units (delay unit, DU) are connected together in series. The input of the first DU is the reference clock, and the input of the next DU is the output of the previous DU. At the same time, the output of each DU is sent to the multiplexer (MUX), and the output clock CKFB is selected by code. DU is the minimum delay module that constitutes the digitally controlled delay line (DCDL), and each DU provides a fixed basic delay time T_unit_delay. DU can be a buffer (Buffer), an inverter (Inverter) or a dedicated delay structure (such as a lattice delay unit, LDU), and this application does not make specific restrictions. In the case of locking, according to the formula T_delay = Tunit_delay*code, it can be obtained that Tunit_delay = T_delay / code, in Figure 4 In the circuit shown, the delay of one clock cycle is recorded as T_clk_period, and code represents the number of activated DUs, which is determined by the control code code. The delay module in the lock detection circuit LKD is also formed in series with the same delay unit DU as in the digital control delay line, so that the DU is affected by PVT in the same way. However, the number of delay units DU in LKD is less than that in DCDL. Therefore, the delay time of each delay unit in LKD is the same as the delay time of the delay unit in DCDL, which is T_clk_period / code. The number of delay units DU used in LKD can be determined by code2. In this embodiment, code2 is a product of code and a coefficient k (1 / 2 n , that is, k = 1 / 2, 1 / 4, 1 / 8, ...) multiplied together, that is, code2 is implemented using the most significant bit (MSB) of the code. Therefore, the delay time in LKD can be obtained.
[0033] Td=(T_clk_period / code)*code*k=T_clk_period*k
[0034] By controlling the value of k, the delay module's delay can be roughly controlled to the reference clock period multiplied by the coefficient k. This value is independent of the unit delay time of the code and DU, and only depends on the input clock period and the value of k. Therefore, when the input clock is fixed, the delay time of the delay module in LKD is almost independent of PVT.
[0035] Next, let's use a specific example to further explain. Assuming a 200MHz reference clock with a 5ns period, and a typical delay time of 30ps for each delay unit (DU), then the lock code is 5n / 30p≈167 (units), or 167 delay units. Assuming we want the lock detection range to be within ±1 / 16th of a period (5n / 16≈313ps), k=1 / 16, meaning code2 can discard the least significant bits (LSBs) of the binary code. The binary code is 1010_0111, and code2 discards the last four bits to get 1010, which converts to decimal to 10. Therefore, the delay module's delay time Td=30p*10=300ps, close to the target value of 313p. In the best case, assuming the delay time of each delay unit DU is 21ps, then the code at lock = 5n / 21p ≈ 238 (codes), which translates to 1110_1110 in binary, with code2 being 1110, or 14 codes. In this case, Td = 21p*14 = 294ps. In the worst case, assuming the delay time of each delay unit DU is 43ps, then the code at lock = 5n / 43p = 116 (codes), which translates to 0111_0100 in binary, with code2 being 0111, or 7 codes. In this case, Td = 43p*7 = 301ps. Although there will be some error in the code obtained during loop lock, and also in the conversion of code*k to code2, the results show that the results are close across the various cases.
[0036] For example, Figure 5 FIG. 1 is a flow chart showing a method for enhancing the accuracy of the lock detection circuit of ADDLL provided by an embodiment of the present application. Figure 5 As shown, the method may include the following steps:
[0037] S51: Multiplexing the delay units in the digitally controlled delay line in the lock detection circuit.
[0038] In this embodiment, the digitally controlled delay line (DCDL) is composed of a plurality of delay units (DU) connected in series, and the delay time (T_unit_delay) of each DU varies with the influence of process, voltage, and temperature (PVT). The delay module of the traditional lock detection circuit (LKD) uses independently designed delay units, and its delay time (Td) will also deviate from the design value due to PVT fluctuations, resulting in a decrease in detection accuracy. In order to avoid the influence of PVT on the detection accuracy, in the embodiment of the present application, the delay units in the digitally controlled delay line are reused in the lock detection circuit to ensure that the delay units of the two operate under the same PVT conditions. Since the DCDL meets the requirements of the PVT when locked, the delay unit Td of the digital controlled delay line is less than the delay unit Td of the digital controlled delay line.
[0039] T_clk_period = Tunit_delay * code, that is, Tunit_delay = T_clk_period / code. The delay module of LKD obtains consistent Tunit_delay through the same DU, thereby ensuring that the delay characteristics of the two change synchronously and avoiding detection errors caused by PVT differences.
[0040] S52: Determine a second control code of the lock detection circuit based on a first control code of the digitally controlled delay line, wherein the first control code is used to represent the number of delay units turned on in the digitally controlled delay line, and the second control code is used to represent the number of delay units turned on in the lock detection circuit.
[0041] In this embodiment, code is the first control code, which is a digital signal used in the DCDL to select the number of activated DUs. The second control code is code2, which is generated by truncating the high-order bits of code, specifically code2 = code*k. k is a coefficient. For example, if code is 167 (binary 10100111) and k = 1 / 16, code2 truncates the high-order 4 bits of code, 1010 (decimal 10). The purpose of this operation is to scale down code to generate a control code that is proportional to code but has fewer bits. Since k is usually a negative integer power of 2 (such as 1 / 16, 1 / 8), hardware implementation can be completed through simple shifting or high-order truncation without complex calculations. In this way, the generation of code2 depends only on the value of code and the selection of k, and is independent of the specific delay time of the DU, thereby binding the delay time (Td) of the LKD to the clock period (T_clk_period).
[0042] S53: Determine the number of delay units in the lock detection circuit based on the second control code.
[0043] In this embodiment, the delay module of LKD is composed of multiple DUs connected in series that are the same as DCDL, and the number of activated DUs is determined by code2. The delay time of each DU is the same as that of the DU in DCDL. Therefore, the total delay time of LKD is Td = code2 * Tunit_delay. Finally, Td = T_clk_period * k is obtained. This shows that Td is only determined by the clock period and the coefficient k, and is completely independent of the DU delay variation caused by PVT. For example, when k = 1 / 16, Td is 1 / 16 of the clock period. If the clock period is 5ns (200MHz), then Td = 313ps. Under different PVT conditions, although the specific values of code and code2 will change (such as code = 167, 238, 116), through the above relationship, Td is always close to the target value (300ps, 294ps, 301ps), the error range is significantly reduced, and the influence of PVT is basically avoided.
[0044] The above is the method for enhancing the accuracy of the lock detection circuit of ADDLL provided in the embodiment of the present application. By reusing the delay unit DU in DCDL in the lock detection circuit, the delay characteristics of the two are changed synchronously. Based on the control code code of DCDL, the control code code2 of the lock detection circuit is generated, and code2 is used to accurately control the number of delay units in the lock detection circuit. In this way, the influence of process, voltage and temperature (PVT) changes is largely eliminated, and the detection accuracy is improved. In addition, when the input clock frequency of the DLL varies widely, the traditional lock detection circuit needs to design the delay time of multiple Delay modules to adapt to different input clock frequencies, and the circuit is complicated. The present application uses a multi-stage DU series connection method, and only the total number of DUs is modified to meet the minimum frequency operation, and the circuit structure is also simpler.
[0045] It is understandable that the size of the sequence number of each step in the above-mentioned embodiments does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. In addition, in some possible implementations, the steps in the above-mentioned embodiments can be selectively executed according to actual conditions, and can be partially executed or fully executed, which is not limited here. All or part of any features of any embodiment of the present application can be freely and arbitrarily combined without contradiction. The combined technical solution is also within the scope of the present application.
[0046] Based on the method in the above embodiment, an embodiment of the present application provides a digital delay phase-locked loop, which implements lock detection based on the method in the above embodiment.
[0047] Based on the method in the above embodiment, an embodiment of the present application provides a master-slave digital delay phase-locked loop system, including: a master delay phase-locked loop, which adopts the all-digital delay phase-locked loop as described above; at least one slave delay phase-locked loop, whose digitally controlled delay line is configured by the first control code of the master delay phase-locked loop.
[0048] Based on the method in the above embodiment, an embodiment of the present application provides an integrated circuit chip, which integrates the above-mentioned digital delay phase-locked loop or the above-mentioned master-slave digital delay phase-locked loop system.
[0049] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.
Claims
1. A method for enhancing the accuracy of a lock detection circuit of a digital DLL, characterized in that: The method comprises: multiplexing delay cells in a digitally controlled delay line in a lock detection circuit; Determining a second control code for the lock detection circuit based on a first control code for the digitally controlled delay line, wherein the first control code is used to represent the number of delay units enabled in the digitally controlled delay line, and the second control code is used to represent the number of delay units enabled in the lock detection circuit; and the second control code is the product of the first control code and a preset coefficient; The number of delay units in the lock detection circuit is determined based on the second control code.
2. The method according to claim 1, characterized in that The value range of the preset coefficient is 1 / 2 n , where n is a positive integer.
3. The method according to claim 2, characterized in that The determining of the second control code of the lock detection circuit based on the first control code of the digitally controlled delay line is specifically: The first control code is shifted right by n bits, or the highest mn bits of the binary representation of the first control code are truncated, where m is the bit width of the first control code, m>n, and both m and n are positive integers.
4. The method according to claim 1, wherein The lock detection circuit includes a smaller number of delay unit stages than the digitally controlled delay line.
5. The method according to claim 1, wherein The delay unit is a buffer or a lattice delay unit.
6. The method according to claim 1, characterized in that The method further comprises: Compare the phase difference between the reference clock and the feedback clock; When the absolute value of the phase difference does not exceed the delay time, it is determined that the delay locked loop is in a locked state.
7. The method according to claim 6, characterized in that The step of determining whether the delay locked loop is in a locked state further includes: The phase difference does not exceed the delay time Td in N consecutive clock cycles.
8. A digital delay-locked loop, characterized in that: Lock detection is achieved based on the method according to any one of claims 1 to 7.
9. A master-slave digital delay-locked loop system, characterized in that: include: A main delay-locked loop, comprising a fully digital delay-locked loop as claimed in claim 8; At least one slave delay locked loop has a digitally controlled delay line configured by the first control code of the master delay locked loop.
10. An integrated circuit chip, characterized in that: The digital delay locked loop according to claim 8 or the master-slave digital delay locked loop system according to claim 9 is integrated.