Indirect measurement clock compensation device suitable for distributed data acquisition system

Abstract

The invention discloses an indirect measurement clock compensation device suitable for a distributed data acquisition system, which comprises the following steps that: firstly, each sub-node data acquisition system transmits a waveform signal acquired by the sub-node data acquisition system to a main node data processing system through an optical fiber link; and then high-precision measurement of the phase difference of the sampling clocks among the nodes is realized through a phase difference indirect measurement algorithm, and high-precision clock synchronization among the nodes is realized by means of a synchronous dynamic phase compensation algorithm.

Description

Technical Field

[0001] The present invention belongs to the technical field of distributed data acquisition systems, and more particularly, relates to an indirect measurement clock compensation device suitable for distributed data acquisition systems. Background Art

[0002] In modern industry and scientific research, the demand for high-precision, large-scale data acquisition continues to grow. Traditional centralized data acquisition systems have a limited number of sampling channels. Therefore, as the number of sampled signals increases, multiple data acquisition systems must operate simultaneously, reducing the real-time performance and flexibility of signal acquisition. Distributed data acquisition systems, with their highly flexible architecture and efficient resource allocation mechanisms, have become a key solution to meeting this demand.

[0003] For distributed data acquisition systems, achieving sampling clock synchronization across all nodes is crucial. During this process, achieving phase synchronization is particularly challenging. During the initial stages of a distributed data acquisition system, if synchronization of the sampling clocks is difficult, algorithms can be used to accurately measure the phase difference between the sampling clocks of the sub-node systems. Effective phase compensation algorithms can then be used to minimize this phase difference. This problem has become a research focus.

[0004] The traditional direct phase difference measurement algorithm has the following disadvantages:

[0005] 1. If the sampling clock phase difference is measured directly, when the sampling clock frequency is F, the Nyquist sampling theorem shows that a sampling rate of 2F is required to acquire the signal without distortion. Therefore, this method is not suitable for scenarios with limited ADC sampling rates.

[0006] 2. Direct measurement methods often require instruments such as oscilloscopes, which take hundreds of microseconds for a single measurement and cannot capture rapidly changing phases. Furthermore, due to the limited accuracy of oscilloscope math measurement functions, they are not suitable for high-precision phase difference measurements.

[0007] 3. Direct measurement methods require synchronous sampling of multiple high-speed ADCs, which introduces additional errors due to clock jitter and skew. Furthermore, data processing relies on high-speed DSPs or FPGAs, limiting real-time performance.

[0008] In summary, the direct phase difference measurement algorithm is difficult to apply to high-precision phase difference measurement scenarios, and it is also difficult to meet the application scenarios with low ADC sampling rate. Summary of the Invention

[0009] The purpose of the present invention is to overcome the shortcomings of the prior art and provide an indirect measurement clock compensation device suitable for a distributed data acquisition system, which ensures the synchronization accuracy of the sampling clocks of each sub-node data acquisition system by indirectly measuring the high-precision phase difference.

[0010] To achieve the above-mentioned object of the invention, the present invention provides an indirect measurement clock compensation device suitable for a distributed data acquisition system, characterized in that it comprises: a signal source, a power divider and a distributed data acquisition system;

[0011] The signal source generates an analog input signal, and converts it into n-way input signals through a 1:n power splitter and inputs them into the acquisition module of each sub-node data acquisition system;

[0012] The distributed acquisition system further comprises a master node data processing system and n sub-node data acquisition systems;

[0013] In the master node data processing system, a high-precision clock source is used to generate an analog clock signal. This analog clock signal is then converted into a digital optical signal by an electro-optical modulator. This optical signal is then converted into n optical signals by a 1:n optical splitter and input to each sub-node data acquisition system.

[0014] In each sub-node data acquisition system, the optoelectronic modulator converts the optical signal into an electrical signal, which is then fed into the clock module as an external reference clock source.

[0015] Each clock module generates a corresponding sampling clock signal based on the clock signal input from the external reference clock source, and then controls the sampling module to collect the input signal under the sampling clock signal to obtain n sampling signals, which are recorded as x1, x2, ..., x i ,…,x n , x i represents the sampling signal of the acquisition module in the data acquisition system of the i-th child node;

[0016] The n sampling signals are transmitted to the phase difference measurement module of the master node data processing system through the optical fiber transmission link. Then, the first sampling signal x1 is used as the reference signal to calculate the phase difference between x1 and the other n-1 sampling signals respectively.

[0017] The master node data processing system then transmits the measured phase difference back to the phase adjustment module of each sub-node data acquisition system. The phase adjustment module then adjusts the delay parameter according to the phase difference value, thereby delaying the input clock of the sub-node data acquisition system and outputting a synchronized clock signal.

[0018] The object of the invention of the present invention is achieved like this:

[0019] The present invention provides an indirect measurement clock compensation device suitable for a distributed data acquisition system. First, each sub-node data acquisition system transmits the waveform signal it has collected to the main node data processing system through an optical fiber link. Then, a phase difference indirect measurement algorithm is used to achieve high-precision measurement of the sampling clock phase difference between each node, and a synchronous dynamic phase compensation algorithm is used to achieve high-precision clock synchronization between each node.

[0020] At the same time, the indirect measurement clock compensation device applicable to a distributed data acquisition system of the present invention also has the following beneficial effects:

[0021] (1) The present invention abandons the traditional hardware manual phase adjustment method and adopts an indirect measurement method, that is, instead of directly measuring the sampling clock, the phase difference of the data collected under the sampling clock is measured. The measured phase difference is sent to the dynamic phase compensation module, and the phase adjustment is performed according to the two key parameters of the system minimum measurement phase difference and the phase compensation step value, so that the phase difference of each sampling clock is maintained at a certain accuracy value;

[0022] (2) The present invention cleverly uses an indirect measurement method to measure the phase difference with high precision, and uses a dynamic phase compensation algorithm to perform phase compensation, so that the phase difference accuracy is maintained near a certain value, greatly improving the sampling clock synchronization performance;

[0023] (3) The present invention adopts an indirect measurement method, which is different from the direct measurement method. When the sampling clock frequency is F, it can be seen from the Nyquist sampling theorem that a sampling rate of 2F is required to collect the signal without distortion. Therefore, this method is more suitable for scenarios with limited ADC sampling rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a diagram of an indirect measurement clock compensation device suitable for a distributed data acquisition system according to the present invention;

[0025] Figure 2 Schematic diagram of the phase difference measurement module structure;

[0026] Figure 3 Schematic diagram of the phase adjustment module structure;

[0027] Figure 4 This is a simulation test diagram of the phase difference measurement algorithm. DETAILED DESCRIPTION

[0028] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, such descriptions will be omitted here.

[0029] Example

[0030] Figure 1 This is a diagram of an indirect measurement clock compensation device suitable for a distributed data acquisition system according to the present invention.

[0031] In this embodiment, if Figure 1 As shown, the present invention is an indirect measurement clock compensation device suitable for a distributed data acquisition system, comprising: a signal source, a power divider and a distributed acquisition system;

[0032] like Figure 1 As shown, the signal source generates an analog input signal, which is converted into 4-way input signals through a 1:4 power splitter and input to the acquisition module of each sub-node data acquisition system;

[0033] The distributed data collection system includes a master node data processing system and four sub-node data collection systems;

[0034] The master node data processing system includes a high-precision clock source that provides clock signals to the sub-node data acquisition system, an electro-optical conversion circuit consisting of an electro-optical modulator and an optical splitter, and a phase difference measurement module for measuring phase difference.

[0035] like Figure 2 As shown, the phase difference measurement module includes a cos-sin module, a multiplication module, an addition and subtraction module, and an angle calculation module that are cascaded in sequence, and is used to measure the phase difference between two signals.

[0036] In this embodiment, the structure of each sub-node data acquisition system is the same, including: an optoelectronic modulator, a clock module, an acquisition module and a phase adjustment module;

[0037] Among them, Figure 3 As shown, the phase adjustment module further includes: a control module, a delay line control unit and an IDELAYE3 cascade unit.

[0038] In the master node data processing system, a high-precision clock source is used to generate an analog clock signal. This signal is then converted into a digital optical signal via an electro-optical modulator. This optical signal is then converted into four optical signals via a 1:4 optical splitter and fed into the data acquisition system of each sub-node.

[0039] In each sub-node data acquisition system, the optoelectronic modulator converts the optical signal into an electrical signal, which is then fed into the clock module as an external reference clock source.

[0040] Each clock module generates a corresponding sampling clock signal based on the clock signal input from the external reference clock source, and then controls the sampling module to collect the input signal under the sampling clock signal to obtain n sampling signals, which are recorded as x1, x2, x3, and x4;

[0041] The four sampling signals are transmitted to the phase difference measurement module of the master node data processing system through an optical fiber transmission link. Then, the first sampling signal x1 is used as the reference signal to calculate the phase difference between x1 and the other three sampling signals.

[0042] In this embodiment, the sampling signal x1 and the sampling signal x2 are taken as examples for description, as follows:

[0043] Assume that the signal collected by the sub-node data acquisition system is a cosine signal, where the reference signal x1(t) = cos(2πf0t+θ1). Compared with the signals collected by the other sub-node data acquisition systems, the frequency is consistent with that of the cosine signal, and only the phase is different. Take x2(t) = cos(2πf0t+θ2) to enter the phase difference measurement module for phase difference measurement;

[0044] When x1 and x2 enter the cos-sin module for Hilbert filter transformation, orthogonal signals y1 and y2 are generated, and y1(t) = sin(2πf0t+θ1) and y2(t) = sin(2πf0t+θ2) are recorded.

[0045] The cos-sin module inputs x1, x2, y1, and y2 together into the multiplication module to calculate x1x2, x1y2, y1x2, and y1y2 respectively;

[0046] z1(t)=x1(t)*x2(t)=cos(2πf0t+θ1)*cos(2πf0t+θ2)

[0047] z2(t)=y1(t)*y2(t)=sin(2πf0t+θ1)*sin(2πf0t+θ2)

[0048] z3(t)=x1(t)*y2(t)=cos(2πf0t+θ1)*sin(2πf0t+θ2)

[0049] z4(t)=y1(t)*x2(t)=sin(2πf0t+θ1)*cos(2πf0t+θ2)

[0050] Then calculate x1x in the addition and subtraction module i +y1y i ,x1y i -y1x i ,Right now:

[0051] m1(t)=z4(t)-z3(t)

[0052] =sin(2πf0t+θ1)*cos(2πf0t+θ2)-cos(2πf0t+θ1)*sin(2πf0t+θ2)

[0053] m1(t)=z2(t)+z1(t)

[0054] =sin(2πf0t+θ1)*sin(2πf0t+θ2)+cos(2πf0t+θ1)*cos(2πf0t+θ2)

[0055] Finally, the phase difference Δθ2 is calculated in the angle calculation module.

[0056]

[0057] Similarly, the phase differences Δθ3 and Δθ4 between x1, x3 and x1, x4 can be calculated respectively;

[0058] The master node data processing system then transmits the measured phase difference back to the phase adjustment module of each sub-node data acquisition system. The control module in the phase adjustment module uses the PID control algorithm to perform proportional and differential adjustment on the phase difference value, thereby dynamically converting the phase difference value into a delay line control signal. The specific adjustment formula is:

[0059]

[0060] Where τ[i] represents the phase difference Δθ i The delay line control signal after conversion, T i K is the reference clock input to the data acquisition system of the i-th child node, p is the proportional gain, K d is the differential gain, K p =0.5, K d =0.02;

[0061] Next, the delay line control unit performs signal delay module tap processing on the delay line control signal to obtain the signal delay module tap value:

[0062]

[0063] Among them, f ref represents the reference clock frequency, τ step Single tap delay for signal delay module;

[0064] Finally, the signal delay module cascade unit adjusts the delay of the input clock of the sub-node data acquisition system according to the signal delay module tap value of each delay line control signal, thereby outputting a synchronized clock signal.

[0065] In this embodiment, a 5-level IDELAYE3 cascade structure is adopted, and the cascade module is dynamically instantiated using the Generate Statement in the Hardware Description Language (HDL). The number of cascades is defined by the parameter N, and the IDATAIN and DATAOUT ports of each module are automatically connected. By modifying the phase control word, the phase difference between the two signals is gradually reduced. The measurement is continued. When the phase difference between the two signals is reduced to 1.9ps, the corresponding radian value is calculated to be 0.000122. Figure 4 It can be seen that the simulation test result is 0.0001220703125, and the measurement accuracy is 0.05763%. Therefore, the minimum phase difference that can be measured by this phase difference indirect measurement algorithm meets the minimum resolution of the system.

[0066] Although the above describes the illustrative specific embodiments of the present invention to facilitate understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concepts of the present invention are protected.

Claims

1. An indirect measurement clock compensation device suitable for a distributed data acquisition system, characterized in that: include: Signal source, power splitter and distributed data acquisition system; The signal source generates an analog input signal, and converts it into n-way input signals through a 1:n power splitter and inputs them into the acquisition module of each sub-node data acquisition system; The distributed data acquisition system further comprises a master node data processing system and n sub-node data acquisition systems; In the master node data processing system, a high-precision clock source is used to generate an analog clock signal. This analog clock signal is then converted into a digital optical signal by an electro-optical modulator. This optical signal is then converted into n optical signals by a 1:n optical splitter and input to each sub-node data acquisition system. In each sub-node data acquisition system, the optoelectronic modulator converts the optical signal into an electrical signal, which is then fed into the clock module as an external reference clock source. Each clock module generates a corresponding sampling clock signal according to the clock signal input from the external reference clock source, and then controls the sampling module to collect the input signal under the sampling clock signal to obtain n sampling signals, which are recorded as x1, x2, ..., x i ,…,x n , x i represents the sampling signal of the acquisition module in the data acquisition system of the i-th child node; The n sampling signals are transmitted to the phase difference measurement module of the master node data processing system through the optical fiber transmission link. Then, the first sampling signal x1 is used as the reference signal to calculate the phase difference between x1 and the other n-1 sampling signals respectively. The master node data processing system then transmits the measured phase difference back to the phase adjustment module of each sub-node data acquisition system. The phase adjustment module then adjusts the delay parameter according to the phase difference value, thereby delaying the input clock of the sub-node data acquisition system and outputting a synchronized clock signal.

2. The indirect measurement clock compensation device suitable for a distributed data acquisition system according to claim 1, characterized in that: The master node data processing system includes a high-precision clock source that provides a clock signal to the sub-node data acquisition system, an electro-optical conversion circuit composed of an electro-optical modulator and an optical splitter; and a phase difference measurement module for measuring the phase difference. The phase difference measurement module further comprises a cos-sin module, a multiplication module, an addition and subtraction module and an angle calculation module which are cascaded in sequence, and is used to measure the phase difference between two signals.

3. The indirect measurement clock compensation device suitable for a distributed data acquisition system according to claim 1, characterized in that: The n sub-node data acquisition systems have the same structure, including: an optoelectronic modulator, a clock module, an acquisition module and a phase adjustment module; The phase adjustment module further comprises: a control module, a delay line control unit and an IDELAYE3 cascade unit.

4. The indirect measurement clock compensation device suitable for a distributed data acquisition system according to claim 1, characterized in that: The method for measuring the phase difference by the phase difference measurement module is: (4.1), the sampling signal x1 and the sampling signal x i Enter the cos-sin module to perform Hilbert filter transform and generate orthogonal signals y1,y i ; where i = 2, 3, ..., n; (4.2), the cos-sin module converts the input signals x1, x i With the orthogonal signals y1, y i Input them together into the multiplication module and calculate x1x respectively i ,x1y i ,y1x i ,y1y i ; (4.3) Calculate x1x in the addition and subtraction module i +y1y i ,x1y i -y1x i ; (4.4) Calculate in the angle calculation module Thus, the phase difference Δθ is calculated i .

5. The indirect measurement clock compensation device suitable for a distributed data acquisition system according to claim 1, characterized in that: The method for the phase adjustment module to adjust the delay parameter according to the phase difference is: (5.1) Dynamically converting the phase difference value into a delay line control signal through the control module; The PID control algorithm is used to adjust the phase difference proportionally and differentially. The adjustment formula is: Where τ[i] represents the phase difference Δθ i The delay line control signal after conversion, T i K is the reference clock input to the data acquisition system of the i-th child node, p is the proportional gain, K d is the differential gain; (5.2) The delay line control unit performs IDELAYE3 tap processing on the delay line control signal to obtain the IDELAYE3 tap value: Among them, f ref represents the reference clock frequency, τ step It is IDELAYE3 single tap delay; (5.3) The IDELAYE3 cascade unit adjusts the delay of the input clock of the sub-node data acquisition system according to the IDELAYE3 tap value of each delay line control signal, thereby outputting a synchronized clock signal.

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