Circuit board

Abstract

The invention discloses a circuit board, and relates to the technical field of circuit boards, the circuit board comprises a substrate, the substrate is provided with a plurality of wiring layers, a high-speed signal layer and a grounding layer are arranged in the plurality of wiring layers, and at least one intermediate layer is arranged between the high-speed signal layer and the grounding layer; wherein the high-speed signal layer is provided with a high-speed signal access area for accessing high-speed signals; a grounding region is arranged at a position, corresponding to the high-speed signal access region, on the grounding layer, and the projection of the high-speed signal access region on the grounding layer is in the grounding region or is consistent with the grounding region in size; a wiring forbidding area is arranged at the position, corresponding to the high-speed signal access area, of the middle layer, and the projection of the high-speed signal access area on the middle layer is in the wiring forbidding area or is consistent with the wiring forbidding area in size. The invention aims to reduce the influence caused by the change of impedance on a signal transmission path and ensure the continuity and integrity of signals, thereby improving the quality and stability of the signals.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and in particular to a circuit board. Background Art

[0002] With the rapid development and application of integrated circuits, the frequency and speed of electronic signal transmission have increased significantly. To meet this demand, printed circuit board (PCB) designs must provide higher-performance transmission lines to ensure that signals at the output end are fully and accurately transmitted to the input of the receiving device. However, in reality, signal integrity is often difficult to ensure during signal transmission due to various factors. This is particularly evident at high transmission rates, which degrades signal quality. A key factor affecting signal integrity is signal reflection. When a signal propagates along a transmission line and encounters a change in line impedance, signal reflection occurs. This occurs because discontinuities cause some signal energy to be reflected back, rather than being fully transmitted to the input of the receiving device. This phenomenon typically occurs where the signal path width changes, as this width change causes a sudden change in impedance, leading to signal discontinuities and reflections. Summary of the Invention

[0003] The main purpose of the present invention is to provide a circuit board, which aims to reduce the impact caused by changes in impedance on the signal transmission path, ensure the continuity and integrity of the signal, and thus improve the signal quality and stability.

[0004] To achieve the above object, the present invention provides a circuit board, comprising:

[0005] A substrate having a plurality of wiring layers, wherein the plurality of wiring layers include a high-speed signal layer and a ground layer, and at least one intermediate layer is provided between the high-speed signal layer and the ground layer;

[0006] Wherein, a high-speed signal access area for accessing high-speed signals is provided on the high-speed signal layer;

[0007] A grounding area is provided on the grounding layer at a position corresponding to the high-speed signal access area, and a projection of the high-speed signal access area on the grounding layer is within the grounding area or has the same size as the grounding area;

[0008] A keep-out area is provided on the middle layer at a position corresponding to the high-speed signal access area. The projection of the high-speed signal access area on the middle layer is within the keep-out area or has the same size as the keep-out area.

[0009] In one embodiment, at least two of the plurality of keep-out regions have the same size; or, any two of the plurality of keep-out regions have different sizes.

[0010] In one embodiment, the high-speed signal access area includes a pad.

[0011] In one embodiment, the width of the prohibited wiring area is equal to the sum of 2 times the spacing and the width of the high-speed signal access area, wherein the spacing is greater than or equal to the width of the high-speed signal, and the spacing is less than 1 / 2 times the minimum distance between two adjacent pads.

[0012] In one embodiment, an isolation area is provided on the high-speed signal layer, surrounding the high-speed signal access area.

[0013] In one embodiment, a ground layer is provided in the isolation region.

[0014] In one embodiment, the distance between the outer boundary of the isolation region and the pad closest to the isolation region is greater than or equal to 20 times the thickness of the dielectric between the high-speed signal layer and the intermediate layer where the keep-out region is located.

[0015] In one embodiment, a grounding region is provided on the middle layer, and the grounding region on the middle layer at least includes a projection of the isolation region on the middle layer and a space between the keep-out region.

[0016] In one embodiment, a via hole connected to the high-speed signal access area is further provided on the high-speed signal layer; wherein the via hole includes a blind hole or a through hole processed by a drilling process.

[0017] In one embodiment, a plurality of device signal installation areas are further provided on the high-speed signal layer. The device signal installation areas are used to access devices. An isolation area is provided on the high-speed signal layer surrounding the high-speed signal access area and the device signal installation area.

[0018] In practical applications, by setting a prohibited wiring area at the position corresponding to the high-speed signal access area on the middle layer between the high-speed signal layer and the ground layer, increasing the dielectric thickness at the impedance mutation point (such as the high-speed signal pad), increasing the characteristic impedance, and reducing the amplitude of the impedance mutation, better impedance continuity and signal integrity are ensured, thereby improving signal quality and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0020] Figure 1is a cross-sectional view of an embodiment of a circuit board of the present invention;

[0021] Figure 2 A schematic diagram of the distribution of a high-speed single-ended signal according to an embodiment;

[0022] Figure 3 A schematic diagram of the distribution of a high-speed differential signal according to an embodiment;

[0023] Figure 4 This is a schematic diagram of the top layer structure of a circuit board according to an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of the L2 layer of an embodiment of a circuit board of the present invention;

[0025] Figure 6 This is a schematic diagram of the L3 layer of an embodiment of a circuit board of the present invention;

[0026] Figure 7 This is a schematic diagram of the top layer and L2 layer stacking of an embodiment of a circuit board of the present invention;

[0027] Figure 8 This is a schematic diagram of the top layer, L2 layer, and L3 layer stacking of an embodiment of a circuit board of the present invention;

[0028] Figure 9 This is a layer cross-section of another embodiment of the circuit board of the present invention.

[0029] Description of Figure Numbers:

[0030] 100, high-speed signal access area; 200, prohibited wiring area; 300, isolation area; 400, via.

[0031] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0033] With the rapid development and application of integrated circuits, the transmission frequency and speed of electronic signals have increased significantly. To meet this demand, printed circuit board (PCB) designs must provide higher-performance transmission lines to ensure that signals at the output end are fully and accurately transmitted to the input of the receiving device. However, in reality, signal integrity is often difficult to ensure during signal transmission due to various factors, such as signal reflection, oscillation, ground bounce, crosstalk, and timing. This is particularly evident at high transmission rates, which degrades signal quality. A key factor affecting signal integrity is signal reflection. When a signal propagates along a transmission line and encounters a change in line impedance, signal reflection occurs. This occurs because discontinuities cause some signal energy to be reflected back, rather than being fully transmitted to the input of the receiving device. This phenomenon typically occurs where the signal path width changes, as this width change causes a sudden change in impedance, leading to signal discontinuities and reflections.

[0034] Common high-speed signals are of two types: differential and single-ended. Figure 3 and Figure 4 , Figure 3 This is a wiring diagram for the signal access area of high-speed (differential) signals. High-speed signals include HDMI, LVDS (Low-Voltage Differential Signaling), SATA, PCIE, USB, MIPI and other signals. Figure 4 This is a schematic diagram of the signal access area wiring for high-speed (single-ended) signals. High-speed single-ended signals include LVDS, DDR, clock signals, and other signals. A represents the pad corresponding to the high-speed signal, B represents the GND signal pad, and C represents the power and other signal pads. W1 is the width of the high-speed single-ended signal; W2 is the via pad diameter; and W3 is the width of the pad corresponding to the high-speed signal.

[0035] It is understandable that the factors that affect the characteristic impedance of high-speed signals mainly include dielectric thickness, dielectric constant, copper thickness, line width, etc. Among them, the approximate formula for the characteristic impedance of a microstrip line is:

[0036]

[0037] Approximate formula for stripline characteristic components:

[0038]

[0039] ε ris the relative dielectric constant of the dielectric, h is the total thickness of the upper and lower dielectric layers (dielectric thickness), w is the line width, and t is the copper line thickness. Generally speaking, characteristic impedance is proportional to dielectric thickness and inversely proportional to dielectric constant, copper line thickness, and line width. When high-speed signals exit the pad, changes in width (generally increasing) can cause impedance abrupt changes (generally decreasing), leading to signal discontinuity and prone to signal reflections, compromising signal integrity.

[0040] For this purpose, refer to Figure 1 The present invention provides a circuit board, characterized in that the circuit board comprises:

[0041] A substrate having a plurality of wiring layers, wherein the plurality of wiring layers include a high-speed signal layer and a ground layer, and at least one intermediate layer is provided between the high-speed signal layer and the ground layer;

[0042] Wherein, a high-speed signal access area 100 for accessing high-speed signals is provided on the high-speed signal layer;

[0043] A grounding area is provided on the grounding layer at a position corresponding to the high-speed signal access area 100 , and a projection of the high-speed signal access area 100 on the grounding layer is within the grounding area or has the same size as the grounding area;

[0044] On the middle layer, a keep-out area 200 is provided at a position corresponding to the high-speed signal access area 100 , and the projection of the high-speed signal access area 100 on the middle layer is within the keep-out area 200 or has the same size as the keep-out area 200 .

[0045] In this embodiment, the substrate is the basic structure of the circuit board, providing physical support and electrical connection. The substrate can be implemented by glass fiber board, metal substrate, ceramic substrate, etc.

[0046] Optionally, the high-speed signal layer can be located on the top, bottom, or middle layer of the substrate, for arranging high-speed signal transmission lines. A high-speed signal access area 100 is provided on the high-speed signal layer. This area serves as the interface point for high-speed signals to enter or exit the PCB (printed circuit board), ensuring that signals can be accurately transmitted from the source to the target receiving end, i.e., the input end of the receiving device. The high-speed signal access area 100 includes solder pads. A solder pad is the physical connection point between the high-speed signal and the circuit board, ensuring that electrical signals can be transmitted from the source to other parts of the circuit through the soldering process. The solder pad design must minimize contact resistance to avoid signal loss or distortion due to poor contact. During the soldering process, the solder pad must withstand high temperatures, so the material selection and design must ensure sufficient thermal stability to prevent problems caused by temperature fluctuations. If the solder pad size exceeds the keep-out area 200, it may affect the surrounding dielectric environment, thereby changing the characteristic impedance of this area, leading to signal reflections and other signal integrity issues. Therefore, the projection of the solder pad on the middle layer should be within the keep-out area 200 or be consistent with the size of the keep-out area 200. In addition, there is enough “blank” area around the pad, that is, when the projection of the pad on the middle layer falls within the keep-out area 200 , interference from other signal lines can be effectively reduced, thereby ensuring signal transmission quality.

[0047] Understandably, pads are typically designed to be much wider than typical signal lines to provide ample soldering area and mechanical stability. Due to the significant increase in line width in the pad area, the characteristic impedance of this area decreases accordingly, as can be seen from the approximate formula for characteristic impedance. This sudden impedance change can cause some signal energy to be reflected back to the source rather than fully transmitted to the receiver, resulting in signal reflection issues and, in turn, affecting signal integrity.

[0048] In this embodiment, the grounding layer is used to provide a stable reference ground plane. On the grounding layer, a grounding area is provided at a position corresponding to the high-speed signal access area 100. The grounding area is provided to provide a low-impedance return path for the high-speed signal, thereby reducing signal reflection and crosstalk. The grounding area can be realized by copper cladding, a grid-like wire network, etc. The middle layer is located between the high-speed signal layer and the grounding layer, and plays the role of isolation and shielding. On the middle layer, a prohibited wiring area 200 is provided at a position corresponding to the high-speed signal access area 100. That is, no other signal lines or components are allowed to be arranged in this area. By setting a prohibited wiring area 200 in the adjacent middle layer of the high-speed signal access area 100, the actual reference plane of the high-speed signal access area 100 can be changed, thereby increasing the dielectric thickness between the high-speed signal access area 100 and the reference layer.

[0049] Take the 6-layer PCB board of the crystal oscillator signal clk as an example to illustrate, refer to Figure 1, Top Silkscreen and BotSilkscreen refer to the silkscreen layer (Silkscreen Layer), which are used to print identification information on the surface of the PCB. This information helps in assembling, debugging and maintaining the circuit board. M is the insulating layer, the top layer is the top layer, the bot layer is the bottom layer, and L2, L3, L4, and L5 are the middle layers. In this embodiment, the top layer is the high-speed signal layer, and the bot layer is the ground layer. The high-speed signal access area 100 is designed on the top layer, and the high-speed signal wiring part refers to the L2 layer. The high-speed signal access area 100 refers to the L3 layer, and the L2 layer is designed with a prohibited wiring area 200 corresponding to the high-speed signal access area 100. In this way, the high-speed signal wiring part should originally refer to the L2 layer. By setting the prohibited wiring area 200 on the L2 layer, the high-speed signal wiring part refers to the L3 layer. At this time, the dielectric thickness is the sum of h1 and h2. h1 is the thickness of the dielectric layer between the top layer and the L2 layer; h2 is the thickness of the dielectric layer between the L2 layer and the L3 layer. Reference Figure 7 , Figure 7 Schematic diagram of the superposition of the top layer and L2 layer.

[0050] It should be noted that if the above-mentioned setting still does not increase the dielectric thickness between the high-speed signal layer and the reference layer of the high-speed signal access area 100, and the change in characteristic impedance caused by the enlargement of the pad, the dielectric thickness between the high-speed signal access area 100 and the reference layer of the high-speed signal can be further increased. Figure 9 At this time, by setting the keep-out area 200 on both L2 and L3 layers, the high-speed signal wiring part is referenced to the L4 layer. At this time, the dielectric thickness is the sum of h1, h2 and h3. h1 is the dielectric layer thickness between the top layer and L2 layer; h2 is the dielectric layer thickness between L2 layer and L3 layer; h3 is the dielectric layer thickness between L3 layer and L4 layer. Figure 8 , Figure 8 This is a schematic diagram of the top layer, L2, and L3 layers stacked together. If this is insufficient to offset the impedance jump, the design can be extended to the layers below. R&D personnel will determine the specific design based on actual simulation results to achieve more stable overall impedance.

[0051] In practical applications, a prohibited wiring area 200 is set on the middle layer between the high-speed signal layer and the ground layer at a position corresponding to the high-speed signal access area 100, thereby increasing the dielectric thickness at the impedance mutation point (such as the high-speed signal pad), increasing the characteristic impedance, and reducing the amplitude of the impedance mutation, thereby ensuring better impedance continuity and signal integrity, and improving signal quality and stability.

[0052] In one embodiment, at least two of the multiple no-wiring areas 200 have the same size; or, any two of the multiple no-wiring areas 200 have different sizes. No-wiring areas 200 of the same size can simplify the design process and reduce design complexity. During the manufacturing process, the same size of the no-wiring areas 200 helps to reduce the complexity of processes such as drilling and etching, improve production efficiency and reduce costs. In addition, the same size of the no-wiring areas 200 helps to maintain the characteristic impedance of the signal path and reduce impedance mutations caused by differences between layers. In this embodiment, reference Figure 9 Keepout areas 200 on L2 and L3 are of the same size. If the sizes of keepout areas 200 vary, for example, different keepout areas 200 can be optimized based on the specific functional requirements of each layer. For example, a smaller area can be selected for L3 to save space or meet other layout requirements, avoiding excessive PCB space occupation, thereby improving routing density and overall design efficiency.

[0053] Optionally, the width of the prohibited wiring area 200 is equal to the sum of 2 times the spacing and the width of the high-speed signal access area 100, wherein the spacing is greater than or equal to the width of the high-speed signal, and the spacing is less than 1 / 2 times the minimum distance between two adjacent pads.

[0054] In this embodiment, if Figure 1 As shown, the width of the forbidden wiring area 200 satisfies the following formula: w=w3+2*d1, where w1≤d1<gap / 2, where w3 is the width of the high-speed signal pad, that is, the width of the high-speed signal access area 100, and d1 is the spacing. Figure 2 As shown, a is the high-speed signal, A is the pad corresponding to the high-speed signal, b is the GND signal, B is the pad corresponding to the GND signal, c is the power supply and other signals, C is the pad corresponding to the power supply and other signals, and gap is the minimum distance between two adjacent pads.

[0055] Keepout areas 200 of the same size help maintain the characteristic impedance of the signal path and reduce impedance mutations caused by layer differences. In addition, smaller keepout areas 200 are selected on certain layers to save space or meet other layout requirements, avoiding excessive PCB space occupation, thereby improving wiring density and overall design efficiency.

[0056] Crosstalk is particularly critical for high-speed signals. Crosstalk refers to the interference between two or more signal paths, typically caused by electromagnetic coupling between adjacent signal lines. Crosstalk can cause high-speed signal distortion and reduce the signal-to-noise ratio.

[0057] To this end, in one embodiment, reference Figure 4 On the high-speed signal layer, an isolation area 300 is provided surrounding the high-speed signal access area 100 .

[0058] In this embodiment, it is a common practice to set up an isolation area 300 around the high-speed signal access area 100, which is intended to reduce problems such as electromagnetic interference (EMI), crosstalk and signal reflection, thereby improving signal integrity and reliability. The isolation area 300 can be implemented in a variety of ways, including but not limited to copper-clad landing areas, metal rings, etc. Optionally, a copper-clad landing area is set around the pad corresponding to the high-speed signal, that is, a continuous layer of copper foil is covered in the area to form an effective electromagnetic shielding, thereby reducing the interference of external noise on the high-speed signal. Optionally, a metal ring is set around the high-speed signal access area 100, which is usually an annular structure made of conductive material (such as copper). In addition to the electromagnetic shielding function, the metal ring can also provide additional physical support to enhance the mechanical stability of the pad. Compared with the copper-clad landing area, the metal ring can provide a shielding effect without affecting the layout of the signal line.

[0059] Optionally, a ground layer is provided in the isolation region 300 .

[0060] In this embodiment, the grounding area can be copper-clad. In other words, the grounding area can be copper-clad. Alternatively, a grid-like conductor network can be used instead of a complete copper-clad area. This reduces the amount of copper used and lowers manufacturing costs.

[0061] In one embodiment, the distance between the outer boundary of the isolation region 300 and the pad closest to the isolation region 300 is greater than or equal to 20 times the thickness of the dielectric between the high-speed signal layer and the middle layer where the keep-out region 200 is located.

[0062] In this embodiment, the range of the isolation area 300 on the high-speed signal layer is determined according to the physical size of the device or the distribution of the high-speed signal. The size of the GND copper foil laid on the TOP layer is D. The distance D between the outer boundary of the isolation area 300 and the pad closest to the isolation area 300 needs to be greater than or equal to the dielectric thickness. Figure 4 , D ≥ h1. For example, the top crystal oscillator can be completely surrounded by a ground layer. However, for other high-speed signals such as MIPI, LVDS, and DDR, due to their high number and dense distribution, the same complete GND wrapping as for the crystal oscillator signal may not be achieved in actual designs. This means that the isolation area 300 on the high-speed signal layer may not be completely enclosed.

[0063] In one embodiment, a plurality of device signal installation areas are further provided on the high-speed signal layer. The device signal installation areas are used to access devices. An isolation area 300 is provided on the high-speed signal layer surrounding the high-speed signal access area 100 and the device signal installation area.

[0064] In this embodiment, the device signal installation area refers to an area for installing electronic components (such as integrated circuits, resistors, capacitors, etc.). These areas usually contain multiple pads (Pads), each pad corresponding to a device pin. By soldering the pins of the device to these pads, electrical connection and mechanical fixation are achieved. Suppose in a multi-layer PCB design, there is a device signal installation area for installing a complex microcontroller (MCU). The MCU has the following types of pins: high-speed signal pins, GND signal pins, power signal pins, control signal pins, RST pins, debug interface pins, etc. An isolation area 300 can be set around the pads corresponding to these pins to improve signal isolation.

[0065] By providing the isolation region 300 around the high-speed signal or other signals, the interference between the high-speed signal and the surrounding signals is reduced, thereby improving the signal integrity.

[0066] In another embodiment, a grounding region is provided on the middle layer, and the grounding region on the middle layer at least includes a space between a projection of the isolation region 300 on the middle layer and the keep-out region 200 .

[0067] In this embodiment, the 6-layer PCB design of the crystal oscillator clk signal is used as an example for explanation. Figure 1 and Figure 5 , where the top layer is the high-speed signal layer, L2 is provided with a forbidden wiring area 200, and L3 is the high-speed signal pad reference layer. The L2 layer is the middle layer, such as Figure 5 As shown, Figure 5 FIG2 is a schematic diagram of the layout of the L2 layer. The area other than the forbidden wiring area 200 is copper-clad. In this embodiment, the L3 layer is also provided with a grounding area, such as Figure 6 As shown. On the L2 and L3 layers, laying GND copper foil in the area directly below the crystal oscillator helps provide electromagnetic shielding, reduces external interference on the crystal oscillator, and prevents the electromagnetic field generated by the crystal oscillator from affecting other signals. In addition, the length and width of the GND copper foil laid on the L2 and L3 layers must be at least consistent with the GND copper foil boundary around the crystal oscillator pad on the top layer. This ensures a continuous shielding effect from the top layer to the bottom layer. If space permits, the GND copper foil laid on the L2 and L3 layers can be further expanded to provide a wider shielding effect. Specifically, the range of expansion compared to the crystal oscillator entity is at least D, that is, at least 20 times the dielectric thickness (h1).

[0068] It should be noted that the reference Figure 9If keepout zones 200 are set on both L2 and L3 layers, and both L2 and L3 are intermediate layers, an isolation zone 300 should be provided, with a grounding zone within it. The grounding zone dimensions should remain the same as those for L2. The GND copper foil on L2, L3, and L4 layers can be further extended to provide a wider shielding effect.

[0069] Through the above configuration, grounding areas are provided on the wiring reference layer L2 and the pad reference layer L3, which reduces the mutual influence between high-speed signals and peripheral signals, reduces signal reflection and crosstalk, and improves signal integrity.

[0070] It is understood that when a high-speed signal needs to switch from one layer to another, it must pass through via 400. Via 400 itself has certain parasitic capacitance and inductance characteristics. During the process of entering or leaving via 400, the surrounding environment of the signal path (such as dielectric thickness, distance to adjacent conductors, etc.) will change, causing impedance changes. If via 400 is improperly designed, for example, its impact on the signal path impedance is not fully considered, it may cause severe impedance mismatch, further exacerbating signal reflection and crosstalk.

[0071] To this end, in one embodiment, reference Figure 4 The high-speed signal layer is further provided with a via 400 connected to the high-speed signal access area 100; wherein the via 400 includes a blind hole or a through hole processed by a drilling process. Figure 3 , the via 400 is used to connect the electrical signals between different layers of the PCB to ensure that the signal can be transmitted from one layer to another. Using blind vias to connect the high-speed signal pads on the top layer to the L2 layer can reduce unnecessary inter-layer connections and reduce parasitic capacitance and inductance. The through hole runs through multiple layers of the entire PCB. It is suitable for situations where multi-layer connections are required. In this embodiment, the via 400 corresponding to the high-speed signal on the L2 layer is processed with a blind hole or a through hole plus a back drilling process, which can ensure that the high-speed signal via 400 only has the corresponding pad on the layer where the via 400 is located, eliminating the antenna effect of the pad on the redundant layer. When the antenna effect occurs, the unused portion of the via 400 (such as the residual copper pillar in the through hole) will pick up external electromagnetic interference like an antenna and conduct it into the circuit, resulting in increased noise and signal integrity problems. Therefore, this embodiment can remove unnecessary parts by drilling from the back, thereby reducing the length of the residual copper pillar and reducing parasitic effects. In this way, signal integrity is improved and electromagnetic interference is reduced. When the top layer is a high-speed signal layer, the L2 layer is an intermediate layer, and the L3 layer is a ground layer, the circuit board design process is as follows:

[0072] Determine the PCB stackup and the thickness of each layer based on the preset schematic, PCB size, and signal distribution; determine the high-speed signal to be processed and complete the PCB placement, taking the design of high-speed signal devices on the top layer as an example; determine the position and size of the L2 layer's prohibited wiring area 200 based on the position and size of the high-speed signal pads, with the center of the prohibited wiring area 200 coinciding with the high-speed signal pads, and the width of the prohibited wiring area 200 meeting the following requirements: w=w3+2*d1, w1≤d1<gap / 2. Determine the range of laying GND copper foil on the TOP / L2 / L3 layers based on the physical size of the device or the distribution of high-speed signals, determine the size D≥20*h1, and design the top layer GND isolation area 300. Since this implementation case is explained using the crystal oscillator clk signal as an example, the top crystal oscillator can be completely surrounded by a circle of GND. For other high-speed signals such as MIPI, LVDS, DDR, etc., due to the large number of signals and dense distribution, the device layer GND may not be completely covered, but the L2 and L3 layers must ensure that the GND copper is completely laid. Refer to Figure 4 、 Figure 7 and Figure 8 , d2 is the distance from the high-speed signal via 400 to the outside of the laid GND shape, and d3 is the distance from the high-speed signal pad to the outside of the laid GND shape. Among them, d2 and d3 both need to be greater than 20 times the thickness of the dielectric, that is, MIN(d2, d3) ≥ 20*h1 (h1 is the thickness of the dielectric layer between top and L2). It should be noted that if a prohibited wiring area 200 is further set on the L3 layer and the L4 layer is used as the ground layer, MIN(d2, d3) ≥ 20*(h1+h2). Then lay the GND copper foil of the L2 and L3 layers as required; finally, the simulation confirms the above design scheme ( Figure 1 The solution shown in the figure can offset the characteristic impedance change caused by the enlargement of the pad. If the compensation effect is not ideal, it is necessary to design the same forbidden wiring area 200 of the L2 layer on the L3 layer below the high-speed pad, and the position and size are consistent with the forbidden wiring area 200 of the L2 layer (i.e. Figure 9 The two schemes can also be simulated and compared to determine how they offset impedance jumps, allowing the appropriate solution to be selected to complete the PCB design. Furthermore, high-speed signal vias 400 can be blind vias or back-drilled through-holes, while other signals can be conventional through-holes, thus completing the entire PCB design.

[0073] This solution reduces the impact of impedance mutations caused by inconsistencies between pad size and wiring width by designing a prohibited wiring area 200 in the adjacent layer of the high-speed signal corresponding pad, changes the reference layer of the high-speed signal corresponding pad, and increases the dielectric thickness between the high-speed signal corresponding pad and the reference layer (ground layer), thereby ensuring signal integrity. In addition, grounding areas are set around the device periphery, wiring reference layer (middle layer), and pad reference layer (ground layer) of the high-speed signal layer to reduce the mutual influence between high-speed signals and surrounding signals, reduce signal reflection and crosstalk, and further improve signal integrity. At the same time, the high-speed signal via 400 adopts a blind hole or back-drilling design to reduce electromagnetic interference, improve the electromagnetic compatibility of the circuit board, and reduce the loss and crosstalk of high-speed signals, thereby improving signal transmission quality and stability.

[0074] The above descriptions are merely optional embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's description and drawings, or direct / indirect applications in other related technical fields within the scope of the present invention are included in the patent protection scope of the present invention.

Claims

1. A circuit board, characterized in that: The circuit board comprises: A substrate having a plurality of wiring layers, wherein the plurality of wiring layers include a high-speed signal layer and a ground layer, and at least one intermediate layer is provided between the high-speed signal layer and the ground layer; Wherein, a high-speed signal access area for accessing high-speed signals is provided on the high-speed signal layer; A grounding area is provided on the grounding layer at a position corresponding to the high-speed signal access area, and a projection of the high-speed signal access area on the grounding layer is within the grounding area or has the same size as the grounding area; A keep-out area is provided on the middle layer at a position corresponding to the high-speed signal access area. The projection of the high-speed signal access area on the middle layer is within the keep-out area or has the same size as the keep-out area.

2. The circuit board according to claim 1, wherein: At least two of the plurality of keep-out regions have the same size; or, any two of the plurality of keep-out regions have different sizes.

3. The circuit board according to claim 1, wherein: The high-speed signal access area includes a pad.

4. The circuit board according to claim 3, wherein: The width of the prohibited wiring area is equal to the sum of 2 times the spacing and the width of the high-speed signal access area, wherein the spacing is greater than or equal to the width of the high-speed signal and the spacing is less than 1 / 2 times the minimum distance between two adjacent pads.

5. The circuit board according to any one of claims 1 to 4, wherein: An isolation area is provided on the high-speed signal layer and surrounds the high-speed signal access area.

6. The circuit board according to claim 5, wherein: A ground layer is provided in the isolation region.

7. The circuit board according to claim 5, wherein: The distance between the outer boundary of the isolation region and the pad closest to the isolation region is greater than or equal to 20 times the thickness of the dielectric between the high-speed signal layer and the intermediate layer where the keep-out region is located.

8. The circuit board according to claim 5, wherein: A grounding region is provided on the middle layer. The grounding region on the middle layer at least includes a projection of the isolation region on the middle layer and a space between the keep-out region.

9. The circuit board according to any one of claims 1 to 4, wherein: The high-speed signal layer is further provided with a via hole connected to the high-speed signal access area; wherein the via hole includes a blind hole or a through hole processed by a drilling process.

10. The circuit board according to any one of claims 1 to 4, characterized in that: A plurality of device signal installation areas are also provided on the high-speed signal layer. The device signal installation areas are used to access devices. An isolation area is provided on the high-speed signal layer surrounding the high-speed signal access area and the device signal installation area.

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