Memory element and manufacturing method thereof

Abstract

The invention provides a memory element and a manufacturing method thereof. A memory device includes a stack structure, a second conductor layer, a plurality of channel pillars, and a string select line cutting wall. The stacked structure includes a plurality of first insulating layers and a plurality of first conductor layers alternately stacked. A second conductor layer is over the stack structure. A plurality of channel pillars extend through the second conductor layer and the stack structure. Each channel post includes a first portion and a second portion. A first portion extends through the stack structure. A second portion is on the first portion and extends through the second conductor layer. The diameter of the first part is larger than that of the second part. A string select line cutting wall extends through the second conductor layer and is disposed between the second portions of two adjacent channel pillars of the plurality of channel pillars. The memory element can be applied to a 3D NAND flash memory so as to manufacture the memory element with high capacity and high performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a memory device and a manufacturing method thereof. Background Art

[0002] Non-volatile memory has the advantage of ensuring that stored data persists even after a power outage, making it widely used in personal computers and other electronic devices. Currently, the most commonly used three-dimensional memories include NOR memory and NAND memory. Another type of three-dimensional memory is AND memory, which can be used in multi-dimensional memory arrays and offers high density, high area utilization, and fast operation speeds. Therefore, the development of three-dimensional memory devices has become a trend. Summary of the Invention

[0003] The present invention provides a memory element and a manufacturing method thereof, which can reduce the distance between elements to reduce the occupied chip area.

[0004] An embodiment of the present invention provides a memory element comprising: a stacked structure, a second conductor layer, a plurality of channel pillars, a plurality of charge storage structures, and a string select line cut wall. The stacked structure comprises a plurality of first insulating layers and a plurality of first conductor layers stacked alternately. A second conductor layer is above the stacked structure. A plurality of channel pillars extend through the second conductor layer and the stacked structure. Each channel pillar comprises a first portion and a second portion. The first portion extends through the stacked structure. The second portion is located above the first portion and extends through the second conductor layer. The diameter of the first portion is greater than the diameter of the second portion. A plurality of charge storage structures surround the plurality of channel pillars and contact the second conductor layer. A string select line cut wall extends through the second conductor layer and is disposed between the second portions of two adjacent channel pillars among the plurality of channel pillars.

[0005] An embodiment of the present invention provides a memory element comprising: a stacked structure, a second conductor layer, a string select line cut wall, a plurality of first channel pillars, and a plurality of second channel pillars. The stacked structure includes a plurality of insulating layers and a plurality of first conductor layers stacked alternately. The second conductor layer is located between the stacked structure and an interconnect layer having a plurality of conductor plugs. The string select line cut wall has a wavy shape when viewed from above and extends through the second conductor layer, dividing the second conductor layer into a first sub-region and a second sub-region. A plurality of first channel pillars extend through the second conductor layer in the first sub-region and the stacked structure. A plurality of second channel pillars extend through the second conductor layer in the second sub-region and the stacked structure.

[0006] An embodiment of the present invention provides a method for manufacturing a memory element, comprising the following steps: forming a plurality of first openings in a stacked structure; the stacked structure comprising a plurality of first insulating layers and a plurality of intermediate layers alternately stacked above a substrate; filling the plurality of first openings with a sacrificial material; forming a conductor layer above the stacked structure; patterning the conductor layer to form a plurality of second openings and trenches between the plurality of second openings, wherein the width of the trenches is less than the plurality of diameters of the plurality of second openings; removing the sacrificial material to expose the plurality of first openings located below the plurality of second openings; forming a plurality of channel pillars in the plurality of first openings and the plurality of second openings; and forming a string selection line cut wall in the trench.

[0007] Based on the above, the memory device and the manufacturing method thereof according to the embodiments of the present invention can reduce the distance between devices, thereby reducing the occupied chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1J is a cross-sectional schematic diagram of a manufacturing process of a memory device according to an embodiment of the present invention.

[0009] Figure 2A and Figure 2B They are Figure 1F as well as Figure 1J A magnified schematic diagram of a local area.

[0010] Figure 3A yes Figure 1J A top view of line AA'.

[0011] Figure 3B yes Figure 1J Top view of line BB'.

[0012] Figure 4 FIG. 1 is a cross-sectional diagram of a complementary metal oxide semiconductor device under a memory array (CMOS under array, CuA) structure memory device according to an embodiment of the present invention.

[0013] Figure 5 FIG. 1 is a cross-sectional diagram of a complementary metal oxide semiconductor (CMOS) bonding array (CbA) structure memory device according to an embodiment of the present invention.

[0014] Description of reference numerals:

[0015] 100, 50: base

[0016] 60: Component layer

[0017] 70, 138: Internal connection structure

[0018] 80A, 80B: Bonding layer

[0019] 80: Joint structure

[0020] 102, 202; 206: Insulation layer

[0021] 104: Middle layer

[0022] 106: Sacrificial Pillar

[0023] 108: Charge storage structure

[0024] 110: Channel layer

[0025] 112: Insulation layer

[0026] 114: Conductor cover

[0027] 122: Tunneling layer

[0028] 123: Charge storage layer

[0029] 124: Barrier layer

[0030] 125, 132: Barrier layer

[0031] 126: Conductor layer / gate layer

[0032] 134, 204, SGD: conductor layer

[0033] 136: Interlayer Window

[0034] 140: Protective layer

[0035] 142: Lining

[0036] 144: Conductor layer

[0037] 200: Local area

[0038] A-A', B-B': line

[0039] AG: Air Gap

[0040] B: Block

[0041] BL: bit line

[0042] CP, CP1, CP2: channel columns

[0043] d1, d2, d3, d4: distance

[0044] D1, D2: diameter

[0045] COA, COA1, COA2: Conductor plug

[0046] EP: Extension

[0047] IR: Interface Region

[0048] MP: Main body

[0049] OP1, OP2: Opening

[0050] Pl: Part 1

[0051] P2: Part 2

[0052] B: Block

[0053] SB1, SB2: sub-areas

[0054] SK1, SK2, GSK: stacked structure

[0055] ST1: Dividing channel

[0056] ST2: Separation channel

[0057] SSLC: String Selection Line Cutting Wall

[0058] SL: Source line

[0059] SLT: Dividing Wall

[0060] SW1, SW2: side walls

[0061] T1, T2, T3: thickness

[0062] W0, W1, W2: width

[0063] W0, W1, W2: width

[0064] WL: word line

[0065] X, Y: direction DETAILED DESCRIPTION

[0066] As device sizes continue to shrink, the distance between devices must also be reduced, resulting in a reduction in chip area. Embodiments of the present invention modify the structure of the drain-side select gate, channel pillar, and string select line cut wall to reduce the distance between the string select line cut wall and the channel pillar, saving chip area.

[0067] Figures 1A to 1J is a cross-sectional schematic diagram of a manufacturing process of a memory device according to an embodiment of the present invention.

[0068] Reference Figure 1A, providing a substrate 100. The substrate 100 includes an array region (not shown) and a step region (not shown). The substrate 100 is, for example, a semiconductor substrate. A stacking structure SK1 is formed above the substrate 100. The stacking structure SK1 can also be called an insulating stacking structure SK1. In this embodiment, the stacking structure SK1 includes an insulating layer 102 and an intermediate layer 104 stacked sequentially and alternately above the substrate 100. The insulating layer 102 is, for example, a silicon oxide layer. The intermediate layer 104 is, for example, a silicon nitride layer. The intermediate layer 104 can be used as a sacrificial layer and be partially removed in subsequent processes. Refer to Figure 4 In one embodiment, a device 60, an interconnect structure 70, and a source line SL may be formed between the substrate 100 and the stacked structure SK1. The device layer 60 may include a complementary metal oxide semiconductor (CMOS) device. In other embodiments, the stacked structure SK1 is formed on the substrate 100.

[0069] Next, the stacked structure SK1 is patterned to form a stepped structure (not shown) in the stepped region. A dielectric layer (not shown) is then formed on the stepped structure. The dielectric layer (not shown) may be made of, for example, silicon oxide. The dielectric layer (not shown) may be polished using a polishing process, such as a chemical mechanical polishing process.

[0070] Next, refer to Figure 1B A plurality of openings OP1 are formed in the array region of the stacked structure SK1. The openings OP1 pass through the stacked structure SK1 and further extend to the underlying layer (not shown). In this embodiment, the openings OP1 have a circular outline (not shown) when viewed from above, but the present invention is not limited thereto.

[0071] Reference Figure 1C , a sacrificial material is formed on the stacked structure SK1 and in the opening OP1, and then a back etching or chemical mechanical polishing process is performed to remove the excess sacrificial material on the stacked structure SK1 to form a plurality of sacrificial columns 106 in the plurality of openings OP1. The material of the sacrificial column 106 is different from the insulating layer 102 and the intermediate layer 104. The sacrificial column 106 is, for example, amorphous silicon, tungsten or a carbon-containing organic material. The carbon-containing organic material can be a polymer, such as a photoresist. The photoresist can be a positive photoresist or a negative photoresist. The material of the sacrificial column 106 is not limited to this, and other materials can also be used. The sacrificial column 106 has a circular profile (not shown).

[0072] Reference Figure 1C, forming a stacked structure SK2 on the stacked structure SK1. In this embodiment, the stacked structure SK2 may include an insulating layer 202, a conductive layer 204 (also referred to as a drain select gate or SGD), and an insulating layer 206. The materials of the insulating layers 202 and 206 may be the same as or similar to the insulating layer 102. The material of the conductive layer 204 may be a semiconductor, a metal, a metal silicide, or a combination thereof. The semiconductor may be, for example, polycrystalline silicon. The metal may be, for example, tungsten. The metal silicide may be, for example, titanium silicide. The conductive layer 204 may be a single layer or multiple layers.

[0073] Reference Figure 1D Next, photolithography and etching processes are performed to pattern the stacked structure SK2, forming a plurality of openings OP2 and a cutting trench ST1. The openings OP2 expose the sacrificial pillars 106. The cutting trench ST1 exposes the topmost intermediate layer 104. The width W0 of the cutting trench ST1 is smaller than the width W2 of the openings OP2. The cutting trench ST1 has an elongated strip shape (not shown).

[0074] Reference Figure 1E The sacrificial pillars 106 exposed by the openings OP2 are removed to form openings OP1. When the sacrificial pillars 106 are made of a carbon-containing organic material, a dry removal method, such as oxygen plasma ashing, can be used to remove them without over-etching or insufficient etching depth (opening) of the openings OP1. The width W1 of the opening OP1 is greater than the width W2 of the opening OP2.

[0075] Afterwards, refer to Figure 1F , a charge storage structure 108 and a channel pillar CP are formed in the openings OP2 and OP1, and a string selection line cut wall SSLC is formed in the split trench ST1. For clarity, Figure 2A Show Figure 1F The enlarged schematic diagram of the area 200 can be used in conjunction with Figure 2A The formation method of the charge storage structure 108 and the channel pillar CP is described in detail.

[0076] Reference Figure 1F and Figure 2A , between openings OP2 and OP1 (shown in Figure 1F) is formed within the charge storage structure 108. The charge storage structure 108 may include a blocking layer 124, a charge storage layer 123, and a tunneling layer 122. The tunneling layer 122 is, for example, silicon oxide. The charge storage layer 123 is, for example, silicon nitride. The blocking layer 124 is, for example, silicon oxide or a high-k material with a dielectric constant greater than or equal to 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or combinations thereof. In an embodiment of the present invention, the charge storage structure 108 also fills the slicing trench ST1. The width W0 of the slicing trench ST1 is less than twice the thickness T3 of the charge storage structure 108. Therefore, at this stage, the slicing trench ST1 is completely filled with the charge storage structure 108, forming a string select line cut wall SSLC. The width W2 of the opening OP2 and the width W1 of the opening OP1 are greater than the width W0 of the slicing trench ST1 and greater than twice the thickness T3 of the charge storage structure 108. That is, W0<2T3<W2<W1. Therefore, the charge storage structure 108 cannot fill up the opening OP2 and the opening OP1.

[0077] Reference Figure 1F and Figure 2A , at openings OP2 and OP1 (shown in Figure 1F ) in the remaining space. First, a channel layer 110 is formed on the charge storage structure 108. In one embodiment, the material of the channel layer 110 includes polysilicon. In one embodiment, the channel layer 110 covers the charge storage structure 108 on the sidewalls of the openings OP2 and OP1, and also covers the channel layer 110 on the bottom surface of the opening OP1 (not shown). Next, an insulating layer 112 is formed in the openings OP2 and OP1. In one embodiment, the material of the insulating layer 112 includes silicon oxide. In this embodiment, since the width W2 of the opening OP2 is smaller than the width W1 of the opening OP1, the insulating layer 112 fills the remaining space of the opening OP2 and closes the opening OP2. Since the width W1 of the opening OP1 is larger, the insulating layer 112 is on the inner surface of the channel layer 110, and the remaining space cannot be filled by the insulating layer 112. Therefore, an air gap AG is formed in the opening OP1 and is surrounded by the insulating layer 112.

[0078] Next, the insulating layer 112 and channel layer 110 within the opening OP2 are etched back to form a recess (not shown). Subsequently, a conductive cap 114 is formed within the recess. In one embodiment, the conductive cap 114 is made of polysilicon. A chemical mechanical polishing process is then performed to remove excess charge storage structure 108, insulating layer 112, and channel layer 110 from the insulating layer 206. The channel layer 110, insulating layer 112, and conductive cap 114 are collectively referred to as a channel pillar CP. The charge storage structure 108 surrounds the vertical outer surface of the channel pillar CP.

[0079] Reference Figure 1G A capping insulating layer 128 is formed on the insulating layer 206. The capping insulating layer 128 includes silicon oxide, silicon nitride, or a combination thereof. The capping insulating layer 128 can be a single layer or multiple layers. A patterning process is then performed to form a plurality of separation trenches ST2. The separation trenches ST2 extend through the stacked structures SK2 and SK1.

[0080] Reference Figure 1H An etching process, such as a wet etching process, is performed to remove the multilayer interlayer 104 surrounding the isolation trench ST2 to form multiple horizontal openings (not shown). A barrier layer 125 and a gate layer (or conductive layer) 126 are then formed in the horizontal openings. The barrier layer 125 can be made of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The gate layer 126 can also be referred to as a word line WL. The gate layer 126 can be made of, for example, tungsten, cobalt, or ruthenium. The barrier layer 125 and the gate layer 126 are formed by, for example, sequentially forming a barrier material and a conductive material within the isolation trench ST2 and the horizontal openings, and then performing an etch-back process to form the barrier layer 125 and the gate layer 126 within the multiple horizontal openings. This results in a stacked structure GSK. The stacked structure GSK includes the gate layer 126, the channel pillars CP, and the charge storage structure 108, forming a memory array consisting of multiple memory cells MC.

[0081] Reference Figure 1I , forming a separation wall SLT in the separation trench ST2. The method for forming the separation wall SLT includes filling an insulating liner material and a conductor material on the top cover insulating layer 128 and in the separation trench ST2. The insulating liner material is, for example, silicon oxide. The conductor material is, for example, polysilicon, titanium / titanium nitride, tungsten or a combination thereof. Then, the excess insulating liner material and the conductor material on the top cover insulating layer 128 are removed through an etch-back process or a polishing process to form a liner 142 and a conductor layer 144. The liner 142 and the conductor layer 144 are collectively referred to as the separation wall SLT. In some further embodiments, the conductor layer 144 of the separation wall SLT may be further covered with an air gap. In other embodiments, the separation wall SLT may also be completely filled with insulating material without any conductor layer. In some further embodiments, the separation wall SLT may also be a liner 142, and the liner 142 covers the air gap AG without any conductor layer.

[0082] Reference Figure 1J, a dielectric layer 130 is formed on the top cover insulating layer 128. The dielectric layer 130 is, for example, silicon oxide. Then, a conductor plug COA is formed in the dielectric layer 130. The method for forming the conductor plug COA is, for example, forming a contact hole (not shown) in the dielectric layer 130. The contact hole exposes the top surface and upper side wall of the conductor cover layer 114. Then, a barrier layer 132 and a conductor layer 134 are formed in the contact hole. The material of the barrier layer 132 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The conductor layer 134 is, for example, tungsten. The method for forming the barrier layer 132 and the conductor layer 134 is, for example, sequentially forming a barrier material and a conductor material on the dielectric layer 130 and in the contact hole, and then performing an etch-back process or a chemical mechanical polishing process to form a conductor plug COA in the contact hole. Refer to Figure 4 Before, after, or simultaneously with the formation of the conductive plug COA, a conductive plug COA1 connected to the conductive layer 204 and a conductive plug COA2 connected to the gate layer 126 can be formed. Subsequent processes, such as forming the via 136, the bit line BL, the interconnect structure 138, and the protective layer 140, can then be performed.

[0083] Figure 2A and Figure 2B They are Figure 1F as well as Figure 1J An enlarged schematic diagram of a local area 200. Figure 3A yes Figure 1J A top view of line AA'. Figure 3B yes Figure 1J Top view of line BB'.

[0084] Reference Figure 2A In an embodiment of the present invention, each of the channel pillars CP includes a first portion P1 and a second portion P2. The first portion P1 extends below the second portion P2 through the stacked structure GSK. The first portion P1 includes a channel pillar 110, an insulating layer 112, and an air gap AG surrounded by the insulating layer 112. The second portion P2 is located on the first portion P1 and extends through the insulating layer 202, the conductive layer 204 (SGD), and the insulating layer 206. The second portion P2 is above the first portion P1 and connected to the first portion P1. The second portion P2 includes a conductive cover 114, an insulating layer 112, and a channel layer 110. The insulating layer 112 is located below the conductive cover 114. The channel layer 110 is located below the conductive cover 114 and between the charge storage structure 108 and the insulating layer 112. There is no air gap AG in the second portion P2.

[0085] Reference Figure 2A 、 Figure 3A and Figure 3BThe diameter D1 of the first portion P1 is greater than the diameter D2 of the second portion P2. In two adjacent channel columns CP, the distance d2 between the two second portions P2 is greater than the distance d1 between the two first portions P1.

[0086] Reference Figure 2B In this embodiment of the present invention, the charge storage structure 108 surrounds the outer surface of the channel pillar CP. More specifically, the charge storage structure 108 surrounds the conductive cap 114, the channel layer 110, and the insulating layer 112. In this embodiment, the top surfaces of the charge storage layer 123 and the tunneling layer 122 of the charge storage structure 108 also contact the bottom surface of the conductive plug COA. The blocking layer 124 of the charge storage layer 123 also extends upward to cover the lower sidewall of the conductive plug COA. In this embodiment, the charge storage structure 108 contacts the insulating layer 206, the conductive layer 204, the insulating layer 202, the gate layer 126, and the sidewalls of the insulating layer 102.

[0087] Reference Figure 2B In an embodiment of the present invention, the conductive layer 204 (SGD) can be used as a drain-end select gate. The conductive layer 204 is above the topmost gate layer 126 of the stacked structure GSK. The thickness T2 of the conductive layer 204 is greater than the thickness T1 of the gate layer 126. In some embodiments, the thickness T2 of the conductive layer 204 is 1.5 to 15 times the thickness T1 of the gate layer 126. A top view of the conductive layer 204 is shown in FIG. Figure 3B shown.

[0088] Reference Figure 3B The partition walls SLT and the string select line cut walls SSLC extend in the same direction, for example, along direction X. The string select line cut walls SSLC are located between the partition walls SLT. The shape of the string select line cut walls SSLC differs from that of the partition walls SLT. In this embodiment, in a top view, the partition walls SLT have a strip shape, while the string select line cut walls SSLC have a wavy shape. The string select line cut walls SSLC conform to portions of the sidewalls of the plurality of channel pillars CP1 and the plurality of channel pillars CP2.

[0089] Reference Figure 1J and Figure 3B The separation wall SLT separates the conductor layer 204 and the stacked structure GSK below it (shown in FIG. Figure 2B) is divided into multiple blocks B. The string selection line cutting wall SSLC passes through the conductor layer 204 and divides the conductor layer 204 into multiple sub-areas SB1 and SB2. In other words, the string selection line cutting wall SSLC is between the sub-areas SB1 and SB2, so the area around the string selection line cutting wall SSLC can also be called the interface region IR. The channel column CP1 extends through the conductor layer 204 and the stacked structure GSK of the sub-area SB1 respectively. The channel column CP2 extends through the conductor layer 204 and the stacked structure GSK of the sub-area SB2 respectively. The string selection line cutting wall SSLC is set between the channel columns CP1 and CP2, as shown in FIG. Figure 1I as well as Figure 3B shown.

[0090] Reference Figure 2A and Figure 3B In this embodiment, the string select line cut wall SSLC also does not pass through the dummy pillars. There are no dummy pillars in the region surrounding the string select line cut wall SSLC (also known as the interface region IR). Therefore, the string select line cut wall SSLC is very close to the adjacent channel pillar CP1 or CP2. Since no dummy pillars are required in the interface region IR, wafer area can be saved. The dummy pillars described herein can have a similar structure to the channel pillar CP and charge storage structure 108, but do not provide data storage functionality.

[0091] Reference Figure 2B and Figure 3A In this embodiment, the distance d3 between the string select line cut wall SSLC and the second portion P2 of the adjacent channel pillar CP is very small. Distance d3 may be smaller than the distance d4 between the partition wall SLT and the second portion P2 of the adjacent channel pillar CP. Distance d3 is also smaller than the distance d2 between the second portions P2 of adjacent channel pillars CP.

[0092] Reference Figure 2A and Figure 3A The string select line cut wall SSLC passes through the insulating layer 206, the conductive layer 204, and the insulating layer 202, landing on the topmost conductive layer 126 of the stacked structure GSK without extending beyond the topmost conductive layer 126. In other words, the string select line cut wall SSLC passes through the single, thicker conductive layer 204 (SGD) above the stacked structure GSK and does not pass through any of the thinner conductive layers 126 of the stacked structure GSK. The sidewalls SW1 and SW2 of the string select line cut wall SSLC are in contact with the conductive layer 204 (SGD).

[0093] The size of the string selection wire cutting wall SSLC is quite small. Figure 2AThe width W0 of the string select line cut wall SSLC is less than the combined width W2 of the second portion P2 of the channel pillar CP and the surrounding charge storage structure 108. The width W0 of the string select line cut wall SSLC is greater than the thickness T3 of the charge storage structure 108 and less than twice the thickness T3 of the charge storage structure 108. The string select line cut wall SSLC includes the tunneling layer 122, charge storage layer 123, and blocking layer 124 of the charge storage structure 108. The string select line cut wall SSLC does not include the channel layer 110.

[0094] Reference Figure 2B The conductive plug COA extends through the dielectric layer 228 and electrically connects to the conductive cover 114 of the channel pillar CP. The conductive plug COA has an inverted U-shape. The main portion MP of the conductive plug COA contacts the top surface and upper sidewall of the conductive cover 114. The bottom surface and lower sidewall of the extended portion EP of the conductive plug COA contact the charge storage structure 108.

[0095] Reference Figure 4 In at least one embodiment, as described in the previous paragraph, the stacked structure (having a memory array) of the present invention may have a device layer 60, an internal connection structure 70, and a source line layer SL below the GSK and above the substrate 100. The device layer 60 may include complementary metal oxide semiconductor devices. In some embodiments, these complementary metal oxide semiconductor devices and the internal connection structure 70 may be formed before the stacked structure GSK is formed, and thus are located below the memory array. This type of memory is also called a CMOS under Array (CuA) structure memory. Figure 5 In other embodiments, before forming the stacked structure GSK, the substrate 100 (shown in FIG. Figure 1J ) is first formed on the source line layer SL. Thereafter, after forming the stacked structure GSK, the stacked structure SK2, the conductor plugs COA, COA1, COA2 and the bit line BL above the substrate 100 according to the method of the aforementioned embodiment, a bonding layer 80A is first formed. A substrate 50 having the component layer 60 and the internal connection structure 70 and the bonding layer 80B as described in the previous paragraph is then provided. Next, the substrate 100 is turned over. The bonding layer 80A and the bonding layer 80B are bonded to each other to form the bonding structure 80. The substrate 100 can be ground and completely removed or thinned (not shown), and then the internal connection structure 138 and the protective layer 140 are formed above the stacked structure GSK. The substrate 50, the component layer 60, the internal connection structure 70 and the bonding layer 80 are located below the stacked structure GSK. The second portion P2 of the channel column CP is close to the substrate 50. The first portion P1 of the channel column CP is away from the substrate 50.

[0096] The CMOS device is formed below the memory array by bonding, and this type of structure is also called a CMOS bonding array (CbA) structure.

[0097] Based on the foregoing, the memory device and its manufacturing method according to embodiments of the present invention can reduce the size of the string select line cut wall and the distance between the string select line cut wall and the channel pillar, thereby reducing the occupied chip area. Furthermore, the present invention can simplify the process and can be integrated with existing processes, thereby increasing integration, improving process yield, and reducing manufacturing costs.

Claims

1. A memory element comprising: A stacked structure comprising a plurality of first insulating layers and a plurality of first conductor layers stacked alternately; a second conductor layer above the stacked structure; a plurality of channel pillars extending through the second conductor layer and the stacked structure, wherein each of the plurality of channel pillars comprises: a first portion extending through the stacked structure; and a second portion located on the first portion and extending through the second conductor layer, wherein a diameter of the first portion is greater than a diameter of the second portion; a plurality of charge storage structures surrounding the plurality of channel pillars and contacting the outer sidewall of the second conductive layer; and A string selection line cut wall extends through the second conductor layer and is disposed between the second portions of two adjacent via pillars among the plurality of via pillars. 2 . The memory device according to claim 1 , further comprising a substrate located below the stack structure.

3. The memory element according to claim 1, wherein A second distance between the plurality of second portions of two adjacent channel pillars is greater than a first distance between the plurality of first portions of the two adjacent channel pillars.

4. The memory element according to claim 3, wherein A third distance between the string selection line cutting wall and the second portion of the adjacent channel column is smaller than the second distance.

5. The memory element according to claim 1, wherein An area between the string selection line cutting wall and the second portion of the adjacent channel pillar is free of dummy pillars. 6 . The memory device according to claim 3 , further comprising a partition wall extending through the second conductor layer and the stack structure, wherein a fourth distance between the partition wall and the second portion of another channel pillar is greater than the third distance. 7 . The memory element according to claim 1 , wherein a sidewall of the string selection line cut wall is in contact with the second conductor layer.

8. The memory element according to claim 1, wherein The string selection line cut wall does not extend beyond the topmost first conductor layer of the stack structure. 9 . The memory element according to claim 1 , wherein a thickness of the second conductor layer is thicker than a thickness of each of the plurality of first conductor layers.

10. The memory element of claim 1 , wherein the second portion comprises: Conductor cover; a second insulating layer located below the conductor cover; as well as The channel layer is located between the charge storage structure and the second insulating layer, wherein the charge storage structure surrounds the channel layer, the second insulating layer and the conductive cover and contacts the second conductive layer.

11. The memory element according to claim 10, wherein The string selection line cut wall has a width less than twice the thickness of the charge storage structure.

12. The memory element according to claim 10, wherein The string select line cut wall includes the charge storage structure but without the channel layer.

13. The memory element according to claim 10, wherein The first portion includes an air gap surrounded by the second insulating layer, and the second portion does not have an air gap.

14. The memory element according to claim 1, wherein The string selection line cutting wall has a wavy shape from a top view.

15. A memory element comprising: A stacked structure comprising a plurality of insulating layers and a plurality of first conductor layers stacked alternately; A second conductor layer is located between the stacked structure and the inner connection layer having a plurality of conductor plugs; a string selection line cutting wall extending through the second conductor layer; a plurality of first channel pillars extending through the second conductor layer and the stacked structure in the first sub-region; as well as a plurality of second channel pillars extending through the second conductor layer and the stacked structure in the second sub-region, The string selection line cutting wall is disposed between the plurality of first channel pillars and the plurality of second channel pillars, has a wavy shape in a top view, and divides the second conductor layer into a first sub-region and a second sub-region.

16. The memory element according to claim 15, wherein The string selection line cutting wall does not extend beyond the uppermost first conductor layer of the stack structure. 17 . The memory element according to claim 15 , further comprising a separation wall extending through the second conductor layer and the stack structure, wherein the separation wall has a stripe shape that is different from a wavy shape of the string selection line cutting wall. 18 . The memory element according to claim 15 , wherein no dummy pillar is provided in an interface region between the first sub-region and the second sub-region.

19. The memory element according to claim 16, wherein: The string selection line cut walls are conformal to partial sidewalls of the plurality of first channel pillars and partial sidewalls of the plurality of second channel pillars.

20. A method for manufacturing a memory element, comprising: forming a plurality of first openings in a stacked structure, wherein the stacked structure includes a plurality of first insulating layers and a plurality of intermediate layers stacked alternately; filling the plurality of first openings with a sacrificial material; forming a conductor layer on the stacked structure; patterning the conductive layer to form a plurality of second openings and channels between the plurality of second openings, wherein a width of the channels is smaller than a plurality of widths of the plurality of second openings; removing the sacrificial material to expose the plurality of first openings below the plurality of second openings; forming a plurality of channel pillars in the plurality of first openings and the plurality of second openings; as well as A string selection line cut wall is formed in the trench.

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