MOS device and manufacturing method thereof

Abstract

The present invention discloses a MOS device and a method for manufacturing the same, wherein the method comprises the following steps: forming a silicon oxide layer on the surface of a silicon substrate of the MOS device; sequentially depositing a first material layer with a high dielectric constant and a sacrificial layer on the silicon oxide layer, etching the sacrificial layer to form a sacrificial gate structure; forming a second material layer with a low dielectric constant on the sacrificial gate structure and etching it to form offset sidewall structures on both sides of the sacrificial gate structure; etching the first material layer on the silicon substrate on both sides of the offset sidewall structure to form a low-doped drain region on the silicon substrate; forming a third material layer of a certain thickness outside the offset sidewall structure, the third material layer being a low dielectric constant material layer; forming highly doped source and drain regions; etching the sacrificial gate structure and the first material layer thereunder to form a gate region groove, and forming a gate within the gate region groove; and completing subsequent processes of the MOS device. The present invention can increase the on-current of the MOS device and improve device performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and in particular to a MOS device and a manufacturing method thereof. Background Art

[0002] The choice of material for MOS device sidewalls affects the parasitic capacitance between the gate and source / drain, as well as the capacitance between the gate and contact electrodes. Different parasitic capacitances have varying impacts on device performance. In conventional MOS devices, the dielectric constant of the sidewall material is often uniform along the gate, making it impossible to achieve optimal parasitic capacitance.

[0003] The capacitance C1 between the gate and the LDD region (lightly doped drain region) is mainly determined by the dielectric constant of the sidewall material in a small area above the LDD. The equipotential lines on the potential distribution diagram can be used to determine the reach of the electric field lines starting from the gate (the direction of the electric field lines is perpendicular to the equipotential lines). Figure 1 As shown in the TCAD simulation potential distribution diagram of 28nm NMOS, it can be seen that the electric field of the LDD region mainly reaches the LDD region from the gate through a small area of ​​sidewall (A) above the LDD. The height H of the sidewall of this small area is not greater than the lateral length L of the LDD region. Figure 2 As shown, the direction in which the capacitance C1 between the gate and the LDD region increases is the direction in which the device performance is optimized, and the direction in which the capacitance C2 between the gate and the source (or drain) contact electrode decreases is the direction in which the device performance is optimized. Summary of the Invention

[0004] The main purpose of the present invention is to provide a MOS device and a manufacturing method thereof that can effectively increase the parasitic capacitance between the gate and the LDD region, while reducing the parasitic capacitance between the gate and the contact electrode, thereby optimizing performance.

[0005] The technical solution adopted in the present invention is:

[0006] A method for manufacturing a MOS device is provided, comprising the following steps:

[0007] After the MOS device completes the shallow trench isolation and channel doping processes, a silicon oxide layer is formed on the surface of the silicon substrate;

[0008] Depositing a first material layer and a sacrificial layer in sequence on the silicon oxide layer, and etching the sacrificial layer to form a sacrificial gate structure; wherein the first material layer is a high dielectric constant material layer;

[0009] forming a second material layer on the sacrificial gate structure and etching the layer to form offset sidewall structures on both sides of the sacrificial gate structure, wherein the second material layer is a low dielectric constant material layer;

[0010] Etching the first material layer on the silicon substrate on both sides of the offset sidewall structure and forming a low-doped drain region on the silicon substrate;

[0011] forming a third material layer of a certain thickness on the outer side of the offset sidewall structure, wherein the third material layer is a low dielectric constant material layer;

[0012] Etching the third material layer to form a main sidewall structure and forming a source and drain highly doped region on the silicon substrate;

[0013] Etching the sacrificial gate structure and the first material layer thereunder to form a gate region groove, and forming a gate in the gate region groove;

[0014] Complete the subsequent process of MOS devices.

[0015] Following the above technical solution, the second material layer and the third material layer are made of the same material.

[0016] Following the above technical solution, the sum of the thickness of the offset spacer structure and the third material layer is greater than or equal to the width of the low-doped drain region.

[0017] Following the above technical solution, the thickness of the offset sidewall structure is equal to the thickness of the first material layer.

[0018] Following the above technical solution, the steps of forming the third material layer and the gate are further included: forming an interlayer dielectric layer on both sides of the offset sidewall structure; and forming source and drain contact electrodes on the interlayer dielectric layer after forming the gate.

[0019] Following the above technical solution, the step of forming the gate in the gate region groove is specifically as follows: first forming an inner layer of the gate dielectric layer in the gate region groove, and then filling the inner layer with metal to form the gate.

[0020] Following the above technical solution, the process of forming the offset sidewall structure is specifically as follows: depositing the second material layer by a CVD process, and then anisotropically etching the second material layer to form the offset sidewall structure.

[0021] Following the above technical solution, the sacrificial layer is a sacrificial amorphous silicon layer.

[0022] Following the above technical solution, the specific steps for forming the source and drain highly doped regions are: continuing doping on the basis of forming the low-doped drain region to form the source and drain highly doped regions; activating the doped ions through annealing treatment to form a sacrificial amorphous silicon layer into a sacrificial crystalline silicon layer.

[0023] The present invention also provides a MOS device, which is manufactured using the MOS device manufacturing method described in the above technical solution.

[0024] The present invention has the following beneficial effects: The present invention forms sidewalls of high-k dielectric material in the lower portion of both sides of the gate, while the remaining sidewalls are made of low-k dielectric material. This unexpectedly creates a larger parasitic capacitance between the gate and the LDD region (lowly doped drain). When a voltage is applied to the gate, more carriers are induced in the LDD region, thereby reducing the resistance of the LDD region and increasing the on-current of the MOS device. Furthermore, the offset sidewall structure design of the present invention allows the LDD doping concentration to be lower than the conventional doping concentration, thereby reducing the diffusion of LDD dopants into the channel, thereby improving the short-channel effect of the MOS device.

[0025] Furthermore, by setting the thickness of the offset sidewall structure to be equal to the thickness of the first material layer with a high dielectric constant, while increasing the capacitance between the gate and the LDD region, it has certain advantages in reducing the capacitance between the gate and the source (or drain) contact electrode, which can make the parasitic capacitance between the gate and the contact electrode smaller, which is beneficial to reducing RC delay.

[0026] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 is the potential distribution diagram of the gate and LDD region;

[0029] Figure 2 It is a schematic diagram of the capacitance optimization direction between the gate and the LDD region, and between the gate and the source (or drain);

[0030] Figure 3 This is a flow chart of a method for manufacturing a MOS device according to an embodiment of the present invention;

[0031] Figure 4-1 is a cross-sectional view of forming a silicon oxide layer on the surface of a silicon substrate according to an embodiment of the present invention;

[0032] Figure 4-2 is a cross-sectional view of forming a first material layer and a sacrificial layer according to an embodiment of the present invention;

[0033] Figure 4-3 is a cross-sectional view of a sacrificial gate structure formed according to an embodiment of the present invention;

[0034] Figure 4-4 is a cross-sectional view of a second material layer formed according to an embodiment of the present invention;

[0035] Figure 4-5 is a cross-sectional view of an offset sidewall structure formed according to an embodiment of the present invention;

[0036] Figure 4-6 is a cross-sectional view of a first material layer on a silicon substrate on both sides of an etched offset sidewall structure formed in one embodiment of the present invention;

[0037] Figure 4-7 is a cross-sectional view of forming a low-doped drain region on a silicon substrate according to an embodiment of the present invention;

[0038] Figure 4-8 is a cross-sectional view of a third material layer of a certain thickness formed outside the offset sidewall structure according to an embodiment of the present invention;

[0039] Figure 4-9 is a cross-sectional view of etching the third material layer according to one embodiment of the present invention;

[0040] Figure 4-10 is a cross-sectional view of forming a highly doped source and drain region according to an embodiment of the present invention;

[0041] Figure 4-11 is a cross-sectional view of forming a metal silicide layer on the source / drain region and on top of the sacrificial gate structure according to one embodiment of the present invention;

[0042] Figure 4-12 This is a cross-sectional view of an embodiment of the present invention in which an interlayer dielectric layer ILD is formed and chemical mechanical planarization is performed to remove the metal silicide layer on the top of the sacrificial gate structure to expose the sacrificial gate structure;

[0043] Figure 4-13 is a cross-sectional view of a groove in a gate region formed by removing a sacrificial gate structure according to an embodiment of the present invention;

[0044] Figure 4-14 FIG2 is a cross-sectional view of an embodiment of the present invention in which the high-k material at the bottom of the groove is removed, but the high-k material next to the gate and below the offset spacer structure is retained;

[0045] Figure 4-15 is a cross-sectional view of forming a gate dielectric layer and a metal gate layer according to an embodiment of the present invention;

[0046] Figure 4-16 is a cross-sectional view of a contact electrode formed according to an embodiment of the present invention;

[0047] Figure 5-1 This is a schematic diagram of the structure of a MOS device in which the gate and source / drain contact electrodes are all made of SiO2 material;

[0048] Figure 5-2 Schematic diagram of the structure of a MOS device in which the gate and source / drain contact electrodes are all made of SiN material;

[0049] Figure 5-3 Schematic diagram of the structure of a MOS device with HfO2 material between the gate and the source and drain contact electrodes;

[0050] Figure 5-4 This is a schematic diagram of the MOS device structure in which most of the material between the gate and the source and drain contact electrodes is SiO2 material, but HfO2 material is used above the LDD region, and the length and height of the HfO2 region are equal to the thickness of the offset sidewall structure.

[0051] In the picture:

[0052] 101. Silicon substrate; 102. Silicon oxide layer; 103. First material layer; 104. Sacrificial layer; 105. Sacrificial gate structure; 106. Second material layer; 107. Offset sidewall structure; 108. Low-doped drain region; 109. Third material layer; 110. Highly doped source and drain regions; 111. Metal silicide layer; 112. Interlayer dielectric layer; 113. Gate dielectric layer; 114. Metal gate layer; 115. Contact electrode. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0054] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic illustrations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0055] In the present invention, it should also be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like are used to indicate positions or locations based on those shown in the accompanying drawings. These terms are intended solely to facilitate the description of the present application and to simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present application. Furthermore, the terms "first" and "second" are used solely for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0056] In addition, it should be noted that the features of the various embodiments of the present invention may be combined or coupled in part or in whole, and, as will be appreciated by those skilled in the art, may interact and operate in different ways. Each embodiment may be implemented independently of one another or in an associated relationship.

[0057] like Figure 3 As shown, the method for manufacturing a MOS device according to an embodiment of the present invention mainly includes the following steps:

[0058] S1, after the MOS device completes the shallow trench isolation and channel doping processes, a silicon oxide layer 102 is formed on the surface of the silicon substrate 101;

[0059] S2, sequentially depositing a first material layer 103 and a sacrificial layer 104 on the silicon oxide layer 102, and etching the sacrificial layer 104 to form a sacrificial gate structure 105; wherein the first material layer 103 is a high dielectric constant material layer;

[0060] S3, forming a second material layer 106 on the sacrificial gate structure 105 and etching it, forming offset spacer structures 107 on both sides of the sacrificial gate structure 105, wherein the second material layer 106 is a low dielectric constant material layer;

[0061] S4, etching the first material layer 103 on the silicon substrate 101 on both sides of the offset sidewall structure 107, and forming a low-doped drain region 108 on the silicon substrate 101;

[0062] S5, forming a third material layer 109 of a certain thickness outside the offset spacer structure 107, wherein the third material layer 109 is a low-k material layer; etching the third material layer 109 to form a source-drain highly doped region 110 on the silicon substrate 101;

[0063] S6, etching the sacrificial gate structure 105 and the first material layer 103 thereunder to form a gate region groove, and forming a gate in the gate region groove;

[0064] S7. Complete the subsequent process of the MOS device.

[0065] In step S1, Figure 4-1 As shown, after shallow trench isolation and channel doping processes are completed, a silicon oxide layer 102 with a thickness of about 1 nm is oxidized and grown on the surface of the silicon substrate 101. The energy barrier between the silicon oxide layer 102 and the silicon substrate 101 is high, thereby preventing carriers in the silicon substrate from tunneling into the first material layer 103.

[0066] In step S2, if Figure 4-2As shown, a first material layer 103 and a sacrificial layer 104 are sequentially deposited on the silicon oxide layer 102. The first material layer 103 is a high-k material layer (i.e., a material layer with a high dielectric constant, such as an HfO2 layer), and the sacrificial layer 104 is an amorphous silicon layer, which will subsequently become a polycrystalline silicon layer after annealing. Preferably, the thickness of the high-k material layer is equal to the thickness of the offset spacer structure 107 to be formed later. This has certain advantages in increasing the capacitance between the gate and the LDD region while reducing the capacitance between the gate and the source (or drain) contact electrode 115. This reduces the parasitic capacitance between the gate and the contact electrode 115, thereby reducing RC delay.

[0067] In step S2, if Figure 4-3 As shown, when etching the sacrificial layer 104 , the gate mask is used as a mask for etching, but the high-k material layer is retained.

[0068] In step S3, Figure 4-4 As shown, a CVD (chemical vapor deposition) process can be used to deposit the second material layer 106, which is a low-k material layer (i.e., a material layer with a low dielectric constant, such as a SiCH3 layer). The low-k material layer is mainly used to form the offset spacer structure 107 of the gate, as shown in FIG. Figure 4-5 As shown, plasma anisotropic etching of the low-k material layer can be used to form an offset spacer structure 107, wherein the thickness H2 of the offset spacer structure 107 is equal to the thickness H1 of the high-k material (the specific reason has been described in detail above and will not be repeated here).

[0069] In step S4, Figure 4-6 As shown, the first material layer 103 on the silicon substrate 101 on both sides of the offset sidewall structure 107 is etched, and a low-doped drain region 108 is formed on the silicon substrate 101, as shown in FIG. Figure 4-7 Specifically, plasma anisotropic etching can be used to etch the first material layer 103, i.e., the high-k material layer. LDD doping is then performed downward in the area where the first material layer 103 has been etched. Annealing is then performed to activate the doping ions and repair the lattice damage caused by the LDD doping ion implantation. In the present invention, the offset sidewall structure 107 allows the LDD doping concentration to be lower than the conventional doping concentration. 18 ~10 19 Number / cm 3 , thus reducing the diffusion of LDD doping toward the channel direction, thereby improving the short channel effect of MOS devices.

[0070] In step S5, a third material layer 109 of a certain thickness is formed outside the offset spacer structure 107. The third material layer 109 is a low-k dielectric constant material layer. Specifically, a CVD process can be used to deposit a low-k material layer (i.e., a material layer with a low dielectric constant, which can be the same as the second material layer 106, such as a SiCH3 layer). The first material layer 103 and the third material layer 109 together constitute the main gate spacer. The total thickness of the two is greater than or equal to the width of the low-doped drain region 108 (the width of the offset spacer formed by the first material layer 103 can be set to be equal to the width of the LDD region). Figure 4-8 As shown, a low-k material layer can be deposited outside the offset spacer structure 107, the sacrificial gate structure 105 and the silicon oxide layer 102, and then the low-k material layer can be anisotropically etched by plasma, as shown in FIG. Figure 4-9 As shown, only the low-k material layer is retained outside the offset spacer structure 107 , and the low-k material layer on the top of the sacrificial gate structure 105 and the top of the silicon oxide layer 102 is etched away to finally form the main gate spacer.

[0071] In this embodiment, Figure 4-10 As shown, after forming the gate main sidewalls, the source and drain are highly doped to form the source and drain highly doped regions 110. Annealing is then performed to activate the doped ions and repair lattice damage caused by the high-concentration dopant ion implantation. The dark green portion represents the highly doped drain region. The width of the resulting light green low-doped drain region 108 is greater than or equal to the thickness H2 of the sidewalls. The red portion represents a small area that affects MOS device performance. As a capacitor dielectric layer, it is desirable to have a high dielectric constant to increase the capacitance between the gate and LDD, forming more carriers at the LDD and thus increasing current.

[0072] In step S6, the sacrificial gate structure 105 and the first material layer 103 thereunder are etched to form a gate region groove, and a gate is formed in the gate region groove. Figures 4-11 to 4-15As shown, the process includes the following steps: forming a metal silicide layer 111 in the source and drain regions (and also forming a metal silicide layer 111 on top of the sacrificial gate structure 105); depositing an ILD (interlayer dielectric layer 112) above the source and drain regions and on both sides of the main gate spacers; performing a chemical mechanical planarization process to remove the metal silicide layer 111 on top of the sacrificial gate structure 105, exposing the sacrificial gate structure 105; removing the sacrificial gate structure 105 using a TMAH wet etch to form a recess in the gate region; performing anisotropic plasma etching on the first material layer 103, i.e., the high-k material layer, to remove the high-k material at the bottom of the recess, but retaining the high-k material next to the gate and below the offset spacer structure 107; and depositing a high-k gate dielectric layer 113 and a metal gate layer 114 using an atomic layer deposition (ALD) process. This embodiment allows high-k spacers to be formed near the lower portion of both sides of the gate, while the remaining spacers are made of low-k material. This can create a larger parasitic capacitance between the gate and the LDD region. When a voltage is applied to the gate, more carriers can be induced in the LDD region, thereby reducing the resistance of the LDD region and increasing the on-current of the MOS device.

[0073] In step S7, Figure 4-16 As shown, the subsequent process of the MOS device specifically includes: performing a chemical mechanical planarization process on the metal gate layer 114; forming a contact electrode 115 on the interlayer dielectric layer 112 above the source region and the drain region. The formation of the contact electrode 115 may include the steps of: etching at a corresponding position of the interlayer dielectric layer 112 using a mask pattern as a mask to form a contact hole; and filling the contact hole with an electrode metal to form the contact electrode 115.

[0074] The MOS device of the present invention can be manufactured through the above process, wherein a material layer with a higher dielectric constant is formed above the LDD region, and its thickness and height are similar to the thickness of the low dielectric constant offset spacer structure 107 of the gate, and the thickness of the offset spacer structure 107 is less than or equal to the thickness of the LDD region. In addition, a material layer with a higher dielectric constant is formed above the LDD region as a small area that affects the performance of the device. Due to its larger dielectric constant, the capacitance between the gate and the LDD can be larger, and more carriers can be formed at the LDD, thereby increasing the current and improving the performance of the MOS device.

[0075] Taking 28nm NMOS as an example, its gate height is 36nm, the offset spacer structure 107 (offset spacer, that is, the sidewall before LDD ion implantation) thickness is 7nm, and the distance between the gate and the source contact electrode 115 (source contact) or the drain contact electrode 115 (drain contact) is 20nm. According to the above MOS size data, the following four cases are considered. And in these four cases, the capacitance between the gate and the LDD region is mainly determined by the dielectric constant of the sidewall material in a small area above the LDD, and the capacitance between the gate and the source or drain contact electrode 115 is proportional to the dielectric constant of the sidewall material. Figure 5-1 As shown, in Case 1, the capacitance between the gate and the LDD region is recorded as C1, and the capacitance between the gate and the source or drain contact electrode 115 is recorded as C2. It can be calculated that Figure 5-2 、 Figure 5-3 、 Figure 5-4 The capacitances for Case 2, Case 3, and Case 4 are shown in Table 1 below.

[0076] Table 1 Capacitance calculation for four cases

[0077]

[0078] Among them, in Case 1, the gate and the source-drain contact electrode 115 are both made of SiO2 material (the dielectric constant of SiO2 is 3.9); in Case 2, the gate and the source-drain contact electrode 115 are both made of SiN material (the dielectric constant of Si3N4 is about 7.5), and Case 2 is close to the optimization level that can be achieved by the current conventional process; in Case 3, the gate and the source-drain contact electrode 115 are both made of HfO2 material (the dielectric constant of HfO2 is about 25); Case 4 is the optimization level that can be achieved by the present invention.

[0079] In summary, the above process allows for the formation of high-k sidewalls on the lower portions of both sides of the gate, while the remaining sidewalls are constructed of low-k material. This results in a larger parasitic capacitance between the gate and the LDD region (lowly doped drain). When voltage is applied to the gate, more carriers are induced in the LDD region, thereby reducing the resistance of the LDD region and increasing the device's on-current. Furthermore, the smaller parasitic capacitance between the gate and the contact electrode helps reduce RC delay.

[0080] It should be pointed out that, according to the needs of implementation, the various steps / components described in this application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0081] The size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0082] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A method for manufacturing a MOS device, characterized in that: The following steps are involved: After the MOS device completes the shallow trench isolation and channel doping processes, a silicon oxide layer is formed on the surface of the silicon substrate; Depositing a first material layer and a sacrificial layer in sequence on the silicon oxide layer, and etching the sacrificial layer to form a sacrificial gate structure; wherein the first material layer is a high dielectric constant material layer; forming a second material layer on the sacrificial gate structure and etching the layer to form offset sidewall structures on both sides of the sacrificial gate structure, wherein the second material layer is a low dielectric constant material layer; Etching the first material layer on the silicon substrate on both sides of the offset sidewall structure and forming an initial low-doped drain region on the silicon substrate; forming a third material layer of a certain thickness outside the offset sidewall structure, the third material layer being a low-k dielectric constant material layer; etching the third material layer to form a main sidewall structure, and forming a source and drain highly doped region on the silicon substrate; Etching the sacrificial gate structure and the first material layer thereunder to form a gate region groove, and forming a gate in the gate region groove; Complete the subsequent process of MOS devices.

2. The method for manufacturing a MOS device according to claim 1, wherein: The second material layer and the third material layer are made of the same material.

3. The method for manufacturing a MOS device according to claim 1, wherein: The sum of the thickness of the offset spacer structure and the third material layer is greater than or equal to the width of the low-doped drain region.

4. The method for manufacturing a MOS device according to claim 1, wherein: The thickness of the offset sidewall structure is equal to the thickness of the first material layer.

5. The method for manufacturing a MOS device according to claim 1, wherein: The steps between forming the third material layer and the gate are as follows: forming an interlayer dielectric layer on both sides of the offset sidewall structure; and forming contact electrodes of the source and drain on the interlayer dielectric layer after forming the gate.

6. The method for manufacturing a MOS device according to claim 1, wherein: The step of forming the gate in the gate region groove is specifically as follows: first forming an inner layer of the gate dielectric layer in the gate region groove, and then filling the inner layer with metal to form the gate.

7. The method for manufacturing a MOS device according to claim 1, wherein: The formation process of the offset sidewall structure is specifically as follows: depositing a second material layer by a CVD process, and then anisotropically etching the second material layer to form the offset sidewall structure.

8. The method for manufacturing a MOS device according to any one of claims 1 to 7, wherein: The sacrificial layer is a sacrificial amorphous silicon layer.

9. The method for manufacturing a MOS device according to claim 8, wherein: The specific steps of forming the source and drain highly doped regions are: continuing doping on the basis of forming the low doped drain region to form the source and drain highly doped regions; activating the doped ions through annealing treatment to form a sacrificial amorphous silicon layer into a sacrificial crystalline silicon layer.

10. A MOS device, characterized in that: The MOS device is manufactured by the manufacturing method of any one of claims 1 to 9.

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