Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, which can be applied to the technical field of semiconductors. The semiconductor device includes: a semiconductor-on-insulator (SOI) substrate; the gate structure comprises a control gate electrode, a first switching gate electrode and a second switching gate electrode, and the first switching gate electrode and the second switching gate electrode are located on the two opposite sides of the control gate electrode in the first direction respectively; the gate structure is arranged on the SOI substrate, the source electrode and the drain electrode are respectively arranged on two opposite sides of the gate structure on the SOI substrate in a first direction, the first switching gate electrode and the switching gate electrode respectively comprise a gate dielectric layer and a gate conductor layer on the gate dielectric layer, and the gate dielectric layer comprises a ferroelectric material.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a reconfigurable semiconductor device formed by utilizing ferroelectric materials to assist in quantum well formation and a manufacturing method thereof. Background Art

[0002] Fully depleted (FD) semiconductor-on-insulator (SOI) technology is showing increasing potential in quantum device research due to its excellent electrostatic control capabilities and compatibility with complementary metal oxide semiconductor (CMOS) processes. However, as quantum device research deepens, quantum devices based on FDSOI technology still face several key challenges in practical application. Summary of the Invention

[0003] In view of this, the present disclosure provides a reconfigurable semiconductor device using ferroelectric materials to assist in quantum well formation and a method for manufacturing the same.

[0004] One aspect of the present disclosure provides a semiconductor device, comprising: a semiconductor on insulator (SOI) substrate; a gate structure on the SOI substrate, comprising a control gate electrode and a first switching gate electrode and a second switching gate electrode, respectively located on opposite sides of the control gate electrode in a first direction; and a source and a drain, respectively located on opposite sides of the gate structure in the first direction, on the SOI substrate, wherein the first switching gate electrode and the second switching gate electrode each comprise a gate dielectric layer and a gate conductor layer on the gate dielectric layer, and the gate dielectric layer comprises a ferroelectric material.

[0005] According to an embodiment of the present disclosure, the semiconductor device is configured to switch between a single electron transistor and a metal-oxide-semiconductor field-effect transistor (MOSFET) based on the polarization state of the ferroelectric material in the first switching gate electrode and the second switching gate electrode.

[0006] According to an embodiment of the present disclosure, the ferroelectric material in the first switching gate electrode and the second switching gate electrode has a first polarization state, and the semiconductor device operates as a single-electron transistor, or the ferroelectric material in the first switching gate electrode and the second switching gate electrode has a second polarization state different from the first polarization state, and the semiconductor device operates as a MOSFET.

[0007] According to an embodiment of the present disclosure, the first polarization state is a state of polarization in a direction away from the SOI substrate, and the second polarization state is a state of polarization in a direction close to the SOI substrate.

[0008] According to an embodiment of the present disclosure, the first switching gate electrode and the second switching gate electrode in the first polarization state result in a quantum well structure being formed between the source and the drain.

[0009] According to an embodiment of the present disclosure, the ferroelectric materials in the first switching gate electrode and the second switching gate electrode switch between the first polarization state and the second polarization state in response to the voltage applied to the first switching gate electrode and the second switching gate electrode, respectively, and maintain the switched polarization state after the applied voltage is removed.

[0010] According to an embodiment of the present disclosure, a ferroelectric material includes hafnium dioxide doped with a target element including at least one of silicon, aluminum, zirconium, yttrium, gadolinium, lanthanum, and strontium.

[0011] According to an embodiment of the present disclosure, the SOI substrate includes a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer. The source and drain respectively include n-type doped regions on both sides of a gate structure in the SOI layer.

[0012] According to an embodiment of the present disclosure, the semiconductor device further includes: n-type doping regions in the SOI layer respectively between the control gate electrode and the first switching gate electrode and the second switching gate electrode, so as to reduce the spreading resistance of the device.

[0013] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: forming a gate structure on an SOI substrate, the gate structure comprising a control gate electrode and a first switching gate electrode and a second switching gate electrode respectively located on opposite sides of the control gate electrode in a first direction, wherein the first switching gate electrode and the second switching ferroelectric gate electrode each comprise a gate dielectric layer and a gate conductor layer on the gate dielectric layer, and the gate dielectric layer comprises a ferroelectric material; and forming a source and a drain respectively on opposite sides of the gate structure in the first direction on the SOI substrate.

[0014] According to an embodiment of the present disclosure, forming a gate structure includes: forming a first sacrificial gate on an SOI substrate; forming a second sacrificial gate and a third sacrificial gate on opposite sides of the first sacrificial gate in a first direction on the SOI substrate; forming sidewalls on the sidewalls of the first sacrificial gate, the second sacrificial gate, and the third sacrificial gate; replacing the second sacrificial gate and the third sacrificial gate with a first switching gate electrode and a second switching gate electrode, respectively; and replacing the first sacrificial gate with a control gate electrode.

[0015] According to an embodiment of the present disclosure, the top surfaces of the second sacrificial gate and the third sacrificial gate are higher than the top surface of the first sacrificial gate; replacing the second sacrificial gate and the third sacrificial gate with the first switching gate electrode and the second switching gate electrode, respectively, includes: forming a filling layer on the SOI substrate, flattening the filling layer to expose the second sacrificial gate and the third sacrificial gate, and removing the second sacrificial gate and the third sacrificial gate, and forming the first switching gate electrode and the second switching gate electrode in the space released due to the removal of the second sacrificial gate and the third sacrificial gate; replacing the first sacrificial gate with the control gate electrode includes: further flattening to expose the first sacrificial gate, and removing the first sacrificial gate, and forming the control gate electrode in the space released due to the removal of the first sacrificial gate.

[0016] According to an embodiment of the present disclosure, the method further includes: implanting n-type dopants into the SOI substrate using the first sacrificial gate, the second sacrificial gate, the third sacrificial gate and the sidewall spacers as masks.

[0017] According to an embodiment of the present disclosure, by controlling the first switching gate electrode and the second switching gate electrode, the semiconductor device can be reconstructed so that the semiconductor device can be switched between different working states, thereby integrating the quantum state operation circuit and the peripheral reading circuit of the quantum device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0019] Figure 1A Schematically shows a structural diagram of a semiconductor device according to an embodiment of the present disclosure;

[0020] Figure 1B Schematically shows a principle diagram of a semiconductor device according to an embodiment of the present disclosure;

[0021] Figures 2 to 18 Some stages in a process of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically shown. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0023] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0024] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0025] Single-electron transistors can detect the number of electrons in a quantum dot, but they cannot directly determine the electron's spin direction. Therefore, before initializing and manipulating a spin qubit, it is first necessary to read the spin direction of the electrons in the quantum dot and convert this information into a change in the number of electrons in the quantum dot, thus achieving spin-to-charge conversion. After the spin-to-charge conversion is completed, a single-electron transistor is used to read the state of the electrons in the quantum dot. During the reading process, the change in the spin direction of the quantum dot causes a change in the current signal of the single-electron transistor. By comparing the current signal of the single-electron transistor with a set threshold, the spin direction can be determined.

[0026] However, achieving Coulomb blockade in conventional single-electron transistors requires applying voltage to the left base (LB) and right base (RB) to maintain the quantum well, which presents challenges. For example, the application of voltage can introduce additional signal influences on the quantum spin state. Furthermore, the application of voltage requires continuous power supply, increasing power consumption and heat dissipation, which is inconsistent with the ultra-low temperature operation of quantum devices.

[0027] In view of this, the present disclosure provides a FDSOI reconstruction device solution with ferroelectric-assisted quantum well formation.

[0028] Figure 1A The schematic diagram shows the structure of a semiconductor device according to an embodiment of the present disclosure.

[0029] like Figure 1A As shown, the semiconductor device 100 may include an SOI substrate 110 , a gate structure on the SOI substrate 110 , and a source 120 and a drain 130 on the SOI substrate located on opposite sides of the gate structure in a first direction.

[0030] According to an embodiment of the present disclosure, the SOI substrate 110 may include a base substrate 111, a buried oxide layer 112 on the base substrate, and an SOI layer 113 on the buried oxide layer 112. The base substrate 111 may include silicon (Si), the buried oxide layer 112 may include an oxide (e.g., silicon oxide), and the SOI layer 113 may include a suitable semiconductor material, such as the same semiconductor material as the base substrate 111, such as Si, or a semiconductor material different from the base substrate 111, such as SiGe. On the SOI substrate 110, an active region may be defined by, for example, local oxidation of silicon (LOCOS) isolation. Figure 1A One of the active regions is shown schematically.

[0031] According to an embodiment of the present disclosure, the gate structure includes a control gate electrode G0 and a first switching gate electrode G1 and a second switching gate electrode G2 located on opposite sides of the control gate electrode G0 in a first direction. The control gate electrode G0 includes a gate dielectric layer and a gate conductor layer atop the gate dielectric layer. The control gate electrode G0 can have a conventional MOSFET gate configuration, such as a high-k gate dielectric / metal gate configuration. Similarly, the first switching gate electrode G1 and the second switching gate electrode G2 each include a gate dielectric layer and a gate conductor layer atop the gate dielectric layer, with the gate dielectric layer comprising a ferroelectric material. For example, the ferroelectric material includes, but is not limited to, hafnium dioxide (HfO2) doped with a target element, the target element including at least one of silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), gadolinium (Gd), lanthanum (La), and strontium (Sr).

[0032] According to an embodiment of the present disclosure, the ferroelectric materials in the first switching gate electrode G1 and the second switching gate electrode G2 can be switched between different polarization states, and thus the semiconductor device can be reconfigured.

[0033] Figure 1B The schematic diagram shows a principle diagram of a semiconductor device according to an embodiment of the present disclosure.

[0034] Take the semiconductor device as an n-type device as an example. Figure 1B As shown in (a), a negative voltage may be applied to the first switching gate electrode G1 and the second switching gate electrode G2, so that the ferroelectric material in the first switching gate electrode G1 and the second switching gate electrode G2 has a first polarization state, for example, in a direction away from the SOI substrate (for example, Figure 1B(a) The upward direction within the paper. At this point, the channel regions corresponding to the first switching gate electrode G1 and the second switching gate electrode G2 are placed in an accumulation state. Furthermore, even if the negative voltage applied to the first switching gate electrode G1 and the second switching gate electrode G2 is removed, the polarization state of the ferroelectric material remains unchanged, and the corresponding channel region can therefore remain in the accumulation state. Alternatively, a positive voltage can be applied to the control gate electrode G0, placing the corresponding channel region in an inversion state. The electrons therein are located between the electrons in the accumulation state caused by the first switching gate electrode G1 and the second switching gate electrode G2, isolated from the electron reservoirs of the source 120 and the drain 130, forming an electron well. Consequently, the semiconductor device can operate as a single-electron transistor. At extremely low temperatures, quantum spin coupling between the control gate electrode G0 and the electron spin states of adjacent quantum dots is used to confine electrons with a specific spin orientation from the source 120 to the drain 130, thereby reading the electron spin state of the adjacent quantum dot.

[0035] On the other hand, Figure 1B As shown in (b), a positive voltage may be applied to the first switching gate electrode G1 and the second switching gate electrode G2 to make the ferroelectric material in the first switching gate electrode G1 and the second switching gate electrode G2 have a second polarization state, for example, along a direction close to the SOI substrate 110 (for example, Figure 1B (b) The polarization state is in the downward direction within the paper. At this point, the channel regions corresponding to the first switching gate electrode G1 and the second switching gate electrode G2 are placed in an inversion state. Furthermore, even if the positive voltage applied to the first switching gate electrode G1 and the second switching gate electrode G2 is removed, the polarization state remains unchanged, and the corresponding channel regions can therefore remain in an inversion state. Furthermore, a positive voltage can be applied to the control gate electrode G0, placing the corresponding channel regions in an inversion state. This results in the semiconductor device operating in the same manner as a conventional MOSFET.

[0036] The semiconductor device in the embodiment of the present disclosure may be configured to switch between a single electron transistor and a conventional MOSFET based on the polarization state of the ferroelectric material in the first switching gate electrode G1 and the second switching gate electrode G2 .

[0037] For example, the ferroelectric material in the first switching gate electrode G1 and the second switching gate electrode G2 can have a first polarization state, and the semiconductor device operates as a single electron transistor. The first switching gate electrode G1 and the second switching gate electrode G2 in the first polarization state form a quantum well structure between the source 120 and the drain 130.

[0038] Alternatively, the ferroelectric material in the first switching gate electrode G1 and the second switching gate electrode G2 may have a second polarization state different from the first polarization state, and the semiconductor device operates as a conventional MOSFET.

[0039] For example, the first polarization state may be a state of polarization in a direction away from the SOI substrate, and the second polarization state may be a state of polarization in a direction close to the SOI substrate.

[0040] For example, the ferroelectric materials in the first switching gate electrode G1 and the second switching gate electrode G2 switch between the first polarization state and the second polarization state in response to the voltage applied to the first switching gate electrode G1 and the second switching gate electrode G2, respectively, and maintain the switched polarization state after the applied voltage is removed.

[0041] As an n-type device, the source 120 and the drain 130 may each include an n-type doped region in the SOI layer 113. Furthermore, the semiconductor device may further include an n-type doped region in the SOI layer 113 between the control gate electrode G0 and the first and second switching gate electrodes G1 and G2. The n-type doped region between the control gate electrode G0 and the first and second switching gate electrodes G1 and G2 can reduce the spreading resistance of the semiconductor device.

[0042] According to an embodiment of the present disclosure, the reconstruction of the semiconductor device is achieved by controlling the first switching gate electrode G1 and the second switching gate electrode G2, so that the semiconductor device can be switched between different working states, thereby integrating the quantum state operation circuit and the peripheral reading circuit of the quantum device.

[0043] The polarization state of ferroelectric materials does not require voltage maintenance and can be maintained for more than ten years. It can reduce the mutual interference caused by continuous voltage application of multiple gates and reduce power consumption.

[0044] In the single-electron transistor state, the spin states of electrons in adjacent quantum dots can couple to the electron well below the control gate electrode G0. Electrons in the source 120 can only tunnel through the channel region below the control gate electrode G0 and reach the drain 130 if their spin directions match those of the electrons in the electron well below the control gate electrode G0, thereby achieving spin-to-charge conversion. Changes in the spin direction of electrons in the quantum dot cause changes in the current signal of the semiconductor device, which functions as a single-electron transistor. By comparing the current signal of the single-electron transistor with a set threshold, it is possible to determine whether the electrons in the quantum dot are in the spin-up or spin-down state.

[0045] According to an embodiment of the present disclosure, the present disclosure also provides a method for manufacturing a semiconductor device, including: forming a gate structure on a semiconductor-on-insulator (SOI) substrate, the gate structure including a control gate electrode and a first switching gate electrode and a second switching gate electrode respectively located on opposite sides of the control gate electrode in a first direction, wherein the first switching gate electrode and the second switching ferroelectric gate electrode each include a gate dielectric layer and a gate conductor layer on the gate dielectric layer, and the gate dielectric layer includes a ferroelectric material; and forming a source and a drain respectively on opposite sides of the gate structure in the first direction on the SOI substrate.

[0046] The gate structure is formed by forming a first sacrificial gate on an SOI substrate; forming a second sacrificial gate and a third sacrificial gate on opposite sides of the first sacrificial gate in a first direction on the SOI substrate; forming sidewalls on the sidewalls of the first sacrificial gate, the second sacrificial gate and the third sacrificial gate; replacing the second sacrificial gate and the third sacrificial gate with a first switching gate electrode and a second switching gate electrode, respectively; and replacing the first sacrificial gate with a control gate electrode.

[0047] Among them, the top surfaces of the second sacrificial gate and the third sacrificial gate are higher than the top surface of the first sacrificial gate; replacing the second sacrificial gate and the third sacrificial gate with the first switching gate electrode and the second switching gate electrode respectively includes: forming a filling layer on the SOI substrate, flattening the filling layer to expose the second sacrificial gate and the third sacrificial gate, and removing the second sacrificial gate and the third sacrificial gate, and forming the first switching gate electrode and the second switching gate electrode in the space released due to the removal of the second sacrificial gate and the third sacrificial gate; replacing the first sacrificial gate with the control gate electrode includes: further flattening to expose the first sacrificial gate, and removing the first sacrificial gate, and forming the control gate electrode in the space released due to the removal of the first sacrificial gate.

[0048] The present disclosure may be presented in various forms, some of which are described below. In the following description, reference is made to the selection of various materials. In addition to considering their function (for example, semiconductor materials are used to form active areas and dielectric materials are used to form electrical isolation), the selection of materials also takes into account etching selectivity. In the following description, the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when the following mentions etching a certain material layer, if it is not mentioned that other layers are also etched or it is not shown in the figure that other layers are also etched, then such etching can be selective, and the material layer can have etching selectivity relative to other layers exposed to the same etching recipe.

[0049] Figures 2 to 18 Some stages in a process of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically shown.

[0050] like Figure 2As shown, an SOI substrate 110 is provided. The SOI substrate 110 may include a base substrate 111, a buried oxide layer 112 on the base substrate, and an SOI layer 113 on the buried oxide layer 112. For example, the thickness of the SOI layer 113 may be approximately 10 to 55 nm, and the thickness of the buried oxide layer 112 may be approximately 20 to 145 nm. The SOI layer 113 may be thinned to a thickness of approximately 5 to 15 nm, for example, approximately 1 / 3 of the minimum channel length of the semiconductor device, to achieve full depletion.

[0051] like Figure 3 As shown, the active area A1 can be defined in the SOI layer 113 by, for example, using the LOCOS technology. For example, a SiO2 / SiN stack can be used as a hard mask to protect the active area A1, and a furnace oxidation process can be used to fully oxidize the non-active area portion of the SOI layer 113 not covered by the hard mask to serve as isolation between devices.

[0052] A sacrificial gate may be formed on the substrate, particularly an active region defined therein.

[0053] like Figure 4 As shown, a gate oxide layer 410, a first sacrificial layer 420, and a first hard mask layer 430 can be sequentially formed on the SOI substrate 110, for example, by deposition. For example, the gate oxide layer 410 can include SiO2 with a thickness of approximately 2.5 nm and be formed using an in-situ steam generation (ISSG) process. In this example, since the gate oxide layer 410, the buried oxide layer 112, and the LOCOS isolation layer are made of the same material (all oxide), they are displayed in the same color in the figure. The first sacrificial layer 420 can include amorphous silicon and can be approximately 100 nm thick. The first hard mask layer 430 can sequentially include a first hard mask oxide layer 431, a first hard mask nitride layer 432, and a first hard mask oxide layer 433. The first hard mask oxide layer 431 may include SiO 2 with a thickness of about 10-30 nm, the first hard mask nitride layer 432 may include SiN with a thickness of about 20-40 nm, and the first hard mask oxide layer 433 may include SiO 2 with a thickness of about 80-100 nm.

[0054] like Figure 5 As shown, the gate definition can be performed by electron beam. For example, the first sacrificial layer 420 and the first hard mask layer 430 can be etched, and the etching can be stopped at the gate oxide layer 410 to form a first sacrificial gate 510. The first sacrificial gate 510 can have a shape along the first direction ( Figure 5 A second direction ( Figure 5 A strip extending perpendicular to the paper.

[0055] like Figure 6 As shown, a second sacrificial layer 610, a second hardmask layer 620, and a mandrel layer 630 can be further formed on the substrate on which the first sacrificial gate 510 is formed, for example, by deposition. The second sacrificial layer 610 can include amorphous silicon and have a thickness sufficient to cover the already formed first sacrificial gate 510, for example, 150-200 nm. The second hardmask layer 620 can also include, in sequence, a second hardmask oxide layer 621, a second hardmask nitride layer 622, and a second hardmask oxide layer 623. The thickness and structure of the second hardmask layer 620 can be the same as those of the first hardmask layer 430 and will not be further described here. The mandrel layer 630 can include amorphous silicon and can be approximately 50-80 nm thick.

[0056] like Figure 7 As shown, the core mold layer 630 can be patterned into a strip extending along the second direction by, for example, photolithography. Figure 8 As shown, a sidewall spacer 810, such as a nitride (e.g., SiN) extending along the second direction, can be formed on the sidewall of the core mold layer 630 by a sidewall spacer transfer process. In the sidewall spacer formation process, a nitride with a thickness of about 5 to 10 nm can be deposited in a substantially conformal manner, and the deposited nitride is anisotropically etched. Then, as shown in FIG. Figure 9 As shown, the sidewall 810 can be used as an etching mask to etch downward, and the etching can stop at the gate oxide layer 410 to form a first sacrificial gate 510 on opposite sides in the first direction ( Figure 9 A second sacrificial gate 910 and a third sacrificial gate 920 are formed on the left and right sides of the control gate 510. The top surfaces of the second sacrificial gate 910 and the third sacrificial gate 920 are higher than the top surface of the first sacrificial gate 510, so that the formation of the first switching gate electrode G1 and the second switching gate electrode G2 does not affect the formation of the control gate electrode G0.

[0057] In this example, a spacer image transfer (SIT) process is used to form the second sacrificial gate 910 and the third sacrificial gate 920. Thus, three sacrificial gates can be formed through two photolithography steps, thereby reducing process variations.

[0058] like Figure 10 As shown, spacers 1010 can be formed on the sidewalls of the first sacrificial gate 510, the second sacrificial gate 910, and the third sacrificial gate 920. During the spacer formation process, a nitride layer with a thickness of approximately 20 to 40 nm can be deposited in a substantially conformal manner and anisotropically etched. Furthermore, the gate oxide layer 410 can be etched to expose the active area A1.

[0059] After forming the sacrificial gate, source / drain formation may be performed.

[0060] like Figure 11 As shown, using the first sacrificial gate 510, the second sacrificial gate 910, the third sacrificial gate 920 and the spacer 1010 as masks, n-type dopants are implanted into the SOI substrate, particularly the SOI layer, by, for example, ion implantation to form source and drain electrodes. The n-type dopant may include phosphorus (P), with an implantation energy of 10-20 KeV and a dose of 5-8E15 cm -2 The n-type dopant may also include arsenic (As) ions, with an implantation energy of 5 to 10 KeV and a dose of 5 to 8E15 cm 2 .

[0061] Next, a replacement gate process may be performed to replace each sacrificial gate with a control gate electrode or a switching gate electrode.

[0062] For example, Figure 12 and Figure 13 As shown, a filling layer 1210 is formed on the SOI substrate 110 and planarized, such as by chemical mechanical polishing (CMP), to expose the sacrificial layers of the second sacrificial gate 910 and the third sacrificial gate 920. The filling layer 1210 may comprise SiN and may have a thickness of 400-600 nm. The second sacrificial gate 910 and the third sacrificial gate 920 may be removed by selective wet etching.

[0063] like Figure 14 As shown, a first switching gate electrode G1 and a second switching gate electrode G2 are formed in the space freed by the removal of the second sacrificial gate 910 and the third sacrificial gate 920. For example, an interface oxide layer 1410 having a thickness of approximately 0.8 to 1 nm can be formed by ozone oxidation. A gate dielectric layer 1420, a work function layer 1430, and a gate conductor layer 1440 can be sequentially formed on the interface oxide layer 1410 by deposition. For example, the gate dielectric layer 1420 can include hafnium zirconium oxide (HZO) as a ferroelectric material layer having a thickness of approximately 5 to 15 nm, the work function layer 1430 can include TiN having a thickness of approximately 1 to 3 nm, and the gate conductor layer 1440 can include tungsten (W) having a thickness of approximately 70 to 100 nm.

[0064] like Figure 15 and Figure 16As shown, a further planarization process, such as chemical mechanical polishing (CMP), is performed to expose the sacrificial layer in the first sacrificial gate 510. This planarization process allows the first switch gate electrode G1 and the second switch gate electrode G2 to remain inside their respective spacers. Next, the first sacrificial gate 510 is removed, and the control gate electrode G0 is formed in the space created by the removal of the first sacrificial gate 510. For example, an interfacial oxide layer 1610 with a thickness of approximately 0.8-1 nm can be formed by ozone oxidation. A gate dielectric layer 1620, a work function layer 1630, and a gate conductor layer 1640 can be sequentially formed on the interfacial oxide layer 1610 by deposition. For example, the gate dielectric layer 1620 can include a high-k gate dielectric such as hafnium oxide (HfO2) with a thickness of approximately 2-4 nm, the work function layer 1630 can include TiN with a thickness of approximately 1-3 nm, and the gate conductor layer 1640 can include tungsten (W) with a thickness of approximately 70-100 nm. The gate dielectric layer 1620 may not include ferroelectric material.

[0065] like Figure 17 As shown, a planarization process such as chemical mechanical polishing (CMP) is further performed. Through the planarization process, the control gate electrode G0 can remain inside the corresponding sidewall spacer.

[0066] At this point, the semiconductor device according to the embodiment of the present disclosure has been substantially completed. Next, interconnection fabrication can be performed.

[0067] For example, 1 to 3 nm of TiN can be grown first to act as a diffusion barrier layer and as a seed layer for the growth of the metal electrode, and then a 70 to 100 nm metal layer can be grown. The metal layer can be W, and the diffusion barrier layer and the metal layer are etched to form landing pads for the contact parts of the control gate electrode G0, the first switching gate electrode G1, and the second switching gate electrode G2.

[0068] like Figure 18 As shown, an isolation layer 1810 may be formed on the filling layer 1210, the control gate electrode G0, the first switching gate electrode G1, and the second switching gate electrode G2. For example, the isolation layer 1810 may have a thickness of 300-500 nm and may be made of SiO2.

[0069] Referring back to Figure 1 , a contact portion can be formed in isolation layer 1810. For example, a contact hole can be formed in isolation layer 1810 using photolithography. A 1-3 nm layer of TiN is grown in the contact hole to act as a diffusion barrier and a seed layer for W growth. A metal layer, which can be 100-300 nm of W, is then formed using chemical vapor deposition (CVD). A planarization process, such as CMP, can be performed, stopping at isolation layer 1810, so that the diffusion barrier and metal layers remain within the contact hole. Alternatively, a 20-40 nm layer of TiN can be deposited, followed by photolithography or etching to form the electrode pattern.

[0070] The semiconductor device according to the embodiment of the present disclosure can be applied to silicon-based quantum devices. By controlling the first switching gate electrode G1 and the second switching gate electrode G2, the semiconductor device is reconstructed, so that the semiconductor device can be switched between different working states, thereby integrating the quantum state operation circuit and the peripheral reading circuit of the quantum device.

[0071] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0072] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A semiconductor device comprising: Semiconductor-on-insulator SOI substrate; The gate structure on the SOI substrate includes a control gate electrode and a first switching gate electrode and a second switching gate electrode located on opposite sides of the control gate electrode in a first direction; and a source and a drain located on opposite sides of the gate structure in the first direction on the SOI substrate, The first switching gate electrode and the second switching gate electrode each include a gate dielectric layer and a gate conductor layer on the gate dielectric layer, and the gate dielectric layer includes a ferroelectric material. 2 . The semiconductor device according to claim 1 , configured to switch between a single electron transistor and a metal oxide semiconductor field effect transistor (MOSFET) based on a polarization state of a ferroelectric material in the first switching gate electrode and the second switching gate electrode.

3. The semiconductor device according to claim 1 or 2, wherein The ferroelectric material in the first switching gate electrode and the second switching gate electrode has a first polarization state, and the semiconductor device operates as a single electron transistor, or The ferroelectric material in the first switching gate electrode and the second switching gate electrode has a second polarization state different from the first polarization state, and the semiconductor device operates as a MOSFET.

4. The semiconductor device according to claim 3, wherein The first polarization state is a state of polarization in a direction away from the SOI substrate, and the second polarization state is a state of polarization in a direction close to the SOI substrate.

5. The semiconductor device according to claim 3, wherein The first switching gate electrode and the second switching gate electrode in the first polarization state result in a quantum well structure being formed between a source and a drain. The semiconductor device according to claim 3 , wherein: The ferroelectric materials in the first switching gate electrode and the second switching gate electrode switch between a first polarization state and a second polarization state in response to a voltage applied to the first switching gate electrode and the second switching gate electrode, respectively, and maintain the switched polarization state after the applied voltage is removed.

7. The semiconductor device according to claim 1 or 2, wherein: The ferroelectric material includes hafnium dioxide doped with a target element, the target element including at least one of silicon, aluminum, zirconium, yttrium, gadolinium, lanthanum, and strontium.

8. The semiconductor device according to claim 1 or 2, wherein The SOI substrate includes a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer. The source and the drain respectively include n-type doping regions on both sides of the gate structure in the SOI layer, The semiconductor device further includes n-type doping regions in the SOI layer respectively between the control gate electrode and the first and second switching gate electrodes.

9. A method for manufacturing a semiconductor device, comprising: forming a gate structure on a semiconductor-on-insulator (SOI) substrate, the gate structure comprising a control gate electrode and a first switching gate electrode and a second switching gate electrode located on opposite sides of the control gate electrode in a first direction, wherein the first switching gate electrode and the second switching gate electrode each comprise a gate dielectric layer and a gate conductor layer on the gate dielectric layer, the gate dielectric layer comprising a ferroelectric material; A source and a drain are respectively formed on two opposite sides of the gate structure in the first direction on the SOI substrate.

10. The method according to claim 9, wherein: Forming the gate structure includes: forming a first sacrificial gate on the SOI substrate; forming a second sacrificial gate and a third sacrificial gate on opposite sides of the first sacrificial gate in the first direction on the SOI substrate; forming sidewall spacers on sidewalls of the first sacrificial gate, the second sacrificial gate, and the third sacrificial gate; replacing the second sacrificial gate and the third sacrificial gate with the first switching gate electrode and the second switching gate electrode, respectively; and The first sacrificial gate is replaced by the control gate electrode.

11. The method according to claim 10, wherein: The top surfaces of the second sacrificial gate and the third sacrificial gate are higher than the top surface of the first sacrificial gate; Replacing the second sacrificial gate and the third sacrificial gate with the first switching gate electrode and the second switching gate electrode, respectively, comprises: forming a filling layer on the SOI substrate, performing a planarization process on the filling layer to expose the second sacrificial gate and the third sacrificial gate, and removing the second sacrificial gate and the third sacrificial gate, and forming the first switching gate electrode and the second switching gate electrode in spaces released by the removal of the second sacrificial gate and the third sacrificial gate; Replacing the first sacrificial gate with the control gate electrode includes: Further performing a planarization process to expose the first sacrificial gate, and The first sacrificial gate is removed, and the control gate electrode is formed in a space released by the removal of the first sacrificial gate.

12. The method according to claim 10, further comprising: N-type dopants are implanted into the SOI substrate using the first sacrificial gate, the second sacrificial gate, the third sacrificial gate and the sidewall as masks.

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