Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first region and a second region, and the device working voltage of the first region is smaller than the device working voltage of the second region; the fin parts are separately arranged on the substrate in the first region and the second region; the isolation layer is located on the substrate and surrounds part of the side walls of the fin parts, the fin parts exposed by the isolation layer serve as effective fin parts, and the height of the effective fin parts in the first region is larger than that of the effective fin parts in the second region; the first gate dielectric layer is positioned on the effective fin part of the second region; the second gate dielectric layer is located on the effective fin part of the first region, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer; and the gate layer stretches across the effective fin part and covers the first gate dielectric layer and the second gate dielectric layer, and the gate layer covers part of the top and part of the side wall of the effective fin part. According to the embodiment of the invention, the depth-to-width ratio of the space defined by the first gate dielectric layer and the isolation layer is reduced, and the probability of generating defects such as gaps and holes in the gate layer of the second region is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to advance towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] To better adapt to the requirement of device size reduction, semiconductor technology has gradually begun to transition from planar transistors to more efficient three-dimensional transistors, such as FinFETs. In FinFETs, the gate surrounds a fin-shaped channel on three sides. Compared with planar transistors, the gate of FinFETs has stronger control over the channel and can better suppress short channel effects.

[0004] However, the performance of FinFETs still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region, the device operating voltage in the first region being lower than the device operating voltage in the second region; a fin, separated on the substrate in the first and second regions; an isolation layer, located on the substrate and surrounding a portion of the sidewall of the fin, the fin exposed by the isolation layer serving as an effective fin, the effective fin height in the first region being greater than the effective fin height in the second region; a first gate dielectric layer, located on the effective fin in the second region; a second gate dielectric layer, located on the effective fin in the first region, the thickness of the second gate dielectric layer being lower than the thickness of the first gate dielectric layer; a gate layer, spanning the effective fin and covering the first and second gate dielectric layers, the gate layer covering a portion of the top and a portion of the sidewall of the effective fin.

[0007] Accordingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region, the device operating voltage of the first region being lower than the device operating voltage of the second region, and fins separated from each other are formed on the substrates of the first region and the second region; forming an isolation layer surrounding the fins on the substrate on the sides of the fins, the fins exposed by the isolation layer serving as effective fins, the effective fin height of the first region being greater than the effective fin height of the second region; forming a first gate dielectric layer on the effective fins of the second region; forming a second gate dielectric layer on the effective fins of the first region, the thickness of the second gate dielectric layer being lower than the thickness of the first gate dielectric layer; forming a gate layer across the effective fins on the first gate dielectric layer and the second gate dielectric layer, the gate layer covering part of the top and part of the sidewalls of the effective fins.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] The semiconductor structure provided by an embodiment of the present invention includes an isolation layer located on the substrate and surrounding a portion of the sidewall of the fin, the fin exposed by the isolation layer serving as an effective fin, the effective fin height of the first region being greater than the effective fin height of the second region, a first gate dielectric layer located on the effective fin of the second region, and a second gate dielectric layer located on the effective fin of the first region, wherein the thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer. Although the thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer, the effective fin height of the second region is less than the effective fin height of the first region, thereby reducing the aspect ratio of the space enclosed by the first gate dielectric layer and the isolation layer between adjacent effective fins in the second region. Accordingly, during the formation of the gate layer, the top of the space is less likely to be prematurely closed, thereby reducing the probability of defects such as seams and voids in the gate layer of the second region, improving the uniformity of the gate layer thickness, and correspondingly improving the uniformity of semiconductor device performance, thereby improving the performance of the semiconductor structure.

[0010] In a method for forming a semiconductor structure provided by an embodiment of the present invention, an isolation layer is formed on a substrate surrounding the fin on the side of the fin, and the fin exposed by the isolation layer serves as an effective fin. The effective fin height in the first region is greater than that in the second region. A first gate dielectric layer is formed on the effective fin in the second region, and a second gate dielectric layer is formed on the effective fin in the first region. The thickness of the first gate dielectric layer is greater than that of the second gate dielectric layer. Although the thickness of the first gate dielectric layer is greater than that of the second gate dielectric layer, the effective fin height in the second region is less than that in the first region. This reduces the aspect ratio of the space enclosed by the first gate dielectric layer and the isolation layer between adjacent effective fins in the second region. Consequently, during the formation of the gate layer, the top of the space is less likely to be prematurely closed, thereby reducing the probability of defects such as gaps and voids forming in the gate layer in the second region, improving the uniformity of the gate layer thickness, and correspondingly improving the uniformity of semiconductor device performance, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 9 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figure 10 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0013] Figure 11 yes Figure 10 A schematic diagram of the structure after omitting the second gate dielectric layer and the gate layer;

[0014] Figures 12 to 22 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0015] Currently, the performance of semiconductor structures still needs to be improved. This paper analyzes the reasons why the performance of semiconductor structures needs to be improved by combining a method for forming a semiconductor structure. Figures 1 to 9 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1 A substrate 10 is provided, the substrate including a first region i' and a second region ii', the device operating voltage of the first region i' is lower than the device operating voltage of the second region ii', and separate fins 11 are formed on the substrate 10 in the first region i' and the second region ii'.

[0017] refer to Figures 2 to 3 An isolation layer 12 surrounding the fin 11 is formed on the substrate 10 at the side of the fin 11 , and the fin 11 exposed by the isolation layer 12 serves as an effective fin 13 .

[0018] refer to Figures 4 and 5 , a first gate dielectric layer 14 is formed on the active fin 13 in the second region ii′.

[0019] refer to Figure 6 A second gate dielectric layer 15 is formed on the active fin 13 of the first region i′. The thickness of the second gate dielectric layer 15 is less than that of the first gate dielectric layer 14 .

[0020] refer to Figures 7 to 9 , Figure 9 for Figure 8 In the partial enlarged view of region A, a gate layer 16 is formed on the first gate dielectric layer 14 and the second gate dielectric layer 15 across the active fin 13 , and the gate layer 16 covers a portion of the top and a portion of the sidewall of the active fin 13 .

[0021] Through research, it is found that since the device operating voltage of the first region i' is lower than the device operating voltage of the second region ii', that is, the device operating voltage of the second region ii' is higher than the device operating voltage of the first region i', the thickness of the first gate dielectric layer 14 located in the second region ii' needs to be greater than the thickness of the second gate dielectric layer 15 located in the first region i', that is, the thickness of the second gate dielectric layer 15 is less than the thickness of the first gate dielectric layer 14. Accordingly, the depth and width of the space enclosed by the first gate dielectric layer 14 and the isolation layer 12 between adjacent effective fins 13 in the second region ii' are relatively large, so that in the process of forming the gate layer 16, the top position of the space is easily closed prematurely, thereby generating defects such as gaps 17 and voids in the gate layer 16 of the second region ii' (such as Figure 9 As shown in FIG, the thickness of the gate layer 16 is not uniform, thereby affecting the performance of the semiconductor structure.

[0022] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a first region and a second region, the device operating voltage of the first region is lower than the device operating voltage of the second region; a fin, separated on the substrate in the first and second regions; an isolation layer, located on the substrate and surrounding a portion of the sidewall of the fin, the fin exposed by the isolation layer serving as an effective fin, the effective fin height of the first region being greater than the effective fin height of the second region; a first gate dielectric layer, located on the effective fin of the second region; a second gate dielectric layer, located on the effective fin of the first region, the thickness of the second gate dielectric layer being lower than the thickness of the first gate dielectric layer; a gate layer, spanning the effective fin and covering the first and second gate dielectric layers, the gate layer covering a portion of the top and a portion of the sidewall of the effective fin.

[0023] The semiconductor structure provided by an embodiment of the present invention includes an isolation layer located on the substrate and surrounding a portion of the sidewall of the fin, the fin exposed by the isolation layer serving as an effective fin, the effective fin height in the first region being greater than the effective fin height in the second region, a first gate dielectric layer located on the effective fin in the second region, and a second gate dielectric layer located on the effective fin in the first region, wherein the thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer. Although the thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer, the effective fin height in the second region is less than the effective fin height in the first region, thereby reducing the aspect ratio of the space enclosed by the first gate dielectric layer and the isolation layer between adjacent effective fins in the second region. Accordingly, during the formation of the gate layer, the top of the space is less likely to be prematurely closed, thereby reducing the probability of defects such as gaps and voids in the gate layer in the second region, improving the uniformity of the gate layer thickness, and correspondingly improving the uniformity of semiconductor device performance, thereby improving the performance of the semiconductor structure.

[0024] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] Figure 10 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention; Figure 11 yes Figure 10 The schematic diagram of the structure after the second gate dielectric layer and the gate layer are omitted.

[0026] refer to Figures 10 and 11 In this embodiment, the semiconductor structure includes: a substrate 100, the substrate 100 including a first region i and a second region ii, wherein the device operating voltage of the first region i is lower than the device operating voltage of the second region ii; a fin 110, separated on the substrate 100 in the first region i and the second region ii; an isolation layer 120, located on the substrate 100 and surrounding a portion of the sidewall of the fin 110, the fin 110 exposed by the isolation layer 120 serving as an effective fin 111, the effective fin 111 of the first region i having a height greater than that of the effective fin 111 of the second region ii; a first gate dielectric layer 140, located on the effective fin 111 of the second region ii; a second gate dielectric layer 150, located on the effective fin 111 of the first region i, the thickness of the second gate dielectric layer 150 being lower than the thickness of the first gate dielectric layer 140; and a gate layer 160, spanning the effective fin 111 and covering the first gate dielectric layer 140 and the second gate dielectric layer 150, wherein the gate layer 160 covers a portion of the top and a portion of the sidewall of the effective fin 111.

[0027] Here, the height of the effective fin 111 refers to the distance along the normal direction of the top surface of the substrate 100 .

[0028] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0029] In this embodiment, the substrate 100 is used to form a field effect transistor. As an example, the substrate 100 is used to form a fin field effect transistor.

[0030] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0031] The substrate 100 includes a first region i and a second region ii.

[0032] The first region i and the second region ii are used to form field effect transistors with different operating voltages.

[0033] In this embodiment, the first area i is used to form a core device, and the second area ii is used to form an input / output device (I / O device).

[0034] Core devices mainly refer to the devices used inside the chip, which usually use a lower voltage and a higher operating frequency; input / output devices usually refer to the devices used when the chip interacts with external interfaces. The operating voltage of such devices is generally higher. The operating voltage of input / output devices is usually greater than the operating voltage of core devices, and the operating frequency of input / output devices is usually less than the operating frequency of core devices.

[0035] The fin 110 provides a process basis for forming the effective fin 111 .

[0036] In this embodiment, the material of the fin 110 includes silicon. In other embodiments, the material of the fin may also include other materials such as germanium, silicon germanium, and Group III-V semiconductor materials.

[0037] As an example, the fin 110 and the substrate 100 are an integral structure.

[0038] The isolation layer 120 is used to isolate adjacent fins 110 and to isolate the substrate 100 from various semiconductor devices.

[0039] In this embodiment, the isolation layer 120 is a shallow trench isolation (STI) structure. As an example, the material of the isolation layer 120 is silicon oxide. In other embodiments, the material of the isolation layer can also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0040] In this embodiment, along the normal direction of the top surface of the substrate 100 , the thickness of the isolation layer 120 in the first region i is less than the thickness of the isolation layer 120 in the second region ii.

[0041] The steps for forming the isolation layer 120 generally include: forming an isolation material layer (not shown) surrounding the fin 110 on the substrate 100 at the side of the fin 110, the isolation material layer covering the top and sidewalls of the fin 110; removing a first portion of the thickness of the isolation material layer in the second region ii to form an effective fin 111 in the second region ii; removing a second portion of the thickness of the isolation material layer in the first region i to form an effective fin 111 in the first region i, the second portion being thicker than the first portion; after removing the first portion of the thickness of the isolation material layer in the second region ii and the second portion of the thickness of the isolation material layer in the first region i, the remaining isolation material layer serves as the isolation layer 120. Therefore, the thickness of the isolation layer 120 in the first region i is less than that in the second region ii, facilitating that the height of the effective fin 111 in the first region i is greater than that of the effective fin 111 in the second region ii.

[0042] In other embodiments, the fin height of the first region may be greater than that of the second region, so that when the isolation layer thickness of the first region is equal to that of the second region, the effective fin height of the first region is still greater than that of the second region.

[0043] The active fin 111 is used to provide a conductive channel when the semiconductor device is in operation.

[0044] Although the thickness of the first gate dielectric layer 140 is greater than the thickness of the second gate dielectric layer 150, the height of the effective fin 111 in the first region i is greater than the height of the effective fin 111 in the second region ii, thereby reducing the aspect ratio of the space 142 enclosed by the first gate dielectric layer 140 and the isolation layer 120 between adjacent effective fins 111 in the second region ii. Accordingly, in the process of forming the gate layer 160, the top position of the space 142 is not easily closed prematurely, thereby reducing the probability of defects such as gaps and voids in the gate layer 160 in the second region ii, improving the uniformity of the thickness of the gate layer 160, and correspondingly improving the uniformity of the performance of the semiconductor device, thereby improving the performance of the semiconductor structure.

[0045] In this embodiment, the first region i is used to form the core device, and the second region ii is used to form the input / output device. The operating frequency of the input / output device is generally lower than the operating frequency of the core device. Therefore, the effective fin 111 height of the first region i is greater than the effective fin 111 height of the second region ii, that is, the effective fin 111 height of the second region ii is lower than the effective fin 111 height of the first region i, which has little impact on the operating frequency of the input / output device.

[0046] It should be noted that, along the normal direction of the top surface of the substrate 100, the height difference between the effective fins 111 in the first region i and the effective fins 111 in the second region ii should not be too small or too large. If the height difference between the effective fins 111 in the first region i and the effective fins 111 in the second region ii is too small, it is likely that the aspect ratio of the space 142 enclosed by the first gate dielectric layer 140 and the isolation layer 120 between adjacent effective fins 111 in the second region ii will be reduced. If the height difference between the effective fins 111 in the first region i and the effective fins 111 in the second region ii is too large, it is likely that the height of the effective fins 111 in the second region ii will be too small, making it difficult to meet design requirements. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 100, the height difference between the effective fins 111 in the first region i and the effective fins 111 in the second region ii is 50 angstroms to 200 angstroms.

[0047] The first gate dielectric layer 140 is used to isolate the gate layer 160 from the substrate 100 in the second region ii.

[0048] In this embodiment, the material of the first gate dielectric layer 140 is a dielectric material. As an example, the material of the first gate dielectric layer 140 is silicon oxide. In other embodiments, the material of the first gate dielectric layer can also be other suitable dielectric materials.

[0049] It should be noted that the depth-to-width ratio of the space 142 enclosed by the first gate dielectric layer 140 and the isolation layer 120 between adjacent active fins 111 in the second region ii should not be too large. If the aspect ratio of the space 142 enclosed by the first gate dielectric layer 140 and the isolation layer 120 is too large, it may be difficult to effectively reduce defects such as gaps and voids in the gate layer 160 in the second region ii during the formation of the gate layer 160. Therefore, in this embodiment, the aspect ratio of the space 142 enclosed by the first gate dielectric layer 140 and the isolation layer 120 between adjacent active fins 111 in the second region ii is less than 1.5:1.

[0050] The second gate dielectric layer 150 is used to isolate the gate layer 160 from the substrate 100 in the first region i.

[0051] Since the device operating voltage of the first region i is lower than that of the second region II, the thickness requirement of the second gate dielectric layer 150 is also correspondingly smaller. Therefore, the thickness of the second gate dielectric layer 150 is lower than that of the first gate dielectric layer 140 .

[0052] Although the thickness of the first gate dielectric layer 140 is greater than the thickness of the second gate dielectric layer 150, the height of the effective fin 111 in the second region ii is less than the height of the effective fin 111 in the first region i, thereby reducing the aspect ratio of the space 142 enclosed by the first gate dielectric layer 140 and the isolation layer 120 between adjacent effective fins 111 in the second region ii. Accordingly, in the process of forming the gate layer 160, the top position of the space 142 is not easily closed prematurely, thereby reducing the probability of defects such as gaps and voids in the gate layer 160 in the second region ii, improving the uniformity of the thickness of the gate layer 160, and correspondingly improving the uniformity of the performance of the semiconductor device, thereby improving the performance of the semiconductor structure.

[0053] In this embodiment, the material of the second gate dielectric layer 150 is a dielectric material. As an example, the material of the second gate dielectric layer 150 is silicon oxide. In other embodiments, the material of the second gate dielectric layer can also be other suitable dielectric materials.

[0054] In this embodiment, the second gate dielectric layer 150 further covers the first gate dielectric layer 140 .

[0055] The second gate dielectric layer 150 also covers the first gate dielectric layer 140 , which is beneficial to simplifying the process steps and saving process costs.

[0056] The gate layer 160 is used to control the opening or closing of the conductive channel when the device is in operation.

[0057] In this embodiment, the gate layer 160 includes one or more work function layers 161 .

[0058] The work function layer 161 is used to adjust the work function of the gate layer 160 , thereby adjusting the threshold voltage of the field effect transistor.

[0059] It should be noted that since the threshold voltage requirements of the field-effect transistors in each region may vary, the thickness of the work function layer 161 in each region may also vary accordingly. Therefore, it is necessary to provide different numbers of work function layers in each region to adjust the threshold voltage requirements of the field-effect transistors in each region.

[0060] It should also be noted that reducing the probability of defects such as gaps and voids in the gate layer 160 in the second region ii is also beneficial to improving the uniformity of the thickness of the work function layer 161.

[0061] Specifically, when an NMOS transistor is formed, the work function layer 161 is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when a PMOS transistor is formed, the work function layer 161 is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.

[0062] In this embodiment, the gate layer 160 further includes a gate electrode layer (not shown) covering the work function layer 161 .

[0063] The gate electrode layer is used as an external electrode for electrically connecting the gate layer 160 to an external circuit.

[0064] Specifically, the gate electrode layer 160 is made of a conductive material, such as titanium aluminide, tungsten, aluminum, copper, silver, gold, platinum, nickel or titanium.

[0065] In this embodiment, the semiconductor structure also includes: a gate sidewall (not shown), located on the side wall of the gate layer; a source and drain doped layer (not shown), located in the effective fin 111 on both sides of the gate layer 160; and an interlayer dielectric layer (not shown), covering the source and drain doped layer and the top of the gate layer 160.

[0066] The gate spacer is used to define the formation position of the source and drain doped layers during the process of forming the source and drain doped layers, and is also used to protect the sidewalls of the gate layer 160. The gate spacer can be a single-layer structure or a stacked structure, and the material of the gate spacer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon nitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0067] The source / drain doped layers are used to serve as the source or drain regions of the transistor being formed. Specifically, the material of the source / drain doped layers may include silicon germanium doped with P-type ions, such as B, Ga, or In. The material of the source / drain doped layers may also include silicon or silicon carbide doped with N-type ions, such as P, As, or Sb.

[0068] The interlayer dielectric layer is used to isolate adjacent devices. Specifically, the material of the interlayer dielectric layer includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, and silicon oxynitride.

[0069] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 12 to 22 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0070] refer to Figure 12 A substrate 500 is provided, the substrate 500 includes a first region I and a second region II, the device operating voltage of the first region I is lower than the device operating voltage of the second region II, and separate fins 510 are formed on the substrate 500 in the first region I and the second region II.

[0071] The substrate 500 is used to provide a process platform for subsequent process steps.

[0072] In this embodiment, the substrate 500 is used to form a field effect transistor. As an example, the substrate 500 is used to form a fin field effect transistor.

[0073] In this embodiment, the substrate 500 is a silicon substrate. In other embodiments, the substrate material may be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0074] The substrate 500 includes a first region I and a second region II.

[0075] The first region I and the second region II are used to form field effect transistors with different operating voltages.

[0076] In this embodiment, the first region I is used to form core devices, and the second region II is used to form input / output devices.

[0077] Core devices mainly refer to the devices used inside the chip, which usually use a lower voltage and a higher operating frequency; input / output devices usually refer to the devices used when the chip interacts with external interfaces. The operating voltage of such devices is generally higher. The operating voltage of input / output devices is usually greater than the operating voltage of core devices, and the operating frequency of input / output devices is usually less than the operating frequency of core devices.

[0078] The fin 510 provides a process foundation for the subsequent formation of effective fins.

[0079] In this embodiment, the material of the fin 510 includes silicon. In other embodiments, the material of the fin may also include other materials such as germanium, silicon germanium, and Group III-V semiconductor materials.

[0080] As an example, the fin 510 and the substrate 500 are an integral structure.

[0081] refer to Figures 13 to 17 An isolation layer 520 surrounding the fin 510 is formed on the substrate 500 on the side of the fin 510, and the fin 510 exposed by the isolation layer 520 serves as an effective fin 511. The height of the effective fin 511 in the first region I is greater than the height of the effective fin 511 in the second region II.

[0082] Here, the height of the effective fin 511 refers to the distance along the normal direction of the top surface of the substrate 500 .

[0083] The isolation layer 520 is used to isolate adjacent fins 510 and to isolate the substrate 500 from various semiconductor devices formed subsequently.

[0084] In this embodiment, the isolation layer 520 is a shallow trench isolation structure. As an example, the material of the isolation layer 520 is silicon oxide. In other embodiments, the material of the isolation layer can also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0085] In this embodiment, the steps of forming the isolation layer 520 include: Figure 13 As shown, an isolation material layer 521 surrounding the fin 510 is formed on the substrate 500 at the side of the fin 510, and the isolation material layer 521 covers the top and sidewalls of the fin 510; Figure 14 As shown, the first portion of the thickness of the isolation material layer 521 in the second region II is removed to form an effective fin 511 in the second region II; the second portion of the thickness of the isolation material layer 521 in the first region I is removed to form an effective fin 511 in the first region I, and the thickness of the second portion is greater than the thickness of the first portion; after removing the first portion of the thickness of the isolation material layer 521 in the second region II and removing the second portion of the thickness of the isolation material layer 521 in the first region I, the remaining isolation material layer 521 serves as an isolation layer 520.

[0086] First, an isolation material layer 521 surrounding the fin 510 is formed on the substrate 500 on the side of the fin 510, and then the first portion of the thickness of the isolation material layer 521 in the second region II is removed, and the second portion of the thickness of the isolation material layer 521 in the first region I is removed. The thickness of the second portion is greater than the thickness of the first portion, so that the thickness of the remaining isolation material layer 521 in the second region II is greater than the thickness of the remaining isolation material layer 521 in the first region I, thereby making the effective fin 511 height of the first region I greater than the effective fin 511 height of the second region II.

[0087] In other embodiments, in the step of providing the substrate, the fin height of the first region can be made greater than the fin height of the second region, so that in the step of forming the isolation layer, when the thickness of the isolation layer in the first region is equal to the thickness of the isolation layer in the second region, the effective fin height of the first region is still greater than the effective fin height of the second region.

[0088] Specifically, the step of removing the second portion of the thickness of the isolation material layer 521 in the first region I includes: in the step of removing the first portion of the thickness of the isolation material layer 521 in the second region II, removing the first portion of the thickness of the isolation material layer 521 in the second region II and the first region I (e.g., Figure 14 After removing the first portion of the thickness of the isolation material layer 521, the third portion of the thickness of the isolation material layer 521 in the first region I is removed, and the sum of the thickness of the first portion and the thickness of the third portion is the thickness of the second portion (as shown); Figure 16 shown).

[0089] In the step of removing the first portion of the thickness of the isolation material layer 521 in the second region II, after removing the first portion of the thickness of the isolation material layer 521 in the second region II and the first region I, the third portion of the thickness of the isolation material layer 521 in the first region I is removed. The sum of the thickness of the first portion and the thickness of the third portion is the thickness of the second portion, which is conducive to reducing the difficulty of removing the second portion of the thickness of the isolation material layer 521 in the first region I, and is also conducive to combining with the existing process flow.

[0090] More specifically, the process of removing the third portion of the thickness of the isolation material layer 521 in the first region I includes a dry etching process.

[0091] The dry etching process can more evenly remove the third portion of the thickness of the isolation material layer 521 in the first region I, thereby facilitating better thickness uniformity of the isolation layer 520 and facilitating integration with existing process steps.

[0092] In this embodiment, after removing the first portion of the thickness of the isolation material layer 521 in the second region II and the first region I, and before removing the third portion of the thickness of the isolation material layer 521 in the first region I, the method further includes: forming a first mask layer 530 (such as Figure 15 In the process of removing the third portion of the thickness of the isolation material layer 521 in the first region I, the first mask layer 530 is used to protect the isolation material layer 521 in the second region II (as shown); Figure 16 After forming the isolation layer 520, the method further includes: removing the first mask layer 530 (as shown in FIG. Figure 17 shown).

[0093] Before removing the third portion of the thickness of the isolation material layer 521 in the first region I, a first mask layer 530 is formed on the isolation material layer 521 in the second region II, so that during the process of removing the third portion of the thickness of the isolation material layer 521 in the first region I, the first mask layer 530 can protect the isolation material layer 521 in the second region II, thereby reducing the probability of damage to the isolation material layer 521 in the second region II, improving the quality of the isolation material layer 521 in the second region II, and correspondingly improving the quality of the isolation layer 520 in the second region II, and also reducing the difficulty of removing the third portion of the thickness of the isolation material layer 521 in the first region I.

[0094] It should be noted that the process of forming the first mask layer 530 includes a spin coating process, an exposure process, and a development process, which have the characteristics of high process maturity and low process cost.

[0095] It should also be noted that, in the step of forming the first mask layer 530 , the material of the first mask layer 530 includes photoresist.

[0096] The material of the first mask layer 530 includes photoresist, which facilitates the subsequent removal of the first mask layer 530. In other embodiments, the first mask layer may also be other spin-on materials or other materials that can make the first mask layer 530 have better flatness.

[0097] It should be noted that the process of removing the first mask layer 530 includes one or both of a dry etching process and a wet cleaning process.

[0098] The dry etching process is a commonly used process in semiconductor technology and has a high degree of maturity.

[0099] The wet cleaning process is convenient for removing impurities and has the characteristics of low process cost and simple operation.

[0100] The active fin 511 is used to provide a conductive channel when the semiconductor device is in operation.

[0101] Although the thickness of the first gate dielectric layer formed subsequently is greater than the thickness of the second gate dielectric layer, the height of the effective fin 511 in the first region I is greater than the height of the effective fin 511 in the second region II, thereby reducing the aspect ratio of the space enclosed by the first gate dielectric layer and the isolation layer 520 between adjacent effective fins 511 in the second region II. Accordingly, in the process of subsequently forming the gate layer, the top position of the space is not easily closed prematurely, thereby reducing the probability of defects such as gaps and voids in the gate layer of the second region II, improving the uniformity of the gate layer thickness, and correspondingly improving the uniformity of the performance of the semiconductor device, thereby improving the performance of the semiconductor structure.

[0102] In this embodiment, the first region I is used to form the core device, and the second region II is used to form the input / output device. The operating frequency of the input / output device is generally lower than the operating frequency of the core device. Therefore, the effective fin 511 height of the first region I is greater than the effective fin 511 height of the second region II, that is, the effective fin 511 height of the second region II is less than the effective fin 511 height of the first region I, which has little impact on the operating frequency of the input / output device.

[0103] It should be noted that the height difference between the effective fins 511 in the first region I and the effective fins 511 in the second region II should not be too small or too large. If the height difference between the effective fins 511 in the first region I and the effective fins 511 in the second region II is too small, it is likely that the aspect ratio of the space enclosed by the first gate dielectric layer and the isolation layer 520 between adjacent effective fins 511 in the second region II will be reduced. If the height difference between the effective fins 511 in the first region I and the effective fins 511 in the second region II is too large, it is likely that the height of the effective fins 511 in the second region II will be too small, making it difficult to meet design requirements. Therefore, in this embodiment, in the step of forming the isolation layer 520, the height difference between the effective fins 511 in the first region I and the effective fins 511 in the second region II is 50 angstroms to 200 angstroms along the normal direction of the top surface of the substrate 500.

[0104] refer to Figures 18 and 19 , a first gate dielectric layer 540 is formed on the active fin 511 in the second region II.

[0105] The first gate dielectric layer 540 is used to isolate a subsequently formed gate layer from the substrate 500 in the second region II.

[0106] In this embodiment, the material of the first gate dielectric layer 540 is a dielectric material. As an example, the material of the first gate dielectric layer 540 is silicon oxide. In other embodiments, the material of the first gate dielectric layer can also be other suitable dielectric materials.

[0107] In this embodiment, the step of forming the first gate dielectric layer 540 includes: forming an initial first gate dielectric layer 541 (eg, Figure 18 ); forming a second mask layer (not shown) on the initial first gate dielectric layer 541 in the second region II, the second mask layer and the first mask layer are formed by the same mask; removing the initial first gate dielectric layer 541 in the first region I, and the remaining initial first gate dielectric layer 541 is used as the first gate dielectric layer 540 (as shown); forming a second mask layer (not shown) on the initial first gate dielectric layer 541 in the second region II, and the second mask layer and the first mask layer are formed by the same mask; removing the initial first gate dielectric layer 541 in the first region I, and the remaining initial first gate dielectric layer 541 is used as the first gate dielectric layer 540 (as shown); Figure 19 After forming the first gate dielectric layer 540, the method further includes: removing the second mask layer.

[0108] The second mask layer and the first mask layer 530 are formed by using the same photomask, which helps to save the number of photomasks and further reduces the process cost of integrated circuit manufacturing.

[0109] In this embodiment, the process for forming the first gate dielectric layer 540 includes a furnace thermal oxidation process. In other embodiments, the process for forming the first gate dielectric layer 540 may also include other suitable thermal oxidation processes.

[0110] It should be noted that a first groove 542 is formed between the active fins 511 of adjacent second regions II, surrounded by the first gate dielectric layer 540 and the isolation layer 520. The depth-to-width ratio of the first groove 542 should not be too large. If the depth-to-width ratio of the first groove 542 is too large, it may be difficult to effectively reduce defects such as gaps and voids in the gate layer of the second region II during the subsequent formation of the gate layer. Therefore, in this embodiment, during the step of forming the first gate dielectric layer 540 on the active fins 511 of the second region II, a first groove 542 is formed between the active fins 511 of adjacent second regions II, surrounded by the first gate dielectric layer 540 and the isolation layer 520. The depth-to-width ratio of the first groove 542 is less than 1.5:1.

[0111] refer to Figure 20 , a second gate dielectric layer 550 is formed on the effective fin 511 of the first region I, and the thickness of the second gate dielectric layer 550 is less than the thickness of the first gate dielectric layer 540 .

[0112] The second gate dielectric layer 550 is used to isolate a subsequently formed gate layer from the substrate 500 in the first region I.

[0113] Since the device operating voltage in the first region I is lower than that in the second region II, the thickness requirement of the second gate dielectric layer 550 is also correspondingly smaller. Therefore, the thickness of the second gate dielectric layer 550 is lower than that of the first gate dielectric layer 540 .

[0114] Although the thickness of the first gate dielectric layer 540 is greater than the thickness of the second gate dielectric layer 550, the height of the effective fin 511 in the second region II is less than the height of the effective fin 511 in the first region I, thereby reducing the aspect ratio of the space enclosed by the first gate dielectric layer 540 and the isolation layer 520 between adjacent effective fins 511 in the second region II. Accordingly, in the subsequent process of forming the gate layer, the top position of the space is not easily closed prematurely, thereby reducing the probability of defects such as gaps and voids in the gate layer of the second region II, improving the uniformity of the gate layer thickness, and correspondingly improving the uniformity of the performance of the semiconductor device, thereby improving the performance of the semiconductor structure.

[0115] In this embodiment, the material of the second gate dielectric layer 550 is a dielectric material. As an example, the material of the second gate dielectric layer 550 is silicon oxide. In other embodiments, the material of the second gate dielectric layer can also be other suitable dielectric materials.

[0116] In this embodiment, in the step of forming the second gate dielectric layer 550 , the second gate dielectric layer 550 also covers the first gate dielectric layer 540 .

[0117] The second gate dielectric layer 550 also covers the first gate dielectric layer 540 , which is beneficial to simplifying the process steps and saving process costs.

[0118] In this embodiment, the process for forming the second gate dielectric layer 550 includes an ozone oxidation process. In other embodiments, the process for forming the second gate dielectric layer 550 may also include other suitable thermal oxidation processes.

[0119] In this embodiment, the second gate dielectric layer 550 is formed after the first gate dielectric layer 540 is formed. In other embodiments, the first gate dielectric layer 540 may also be formed after the second gate dielectric layer 550 is formed.

[0120] refer to Figures 21 to 22 A gate layer 560 is formed on the first gate dielectric layer 540 and the second gate dielectric layer 550 , crossing the active fin 511 . The gate layer 560 covers a portion of the top and a portion of the sidewall of the active fin 511 .

[0121] The gate layer 560 is used to control the opening or closing of the conductive channel when the device is in operation.

[0122] In this embodiment, in the step of forming the gate layer 560 , the gate layer 560 includes one or more work function layers 561 .

[0123] The work function layer 561 is used to adjust the work function of the gate layer 560 , thereby adjusting the threshold voltage of the field effect transistor.

[0124] It should be noted that since the threshold voltage requirements of the field-effect transistors in each region may vary, the thickness of the work function layer 561 in each region may also vary accordingly. Therefore, it is necessary to provide different numbers of work function layers in each region to adjust the threshold voltage requirements of the field-effect transistors in each region.

[0125] It should also be noted that reducing the probability of defects such as gaps and voids in the gate layer 560 in the second region II is also beneficial to improving the uniformity of the thickness of the work function layer 561 .

[0126] Specifically, when an NMOS transistor is formed, the work function layer 561 is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when a PMOS transistor is formed, the work function layer 561 is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.

[0127] In this embodiment, in the step of forming the gate layer 560 , the gate layer 560 further includes a gate electrode layer (not shown) covering the work function layer 561 .

[0128] The gate electrode layer is used as an external electrode for electrically connecting the gate layer 560 to an external circuit.

[0129] Specifically, the gate electrode layer is made of a conductive material, such as titanium aluminide, tungsten, aluminum, copper, silver, gold, platinum, nickel or titanium.

[0130] In this embodiment, after forming the first gate dielectric layer 540 and the second gate dielectric layer 550, and before forming the gate layer 560, it also includes: forming a dummy gate layer (not shown) across the effective fin 511 on the first gate dielectric layer 540 and the second gate dielectric layer 550; forming gate sidewalls on the sidewalls of the dummy gate layer (not shown); forming source and drain doped layers in the effective fins 511 on both sides of the dummy gate layer (not shown); forming an interlayer dielectric layer covering the source and drain doped layers (not shown); and after forming the interlayer dielectric layer, removing the dummy gate layer to form a gate opening (not shown).

[0131] The dummy gate layer is used to define the position of the formed gate layer 560. The material of the dummy gate layer may include one or more of polysilicon, amorphous silicon, or amorphous carbon.

[0132] The gate sidewalls and dummy gate layer define the formation locations of the source and drain doped layers. The gate sidewalls also protect the sidewalls of the dummy gate layer and gate layer. The gate sidewalls can be a single-layer structure or a stacked-layer structure, and the materials for the gate sidewalls include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0133] The source / drain doped layers are used to serve as the source or drain regions of the transistor being formed. Specifically, the material of the source / drain doped layers may include silicon germanium doped with P-type ions, such as B, Ga, or In. The material of the source / drain doped layers may also include silicon or silicon carbide doped with N-type ions, such as P, As, or Sb.

[0134] The interlayer dielectric layer is used to isolate adjacent devices. Specifically, the material of the interlayer dielectric layer includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, and silicon oxynitride.

[0135] Accordingly, in this embodiment, in the step of forming the gate layer 560 , the gate layer 560 is formed in the gate opening.

[0136] It should be noted that the semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0137] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first region and a second region, wherein a device operating voltage in the first region is lower than a device operating voltage in the second region; Fins are separated on the substrate in the first and second regions; an isolation layer located on the substrate and surrounding a portion of a sidewall of the fin portion, wherein the fin portion exposed by the isolation layer serves as an effective fin portion, and a height of the effective fin portion in the first region is greater than a height of the effective fin portion in the second region; a first gate dielectric layer, located on the effective fin portion of the second region; a second gate dielectric layer, located on the effective fin portion of the first region, wherein the thickness of the second gate dielectric layer is less than that of the first gate dielectric layer; A gate layer spans the active fin and covers the first gate dielectric layer and the second gate dielectric layer. The gate layer covers a portion of the top and a portion of the sidewall of the active fin.

2. The semiconductor structure according to claim 1, wherein Along a normal direction of the top surface of the substrate, a thickness of the isolation layer in the first region is smaller than a thickness of the isolation layer in the second region.

3. The semiconductor structure according to claim 1 or 2, wherein: Along a normal direction of the top surface of the substrate, a height difference between the effective fins in the first region and the effective fins in the second region is 50 angstroms to 200 angstroms.

4. The semiconductor structure according to claim 1 or 2, wherein: Between adjacent effective fins in the second region, a space enclosed by the first gate dielectric layer and the isolation layer has an aspect ratio less than 1.5:

1.

5. The semiconductor structure according to claim 1 or 2, wherein: The gate layer includes one or more work function layers.

6. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region, wherein a device operating voltage in the first region is lower than a device operating voltage in the second region, and separate fins are formed on the substrate in both the first and second regions; forming an isolation layer surrounding the fin on the substrate at the side of the fin, wherein the fin exposed by the isolation layer serves as an effective fin, and the effective fin height of the first region is greater than the effective fin height of the second region; forming a first gate dielectric layer on the effective fin portion of the second region; forming a second gate dielectric layer on the effective fin portion of the first region, wherein the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer; A gate layer is formed on the first gate dielectric layer and the second gate dielectric layer, crossing the active fin portion. The gate layer covers a portion of a top portion and a portion of a sidewall of the active fin portion.

7. The method for forming a semiconductor structure according to claim 6, wherein: The steps of forming the isolation layer include: forming an isolation material layer surrounding the fin on the substrate at the side of the fin, wherein the isolation material layer covers the top and sidewalls of the fin; removing a first portion of the thickness of the isolation material layer in the second region to form an effective fin in the second region; removing a second portion of the isolation material layer in the first region to form an effective fin in the first region, wherein the second portion has a thickness greater than the first portion; After removing a first portion of the thickness of the isolation material layer in the second region and removing a second portion of the thickness of the isolation material layer in the first region, the remaining isolation material layer serves as an isolation layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The step of removing the second portion of the thickness of the isolation material layer in the first region comprises: In the step of removing the first portion of the thickness of the isolation material layer in the second region, the first portion of the thickness of the isolation material layer in the second region and the first region is removed; After removing the first portion of the isolation material layer, the third portion of the isolation material layer in the first region is removed, and the sum of the first portion and the third portion is the second portion.

9. The method for forming a semiconductor structure according to claim 8, wherein: After removing the first portion of the thickness of the isolation material layer in the second region and the first region and before removing the third portion of the thickness of the isolation material layer in the first region, the method further includes: forming a first mask layer on the isolation material layer in the second region; During the process of removing the isolation material layer having a third portion of thickness in the first region, the first mask layer is used to protect the isolation material layer in the second region; After forming the isolation layer, the method further includes: removing the first mask layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming the first gate dielectric layer includes: forming an initial first gate dielectric layer on the effective fins of the first region and the effective fins of the second region; forming a second mask layer on the initial first gate dielectric layer in the second region, wherein the second mask layer and the first mask layer are formed by the same photomask; removing the initial first gate dielectric layer in the first region, and using the remaining initial first gate dielectric layer as the first gate dielectric layer; After forming the first gate dielectric layer, the method further includes: removing the second mask layer.

11. The method for forming a semiconductor structure according to claim 9, wherein: The process of forming the first mask layer includes a spin coating process, an exposure process and a development process.

12. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming the first mask layer, the material of the first mask layer includes photoresist.

13. The method for forming a semiconductor structure according to claim 9, wherein: The process of removing the first mask layer includes one or both of a dry etching process and a wet cleaning process.

14. The method for forming a semiconductor structure according to claim 13, wherein: The process of removing the third portion of the thickness of the isolation material layer in the first region includes a dry etching process.

15. The method for forming a semiconductor structure according to claim 6, wherein: In the step of forming a first gate dielectric layer on the effective fins of the second region, first grooves surrounded by the first gate dielectric layer and the isolation layer are formed between adjacent effective fins of the second region, and a ratio of depth to width of the first grooves is less than 1.5:

1.

16. The method for forming a semiconductor structure according to claim 6, wherein: In the step of forming the isolation layer, along a normal direction of the top surface of the substrate, a height difference between the effective fin portion in the first region and the effective fin portion in the second region is 50 angstroms to 200 angstroms.

17. The method for forming a semiconductor structure according to claim 6, wherein: In the step of forming the gate layer, the gate layer includes one or more work function layers.

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