Image sensor with deep trench isolation structure and method thereof

Abstract

The invention relates to an image sensor with a deep trench isolation structure and a method thereof. An image sensor is described that includes a photodiode, an interlayer dielectric layer, and a deep trench isolation structure. The photodiode is disposed within a semiconductor substrate having a front side and a back side opposite the front side. The interlayer dielectric layer is disposed over the front side of the semiconductor substrate such that the front side is disposed between the interlayer dielectric layer and the back side. The deep trench isolation structure is configured to isolate the photodiode from an adjacent photodiode included in the image sensor. The deep trench isolation structure includes a trench disposed within the interlayer dielectric layer and the semiconductor substrate, and a fill material disposed within the trench. The trench extends through the interlayer dielectric layer and the front side of the semiconductor substrate toward the back side of the semiconductor substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 550,397, filed February 6, 2024, the entirety of which is hereby incorporated by reference. Technical Field

[0003] The present disclosure relates generally to image sensors and, in particular, but not exclusively, to CMOS image sensors and corresponding fabrication methods. Background Art

[0004] Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, surveillance cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, their functionality, performance metrics, and the like are expected to be enhanced in as many ways as possible (e.g., resolution, power consumption, dynamic range), both through device architecture design and image acquisition processing. The technology used to manufacture image sensors continues to advance at a rapid pace. For example, the demand for higher resolution and lower power consumption has driven the further miniaturization and integration of these devices.

[0005] A typical complementary metal-oxide semiconductor (CMOS) image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and, upon absorbing the image light, photogenerate image charge. The image charge photogenerated by the pixels can be measured as an analog output image signal on a column bit line, which varies depending on the incident image light. In other words, the amount of photogenerated image charge is proportional to the intensity of the image light. This image charge is read out from the column bit line as an analog signal and converted into a digital value to produce a digital image representing the external scene (i.e., image data). Summary of the Invention

[0006] According to one aspect of the present disclosure, an image sensor is provided. The image sensor includes: a photodiode disposed in a semiconductor substrate having a front side and a back side opposite the front side; an interlayer dielectric layer disposed over the front side of the semiconductor substrate such that the front side is disposed between the interlayer dielectric layer and the back side; and a deep trench isolation (DTI) structure configured to isolate the photodiode from adjacent photodiodes included in the image sensor, wherein the DTI structure includes: a trench disposed in the interlayer dielectric layer and the semiconductor substrate, wherein the trench extends through the interlayer dielectric layer and the front side of the semiconductor substrate toward the back side of the semiconductor substrate; and a filling material disposed in the trench.

[0007] According to another aspect of the present disclosure, a method for manufacturing an image sensor is provided. The method includes etching through an interlayer dielectric layer and into a semiconductor substrate to form a trench disposed proximate a photodiode disposed within the semiconductor substrate, wherein the semiconductor substrate includes a front side and a back side opposite the front side, and wherein the interlayer dielectric layer is disposed over the front side of the semiconductor substrate such that the front side is disposed between the interlayer dielectric layer and the back side; and depositing a fill material within the trench to form a deep trench isolation structure configured to isolate the photodiode from adjacent photodiodes included in the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. Not all instances of components are necessarily labeled to avoid cluttering the drawings where appropriate. The figures are not necessarily drawn to scale, emphasis instead being placed upon illustrating the principles being described.

[0009] Figure 1A A block diagram illustrating an imaging system according to an embodiment of the present disclosure.

[0010] Figure 1B The embodiment of the present disclosure corresponds to Figure 1A An example stacked semiconductor device with a deep trench isolation structure of the imaging system described in .

[0011] Figure 2A A front-side view illustrating a portion of a pixel array included in an image sensor having a deep trench isolation structure according to an embodiment of the present disclosure is illustrated.

[0012] Figure 2B The embodiment of the present disclosure includes Figure 2A A rear-side view of a portion of the pixel array in an image sensor.

[0013] Figures 3A to 3B are block diagrams that collectively illustrate example methods for fabricating an example image sensor having a deep trench isolation structure according to embodiments of the present disclosure.

[0014] Figures 4A to 4M Describe the embodiment of the present disclosure Figures 3A to 3B Cross-sectional view of a manufacturing state associated with the described method.

[0015] Figures 5A to 5EA manufacturing state for forming an image sensor including a deep trench isolation structure having a dielectric cap structure to protect the deep trench isolation structure from damage during backside thinning or etching according to an embodiment of the present disclosure is shown.

[0016] Figures 6A to 6C An embodiment is described in which a fill material of a deep trench isolation structure is coupled to receive a bias voltage to provide enhanced passivation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] Embodiments of devices, systems, and methods are described herein, each relating to an image sensor having a deep trench isolation structure. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, one skilled in the relevant art will recognize that the techniques described herein can be practiced without one or more of these specific details, or with other methods, components, materials, and the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0018] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0019] Throughout this specification, several technical terms are used. These terms have their ordinary meaning in the art to which they pertain, unless explicitly defined herein or the context of their use clearly indicates otherwise. It should be noted that element names and symbols (e.g., Si and silicon) may be used interchangeably throughout this document; however, both have the same meaning.

[0020] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings of the inventive concept.

[0021] For ease of description, spatially relative terms (such as "below," "beneath," "beneath," "beneath," "above," "upper," and the like) may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, an element described as "below" or "beneath" or "under" another element or feature would then be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" would encompass both orientations of "above" and "beneath." The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0022] In addition, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element or there may be an intervening element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). In addition, it will be understood that when an element or layer is referred to as being "formed on" another element or layer, it may be formed directly or indirectly on the other element or layer. That is, for example, there may be an intervening element or layer. In contrast, when an element or layer is referred to as being "formed directly on" another element, there are no intervening elements or layers.

[0023] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit example embodiments of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] As used herein, the terms "having," "may have," "include," "may include," or "comprise" indicate the presence of corresponding features (e.g., number, function, operation, or element) and do not exclude the presence of additional features. The terms "A or B," "at least one of A and / or B," or "one or more of A and / or B" may include all possible combinations of the items listed together. For example, the terms "A or B," "at least one of A and B," or "at least one of A or B" may indicate all of the following: (1) including at least one A, (2) including at least one B, and (3) including at least one A and at least one B.

[0025] The term "pixel cell" or "pixel group" may be used to indicate a unit pixel structure that includes multiple photodiodes (e.g., two photodiodes, four photodiodes, 8 photodiodes, 16 photodiodes, or more photodiodes) that share common components of the circuitry in the pixel cell or common optical elements (e.g., common or shared circuitry (e.g., floating diffusion regions), common or shared optical elements (e.g., shared color filters or microlenses), or the like). For example, the multiple photodiodes included in the pixel cell may be arranged under a single color filter and / or a single microlens. The number of sub-pixels in each pixel cell may vary depending on the implementation of the disclosed technology. In one example, a pixel cell may refer to a unit pixel that includes four photodiodes. In another example, a pixel cell may refer to a unit pixel that includes two photodiodes. In yet another example, a pixel cell may refer to a unit pixel that includes eight photodiodes. In another example, a pixel cell may refer to a unit pixel that includes sixteen photodiodes.

[0026] The term “configured (or arranged) to” may be used interchangeably with terms such as “suitable for,” “capable of,” “designed to,” “adapted to,” “made to,” or “capable of.” The term “configured (or arranged) to” may not necessarily have the meaning of “specially designed to.” In some cases, the term “a device configured to” may indicate that the device “can perform together with other devices or components.” For example, the term “a processor configured (or arranged) to perform A, B, and C” may represent a dedicated processor (e.g., an embedded processor) for performing the corresponding operations, or a general-purpose processor (e.g., a CPU or application processor) for executing at least one item of software or program stored in a memory device to perform the corresponding operations.

[0027] The term "vertical" refers to a direction perpendicular to the surface of a substrate or material layer. The term "high-κ material" herein refers to a material having a relative dielectric constant greater than 3.9. In some embodiments, the term "high-κ material" may also refer to a material having a relative dielectric constant greater than that of silicon dioxide (SiO2). The term "p-type" defines a structure, layer, and / or region in a substrate material layer (e.g., a semiconductor substrate or epitaxial layer) as being doped with a p-type dopant, such as boron. The term "n-type" defines a structure, layer, and / or region in a substrate material layer (e.g., a semiconductor substrate or epitaxial layer) as being doped with an n-type dopant, such as phosphorus and / or arsenic.

[0028] In some embodiments, the term "about" and the term "substantially" may refer to a value of a given quantity or manufacturing parameter that varies within 5% of the stated value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the stated value). These values are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one of ordinary skill in the relevant art in view of the teachings of the present disclosure.

[0029] Deep trench isolation structures (e.g., trench structures filled with dielectric material) are used in image sensors to provide electrical and / or optical isolation between adjacent pixels in a pixel array. The effectiveness of the deep trench isolation structures depends on the associated trench depth, where deeper isolation depths exhibit improved electrical and / or optical isolation between pixels, which can reduce or prevent inter-pixel electron leakage (e.g., blooming) and optical crosstalk. In some embodiments of the present disclosure, an image sensor having a full-depth trench isolation structure is described by forming trenches that extend the full depth or thickness of a semiconductor substrate (e.g., a silicon substrate, a wafer substrate, or an epitaxial layer) in which the photodiodes are formed. It should be understood that a full-depth trench isolation structure generally provides more effective isolation than a partially deep trench isolation structure that does not extend completely through the semiconductor substrate but may be simpler or less expensive to manufacture. It should be understood that the trenches of a full-depth trench isolation structure may be referred to as through-trench because each trench extends completely or entirely through the semiconductor substrate, rather than terminating at a point within the semiconductor substrate. It should be understood that the thickness of the semiconductor substrate may change during the fabrication of the image sensor (e.g., at least a portion of the semiconductor substrate may be removed from its backside or the semiconductor substrate may be thinned in other ways), such that during one or more intermediate fabrication stages, the deep trench isolation structure may not extend completely through the semiconductor substrate. However, in some embodiments, the deep trench isolation structure extends completely through the final thickness of the semiconductor substrate (e.g., the thickness of the semiconductor substrate after the image sensor fabrication process is completed).

[0030] It should be understood that deep trench isolation structures may be referred to by their manner of fabrication, including backside deep trench isolation structures and frontside deep trench isolation structures.

[0031] Backside deep trench isolation structures are formed by etching through the backside (e.g., the illuminated or light receiving side) of a semiconductor substrate. However, backside deep trench isolation structures may be limited in processing because they are typically formed after forming frontside components (e.g., transistors, contacts, metallization layer structures), which means that high temperature processes (e.g., high temperature anneals, such as hydrogen anneals) that can be used to repair etch damage (e.g., plasma damage) to improve dark current noise may not be feasible. Additionally, it may be difficult to align the backside deep trench isolation structures with the frontside components and due to possible damage to the frontside components, it may also be difficult to form full or through-substrate isolation structures. As pixel sizes continue to shrink, the challenges to backside deep trench isolation structures may intensify, resulting in deep trench isolation structures with reduced electrical and / or optical isolation performance or that affect the full well capacity of nearby photodiodes.

[0032] Frontside deep trench isolation structures are formed by etching through the front side (e.g., the non-illuminated side) of a semiconductor substrate and can be formed on the front side of a semiconductor substrate after shallow trench isolation structures are formed (e.g., formed on the back side of the semiconductor substrate). Fabrication of frontside deep trench isolation structures can be simplified because tolerances on trench depth are relaxed relative to corresponding backside processes. Furthermore, trenches formed deeper within the semiconductor substrate do not risk damaging the front-side components of the image sensor (e.g., because the frontside deep trench isolation structures are formed before the front-side components). Surface passivation of high-κ materials has been found to limit the use of high-temperature processes (e.g., annealing processes for dopant activation and silicon damage recovery) because high temperatures (e.g., processes with applied temperatures greater than 700°C) can damage or degrade the high-κ material and reduce the surface passivation effect provided by the high-κ material (e.g., reducing the number of negative charges). Furthermore, processes forming trenches by plasma etching can induce defects on the surface of the semiconductor substrate surrounding the trenches, resulting in charge trapping sites. Consequently, insufficient passivation of defects can lead to increased dark current and noise during operation of the image sensor.

[0033] The embodiments described herein illustrate various image sensors that may have full-deep trench isolation structures fabricated from the front side of a semiconductor substrate, overcoming the aforementioned disadvantages of both front-side and back-side full-deep trench isolation structures. In embodiments of the present disclosure, a plurality of front-side deep trenches may be formed by etching (e.g., a dry and / or wet etching process) through an interlayer dielectric layer formed on the front side of a semiconductor substrate enclosing at least one front-side circuitry element, followed by a high-temperature process (e.g., a high-temperature anneal). Subsequently, a lining material may be formed to line the plurality of front-side deep trenches. Thereafter, a first high-κ passivation layer is deposited into the plurality of front-side deep trenches through openings formed in the interlayer dielectric layer to form a continuous layer coating the lining material and extending the full depth of the plurality of front-side deep trenches. Following formation of the first high-κ passivation layer, the plurality of front-side trenches may be filled with a fill material (e.g., a dielectric or conductive material) to form a full front-side deep trench isolation structure enclosed by a cap layer (e.g., an oxide-based material). Subsequently, contacts and metallization layers may be formed proximate to the cap layer. In embodiments of the present disclosure, the semiconductor substrate is thinned or otherwise processed to remove at least a portion of the substrate material contained in the semiconductor substrate from the back side to expose the deep trench isolation structure. Subsequently, a second high-κ passivation layer may be formed covering the back side of the semiconductor substrate. After thinning the semiconductor substrate, the deep trench isolation trench has a trench depth substantially equal to the substrate thickness of the thinned semiconductor substrate (i.e., the final thickness of the deep trench isolation trench structure extends completely through the semiconductor substrate). In such embodiments, the final thickness of the semiconductor substrate may be referred to as the thickness of the semiconductor substrate after the thinning process, which may also correspond to the resulting thickness after the image sensor manufacturing process is completed. Subsequently, optical elements of the image sensor (e.g., color filters, metal grid structures, microlens arrays, and the like) may then be formed on the back side of the semiconductor substrate (e.g., formed on the second high-κ passivation layer and / or over one or more additional layers (e.g., an oxide-based layer)).

[0034] It should be understood that forming the trenches for the deep trench isolation structure from the front side of the semiconductor substrate (e.g., frontside trenches) after forming (e.g., depositing or growing) the interlayer dielectric layer is advantageous because the frontside trenches can be easily aligned with the pixel elements and further extend deep enough to improve the isolation of the photodiode regions of all pixels of the image sensor. In addition, a high-temperature process (e.g., hydrogen annealing) can be applied to eliminate defects (e.g., dangling bonds) caused by etching the trenches, which improves white pixel and dark current performance.

[0035] Figure 1AA block diagram illustrates an imaging system 100 according to an embodiment of the present disclosure. Imaging system 100 includes a pixel array 105, control circuitry 121, readout circuitry 111, and function logic 115. In one embodiment, pixel array 105 is an array of photodiodes or image sensor pixels (e.g., pixels P1, P2, ..., Pn) in which individual photodiodes or pixels are isolated from adjacent photodiodes or pixels by deep trench isolation structures. As illustrated, the image sensor pixels are arranged in rows (e.g., rows R1 through Ry) and columns (e.g., columns C1 through Cx) to acquire image data of a person, place, object, etc., which can then be used to render an image or video representing the person, place, object, etc. However, it should be understood that in other embodiments, the photodiodes or image sensor pixels need not be arranged in rows and columns and may take other configurations.

[0036] In one embodiment, each of the image sensor pixels or photodiodes is separated and isolated from each other by a full front-side deep trench isolation structure. In various example embodiments, the full-deep trench isolation structure can be arranged in a trench grid to provide optical and / or electrical isolation between adjacent photodiodes or pixels in the pixel array 105. In some embodiments, the image sensor pixels or photodiodes are grouped into a plurality of pixel cells that form the pixel array 105. It should be understood that each of the plurality of pixel cells can include any number of photodiodes or image sensor pixels (e.g., one, two, four, eight, or more photodiodes or image sensor pixels per pixel cell). In most embodiments, the number of photodiodes or image sensor pixels per pixel cell included in the plurality of pixel cells is uniform.

[0037] In various embodiments, readout circuitry 111 may be configured to read out image signals (e.g., image charge photogenerated in response to incident light) via column bit lines (e.g., readout columns) with different conversion gains. In various embodiments, readout circuitry 111 may include one or more current sources, routing circuitry, and comparators, which may be included in an analog-to-digital converter or other converter.

[0038] In one embodiment, after each image sensor pixel or photodiode included in pixel array 105 has acquired its image charge, the image charge is read out by readout circuitry 111 as image data and then transferred to function logic 115. In various embodiments, readout circuitry 111 may include amplification circuitry, analog-to-digital (ADC) conversion circuitry, or other circuitry. Function logic 115 may simply store the image data, or even manipulate the image data by applying post-processing effects (e.g., autofocus, cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or otherwise). In the same or another embodiment, readout circuitry 111 may read out the image data one row at a time along readout column lines (illustrated) or may read out the image data using various other techniques (not illustrated), such as serial readout of all image pixels simultaneously or fully parallel readout. In one embodiment, control circuitry 121 is coupled to pixel array 105 to control the operation of the plurality of image sensor pixels in pixel array 105. For example, control circuitry 121 may generate a shutter signal for controlling image acquisition. In some embodiments, control circuitry 121 may be configured to generate drive signals (eg, transfer signals, reset signals, and row select signals) for controlling the operation of pixel circuitry associated with image sensor pixels in pixel array 105 .

[0039] It should be understood that the imaging system 100 may be included in an image sensor that may be incorporated into a digital camera, a cell phone, a laptop computer, an automobile, a surveillance camera, or the like. Additionally, the imaging system 100 may be coupled to other hardware blocks, such as a processor (general purpose or otherwise), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), lighting / flash, electrical inputs (keyboard, touch display, trackpad, mouse, microphone, etc.), and / or a display. The other hardware blocks may deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate the image data supplied by the imaging system 100.

[0040] Although Figure 1AThe block diagram illustrated in FIGURE 1 shows pixel array 105, readout circuitry 111, function logic 115, and control circuitry 121 as distinct and separate elements from pixel array 105, but it should be understood that this is not necessarily the case, as such features may be combined directly with the pixel array or otherwise incorporated (e.g., within and / or between individual pixels, in the form of a stacked substrate, or otherwise). For example, according to embodiments of the present disclosure, readout circuitry 111 may include one or more transistors having elements disposed between segments of individual photodiodes (e.g., associated with a 3T, 4T, 5T, or other pixel architecture for reading out image charge from individual pixels). Furthermore, imaging system 100 may include features not explicitly illustrated or discussed but known to those of ordinary skill in the art, such as color filters, microlenses, metal grid structures, composite metal-dielectric grids, or combinations thereof. Additionally, it should be understood that imaging system 100 may be included in an image sensor, which may be fabricated by conventional CMOS fabrication techniques known to those of ordinary skill in the art, which may include, but are not limited to, photolithography, chemical vapor deposition, physical vapor deposition, atomic layer deposition, ion implantation or diffusion, thermal oxidation, reactive ion etching, wet chemical etching, chemical mechanical polishing, and the like.

[0041] Figure 1B An example stacked semiconductor device configuration STACK 1 corresponding to an imaging system 100 according to an embodiment of the present disclosure is described. The imaging system 100 corresponds to an image sensor for imaging an external scene. The imaging system 100 includes a first semiconductor substrate 150 and a second semiconductor substrate 180, each of which may correspond to a portion or the entirety of a semiconductor wafer or die according to an embodiment of the present disclosure. The first semiconductor substrate 150 includes a plurality of pixels 1051, a deep trench isolation structure 127, and a peripheral circuit system 155 formed thereon or therein, constituting a pixel array 105. In the illustrated embodiment, each pixel included in the plurality of pixels 1051 includes a photodiode isolated from other photodiodes included in the plurality of pixels 1051 by the deep trench isolation structure 127. In other words, the deep trench isolation structure 127 forms a grid structure defining a pixel region of the first semiconductor substrate 150, in which components of a given pixel in the plurality of pixels 1051 (e.g., photodiodes, source / drain regions, electrodes, etc.) are disposed. That is, each pixel included in the plurality of pixels 1051 is separated and isolated from each other by corresponding segments of the deep trench isolation structure 127 to effectively reduce electrical and / or optical crosstalk.

[0042] In some embodiments, the pixels included in the plurality of pixels 1051 are grouped together to form a plurality of pixel cells having a regular arrangement (e.g., a two-by-two arrangement of four photodiodes or image sensor pixels, a two-by-three arrangement of six photodiodes or image sensor pixels, a two-by-four arrangement of eight photodiodes or image sensor pixels, a four-by-four arrangement of sixteen photodiodes or image sensor pixels, or other arrangements). In some embodiments, individual pixel cells formed by the plurality of pixels 1051 may correspond to minimal repeating units of the first semiconductor substrate 150. In some embodiments, the pixel circuitry 185 of the second semiconductor substrate 180 is arranged based on the corresponding arrangement of the plurality of pixels 1051. For example, in some embodiments, individual pixels included in the plurality of pixels 1051 of the first semiconductor substrate 150 may be respectively coupled to individual groups of components in the pixel circuitry 185 included in the second semiconductor substrate 180 on a per-pixel or per-pixel-cell basis, which may result in a regular and / or repeating arrangement of the pixel circuitry 185 (e.g., in rows and columns, as illustrated).

[0043] In some embodiments, individual pixels included in the plurality of pixels 1051 are grouped together as a pixel cell having two or more photodiodes or image sensor pixels that share a common color filter or are otherwise optically aligned with a color filter having a common spectral photoresponse (e.g., a group of four adjacent photodiodes or image sensor pixels arranged in a two-by-two pattern included in the plurality of pixels 1051 can be optically aligned with a first color filter to form a first pixel cell included in the plurality of pixels 1051). In other embodiments, adjacent pixels included in the plurality of pixels 1051 do not share a common color filter or microlens (e.g., the color filters of adjacent pixels included in the plurality of pixels 1051 have different spectral photoresponses). In some embodiments, a group of pixels included in the plurality of pixels 1051 that form a pixel cell can share a common microlens or be otherwise optically aligned with a single microlens.

[0044] In the illustrated embodiment, the second semiconductor substrate 180 includes pixel circuitry 185 and peripheral circuitry 187 formed or otherwise disposed thereon. In some embodiments, the pixel circuitry 185 can be partitioned into groups of components associated with respective pixels included in the plurality of pixels 1051 or pixel cells formed by groups of the plurality of pixels 1051 to facilitate operation and / or readout of the imaging system 100, the groups of components being physically aligned or otherwise overlapping across the substrate (e.g., components of the readout circuitry for a given pixel or pixel cell included in the plurality of pixels 1051 located in or on the second semiconductor substrate 180 may vertically overlap with a given pixel or pixel cell located in or on the first semiconductor substrate 150).

[0045] In the illustrated embodiment, the imaging system 100 is a complementary metal oxide semiconductor (CMOS) image sensor formed at least in part by a first semiconductor substrate 150 (e.g., a first die) and a second semiconductor substrate 180 (e.g., a second die) stacked and coupled together in a stacked chip scheme (e.g., electrically and physically) implemented at least in part on a per-pixel or per-pixel unit basis via hybrid bonding. It should be understood that other types of bonding (e.g., oxide bonding, metal bonding), silicon connections (e.g., through-silicon vias), other suitable circuit coupling techniques, or combinations thereof, may also be used in combination with hybrid bonding to form the imaging system 100. It should be understood that while in Figure 1B Only the first semiconductor substrate 150 and the second semiconductor substrate 180 are illustrated, but the stacked chip solution of the imaging system 100 may include additional substrates (e.g., one or more additional substrates, dies, or chips different from the first semiconductor substrate 150 and the second semiconductor substrate 180) that can be integrated into the stacked chip solution of the imaging system 100.

[0046] Figure 1B The STACK 1 configuration described in distributes components of the imaging system 100 across multiple substrates. Specifically, the first semiconductor substrate 150 includes photosensitive elements (e.g., multiple photodiodes (e.g., pinned photodiodes or the like to form image sensor pixels)) included in the multiple pixels 1051, and the second semiconductor substrate 180 includes pixel circuitry 185 associated with the multiple pixels 1051 (e.g., any one or combination of pixel transistors (e.g., reset transistors, source follower transistors, row select transistors, etc.), analog / digital circuitry, signal processing circuitry, or other circuitry to facilitate imaging of an external scene using the pixels included in the multiple pixels 1051). In other words, the second semiconductor substrate 180 offloads at least the portion of the circuitry associated with the multiple pixels 1051 from the first semiconductor substrate 150, which advantageously provides additional space on the first semiconductor substrate 150 (e.g., to reduce pixel pitch, increase photodiode sensing area relative to total pixel area, etc.).

[0047] In some embodiments, the plurality of pixels 1051 can be coupled to the pixel circuitry 185 via a plurality of connection pads embedded in an insulating medium or matrix. It will be appreciated that the plurality of connection pads can be positioned at a bonding interface disposed between the first semiconductor substrate 150 and the second semiconductor substrate 180. One or more connection vias, metal lines, wires or traces, contacts, or a combination thereof (e.g., interconnects) can further electrically couple the plurality of connection pads to various components (e.g., floating diffusion regions) positioned in or on the first semiconductor substrate 150 and / or the second semiconductor substrate 180. In some embodiments, the plurality of pixels 1051 can be coupled to the pixel circuitry 185 via a plurality of through-silicon vias (TSVs) disposed within a peripheral region (e.g., peripheral circuitry 155) of the first semiconductor substrate 150. In some embodiments, the space saved on the first semiconductor substrate 150 by offloading the circuitry to the second semiconductor substrate 180 (or other subsequent substrate in a stacked chip approach) can be reused to increase the size of the individual photodiodes included in each of the plurality of pixels 1051, thereby allowing for an increase in pixel size, density, sensitivity, a combination thereof, or the like.

[0048] In some embodiments, first semiconductor substrate 150 and second semiconductor substrate 180 include various analog and / or digital support circuitry for imaging system 100, which may correspond to peripheral circuitry 155 and peripheral circuitry 187, respectively. In some embodiments, the support circuitry that may be included in peripheral circuitry 155 and / or peripheral circuitry 187 may include, but is not limited to, row and column decoders and drivers, analog signal processing chains, digital imaging processing blocks, memory, timing and control circuitry, input / output interfaces, vertical scanners, sample and hold circuitry, amplifiers, analog / digital converter circuitry, and any other embodiments of logic and / or circuitry suitable for the functionality of imaging system 100.

[0049] You should understand that Figures 1A to 1B The views presented in the drawings may omit certain elements of the imaging system 100 to avoid obscuring the details of the present disclosure. In other words, throughout the present disclosure, some elements may not be shown in the drawings. Figures 1A to 1B or other figures, all elements of the imaging system 100 are labeled, illustrated, or otherwise shown. It should be further understood that in some embodiments, the imaging system 100 may not necessarily include all of the shown elements.

[0050] Figure 2A 1 illustrates a front side view (eg, non-illuminated side) of a portion of a pixel array included in an image sensor 200 according to an embodiment of the present disclosure. It should be understood that the image sensor 200 is Figure 1A One possible implementation of image sensor 100 is described in . Figure 2AAn example pixel layout of may be formed collectively when viewed from the front side (eg, non-illuminated side) of the semiconductor substrate 210. Figure 1B pixel array and / or Figure 1A It should be understood that the semiconductor substrate 210 may correspond to a possible embodiment of a pixel included in the plurality of pixels 1051 of the pixel array 105. Figure 1B In some embodiments, the semiconductor substrate 210 may correspond to a portion or the entirety of a semiconductor wafer (eg, a silicon wafer, one or more epitaxial layers of the aforementioned materials, or a bulk substrate thereof). Figure 2A The illustrated embodiment of shows pixel cell PC1, which can represent each pixel cell (e.g., pixel cell PC2) included in the pixel array of image sensor 200. As illustrated, pixel cell PC1 includes photodiodes 212, 214, 216, 218 arranged in a two-by-two pattern, a plurality of transfer gates 222, 224, 226, 228, a plurality of floating diffusion regions 232, 234, 236, 238, and a deep trench isolation structure 227, each of which is formed in or on semiconductor substrate 210. It should be understood that deep trench isolation structure 227 can correspond to Figure 1B The deep trench isolation structure 127 is described in detail.

[0051] In some embodiments, the deep trench isolation structure 227 is configured to form a grid that defines individual pixel regions. In this embodiment, the deep trench isolation structure 227 laterally surrounds or encloses the pixel region of the semiconductor substrate 210. It should be understood that each of the photodiodes 212, 214, 216, and 218 is disposed within a respective one of the enclosed pixel regions, such that each of the photodiodes 212, 214, 216, and 218 is individually isolated. In addition to providing individual isolation for the photodiodes, the grid structure of the deep trench isolation structure 227 can also provide separation between different pixel cells (for example, pixel cell PC1 is isolated from pixel cell PC2 by the deep trench isolation structure 227). In some embodiments, the deep trench isolation structure 227 provides electrical, optical, and / or physical isolation between individual pixel regions and individual pixel cells. In the same or other embodiments, deep trench isolation structure 227 defines areas or regions for individual pixels and / or pixel cells (e.g., PC1 and PC2) (i.e., enclosed pixel regions), and further defines areas or regions (e.g., shaded photodiode regions) for each of individual photodiodes 212, 214, 216, and 218. In other words, the deep trench isolation structure separates and isolates each of the plurality of photodiodes 212, 214, 216, and 218, and further provides electrical and / or optical isolation between the plurality of photodiodes 212, 214, 216, and 218.

[0052] A plurality of floating diffusion regions 232, 234, 236, 238 and a plurality of transfer gates 222, 224, 226, 228 are disposed in or on corresponding enclosed pixel regions defined by deep trench isolation structure 227. In some embodiments, a plurality of floating diffusion regions 232, 234, 236, 238 and a plurality of transfer gates 222, 224, 226, 228 are disposed in or on respective ones of photodiodes 212, 214, 216, and 218 (e.g., when the plurality of floating diffusion regions 232, 234, 236, 238 and the plurality of transfer gates 222, 224, 226, 228 are disposed in or on respective ones of photodiodes 212, 214, 216, and 218). Figure 2A In some embodiments, floating diffusion region 232 is disposed within the photodiode region of photodiode 212, and transfer gate 222 is disposed in or on the photodiode region of photodiode 212 and configured to selectively couple photodiode 212 to floating diffusion region 232. In some embodiments, floating diffusion region 234 is disposed within the photodiode region of photodiode 214, and transfer gate 224 is disposed in or on the photodiode region of photodiode 214 and configured to selectively couple photodiode 214 to floating diffusion region 234. In some embodiments, floating diffusion region 236 is disposed within the photodiode region of photodiode 216, and transfer gate 226 is disposed in or on the photodiode region of photodiode 216 and configured to selectively couple photodiode 216 to floating diffusion region 236. In some embodiments, floating diffusion region 238 is disposed within the photodiode region of photodiode 218 , and transfer gate 228 is disposed in or on the photodiode region of photodiode 218 and configured to selectively couple photodiode 218 to floating diffusion region 238 .

[0053] In some embodiments, each of the plurality of transfer gates 222, 224, 226, and 228 includes a planar gate portion and a vertical gate portion (e.g., collectively referred to as a vertical transfer gate or VTG) extending from the planar gate portion. The vertical gate portion is disposed proximate to a photodiode doped region (e.g., an n-type photodiode doped region) of each respective photodiode to facilitate charge transfer between each photodiode and a corresponding floating diffusion region. In some embodiments, the plurality of floating diffusion regions 232, 234, 236, 238 and the photodiode doped region included in each of the plurality of photodiodes 212, 214, 216, 218 may have the same conductivity type (e.g., n-type or p-type), which is opposite to the conductivity type (p-type or n-type) of the semiconductor substrate 210.

[0054] In some embodiments, the plurality of floating diffusion regions 232, 234, 236, 238 may be coupled together (e.g., via polysilicon connectors or metal interconnects in a metal layer) for charge binning. In this embodiment, one or more transistors (e.g., source follower transistors, reset transistors, or row select transistors) shared by the plurality of photodiodes 212, 214, 216, 218 may be formed in or on respective photodiode regions of the plurality of photodiodes 212, 214, 216, 218. The one or more transistors (e.g., source follower transistors, reset transistors, or row select transistors) may have an interlayer dielectric layer (ILD) formed between respective photodiode regions of the photodiodes and encapsulating the plurality of transfer gates 222, 224, 226, 228 and respective gates of the one or more transistors. Figure 2A In the illustrated embodiment, components of the source follower transistor (e.g., gate SF) and the row select transistor (e.g., gate RS) may be formed in or on the photodiode region of the photodiode 212. For example, the source and drain regions of the source follower transistor and the row select transistor may be formed in or on the semiconductor substrate 210, with an interlayer dielectric layer ( Figure 2A The source follower gate and the row select gate may be formed near a surface (e.g., a front surface) of the semiconductor substrate 210. In the illustrated embodiment, components of the reset transistor (e.g., gate RST) may be formed in or on the photodiode region of the photodiode 214. For example, the source and drain regions of the reset transistor RST may be formed on the semiconductor substrate 210, between the interlayer dielectric layer ( Figure 2A The reset gate may be formed between the semiconductor substrate 210 and the photodiode region of the photodiode 214, and the reset gate may be formed close to a surface (eg, a front surface) of the semiconductor substrate 210.

[0055] In some embodiments, the source follower transistor has a gate SF coupled (e.g., via a polysilicon layer or a metal layer) to the plurality of floating diffusion regions 232, 234, 236, 238. In some embodiments, a row select transistor is coupled to the source follower transistor such that the source follower transistor and the row select transistor are coupled between a power supply line AVDD (not illustrated) and a bit line (not illustrated) in response to a row select control signal RS applied to the gate RS. SIG In the same or other embodiments, the reset transistor is coupled to the reset voltage source Pix. VDD and a plurality of floating diffusion regions 232, 234, 236, 238, and the reset transistor is coupled to respond to a reset control signal RST applied to a gate RST. SIGAnd control it.

[0056] Figure 2B The embodiment of the present disclosure includes Figure 2A FIG20 is a backside view (e.g., illuminated side) of a portion of the pixel array in image sensor 200. As illustrated, deep trench isolation structure 227 extends completely through semiconductor substrate 210 to provide full depth isolation for the enclosed pixel region of semiconductor substrate 210. Although illustrated in a plan view, semiconductor substrate 210 may be an example fabricated substrate structure in image sensor 200. Therefore, deep trench isolation structure 227 is referred to as a full-depth trench isolation structure formed in semiconductor substrate 210 and having a depth substantially equal to the final thickness of semiconductor substrate 210 (e.g., from 2.5 μm to 7 μm). In other words, the deep trench isolation structure 227 is a through-substrate structure that is configured to provide complete isolation between adjacent photodiodes (for example, the photodiodes 212, 214, 216, and 218 are completely isolated from each other both laterally and vertically relative to the semiconductor substrate 210 by the deep trench isolation structure 227) and between adjacent pixel cells (for example, the pixel cells PC1 and PC2 are completely isolated from each other both laterally and vertically relative to the semiconductor substrate 210 by the deep trench isolation structure 227).

[0057] Figure 3A and Figure 3B is a block diagram that collectively illustrates an example method 300 for fabricating an example image sensor having deep trench isolation structures according to an embodiment of the present disclosure. The order in which some or all of the process blocks (including process blocks 301, 303, 305, 307, 309, 311, 313, 315, 317, 319, 321, 323, 327, 329, 331, 333, and 335) appear in method 300 should not be considered limiting. Indeed, one of ordinary skill in the art having the benefit of this disclosure will appreciate that some of the process blocks of method 300 can be performed in various orders not illustrated, or even in parallel. Although method 300 is described in conjunction with forming an image sensor, it should be understood that deep trench isolation structures may also be included in other semiconductor devices.

[0058] Figures 4A to 4M Describe the embodiment of the present disclosure Figures 3A to 3B 300 is a cross-sectional view of a manufacturing state associated with the method 300 described in FIG. Figures 4A to 4M The illustration depicts a state of manufacture of an example fabrication process for forming an example image sensor (e.g., image sensor 200) having a full-deep trench isolation structure that provides full isolation between adjacent photodiodes, pixels, and / or pixel cells within a semiconductor substrate. More specifically, Figures 4A to 4M The depicted manufacturing state may represent the Figures 3A to 3B Thus, it should be understood that one or more process blocks 301 to 335 of the method 300 of Figures 4A to 4M One or more of the blocks 301 to 335 may represent temporary structures as fabrication proceeds to the example method 300, which includes multiple fabrication, refining, and finishing steps, not all of which are necessarily illustrated. In some embodiments, process blocks 301 to 335 of the method 300 may be repeated, reordered, or omitted. It should be understood that some elements may be omitted to focus on fabricating deep trench isolation structures (e.g., Figures 2A to 2B It will be appreciated that various processing operations have been performed to form the deep trench isolation structure 227. Figures 4A to 4M The illustrated structures shown in FIG, but such operations (e.g., photoresist deposition, patterning, and / or removal) may not all be explicitly disclosed. In fact, a person of ordinary skill in the art having the benefit of this disclosure will be able to Figures 3A to 3B The method 300 and Figures 4A to 4M In addition, according to the embodiment of the present disclosure, where applicable, Figures 4A to 4M At least some of the intermediate states shown in may be optional or alternative forms.

[0059] Process block 301 illustrates forming a photodiode doped region, a floating diffusion region, a source / drain region of a pixel transistor, and a ground contact (e.g., a P+ doped region) of a photodiode in or on a semiconductor substrate. In one embodiment, the photodiode doped region, the floating diffusion region (not illustrated), and the source / drain (not illustrated) of the photodiode may be monolithically formed on a common semiconductor substrate. Figure 4A Frame 301 is represented and a semiconductor substrate 410 is shown having photodiode doping regions, floating diffusion regions (not illustrated), and source / drain regions (not illustrated) corresponding to a plurality of photodiodes formed within the semiconductor substrate 410. As illustrated, the semiconductor substrate 410 includes a plurality of photodiodes (e.g., photodiodes PD1, PD2), floating diffusion regions (not illustrated), and source / drain regions (not illustrated) for one or more pixels or pixel cells. The semiconductor substrate 410 has a front side FS (e.g., a non-illuminated side) and a back side BS (e.g., an illuminated side) opposite the front side FS. The photodiode doping regions, floating diffusion regions (not illustrated), source / drain regions, and contact regions of the plurality of photodiodes may be disposed proximate to the front side and formed through the front side via one or more implantation steps with one or more implantation energies. In some embodiments, the semiconductor substrate 410 may have a thickness T1 (e.g., see FIG. 1 ) of approximately several hundred micrometers (e.g., 600 μm to approximately 700 μm). Figure 4B ).

[0060] It should be understood that semiconductor substrate 410 may correspond to a portion or the entirety of a semiconductor wafer (e.g., a silicon wafer). In some embodiments, semiconductor substrate 410 includes or is otherwise formed of silicon, silicon-germanium alloys, germanium, silicon carbide alloys, indium gallium arsenide alloys, any other alloys formed from Group III to V compounds, combinations thereof, one or more epitaxial layers of the foregoing materials, or a bulk substrate thereof. More specifically, semiconductor substrate 410 may correspond to any semiconductor material or combination of materials that may be doped or otherwise configured to facilitate formation of a photosensitive region (e.g., a region) of a corresponding pixel or pixel cell. Figure 4A The photodiodes PD1 and PD2 described in Figures 2A to 2B The photodiodes 212, 214, 216 and 218 described in Figures 2A to 2B The pixel units PC1 and PC2 described in Figure 1B The photodiodes in the plurality of pixels 1051 described in Figure 1A ). For example, in some embodiments, semiconductor substrate 410 may correspond to one or more epitaxial layers (e.g., P- or N-doped silicon) formed on a carrier or base substrate wafer. In this embodiment, the photodiodes (e.g., PD1, PD2), floating diffusion regions, source / drain regions, or the like included in the respective pixels or pixel cells may be formed in the one or more epitaxial layers corresponding to semiconductor substrate 410, while the carrier or support wafer may be removed or otherwise thinned during fabrication. For example, the photodiodes (e.g., PD1, PD2), floating diffusion regions, source / drain regions, or the like included in the respective pixels or pixel cells may be formed by ion implantation through a surface defined by the front side FS of semiconductor substrate 410 using various implant energies. In one embodiment, semiconductor substrate 410 is formed of intrinsic or extrinsic silicon, having regions sufficiently doped with an appropriate type of impurity to form photodiode regions for forming photodiodes (e.g., photodiodes PD1, PD2) capable of photogenerating image charge in response to incident light.

[0061] Process block 303 shows forming a gate of the pixel transistor in or on the semiconductor substrate. Examples of gates include Figure 2A The source follower gate SF, row select gate RS, reset gate RST and transfer gates 222, 224, 226, 228 are respectively described in Figure 4B The gate or gate electrode of the pixel transistor may be formed close to the front side FS of the semiconductor substrate 410.

[0062] Process block 305 illustrates performing an optional first annealing process to activate dopants in the semiconductor substrate. In some embodiments, for example, the temperature of the first annealing process is at least greater than or equal to 800° C. and the duration of the first annealing process may range from 30 minutes to 2 hours. In some embodiments, the temperature of the first annealing process is from 800° C. to 1200° C.

[0063] Process block 307 illustrates forming an interlayer dielectric layer over the front side of the semiconductor substrate to encapsulate the gate of the pixel transistor. Figure 4B Block 307 is represented, and a dielectric material (e.g., an oxide-based material) is shown deposited according to a CMOS-compatible deposition process (e.g., chemical vapor deposition) to form an interlayer dielectric layer 430 over a surface corresponding to the front side FS of the semiconductor substrate 410. In some embodiments, the interlayer dielectric layer 430 may be formed of tetraethyl orthosilicate (TEOS) material and / or a high-density plasma (HDP) oxide material. In some embodiments, the interlayer dielectric layer 430 is planarized (e.g., via chemical mechanical polishing) after deposition. As illustrated, the interlayer dielectric layer 430 encapsulates or otherwise encloses a plurality of gates 420 (e.g., transfer gates, source follower gates, reset gates, and row select gates of transistors associated with the pixel cell). In some embodiments, the interlayer dielectric layer 430 corresponds to the closest dielectric layer formed on the front side FS of the semiconductor substrate 110 or on a pre-metal dielectric layer (not illustrated). In other words, in some embodiments, the interlayer dielectric layer may be directly coupled to the front side FS of the semiconductor substrate 410 or a pre-metal dielectric layer that also encapsulates or surrounds the gate electrode associated with the pixel-level transistor. In some embodiments, the interlayer dielectric layer 430 may have a thickness T2 (e.g., along a depth or vertical direction perpendicular to the front side FS of the semiconductor substrate 410) in a range from 200 nanometers to 400 nanometers.

[0064] Process block 309 shows etching through the interlayer dielectric layer and into the semiconductor substrate to form a plurality of interconnect trenches defining photodiode or pixel regions within the semiconductor substrate. Figures 4C to 4E Representative process blocks 309 collectively show etching through the interlayer dielectric layer 430 and into the semiconductor substrate 410 to form a plurality of trenches 412, 414, 416 (e.g., interconnect deep trenches) disposed proximate respective photodiodes PD1, PD2 disposed within the semiconductor substrate 410. As illustrated, the interlayer dielectric layer 430 is disposed over a front side FS of the semiconductor substrate 410 such that the front side FS is disposed between the interlayer dielectric layer 430 and a back side BS of the semiconductor substrate 410.

[0065] In some embodiments, forming trenches 412, 414, and 416 is a multi-step process that includes forming a patterned photoresist layer 440 over interlayer dielectric layer 430, such as Figure 4C The patterned photoresist layer 440 includes a plurality of openings 442, 444, 446 to facilitate selective removal of material from the interlayer dielectric layer 430. The plurality of openings 442, 444, 446 correspond to deep trench isolation structures (e.g., Figures 2A to 2B More specifically, the plurality of openings 442, 444, 446 are used to perform a first etching process to remove material of the interlayer dielectric layer 430 through the plurality of openings 442, 444, 446 to form a plurality of trench openings 432, 434, 436, respectively. The trench openings 432, 434, 436 extend completely through the interlayer dielectric layer 430 until reaching the semiconductor substrate 410 (e.g., the front side FS), as shown. Figure 4D In some embodiments, each of the plurality of trench openings 432, 434, 436 has a trench width W1 along a direction (eg, a horizontal or lateral direction) parallel to the front side FS of the semiconductor substrate 410, as shown in FIG. Figure 4E In the same or other embodiments, each of the plurality of trench openings 432, 434, 436 has a depth substantially the same as or equal to the thickness T2 of the interlayer dielectric layer 430 (e.g., perpendicular to the width W1, corresponding to a vertical direction perpendicular to the surface of the interlayer dielectric layer 430 and / or the front side FS of the semiconductor substrate 410).

[0066] In some embodiments, the patterned photoresist layer 440 is removed after the second etching process is performed. For example, the patterned photoresist layer 440 and / or the plurality of trench openings 432, 434, 436 formed in the interlayer dielectric layer 430 can be used as an etching mask to form trenches 412, 414, 416 (e.g., deep interconnect trenches) in the semiconductor substrate. In other words, the second etching process is performed to remove material of the semiconductor substrate 410 by etching through the plurality of trench openings 432, 434, 436 to form trenches 412, 414, 416, which extend through the interlayer dielectric layer 430 and into the semiconductor substrate 410, as shown in FIG. Figure 4E It will be appreciated that in some embodiments, trenches 412, 414, 416 are deep interconnect trenches that can be used to form Figures 2A to 2B The deep trench isolation structure 227 and Figure 1B In other words, although Figures 4A to 4M The cross-sectional views shown in FIG. 5 show distinct and separate grooves, but when viewed from a plan view (e.g., as Figures 1A to 2B ), the trenches are interconnected to form a grid structure.

[0067] Return Reference Figure 4E , trenches 412, 414, 416 may extend a trench depth D1 in semiconductor substrate 410 relative to the front side FS surface. In one embodiment, trench depth D1 is from 2.5 microns to 8 microns, depending on the final thickness of semiconductor substrate 410. In some embodiments, a width W2 of trenches 412, 414, 416 extending through semiconductor substrate 410 is substantially the same as a width W1 of trenches 412, 414, 416 extending through interlayer dielectric layer 430. It should be understood that in some embodiments, width W1 and width W2 are along a direction parallel to the front side FS of semiconductor substrate 410. In the same or other embodiments, each of trenches 412, 414, 416 may have a substantially constant trench width throughout (e.g., width W1 and / or width W2 are constant throughout depth T2 and / or D1, respectively). In some embodiments, the width W1 and / or the width W2 are from 90 nm to 170 nm (e.g., from 90 nm to 120 nm, from 110 nm to 170 nm, or interpolations thereof). In some embodiments, the trench depth D1 may be based on a target final substrate thickness of the semiconductor substrate 410 (e.g., Figure 4J The thickness T1') is configured.

[0068] Process block 311 illustrates applying a second annealing process to the interlayer dielectric layer to improve the reliability of the image sensor. In some embodiments, the second annealing process is performed from 700° C. to 850° C. for at least 30 minutes. The second annealing process may be performed before forming a plurality of interconnect trenches (e.g., deep trenches (e.g., Figure 4E The second annealing process occurs after the trenches 412, 414, 416 illustrated in FIG. 4 are formed, so that the semiconductor substrate that may have been damaged by the second etching process can benefit from the second annealing process. For example, in one embodiment, the second annealing process is a high temperature annealing process (e.g., hydrogen annealing) that can alleviate or eliminate damage or defects to improve the reliability of the image sensor. In one embodiment, the second annealing process is applied from the front side of the semiconductor substrate at a high temperature (700° C. to 850° C. for at least 30 minutes) while (e.g., by Figure 4E The trenches 412, 414, 416 illustrated in FIG4 expose the semiconductor substrate to atoms, such as hydrogen and / or fluorine, to eliminate dangling bonds created by etch damage (e.g., initiated by the second etch process), which can mitigate defects and thereby improve white pixel and dark current performance associated with the image sensor.

[0069] It should be understood that in some embodiments, the first annealing process of block 305 may be referred to as the highest temperature annealing process of method 300 and the second annealing process of block 311 may be referred to as the next highest annealing process. In other words, the temperature of the first annealing process is greater than the temperature of the second annealing process. However, in other embodiments, the first annealing process of block 305 may be omitted, and the annealing process of block 311 may be the highest temperature annealing process of method 300 and provide both dopant activation and defect elimination. In other words, the first annealing process of block 305 and the second annealing process of block 311 may be combined into a single annealing process having an appropriate temperature (e.g., from 750° C. to 1100° C.). In some embodiments, the combined annealing process may have the highest temperature of all the fabrication processes used to fabricate the example image sensor.

[0070] Process block 313 shows applying a first thermal oxidation to form a liner layer that passivates the sidewalls / bottom surfaces of the plurality of interconnect trenches defining the photodiode or pixel region within the semiconductor substrate. Figure 4F The portion represents process block 313 and shows a first thermal oxidation process being performed to form a liner oxide layer LO that conformally coats the sidewalls and bottom surfaces of the trenches 412, 414, 416 (e.g., before depositing the fill material FM). It should be appreciated that the liner oxide layer LO can passivate the sidewalls and bottom surfaces of the trenches 412, 414, 416 and further protect the underlying surface of the semiconductor substrate 410 during subsequent processing steps. In some embodiments, the thickness T of the liner oxide layer LO is 200 nm. LO In some embodiments, the liner oxide layer LO is formed by a plasma oxidation process using a decoupled plasma oxidation reactor.

[0071] Process block 315 illustrates forming a first high-κ material layer (eg, aluminum oxide, hafnium oxide, tantalum oxide, or other high-κ material having a relative dielectric constant greater than 3.9, or silicon dioxide). Figure 4F Process block 315 is also partially represented and shows the deposition of a first high-κ material HK within trenches 412, 414, and 416. In the illustrated embodiment, the first high-κ material HK conformally coats the liner oxide layer LO to form a high-κ material liner layer lining the liner oxide layer LO. In some embodiments, the first high-κ material HK may conform to the contours of trenches 412, 414, and 416. In some embodiments, the thickness of the first high-κ material HK lining or coating the liner oxide layer LO is from 2.0 nanometers to 80.0 nanometers. In the same or other embodiments, the first high-κ material HK may partially fill trenches 412, 414, and 416. In some embodiments, the first high-κ material HK is deposited using an atomic layer deposition process. In the same or other embodiments, the first high-κ material HK comprises aluminum oxide, hafnium oxide, tantalum oxide, or a combination thereof.

[0072] Process block 317 shows depositing a fill material within the plurality of interconnect trenches defining the photodiode or pixel area to form deep trench isolation structures configured to isolate individual photodiodes from adjacent photodiodes (or pixels from adjacent pixels) included in the image sensor. Figure 4F Process block 317 is also partially represented and shows the deposition of a fill material FM into trenches 412, 414, 416 to form a deep trench isolation structure that isolates the photodiodes (e.g., PD1, PD2) from each other. In some embodiments, the fill material FM can be a dielectric or insulating material (e.g., an oxide-based material such as silicon dioxide) or a conductive material (e.g., polysilicon or metal). In some embodiments, the fill material FM can have a lower refractive index than the substrate region of the semiconductor substrate 410.

[0073] Process block 319 shows the application of a chemical mechanical polishing process to remove excess material (e.g., coating the interlayer dielectric layer). It should be understood that in some embodiments, process blocks 313, 315, and 317 may result in the formation or deposition of one or more of a liner layer, a first high-κ material, and / or a filler material on the exposed surface of the interlayer dielectric layer. For example, referring to Figure 4F The liner oxide LO, the first high-κ material HK, and / or the fill material FM may each form a corresponding layer on the surface of the interlayer dielectric layer 430. It should be understood that in some embodiments, the material deposited outside or otherwise beyond the boundaries of the trenches 412, 414, 416 by process blocks 313, 315, and 317 may be considered excess material. Therefore, a chemical mechanical polishing process may be utilized to remove one or more of the liner oxide LO, the first high-κ material HK, and / or the fill material FM from the surface of the interlayer dielectric layer 430 while also forming a planar surface of the interlayer dielectric layer 430 for subsequent processing steps.

[0074] Return Reference Figure 4F Each of the trenches 412, 414, 416 extending through the interlayer dielectric layer 430 and into the semiconductor substrate 410 is filled with a liner oxide LO, a high-κ material HK, and a filling material FM to form a deep trench isolation structure. As previously discussed, the deep trench isolation structure formed by the trenches 412, 414, 416 is an interconnected grid structure that surrounds and separates individual photodiodes, pixel regions, and / or pixel cells within the semiconductor substrate 410 and the interlayer dielectric layer 430 (e.g., see Figures 1B to 2B ).exist Figure 4FIn the illustrated embodiment, the first portion (or upper trench portion UT) of each trench 412, 414, 416 is formed within the interlayer dielectric layer 430. The first portion (or upper trench portion UT) of each trench 412, 414, 416 includes a first high-κ material HK disposed between the fill material FM and the liner oxide material LO because the first high-κ material HK is deposited after performing the first thermal oxidation process and before depositing the fill material. In the same or other embodiments, the liner oxide material LO and the first high-κ material HK are disposed between the interlayer dielectric layer 430 and the fill material FM. The same arrangement of the liner oxide material LO, the first high-κ material HK, and the fill material FM is also shown in the second portion (or lower trench portion LT) of each trench 412, 414, 416 formed within the semiconductor substrate 410. In other words, within the lower trench portion LT, the first high-κ material HK is disposed between the fill material FM and the liner oxide material LO. In other words, for both the first and second portions of the trenches 412 , 414 , 416 , the fill material FM is surrounded or enclosed by the first high-κ material HK and the first high-κ material HK is in turn surrounded or enclosed by the liner oxide material LO.

[0075] Process block 321 illustrates forming a cap layer on the interlayer dielectric layer. Figure 4G Process block 321 is represented, and an oxide-based material is shown deposited to cover the top surface of the interlayer dielectric layer 430 to form a cap layer 450. As illustrated, the interlayer dielectric layer 430 is disposed between the front side FS of the semiconductor substrate 410 and the cap layer 450. More specifically, the cap layer 450 is formed on the top surface of the interlayer dielectric layer 430, which has the deep trench isolation structure embedded therein (e.g., formed by the trenches 412, 414, 416). In some embodiments, the cap layer 450 can protect the trenches 412, 414, 416 and the materials disposed therein (e.g., the liner oxide material LO, the first high-κ material HK, and the fill material FM) from subsequent processing steps (e.g., so that the exposed portions of the deep trench isolation structure are not damaged by the subsequent processing steps).

[0076] Process block 323 shows forming a plurality of contacts on the interlayer dielectric layer, or more specifically, on the cap layer. Figure 4H Process block 323 is represented, and a plurality of contacts 455 are formed that extend through the cap layer 450 and the interlayer dielectric layer 430 to electrically connect or couple corresponding pixel elements (e.g., gate electrodes, floating diffusion regions, source / drain regions of pixel transistors) for signal routing. In some embodiments, one or more of the plurality of contacts 455 lands on a surface of the front side FS of the semiconductor substrate 410.

[0077] Process block 325 illustrates forming a metallization layer for signal routing (e.g., one or more layers or metal lines and / or vias embedded within one or more inter-metal dielectric layers). The one or more metal lines and / or vias may be collectively referred to as a plurality of metal interconnects embedded within the one or more inter-metal dielectric layers. In some embodiments, the plurality of metal interconnects are coupled to a plurality of contacts to provide signal routing. Figure 4I Process block 325 is represented, and metallization layers 460 are shown including four metal layers, each metal layer including a plurality of metal interconnects 464 embedded in an inter-metal dielectric layer 462. In some embodiments, metallization layers 460 may include one or more metal layers having one or more metal interconnects (e.g., metal lines or vias) formed of a conductive material (e.g., Au, Al, Cu, W), one or more alloys (e.g., aluminum alloy), other conductive materials, or combinations thereof to provide signal routing.

[0078] Process block 327 shows thinning the semiconductor substrate from its backside (ie, opposite the frontside of the semiconductor substrate previously used to form the trenches) to expose portions or surfaces of the deep trench isolation structures proximate the backside of the semiconductor substrate. Figure 4J Process block 327 is represented and shows backside processing of the example image sensor by thinning backside BS of semiconductor substrate 410 to expose backsides of trenches 412, 414, 416 (ie, surfaces 412B, 414B, 416B of the deep trench isolation structures). Figure 4J As illustrated in FIG, a portion of the semiconductor substrate 410 proximate to the backside BS is removed from the backside BS, such that the deep trench isolation structure extends completely through the thinned semiconductor substrate 410 (e.g., the remaining or final bulk substrate, wafer substrate, or epitaxial layer). In some embodiments, a portion of the deep trench isolation structure proximate to the backside BS is also removed during the thinning process of the semiconductor substrate 410. In one embodiment, the semiconductor substrate 410 is thinned using etching and / or chemical mechanical polishing to form a backside BS′ (e.g., the backside of the semiconductor substrate 410 opposite the front side FS after thinning). The backside BS′ exposes distal ends of the lower trench portions LT of the trenches 412, 414, 416 of the deep trench isolation structure. As a result, the deep trench isolation structure formed by the trenches 412, 414, 416 has a depth substantially the same as the thickness T1′ of the semiconductor substrate 410. In other words, the deep trench isolation structure has become a full trench isolation structure or a through-substrate structure after the thinning process is completed, and can be referred to as a full front-side deep trench isolation structure that provides full isolation between adjacent photodiodes (e.g., photodiodes PD1 and PD2), adjacent pixels, and / or pixel cells within the semiconductor substrate. In some embodiments, the thickness T1′ of the semiconductor substrate 410 is the final thickness of the semiconductor substrate 410. In some embodiments, the thickness T1′ of the semiconductor substrate 410 can be in a range from 2.5 microns to 7 microns.

[0079] Process block 329 illustrates applying a second thermal oxidation process to the backside of the semiconductor substrate to form a thin oxide layer that passivates the backside (eg, thinned) surface of the semiconductor substrate. Figure 4K The portion represents process block 329 and shows performing a second thermal oxidation process to form a thin oxide layer 470 on the back side BS' of the semiconductor substrate 410 to provide a surface passivation effect on the back side BS'. In some embodiments, the thickness of the thin oxide layer 470 is from 1.5 nanometers to 2.0 nanometers. It should be understood that in some embodiments, process block 329 can be omitted.

[0080] Process block 331 shows forming a second high-κ material layer over the backside surface to enclose the exposed portion near the backside of the deep trench isolation structure. Figure 4K Process box 331 is also partially represented and shows depositing a second high-κ material 472 on the thin oxide layer 470 such that the thin oxide layer 470 is disposed between the back side BS' of the semiconductor substrate 410 and the second high-κ material 472. As illustrated, proximate the back side BS' of the semiconductor substrate 410, the first high-κ material HK may be disposed between the fill material FM and the second high-κ material 472 in a direction perpendicular to the back side surface. In some embodiments, the layer formed by the second high-κ material 472 has a thickness from 5.0 nanometers to 8.0 nanometers. In the same or other embodiments, the second high-κ material 472 is formed by an atomic layer deposition process. As illustrated, the second high-κ material 472 is deposited to cover the back side BS' of the semiconductor substrate 410 and may be formed on the thin oxide layer 470. In some embodiments, the thickness T of the layer formed by the second high-κ material 472 SECOND HK The thickness T of the layer formed by the first high-κ material HK FIRST HK In some embodiments, the second high-κ material comprises aluminum oxide, hafnium oxide, tantalum oxide, or a combination thereof.

[0081] Process block 333 illustrates forming an antireflective layer on the layer formed of the second high-κ material, while process block 335 illustrates forming subsequent backside elements (eg, metal grid, color filters, microlenses, pad formation, and the like). Figure 4L and Figure 4M Process blocks 333 and 335 are represented, and an anti-reflective layer 474 is shown formed on the second high-κ material 472 . Figure 4L and 4M Further shown are a planarization layer 476 (eg, an oxide-based buffer layer) formed on the anti-reflection layer 474 and a metal grid structure (eg, Figure 4L MG and Figure 4M MG'). Figure 4L and4M Further shown is a plurality of color filters (eg, Figure 4L CF1, CF2 and Figure 4M It will be appreciated that the plurality of color filters are aligned with the corresponding underlying photodiodes (e.g., for Figure 4L , color filter CF1 is optically aligned with PD1 and color filter CF2 is optically aligned with PD2, and for Figure 4M , the color filter CF' is optically aligned with both PD1 and PD2). Figure 4L and 4M Further shown is a micro lens array (eg, CF1, CF2, CF') formed on the color filter array Figure 4L Microlens ML and Figure 4M In some embodiments, an additional dielectric layer LN may be disposed on the corresponding metal grid structure to form a composite metal grid structure, wherein the dielectric layer LN may be formed of or otherwise include an oxide material or a dielectric material having a lower refractive index than adjacent color filters included in the plurality of color filters. Although not described in detail, it should be understood that the process for forming the color filter array may include patterned polymer deposition (e.g., via photolithography) followed by planarization (e.g., via chemical mechanical polishing configured to planarize the polymer surface). Similarly, the microlens array may be fabricated separately and subsequently transferred to the color filter array.

[0082] It should be understood that the Figure 4L and 4M Each microlens in the microlens array (e.g., ML or ML') illustrated in FIG is disposed above or on a corresponding color filter included in the color filter array (e.g., CF1, CF2, CF') and is optically aligned with a corresponding photodiode (e.g., PD1, PD2) for directing incident light to the corresponding photodiode. In some embodiments, Figure 4L Can represent along Figure 2A The cross section of line X-X'. Figure 4L In the illustrated embodiment, photodiodes PD1 and PD2 may be in different pixel cells and thus receive light of different wavelength ranges. For example, CF1 may correspond to a red filter and CF2 may correspond to a green filter to form red and green pixels, respectively. Figure 4L As illustrated in FIG, separate microlenses are employed to direct incident light to individual photodiodes (eg, photodiodes PD, PD2 are in different pixel cells). Figure 4M The same color filter CF' and the same microlens ML' are shown optically aligned with the photodiodes PD1, PD2 (eg, PD1 and PD2 are in the same pixel cell). It should be understood that the metal grid structure (eg, Figure 4LMG and Figure 4M MG') can isolate pixel cells (eg, provide optical isolation between color filters with different spectral photoresponses).

[0083] Return Reference Figure 4L or Figure 4M The image sensor includes photodiodes (e.g., PD1, PD2) disposed within a semiconductor substrate 410 having a front side (FS) and a back side (BS') opposite the front side (FS). The image sensor further includes an interlayer dielectric layer 430 disposed above the front side (FS) of the semiconductor substrate 410, such that the front side (FS) is disposed between the interlayer dielectric layer 430 and the back side (BS). The image sensor further includes a deep trench isolation structure configured to isolate the photodiodes (e.g., PD1, PD2) included in the image sensor from adjacent photodiodes (e.g., PD2, PD1). As illustrated, the deep trench isolation structure includes trenches (e.g., trenches 412, 414, 416) disposed within the interlayer dielectric layer 430 and the semiconductor substrate 410. In the illustrated embodiment, the trenches (e.g., trenches 412, 414, 416) extend through the interlayer dielectric layer 430 and the front side (FS) of the semiconductor substrate 410 toward the back side (BS') of the semiconductor substrate 410. As illustrated, fill material FM is disposed within the trench.

[0084] In some embodiments, the first portion (eg, 412, 414, 416) of the trench (eg, 412, 414, 416) Figure 4F The first width of the upper trench portion UT) described in Figure 4E W1) and a second portion of the trench disposed within the semiconductor substrate 410 (eg, Figure 4F The second width of the lower trench portion LT) described in Figure 4E 1 and W2) are substantially equal (e.g., within 5%). In some embodiments, the first width and the second width each extend in a direction parallel to the front side FS of the semiconductor substrate 410. In the same or other embodiments, the second portion extends to the full depth of the semiconductor substrate 410 (e.g., Figure 4J In some embodiments, the trenches (eg, 412 , 414 , 416 ) of the deep trench isolation structure have a substantially uniform trench width along a direction parallel to the front side FS of the semiconductor substrate 410 .

[0085] like Figure 4M and 4L As illustrated in FIG, the deep trench isolation structure further includes a liner oxide material LO and a first high-κ material HK disposed within the trench. As illustrated, for a first portion (e.g., 412, 414, 416) of the trench (e.g., 412, 414, 416) disposed within the interlayer dielectric layer 430, Figure 4F ), a first high-κ material HK is disposed between the fill material FM and the liner oxide material LO. In the same or other embodiments, the liner oxide material LO conformally coats the sidewalls and bottom surfaces of the trenches (e.g., 412, 414, 416) to form nested trenches disposed within the trenches. In some embodiments, the first high-κ material conformally coats the sidewalls and bottom surfaces of the nested trenches such that the first high-κ material HK is surrounded, encapsulated, or otherwise laterally enclosed by the liner oxide material LO.

[0086] In some embodiments, the thickness (eg, Figure 4F T described in LO ) is less than the thickness of the first high-κ material HK disposed in the trench (eg, Figure 4F T described in FIRST HK ). In the same or other embodiments, Figures 4L to 4M 4. The deep trench isolation structure illustrated in FIG. 4 includes a thin oxide layer 470 and a second high-κ material 472 disposed on the thin oxide layer 470, such that the thin oxide layer 470 is disposed between the back side BS of the semiconductor substrate 410 and the second high-κ material 472. In the same or other embodiments, the first high-κ material HK is disposed between the fill material FM and the second high-κ material 472.

[0087] In the same or other embodiments, the image sensor further includes a gate electrode (eg, Figure 4B ) and disposed in a trench (eg, Figures 4L to 4M In some embodiments, the first high-κ material HK is disposed between the gate electrode 420 and the filling material FM. Figures 4L to 4M In the illustrated embodiment of the present invention, the image sensor further includes a cap layer 450 covering a top surface of the interlayer dielectric layer 430, such that the interlayer dielectric layer 430 is disposed between the front side FS of the semiconductor substrate 410 and the cap layer 450. In some embodiments, the first high-κ material HK, the liner oxide layer LO, and / or the filler material FM disposed within the interlayer dielectric layer 430 are disposed between the cap layer 450 and a second high-κ material 472 formed on or near the back side BS′ of the semiconductor substrate 410.

[0088] In some embodiments, the image sensor includes a contact structure (e.g., a plurality of contacts 455) extending through the cap layer 450 and the interlayer dielectric layer 430 until reaching the front side FS of the semiconductor substrate 410. In the same or other embodiments, the contact structure extends adjacent to the deep trench isolation structure (e.g., trenches 412, 414, 416) disposed within the interlayer dielectric layer 430. Figures 4L to 4M As illustrated in FIG, the image sensor further includes a metallization layer 460 including a plurality of metal interconnects 464. In some embodiments, an interlayer dielectric layer 430 is disposed between the semiconductor substrate 410 and the metallization layer 460. In some embodiments, the filling material FM includes a metal material or a polysilicon material. In the same or other embodiments, the filling material FM of the deep trench isolation structure is configured to receive a bias voltage routed by the plurality of metal interconnects 464. Figures 4L to 4M As described in Figures 1B to 2B When viewed in the context of ), a deep trench isolation structure extends laterally around a photodiode (e.g., PD1, PD2) to isolate the photodiode from adjacent photodiodes included in the image sensor.

[0089] In some embodiments, the deep trench isolation structure further includes a dielectric capping material disposed within the trench to form a dielectric cap structure extending from the backside of the semiconductor substrate into the semiconductor substrate. More specifically, the method 300 may include one or more additional steps before block 313 (e.g., before applying the first thermal oxidation) and / or before block 315 (e.g., before forming the first high-κ material layer) to form the dielectric cap structure.

[0090] Figures 5A to 5E A manufacturing state is shown for forming an image sensor including a deep trench isolation structure having a dielectric cap structure to protect the deep trench isolation structure from damage during backside thinning or etching (eg, process block 327 ) according to an embodiment of the present disclosure.

[0091] like Figure 5A As illustrated in FIG, prior to depositing the first high-κ material (e.g., process block 315) and prior to depositing the fill material (e.g., 317), a dielectric capping material is deposited within the trenches 412, 414, 416 through the trench openings 432, 434, 436 to form dielectric cap structures 512, 514, 516 extending from the bottom of the trenches 412, 414, 416 proximate the back side BS of the semiconductor substrate 410. It should be understood that the dielectric capping material can be deposited before or after the first thermal oxidation process (e.g., process block 313). Thus, the first high-κ material HK is disposed between the dielectric capping material (e.g., the material deposited for the dielectric cap structures 512, 514, 516) and the fill material FM (e.g., see FIG. Figures 5B to 5E In some embodiments, the dielectric cap structures 512 , 514 , 516 may also serve as an etch stop layer during the backside thinning or etching process to prevent damage to the high-κ material HK.

[0092] After forming the dielectric cap structures 512, 514, 516 in each of the trenches 412, 414, 416, a liner oxide layer LO, a first high-κ material HK, and a filling material FM may be sequentially deposited into the trenches 412, 414, 416 to form a deep trench isolation structure (i.e., trenches 412, 414, 416 filled with the dielectric cap structures 512, 514, 516, the liner oxide layer LO, the first high-κ material HK, and the filling material FM), as shown in FIG. Figure 5B In some embodiments, the liner oxide layer LO is disposed on the dielectric cap structures 512, 514, 516 (e.g., the liner oxide layer LO is disposed between the dielectric cap structures 512, 514, 516 and the fill material FM). In the same or other embodiments, the first high-κ material HK is disposed on the liner oxide layer LO, and the fill material FM is disposed on the first high-κ material HK (e.g., the first high-κ material HK is disposed between the liner oxide layer LO and the fill material FM). In the same or other embodiments, the first high-κ material HK is disposed between the fill material FM and the dielectric cap structures 512, 514, 516. It should be understood that Figures 4A to 4D The deep trench isolation structure is Figure 1B The deep trench isolation structure 127 and Figures 2A to 2B An example of a deep trench isolation structure 227 is illustrated in FIG. 2 , which forms an interconnect grid structure to isolate individual photodiodes, pixels, and / or pixel cells.

[0093] Fabrication of the image sensor continues according to method 300 (eg, Figure 5B Representing process blocks 313 to 319) and proceeding as Figure 5C , wherein a cap layer 450, a plurality of contacts 455, and a metallization layer 460 are formed from the front side FS of the semiconductor substrate 410, and then the semiconductor substrate 410 is thinned from the back side BS to expose the dielectric cap structures 512, 514, 516. In some embodiments, the dielectric cap structures 512, 514, 516 may serve as etch stop layers (e.g., the dielectric cap structures provide etch selectivity relative to the semiconductor substrate 410) and prevent damage to the first high-κ material HK formed in the trenches 412, 414, 416 near the back side BS′ of the semiconductor substrate 410. In some embodiments, an etch-back process may be applied to remove excess material (e.g., a portion of the dielectric cap structures 512, 514, 516) to planarize and smooth the surface of the back side BS′ of the semiconductor substrate 410 to facilitate subsequent processing (e.g., formatting of backside devices), such as Figure 5D As described in .

[0094] exist Figures 5C to 5D After the thinning and planarization of the back side BS' of the semiconductor substrate 410 as described in , the fabrication of the image sensor continues, wherein Figure 5E The formation of backside elements (e.g., a thin oxide layer 470, a second high-κ material 472, an antireflection layer 474, a planarization layer 476, a stack of metal grid structure MG and a low-n grid structure (not illustrated), a barrier layer (not illustrated), a color filter array CF including color filters CF1, CF2, a microlens array ML, and the like) corresponding to process blocks 329-335 is shown. Figure 5E , a dielectric capping material is disposed within the trenches 412, 414, 416 to form dielectric cap structures 512, 514, 516 extending from the back side BS′ of the semiconductor substrate 410 into the semiconductor substrate 410. In the same or other embodiments, a filler material FM is disposed between the dielectric capping material of the dielectric capping structures 512, 514, 516 and the cap layer 450. In some embodiments, the dielectric capping material included in the dielectric capping structures 512, 514, 516 is disposed between the first high-κ material HK and the second high-κ material 472.

[0095] Figures 6A to 6C An embodiment according to an embodiment of the present disclosure is described in which the filling material FM of the deep trench isolation structure is coupled to receive a bias voltage to provide enhanced passivation. More specifically, the filling material FM includes a metal material or a polysilicon material configured to receive a bias voltage routed by a plurality of metal interconnects 464. In this embodiment, the filling material FM may contact a metal layer (e.g., a first metal layer) of the metallization layer 460 to receive the bias voltage routed by the metal interconnects 464. It should be understood that the bias voltage may be controlled by a control circuit system (e.g., Figure 1A The control circuit system 121) is provided.

[0096] exist Figures 6A to 6B In the illustrated embodiment of FIG, the deep trench isolation structure further extends through the cap layer 450, while Figure 6C The deep trench isolation structure does not extend through the cap layer 450 , such that the cap layer 450 is disposed between the trenches 412 , 414 , 416 of the deep trench isolation structure and the metallization layer 460 to separate and isolate the deep trench isolation structure from the plurality of metal interconnects 464 of the metallization layer 460 .

[0097] You should understand that Figures 1A to 6CThe embodiments of the present disclosure described herein may be fabricated using conventional semiconductor device processing and microfabrication techniques known to those of ordinary skill in the art, including but not limited to photolithography, ion implantation, chemical vapor deposition, physical vapor deposition, thermal evaporation, sputter deposition, reactive ion etching, plasma etching, wafer bonding, chemical mechanical planarization, and the like. It should be understood that the described techniques are merely illustrative and not exhaustive, and that other techniques may be utilized to fabricate one or more components of the various embodiments of the present disclosure.

[0098] The above description of the illustrated examples of the present invention (including what is described in the Abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the present invention are described herein for illustrative purposes, those skilled in the relevant art will recognize that various modifications are possible within the scope of the invention.

[0099] These modifications may be made to the invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the appended claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. An image sensor, comprising: a photodiode disposed in a semiconductor substrate having a front side and a back side opposite the front side; an interlayer dielectric layer disposed over the front side of the semiconductor substrate such that the front side is disposed between the interlayer dielectric layer and the back side; and a deep trench isolation structure configured to isolate the photodiode from an adjacent photodiode included in the image sensor, wherein the deep trench isolation structure comprises: a trench disposed within the interlayer dielectric layer and the semiconductor substrate, wherein the trench extends through the interlayer dielectric layer and the front side of the semiconductor substrate toward the back side of the semiconductor substrate; and A fill material is disposed within the trench.

2. The image sensor according to claim 1 , wherein a first width of a first portion of the trench disposed in the interlayer dielectric layer is substantially equal to a second width of a second portion of the trench disposed in the semiconductor substrate, wherein the first width and the second width each extend in a direction parallel to the front side of the semiconductor substrate. 3 . The image sensor of claim 2 , wherein the second portion of the deep trench isolation structure extends through a full depth of the semiconductor substrate. 4 . The image sensor according to claim 1 , wherein the trenches of the deep trench isolation structure have a substantially uniform trench width along a direction parallel to the front side of the semiconductor substrate.

5. The image sensor of claim 1 , wherein the deep trench isolation structure further comprises a liner oxide material and a first high-κ material disposed within the trench, wherein for a first portion of the trench disposed within the interlayer dielectric layer, the first high-κ material is disposed between the fill material and the liner oxide material.

6. The image sensor of claim 5 , wherein the liner oxide material conformally coats sidewalls and bottom surfaces of the trench to form a nested trench disposed within the trench, and wherein the first high-κ material conformally coats sidewalls and bottom surfaces of the nested trench such that the first high-κ material is surrounded by the liner oxide material. 7 . The image sensor of claim 5 , wherein a thickness of the liner oxide material disposed within the trench is less than a thickness of the first high-κ material disposed within the trench.

8. The image sensor according to claim 5, further comprising: a thin oxide layer formed on the back side of the semiconductor substrate; and A second high-κ material is disposed on the thin oxide layer such that the thin oxide layer is disposed between the backside of the semiconductor substrate and the second high-κ material, and wherein the first high-κ material is disposed between the fill material and the second high-κ material.

9. The image sensor of claim 8, further comprising a dielectric capping material disposed within the trench to form a dielectric cap structure extending from the backside of the semiconductor substrate into the semiconductor substrate, wherein the dielectric capping material is disposed between the first high-κ material and the second high-κ material.

10. The image sensor according to claim 1, further comprising: a cap layer covering a top surface of the interlayer dielectric layer such that the interlayer dielectric layer is disposed between the front side of the semiconductor substrate and the cap layer; and A dielectric capping material is disposed within the trench to form a dielectric cap structure extending from the backside of the semiconductor substrate into the semiconductor substrate, wherein the fill material is disposed between the dielectric capping material and the cap layer.

11. The image sensor of claim 10, further comprising a contact structure extending through the cap layer and the interlayer dielectric layer until reaching the front side of the semiconductor substrate, wherein the contact structure extends adjacent to the deep trench isolation structure disposed within the interlayer dielectric layer. 12 . The image sensor of claim 1 , further comprising a gate electrode disposed within the interlayer dielectric layer and a first high-κ material disposed within the trench, and wherein the first high-κ material is disposed between the gate electrode and the filling material.

13. The image sensor according to claim 1, further comprising a metallization layer including a plurality of metal interconnects, wherein the interlayer dielectric layer is disposed between the semiconductor substrate and the metallization layer, wherein the filling material comprises a metal material or a polysilicon material, and wherein the filling material of the deep trench isolation structure is configured to receive a bias voltage routed by the plurality of metal interconnects.

14. The image sensor of claim 1, wherein the deep trench isolation structure extends laterally around the photodiode to isolate the photodiode from the adjacent photodiodes included in the image sensor.

15. A method of manufacturing an image sensor, comprising: etching through an interlayer dielectric layer and into a semiconductor substrate to form a trench disposed proximate a photodiode disposed within the semiconductor substrate, wherein the semiconductor substrate includes a front side and a back side opposite the front side, and wherein the interlayer dielectric layer is disposed over the front side of the semiconductor substrate such that the front side is disposed between the interlayer dielectric layer and the back side; and A fill material is deposited within the trench to form a deep trench isolation structure configured to isolate the photodiode from adjacent photodiodes included in the image sensor.

16. The method of claim 15, wherein the etching through the interlayer dielectric layer and into the semiconductor substrate to form the trench comprises: forming a patterned photoresist layer over the interlayer dielectric layer, wherein the patterned photoresist layer comprises an opening; performing a first etching process to remove material of the interlayer dielectric layer by etching the interlayer dielectric layer through the opening to form a trench opening; removing the patterned photoresist layer; A second etching process is performed to remove material of the semiconductor substrate by etching through the trench opening to form the trench extending through the interlayer dielectric layer and into the semiconductor substrate.

17. The method of claim 15, further comprising: performing a first thermal oxidation process to form a liner oxide layer conformally coating sidewalls and a bottom surface of the trench before depositing the fill material; and A first high-κ material is deposited within the trench, wherein after performing the first thermal oxidation process and before depositing the fill material, for a first portion of the trench disposed within the interlayer dielectric layer, the first high-κ material is disposed between the fill material and the liner oxide material.

18. The method of claim 17, further comprising: At least a portion of the semiconductor substrate is removed from the backside to expose the deep trench isolation structure from the backside such that the deep trench isolation structure extends completely through the semiconductor substrate.

19. The method of claim 18, further comprising: performing a second thermal oxidation process to form a thin oxide layer on the back side of the semiconductor substrate; and A second high-κ material is deposited on the thin oxide layer such that the thin oxide layer is disposed between the backside of the semiconductor substrate and the second high-κ material, and wherein the first high-κ material is disposed between the fill material and the second high-κ material.

20. The method of claim 18, further comprising: before depositing the first high-κ material and before depositing the fill material, depositing a dielectric cap material within the trench to form a dielectric cap structure extending from a bottom of the trench proximate the backside of the semiconductor substrate, wherein the first high-κ material is disposed between the dielectric cap material and the fill material; and An oxide-based material is deposited to cover a top surface of the interlayer dielectric layer and to form a cap layer, wherein the interlayer dielectric layer is disposed between the front side of the semiconductor substrate and the cap layer.

Images