A low UVID back contact battery and its preparation method and application

Abstract

The present invention belongs to the technical field of back contact cells, and specifically relates to a low UVID back contact cell, a preparation method thereof, and an application thereof, comprising: SO2, sequentially depositing a phosphorus-free oxygen-doped silicon layer and a phosphorus-doped oxygen-doped silicon layer on the light-receiving surface of a silicon wafer; wherein the phosphorus-free oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer are deposited by continuous coating using tubular PECVD in the presence of a continuous glow plasma, and satisfying the following conditions: H0>H1, W0 <W1,C1≤(3D0×10 19 ) / D1, D0 is 1-5nm, and D1 is 1-5nm; S03, depositing an anti-reflection layer; S04, then performing annealing; S05, then forming a second semiconductor layer on the backlight side. This invention eliminates the need for pre-depositing silicon oxide on the light-receiving surface for the passivation layer, and eliminates the need to dope hydrogen into the anti-reflection layer, thereby ensuring a high passivation level and reducing UVID attenuation.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a low UVID back contact battery, a preparation method thereof, and applications thereof. Background Art

[0002] The existing low-cost process for back-contact cells includes forming a first semiconductor layer on the backlight side of a silicon wafer, and then etching an opening to form a second semiconductor opening area; then cleaning the silicon wafer to remove the first semiconductor layer in the second semiconductor opening area; then forming a third semiconductor layer on the light-receiving side, the third semiconductor layer including a light-receiving side passivation layer and an anti-reflection layer, the light-receiving side passivation layer and the anti-reflection layer are formed by PECVD or Hot-wire method, the light-receiving side passivation layer including an intrinsic amorphous silicon layer and an N-type doped amorphous or microcrystalline silicon layer, the anti-reflection layer being at least one of silicon nitride, silicon oxynitride, and silicon oxide; then removing the backlight side coating, and cleaning to further purify the second semiconductor opening area; then depositing the second semiconductor layer on the backlight side.

[0003] In the above preparation method, the light-receiving surface is deposited with a passivation layer and an anti-reflection layer. If a plate-type PECVD device is used for deposition, the cost is relatively high; if a tube-type PECVD device is used, the temperature is relatively high. Generally, it is necessary to deposit an oxide layer on the light-receiving surface and superimpose the structure of the passivation layer on the light-receiving surface, and then inject hydrogen into the anti-reflection layer to achieve a higher passivation level. However, this method has certain UVID attenuation problems that need to be overcome.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or public known technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of the prior art in the preparation process of back-contact cells that cannot take into account low equipment cost, high passivation level and low UVID, and to provide a low-UVID back-contact cell and its preparation method and application. The present invention can ensure a high passivation level without the need to pre-deposit silicon oxide on the light-receiving surface of the passivation layer, and without the need to dope hydrogen into the anti-reflection layer, while helping to reduce UVID attenuation.

[0006] In order to achieve the above objectives, in a first aspect, the present invention provides a method for preparing a low UVID back contact cell, comprising the following steps:

[0007] S01, forming a first semiconductor layer on the backlight side of the silicon wafer; and performing a first etching opening to form a second semiconductor opening region;

[0008] S02. A non-phosphorus-doped oxygen-doped silicon layer and a phosphorus-doped oxygen-doped silicon layer are sequentially deposited on the light-receiving surface of the silicon wafer to form a light-receiving surface passivation layer, wherein the oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer are independently selected from correspondingly doped amorphous silicon or microcrystalline silicon; wherein the non-phosphorus-doped oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer are deposited by continuous coating in the continuous presence of a glow plasma using tubular PECVD, the phosphorus doping concentration of the phosphorus-doped oxygen-doped silicon layer decreases gradually in the direction away from the silicon wafer, and the phosphorus doping concentration corresponding to the first gradient and the thickness corresponding to the first gradient are denoted as C1 and D1, respectively; the frequency, power, and deposition thickness of the non-phosphorus-doped oxygen-doped silicon layer during deposition are H0, W0, and D0, respectively; the frequency and power of the phosphorus-doped oxygen-doped silicon layer during deposition are H1 and W1, respectively, and satisfy: H0>H1, W0 <W1,C1≤(3D0×10 19 ) / D1, D0 is 1-5nm, D1 is 1-5nm;

[0009] S03, depositing an anti-reflection layer outside the passivation layer on the light-receiving surface, wherein the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide, and carbon-doped silicon oxide;

[0010] S04, then annealing;

[0011] S05. Then, a second semiconductor layer is formed on the backlight surface.

[0012] In some preferred embodiments of the present invention, H0 is 320KHZ-5MHZ, W0 is 500-6000w, H1 is 40-320KHZ, and W1 is 5000-15000w.

[0013] In some preferred embodiments of the present invention, C1 is 1.0×10 18 cm -3 -9.9×10 19 cm -3 .

[0014] In some preferred embodiments of the present invention, the phosphorus doping concentration of the phosphorus doped and oxygen doped silicon layer is in the range of 1×10 18 cm -3 -5×10 19 cm -3 .

[0015] In some preferred embodiments of the present invention, the phosphorus-doped and oxygen-doped silicon layer has a phosphorus-doped concentration gradient that satisfies the following conditions: in the direction away from the silicon wafer, the absolute value of the difference between adjacent phosphorus-doped concentrations with different gradients is 0.1×10 18 cm -3 -1×10 19 cm -3 .

[0016] In some preferred embodiments of the present invention, the sum of the thicknesses of the non-phosphorus-doped oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer is 5-15 nm.

[0017] In some preferred embodiments of the present invention, the oxygen concentration of the phosphorus-doped and oxygen-doped silicon layer is in the range of 1×10 18 cm -3 -1×10 21 cm -3 .

[0018] In some preferred embodiments of the present invention, the oxygen doping concentration of the oxygen-doped silicon layer without phosphorus doping is in the range of 0.5×10 18 cm -3 -8.5×10 19 cm -3 .

[0019] In some preferred embodiments of the present invention, the oxygen doping concentration of the phosphorus-doped and oxygen-doped silicon layer increases gradually in a direction away from the silicon wafer.

[0020] In some preferred embodiments of the present invention, the oxygen concentration gradient of the phosphorus-doped and oxygen-doped silicon layer satisfies the following conditions: in the direction away from the silicon wafer, the absolute value of the difference between adjacent oxygen concentrations with different gradients is 1×10 18 cm -3 -1×10 19 cm -3 .

[0021] In some preferred embodiments of the present invention, the conditions for continuous coating include: a deposition temperature of 350-600° C. and a gas pressure of 1200-2000 mtorr;

[0022] and / or,

[0023] The deposition conditions for the non-phosphorus-doped oxygen-doped silicon layer include: a silane flow rate of 800-2000 sccm, a nitrous oxide flow rate of 200-1000 sccm; the deposition conditions for the phosphorus-doped oxygen-doped silicon layer include: a silane flow rate of 800-2000 sccm, a nitrous oxide flow rate range of 200-2000 sccm, and a phosphine flow rate range of 200-1000 sccm.

[0024] In some preferred embodiments of the present invention, the annealing temperature is 400-700° C., and the annealing time is 15-60 min;

[0025] and / or,

[0026] Annealing conditions include: introducing a protective gas, wherein the protective gas includes nitrogen, argon or a nitrogen-argon mixture, and the annealing pressure is 100-900 mbar.

[0027] In some preferred embodiments of the present invention, the anti-reflection layer comprises silicon nitride with a thickness of 50-100 nm, and the silicon nitride contains high-refractive-index silicon nitride with a refractive index of 2.0-2.3 and low-refractive-index silicon nitride with a refractive index of 1.9-2.0 formed sequentially.

[0028] In some preferred embodiments of the present invention, the anti-reflection layer further comprises carbon-doped silicon oxide disposed outside the silicon nitride, and the total thickness of the anti-reflection layer is 80-130 nm, wherein:

[0029] The thickness of the carbon-doped silicon oxide is 30-80 nm, and / or the refractive index of the carbon-doped silicon oxide is 1.3-1.7.

[0030] In some preferred embodiments of the present invention, the anti-reflection layer is deposited by tubular PECVD, and the deposition conditions include: deposition temperature of 350-600° C., deposition pressure of 1300-2500 mtorr, and power of 5 kW-20 kW;

[0031] and / or,

[0032] The conditions for depositing silicon nitride include: a silane flow rate of 800-2000 sccm, a ammonia flow rate of 6000-15000 sccm; the conditions for depositing carbon-doped silicon oxide include: a silane flow rate of 800-2000 sccm, a nitrous oxide flow rate of 6000-15000 sccm, and a methane flow rate of 500-2000 sccm.

[0033] In some preferred embodiments of the present invention, S01 also includes: forming an isolation layer after forming the first semiconductor layer; then performing a first etching opening on the obtained first semiconductor layer on the backlight side and its isolation layer to form a second semiconductor opening area; then performing texturing cleaning, and selecting whether to perform a step of removing the isolation layer outside the second semiconductor opening area on the backlight side of the silicon wafer through cleaning as needed.

[0034] In some preferred embodiments of the present invention, the preparation method further comprises:

[0035] In S05, the backlight surface coating is first removed and the second semiconductor opening area is cleaned, and then the step of forming the second semiconductor layer is performed;

[0036] S06, performing a second etching to open a portion of the second semiconductor layer on the backlight side of the silicon wafer, to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0037] S07, depositing a conductive film layer on the backlit surface obtained in S06;

[0038] S08, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench;

[0039] S09 , forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0040] In a second aspect, the present invention provides a low UVID back contact battery, which is prepared by the preparation method of the low UVID back contact battery described in the first aspect.

[0041] In a third aspect, the present invention provides a low-UVID back-contact cell, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the backlight surface of the silicon wafer, and further comprising a non-phosphorus-doped oxygen-doped silicon layer and a phosphorus-doped oxygen-doped silicon layer sequentially arranged on the light-receiving surface of the silicon wafer to form a light-receiving surface passivation layer, and an anti-reflection layer arranged outside the light-receiving surface passivation layer, wherein the oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer are each independently selected from amorphous silicon or microcrystalline silicon with corresponding doping, and the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide, and carbon-doped silicon oxide; wherein the light-receiving surface passivation layer is doped with hydrogen, and the phosphorus-doped oxygen-doped silicon layer has a phosphorus doping concentration that decreases in a gradient in a direction away from the silicon wafer, and the phosphorus doping concentration corresponding to the first gradient and the thickness corresponding to the first gradient are denoted as C1 and D1, respectively, and the thickness of the non-phosphorus-doped oxygen-doped silicon layer is denoted as D0, and the following conditions are satisfied: C1≤(3D0×10 19 ) / D1, D0 is 1-5nm, D1 is 1-5nm.

[0042] In some preferred embodiments of the present invention, the oxygen concentration of the phosphorus-doped and oxygen-doped silicon layer increases in a gradient in a direction away from the silicon wafer, and the increase in the oxygen concentration of the phosphorus-doped and oxygen-doped silicon layer satisfies the following conditions: in the direction away from the silicon wafer, the absolute value of the difference between adjacent oxygen concentrations with different gradients is 1×10 18 cm -3 -1×10 19 cm -3 .

[0043] In some preferred embodiments of the present invention, the anti-reflection layer includes silicon nitride and carbon-doped silicon oxide arranged in sequence. The total thickness of the anti-reflection layer is 80-130 nm, the thickness of the silicon nitride is 50-100 nm, and the silicon nitride contains high-refractive-index silicon nitride with a refractive index of 2.0-2.3 and low-refractive-index silicon nitride with a refractive index of 1.9-2.0 formed in sequence. The refractive index of carbon-doped silicon oxide is 1.3-1.7.

[0044] In some preferred embodiments of the present invention, the back contact cell has at least one of the following structures:

[0045] Structure 1, C1 is 1.0×10 18 cm-3 -9.9×10 19 cm -3 ;

[0046] Structure 2: The phosphorus concentration of the phosphorus-doped and oxygen-doped silicon layer is in the range of 1×10 18 cm -3 -5×10 19 cm -3 , the oxygen concentration range is 1×10 18 cm -3 -1×10 21 cm -3 ;

[0047] Structure 3: The decrease in the phosphorus concentration gradient of the phosphorus-doped and oxygen-doped silicon layer satisfies the following requirement: In the direction away from the silicon wafer, the absolute value of the difference in the phosphorus concentration of adjacent different gradients is 0.1×10 18 cm -3 -1×10 19 cm -3 ;

[0048] Structure 4: The sum of the thickness of the non-phosphorus-doped oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer is 5-15 nm;

[0049] Structure 5: The oxygen concentration of the oxygen-doped silicon layer without phosphorus doping is in the range of 0.5×10 18 cm -3 -8.5×10 19 cm -3 ;

[0050] Structure 6. The two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer. A second semiconductor opening area is formed between the adjacent first semiconductor layers. The second semiconductor opening area is spaced apart from the first semiconductor opening area, and the area between them is a spacer area. In the spacer area, an isolation layer is provided between the first semiconductor layer and the second semiconductor layer, or no isolation layer is provided. The back-contact battery also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is provided on the portion of the conductive film layer located in the spacer area. The metal electrode is provided on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area.

[0051] In a fourth aspect, the present invention provides a photovoltaic module comprising the low UVID back contact cell according to the second aspect, or the low UVID back contact cell according to the third aspect.

[0052] Beneficial effects:

[0053] The present invention adopts the above-mentioned technical scheme, especially adopts a continuous coating method with specific variable glow frequency and power on the light-receiving surface to deposit a phosphorus-free oxygen-doped silicon layer and a phosphorus-doped oxygen-doped silicon layer of specific structure in sequence through tubular PECVD, combined with a phosphorus doping concentration that has a suitable relationship with the thickness of the light-receiving surface film layer, and an anti-reflection layer. The passivation layer of the light-receiving surface does not need to be deposited with silicon oxide on the light-receiving surface in advance, and there is no need to separately dope hydrogen into the anti-reflection layer, thereby ensuring a higher passivation level and helping to reduce UVID attenuation.

[0054] The present invention sets a phosphorus-free oxygen-doped silicon layer and a phosphorus-doped oxygen-doped silicon layer with a specific structure on the light-receiving surface, and specially controls C1≤(3D0×10 19 ) / D1, which helps to reduce UVID while ensuring the passivation level of the film layer, and effectively prevents excessively high concentrations of phosphorus from passing through the non-phosphorus-doped oxygen-doped silicon layer and contacting the silicon wafer interface to reduce the passivation effect.

[0055] The present invention utilizes a continuous coating method, whereby the gas is exchanged between layers with different gradient doping levels without stopping the glow. This continuous coating method is beneficial for improving film density and passivation levels. The non-phosphorus-doped oxygen-doped silicon layer of the present invention utilizes a high-frequency, low-power deposition method, while the phosphorus-doped oxygen-doped silicon layer utilizes a medium-frequency, high-power deposition method. This facilitates the dissociation of the reaction gases and allows for film formation on the silicon wafer. This, coupled with the absence of an underlying oxide layer on the light-receiving surface, reduces power damage at the silicon wafer interface and improves the passivation effect of the amorphous silicon on the light-receiving surface. Furthermore, the phosphorus concentration of the phosphorus-doped oxygen-doped silicon layer decreases gradually away from the silicon wafer, which helps reduce UVID attenuation.

[0056] The present invention also has a phosphorus doping concentration that has a suitable relationship with the thickness of the light-receiving surface film layer, so that the hydrogen in the anti-reflection layer penetrates into the light-receiving surface passivation layer and the interface between the light-receiving surface passivation layer and the silicon wafer through the annealing process. The hydrogen ions combine with the dangling bonds of the disordered amorphous silicon network in the light-receiving surface passivation layer (forming Si-H bonds) and directly fill the uncoordinated dangling bonds of the silicon atoms, thereby compensating for the band defects caused by structural disorder. This process effectively reduces the local state density and reduces the probability of carrier recombination. At the same time, the light-receiving surface passivation layer and the anti-reflection layer are more compact during the annealing process, especially the density of the anti-reflection layer is enhanced. In the subsequent cleaning process, the corrosion resistance of the solution can be improved, thereby improving the passivation effect and then improving the battery conversion efficiency; at the same time, the front defects are reduced and the passivation effect is improved, which is beneficial to resist the attenuation of ultraviolet radiation and UVID.

[0057] In the preferred embodiment of the present invention, controlling the oxygen concentration gradient of the phosphorus-doped and oxygen-doped silicon layer is beneficial to reducing the refractive index of the film layer, reducing the parasitic absorption of the amorphous silicon layer, and improving the light transmission performance of the film layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0059] Figure 1 This is a schematic structural diagram of an embodiment of a back-contact battery of the present invention.

[0060] Description of Reference Numerals

[0061] Silicon wafer 1, tunneling silicon oxide layer 2, N-type doped polysilicon layer 3, light-receiving surface passivation layer 5, silicon nitride 61, carbon-doped silicon oxide 62, intrinsic hydrogenated amorphous silicon layer 7, P-type doped amorphous silicon layer 8, transparent conductive film layer 9, metal electrode 10. First semiconductor opening region W1, second semiconductor opening region W2, isolation trench W3. DETAILED DESCRIPTION

[0062] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0063] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0064] The endpoints of the ranges and any values ​​disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values ​​can be combined to form one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed herein. The terms "optional" and "optional" both mean that a range may or may not be included (or may or may not be present).

[0065] In the present invention, the area close to the silicon wafer is considered as the inside, and the area far from the silicon wafer is considered as the outside.

[0066] In a first aspect, the present invention provides a method for preparing a low UVID back contact cell, comprising the following steps:

[0067] S01, forming a first semiconductor layer on the backlight side of the silicon wafer; and performing a first etching opening to form a second semiconductor opening region;

[0068] S02. A non-phosphorus-doped oxygen-doped silicon layer and a phosphorus-doped oxygen-doped silicon layer are sequentially deposited on the light-receiving surface of the silicon wafer to form a light-receiving surface passivation layer, wherein the oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer are independently selected from correspondingly doped amorphous silicon or microcrystalline silicon; wherein the non-phosphorus-doped oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer are deposited by continuous coating in the continuous presence of a glow plasma using tubular PECVD, the phosphorus doping concentration of the phosphorus-doped oxygen-doped silicon layer decreases gradually in the direction away from the silicon wafer, and the phosphorus doping concentration corresponding to the first gradient and the thickness corresponding to the first gradient are denoted as C1 and D1, respectively; the frequency, power, and deposition thickness of the non-phosphorus-doped oxygen-doped silicon layer during deposition are H0, W0, and D0, respectively; the frequency and power of the phosphorus-doped oxygen-doped silicon layer during deposition are H1 and W1, respectively, and satisfy: H0>H1, W0 <W1,C1≤(3D0×10 19 ) / D1, D0 is 1-5nm, D1 is 1-5nm;

[0069] S03, depositing an anti-reflection layer outside the passivation layer on the light-receiving surface, wherein the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide, and carbon-doped silicon oxide;

[0070] S04, then annealing;

[0071] S05. Then, a second semiconductor layer is formed on the backlight surface.

[0072] It can be understood that the frequency and power refer to the frequency and power of the glow power supply.

[0073] Wherein, D0 is 1-5 nm, and D1 is 1-5 nm; the range of 1-5 nm means that they are independently selected from 1 nm, 2 nm, 3 nm, 4 nm, 5 nm and the range between any two points, such as D0 can preferably be 2-5 nm.

[0074] In some preferred embodiments of the present invention, H0 is 320KHZ-5MHZ, more preferably 500KHZ-5MHZ, and W0 is 500-6000w, more preferably 500-5000w.

[0075] In the present invention, preferably, H1 is 40-320KHZ, W1 is 5000-15000w, more preferably 7000-15000w.

[0076] In some preferred embodiments of the present invention, C1 is 1.0×10 18 cm -3 -9.9×10 19 cm -3 , more preferably 7.0×10 18 cm -3 -9.9×10 19 cm -3 .

[0077] In some preferred embodiments of the present invention, the phosphorus doping concentration of the phosphorus doped and oxygen doped silicon layer is in the range of 1×10 18 cm -3 -5×10 19 cm -3 .

[0078] In some preferred embodiments of the present invention, the phosphorus-doped and oxygen-doped silicon layer has a phosphorus-doped concentration gradient that satisfies the following conditions: in the direction away from the silicon wafer, the absolute value of the difference between adjacent phosphorus-doped concentrations with different gradients is 0.1×10 18 cm -3 -1×10 19 cm -3 , more preferably 0.5×10 18 cm -3 -1×10 19 cm -3 The phosphorus-doped and oxygen-doped silicon layer adopts an appropriate phosphorus-doped concentration gradient, which is more conducive to achieving both low UVID and passivation effects.

[0079] In some preferred embodiments of the present invention, the sum of the thicknesses of the non-phosphorus-doped oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer is 5-15 nm, and specifically, for example, can be 5 nm, 6 nm, 6.2 nm, 6.5 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, and any range between any two values, more preferably 6.5-15 nm. This preferred embodiment of the present invention is more conducive to achieving both passivation and optical performance.

[0080] In some preferred embodiments of the present invention, the oxygen concentration of the phosphorus-doped and oxygen-doped silicon layer is in the range of 1×10 18 cm -3 -1×10 21 cm -3 .

[0081] In some preferred embodiments of the present invention, the oxygen doping concentration of the oxygen-doped silicon layer without phosphorus doping is in the range of 0.5×10 18 cm -3 -8.5×10 19 cm -3 .

[0082] In some preferred embodiments of the present invention, the oxygen doping concentration of the phosphorus-doped and oxygen-doped silicon layer increases gradually in a direction away from the silicon wafer.

[0083] In some preferred embodiments of the present invention, the oxygen concentration gradient of the phosphorus-doped and oxygen-doped silicon layer satisfies the following conditions: in the direction away from the silicon wafer, the absolute value of the difference between adjacent oxygen concentrations with different gradients is 1×10 18 cm -3 -1×10 19 cm -3 The phosphorus-doped and oxygen-doped silicon layer adopts an appropriate oxygen-doped concentration gradient change, which is more conducive to improving the light transmittance performance of the film layer.

[0084] In some preferred embodiments of the present invention, the conditions for continuous coating include: a deposition temperature of 350-600° C. and a gas pressure of 1200-2000 mtorr. During the continuous coating process, the gas pressures of different gradient film layers can be the same or different.

[0085] In some preferred embodiments of the present invention, the deposition conditions of the non-phosphorus-doped oxygen-doped silicon layer include: a silane flow rate of 800-2000 sccm and a nitrous oxide flow rate of 200-1000 sccm. The oxygen concentration of the non-phosphorus-doped oxygen-doped silicon layer can be controlled by adjusting the nitrous oxide flow rate.

[0086] In some preferred embodiments of the present invention, the deposition conditions for the phosphorus-doped and oxygen-doped silicon layer include: a silane flow rate of 800-2000 sccm, a nitrous oxide flow rate of 200-2000 sccm, and a phosphine flow rate of 200-1000 sccm. The oxygen concentration and phosphorus concentration of the phosphorus-doped and oxygen-doped silicon layer can be controlled by adjusting the nitrous oxide and phosphine flow rates, respectively.

[0087] In some preferred embodiments of the present invention, the annealing temperature is 400-700° C., and the annealing time is 15-60 min.

[0088] In some preferred embodiments of the present invention, the annealing conditions include: introducing a protective gas at an annealing pressure of 100-900 mbar. Further preferably, the protective gas includes nitrogen, argon, or a nitrogen-argon mixture.

[0089] In the present invention, the anti-reflection layer preferably comprises at least one of silicon nitride, silicon oxynitride, and carbon-doped silicon nitride. This preferred embodiment facilitates hydrogen in the anti-reflection layer to penetrate into the light-receiving surface passivation layer and the interface between the light-receiving surface passivation layer and the silicon wafer, thereby further enhancing the passivation effect.

[0090] In some preferred embodiments of the present invention, the anti-reflection layer comprises silicon nitride, and the thickness of the silicon nitride is 50-100 nm.

[0091] Further preferably, the silicon nitride contains high-refractive-index silicon nitride with a refractive index of 2.0-2.3 and low-refractive-index silicon nitride with a refractive index of 1.9-2.0, which is further conducive to improving the current density. It is understood that the refractive index of the high-refractive-index silicon nitride is greater than the refractive index of the low-refractive-index silicon nitride.

[0092] In some preferred embodiments of the present invention, the anti-reflection layer further includes carbon-doped silicon oxide disposed outside the silicon nitride, which is more conducive to improving the corrosion resistance and current density of the anti-reflection layer.

[0093] Preferably, the total thickness of the anti-reflection layer is 80-130 nm.

[0094] In the present invention, preferably, the thickness of the carbon-doped silicon oxide is 30-80 nm.

[0095] Preferably, the refractive index of carbon-doped silicon oxide is 1.3-1.7.

[0096] In some preferred embodiments of the present invention, the anti-reflection layer is deposited using tubular PECVD. Deposition conditions include a deposition temperature of 350-600°C, a deposition pressure of 1300-2500 mtorr, and a power of 5 kW-20 kW. During the deposition process, the deposition pressure and power of different layers can be independently the same or different.

[0097] In some preferred embodiments of the present invention, the conditions for depositing silicon nitride include: a silane flow rate of 800-2000 sccm, and an ammonia flow rate of 6000-15000 sccm. The present invention can control the refractive index change of silicon nitride by adjusting the ammonia flow rate.

[0098] Preferably, the conditions for depositing carbon-doped silicon oxide include: a silane flow rate of 800-2000 sccm, a nitrous oxide flow rate of 6000-15000 sccm, and a methane flow rate of 500-2000 sccm. The refractive index of the carbon-doped silicon oxide can be controlled by adjusting the methane flow rate.

[0099] In some preferred embodiments of the present invention, S01 also includes: forming an isolation layer after forming the first semiconductor layer; then performing a first etching opening on the obtained first semiconductor layer on the backlight side and its isolation layer to form a second semiconductor opening area; then performing texturing cleaning, and selecting whether to perform a step of removing the isolation layer outside the second semiconductor opening area on the backlight side of the silicon wafer through cleaning as needed.

[0100] Preferably, in the present invention, the isolation layer is at least one of silicon nitride, silicon oxide, silicon oxynitride, and nitrogen-containing polysilicon, and the thickness of the isolation layer is 50-100 nm.

[0101] In the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, and the second semiconductor layer includes a second passivation layer and a second doped silicon layer. The first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer. The first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The second doped silicon layer can be doped amorphous silicon or microcrystalline silicon. The intrinsic silicon layer is preferably an intrinsic amorphous silicon layer. One of the first doped silicon layer and the second doped silicon layer is N-type and the other is P-type. The second semiconductor layer of the present invention can be formed by plate-type CVD, and the deposition temperature of the second semiconductor layer is 150-250°C.

[0102] In some preferred embodiments of the present invention, the first semiconductor layer comprises a first tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer is a stack comprising an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, or a stack comprising a second tunneling oxide layer and a second doped polysilicon layer. The present invention further preferably employs a combined passivation structure, combined with the specific light-receiving surface passivation layer and anti-reflection layer of the present invention, to enhance the passivation effect while reducing UVID attenuation.

[0103] The thicknesses and corresponding doping concentrations of the first tunneling oxide layer, the second tunneling oxide layer or the intrinsic hydrogenated amorphous silicon layer, the first doped polysilicon layer, the second doped silicon layer, and the second doped polysilicon layer of the present invention can refer to the ranges of the prior art and can all be used in the present invention. For example, the thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are each independently 1-2 nm, the thickness of the intrinsic hydrogenated amorphous silicon layer is 5-15 nm; the thickness of the second doped silicon layer is 7-45 nm, the thickness of the second doped polysilicon layer is 60-100 nm, and the effective doping concentrations of the second doped silicon layer and the second doped polysilicon layer are each independently 1e18 cm -3 -9e19cm -3 The thickness of the first doped polysilicon layer is 70-120 nm, and the effective doping concentration is greater than 5e18 cm -3 .

[0104] Preferably, in the present invention, a portion of the silicon wafer located at the second semiconductor opening region is a textured surface, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polished surface.

[0105] In some preferred embodiments of the present invention, the preparation method further comprises: first removing the backlight surface coating and cleaning the second semiconductor opening area in S05, and then performing the step of forming the second semiconductor layer.

[0106] In some preferred embodiments of the present invention, the preparation method further comprises:

[0107] S06, performing a second etching to open a portion of the second semiconductor layer on the backlight side of the silicon wafer, to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0108] S07, depositing a conductive film layer on the backlit surface obtained in S06;

[0109] S08, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench;

[0110] S09 , forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0111] The present invention adopts a continuous coating method with a specific power, and at the same time makes the film density of the light-receiving side passivation layer better. Similarly, the density of the naturally formed back-side coating layer is also better. When first removing the backlight side coating layer and cleaning the second semiconductor opening area in S05, it is necessary to relatively increase the cleaning time by 5%-15%, or relatively increase the cleaning concentration by 5wt%-20wt%.

[0112] In S05 of the present invention, the backlight surface coating is removed and the second semiconductor opening region is cleaned using conventional cleaning solutions. For example, standard cleaning solution No. 1 (SC1), standard cleaning solution No. 2 (SC2), or HF solution can be used. The mass concentration of the HF solution is 0.1%-10%. Standard cleaning solution No. 1 is a mixture of NH4OH / H2O2 / H2O (ammonia / hydrogen peroxide / water) in a ratio of 1:1:5, and standard cleaning solution No. 2 is a mixture of HCl / H2O2 / H2O (hydrochloric acid / hydrogen peroxide / water) in a ratio of 1:1:6. Preferably, the cleaning conditions include a processing temperature of 20°C-30°C and a cleaning time of 50-900 seconds.

[0113] In a second aspect, the present invention provides a low UVID back contact battery, which is prepared by the preparation method of the low UVID back contact battery described in the first aspect.

[0114] In a third aspect, the present invention provides a low-UVID back-contact cell, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the backlight surface of the silicon wafer, and further comprising a non-phosphorus-doped oxygen-doped silicon layer and a phosphorus-doped oxygen-doped silicon layer sequentially arranged on the light-receiving surface of the silicon wafer to form a light-receiving surface passivation layer, and an anti-reflection layer arranged outside the light-receiving surface passivation layer, wherein the oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer are each independently selected from amorphous silicon or microcrystalline silicon with corresponding doping, and the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide, and carbon-doped silicon oxide; wherein the light-receiving surface passivation layer is doped with hydrogen, and the phosphorus-doped oxygen-doped silicon layer has a phosphorus doping concentration that decreases in a gradient in a direction away from the silicon wafer, and the phosphorus doping concentration corresponding to the first gradient and the thickness corresponding to the first gradient are denoted as C1 and D1, respectively, and the thickness of the non-phosphorus-doped oxygen-doped silicon layer is denoted as D0, and the following conditions are satisfied: C1≤(3D0×10 19 ) / D1, D0 is 1-5nm, D1 is 1-5nm.

[0115] The low-UVID back-contact solar cell of the present invention utilizes a specifically structured phosphorus-free oxygen-doped silicon layer and a phosphorus-doped oxygen-doped silicon layer on the light-receiving surface, along with a phosphorus doping concentration suitably related to the thickness of the light-receiving surface film layer, and an anti-reflection layer. This eliminates the need for pre-depositing silicon oxide on the light-receiving surface passivation layer, and eliminates the need for separate hydrogen doping in the anti-reflection layer. This ensures a high level of passivation and helps reduce UVID attenuation. Furthermore, the cell is specifically controlled to have a C1≤(3D0×10 19 ) / D1, which helps to reduce UVID while ensuring the passivation level of the film layer, and effectively prevents excessively high concentrations of phosphorus from passing through the non-phosphorus-doped oxygen-doped silicon layer and contacting the silicon wafer interface to reduce the passivation effect.

[0116] In some preferred embodiments of the present invention, the oxygen concentration of the phosphorus-doped and oxygen-doped silicon layer increases gradually in the direction away from the silicon wafer, which is further beneficial to reducing the refractive index of the film layer, reducing the parasitic absorption of the amorphous silicon layer, and improving the light transmittance of the film layer, thereby improving the current density performance of the battery.

[0117] Further preferably, the oxygen concentration gradient of the phosphorus-doped and oxygen-doped silicon layer satisfies the following requirement: in the direction away from the silicon wafer, the absolute value of the difference between adjacent oxygen concentrations with different gradients is 1×10 18 cm -3 -1×10 19 cm -3 .

[0118] In some preferred embodiments of the present invention, the anti-reflection layer comprises silicon nitride and carbon-doped silicon oxide disposed in sequence. The present invention adopts this preferred solution, which is more conducive to improving the current density and conversion efficiency of the battery.

[0119] In the present invention, preferably, the total thickness of the anti-reflection layer is 80-130 nm.

[0120] In the present invention, preferably, the thickness of silicon nitride is 50-100 nm.

[0121] More preferably, the silicon nitride contains high-refractive-index silicon nitride with a refractive index of 2.0-2.3 and low-refractive-index silicon nitride with a refractive index of 1.9-2.0, which are formed sequentially. The present invention adopts this preferred solution, which is more conducive to improving the current density of the battery.

[0122] In the present invention, preferably, the refractive index of carbon-doped silicon oxide is 1.3-1.7.

[0123] In some preferred embodiments of the present invention, C1 is 1.0×10 18 cm -3 -9.9×10 19 cm -3 .

[0124] In some preferred embodiments of the present invention, the phosphorus doping concentration of the phosphorus doped and oxygen doped silicon layer is in the range of 1×10 18 cm -3 -5×10 19 cm -3 , the oxygen concentration range is 1×10 18 cm -3 -1×10 21 cm -3 .

[0125] In some preferred embodiments of the present invention, the phosphorus-doped and oxygen-doped silicon layer has a phosphorus-doped concentration gradient that satisfies the following conditions: in the direction away from the silicon wafer, the absolute value of the difference between adjacent phosphorus-doped concentrations with different gradients is 0.1×10 18 cm -3 -1×10 19 cm -3 , preferably 0.5×10 18 cm -3 -1×10 19 cm -3 The present invention adopts this preferred solution, which is more conducive to taking into account the performance of high passivation and low UVID.

[0126] In some preferred embodiments of the present invention, the sum of the thickness of the non-phosphorus-doped oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer is 5-15 nm. The present invention adopts this preferred solution, which is more conducive to achieving both high passivation and optical performance.

[0127] In some preferred embodiments of the present invention, the oxygen doping concentration of the non-phosphorus-doped oxygen-doped silicon layer is in the range of 0.5×10 18 cm -3 -8.5×10 19 cm -3 .

[0128] In some preferred embodiments of the present invention, both ends of the second semiconductor layer extend outward to cover part of the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer, and a second semiconductor opening region is formed between adjacent first semiconductor layers. The second semiconductor opening region and the first semiconductor opening region are arranged at intervals, and the area between them is a spacing region; in the spacing region, an isolation layer is set between the first semiconductor layer and the second semiconductor layer, or no isolation layer is set.

[0129] Preferably, in the present invention, the back-contact battery further includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is provided on the portion of the conductive film layer located in the spacing area; the metal electrode is arranged on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area.

[0130] In a fourth aspect, the present invention provides a photovoltaic module comprising the low UVID back contact cell according to the second aspect, or the low UVID back contact cell according to the third aspect.

[0131] The embodiments of the present invention are described in detail below, which are exemplary and only used to explain the present invention, and are not to be construed as limiting the present invention.

[0132] Example 1

[0133] A back contact battery, such as Figure 1 As shown, it is prepared by the following method:

[0134] S1, silicon wafer 1 (N-type single crystal silicon wafer) double-sided polishing;

[0135] S2. Form a first semiconductor layer and an isolation layer on the backlight surface of the silicon wafer 1. The first semiconductor layer includes a tunneling silicon oxide layer 2 and an N-type doped polysilicon layer 3. The tunneling silicon oxide layer 2 has a thickness of 1.5 nm, the N-type doped polysilicon layer 3 has a thickness of 120 nm, and an effective doping concentration of 8.5e19 cm -3 The isolation layer is silicon nitride and the thickness of the isolation layer is 70nm.

[0136] S3, etching an opening on the backlight side of the silicon wafer 1 for the first time to form a second semiconductor opening region W2;

[0137] S4, texturing and cleaning the second semiconductor opening area W2 on the light-receiving side and the backlight side of the silicon wafer 1, and simultaneously removing the isolation layer on the backlight side of the silicon wafer 1 through the final cleaning solution;

[0138] S5. Forming a light-receiving surface passivation layer 5 and an anti-reflection layer on the light-receiving surface of the silicon wafer 1:

[0139] The light-receiving surface passivation layer 5 is composed of a non-phosphorus-doped oxygen-doped amorphous silicon layer and a phosphorus-doped oxygen-doped amorphous silicon layer deposited in sequence, and the total thickness of the light-receiving surface passivation layer 5 is 7nm; the non-phosphorus-doped oxygen-doped amorphous silicon layer and the phosphorus-doped oxygen-doped amorphous silicon layer are deposited by continuous coating using tubular PECVD in the continuous presence of glow plasma, and the deposition temperature of the continuous coating is 460°C.

[0140] The phosphorus doping concentration of the phosphorus-doped and oxygen-doped amorphous silicon layer decreases gradually in the direction away from the silicon wafer, and is specifically divided into five gradient decreases from n1 to n5. The phosphorus doping concentration corresponding to the first gradient and the thickness corresponding to the first gradient are recorded as C1 and D1 respectively. The frequency, power and deposition thickness of the glow power supply during the deposition of the non-phosphorus-doped oxygen-doped amorphous silicon layer are H0, W0 and D0 respectively. The frequency and power of the glow power supply during the deposition of the phosphorus-doped and oxygen-doped amorphous silicon layer are H1 and W1 respectively. H0 is 2MHZ, W0 is 4000w, H1 is 320KHZ, and W1 is 9000w; D0 is 3nm, D1 is 4nm; C1 is 8.6×10 18 cm -3 .

[0141] The oxygen doping concentration of the phosphorus-doped and oxygen-doped amorphous silicon layer increases gradually in the direction away from the silicon wafer, and the oxygen doping concentration of the phosphorus-doped and oxygen-doped amorphous silicon layer ranges from 1×10 18 cm -3 -6.5×10 19 cm -3 , and the increase satisfies the following conditions: in the direction away from the silicon wafer, the absolute value of the difference in oxygen doping concentration between adjacent different gradients is 2×10 18 cm -3 The phosphorus doping concentration of the phosphorus-doped and oxygen-doped amorphous silicon layer is in the range of 1×10 18 cm -3 -8.6×10 18 cm -3 , and the decrease in the phosphorus-doping concentration gradient satisfies the following conditions: in the direction away from the silicon wafer, the absolute value of the difference in phosphorus-doping concentration between adjacent different gradients is 1.6×10 18 cm -3 .

[0142] The oxygen doping concentration of the oxygen-doped amorphous silicon layer without phosphorus doping is 4.5×10 18 cm -3 .

[0143] When depositing the oxygen-doped amorphous silicon layer without phosphorus doping, the flow rate of silane is 1600 sccm, the flow rate of nitrous oxide is 200 sccm, and the gas pressure is 1500 mtorr.

[0144] When depositing the phosphorus-doped and oxygen-doped amorphous silicon layer, the silane flow rate was 1000 sccm, the nitrous oxide flow rate started at 200 sccm and varied by 120 sccm per nm of film thickness, and the phosphine flow rate started at 200 sccm and varied by 150 sccm per nm of film thickness. The gas pressure was 1800 mtorr. The phosphine and nitrous oxide levels for the phosphorus-doped and oxygen-doped amorphous silicon layer were varied in five gradients.

[0145] The anti-reflection layer is a combination of silicon nitride 61 and carbon-doped silicon oxide 62. The total thickness of the anti-reflection layer is 100 nm, of which the thickness of silicon nitride 61 is 70 nm. The silicon nitride 61 contains high-refractive-index silicon nitride (refractive index 2.2) and low-refractive-index silicon nitride (refractive index 2.0). The thickness of carbon-doped silicon oxide 62 is 30 nm, and the refractive index of carbon-doped silicon oxide is 1.6.

[0146] The anti-reflection layer is deposited using a tubular PECVD device at a deposition temperature of 400°C. When depositing silicon nitride 61, the silane flow rate is 1000 sccm, and the ammonia flow rates are adjusted to 6000 sccm and 9000 sccm, respectively, to obtain high-refractive-index silicon nitride and low-refractive-index silicon nitride. The deposition pressure is 1800 mtorr and the power is 13 kW. When depositing carbon-doped silicon oxide 62, the silane flow rate is 1000 sccm, the nitrous oxide flow rate is 11000 sccm, the methane flow rate is 1000 sccm, the deposition pressure is 1500 mtorr, and the power is 10.5 kW.

[0147] S6. Annealing the obtained silicon wafer structure at a temperature of 480° C., nitrogen gas, a pressure of 200 mbar, and a time of 20 minutes.

[0148] S7, removing the backlight surface surrounding plating layer and cleaning the second semiconductor opening area; removing the backlight surface surrounding plating layer and cleaning the second semiconductor opening area, using HF solution, the HF solution mass percentage is 0.2%, the balance is deionized water, the processing temperature is 25 ° C, and the cleaning time is 120s;

[0149] S8, forming a second semiconductor layer on the backlight surface of the silicon wafer 1;

[0150] The second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer 7 and a P-type doped amorphous silicon layer 8. The second semiconductor layer is formed by plate CVD at a deposition temperature of 230°C. The intrinsic hydrogenated amorphous silicon layer 7 has a thickness of 6 nm, the P-type doped amorphous silicon layer 8 has a thickness of 10 nm, and an effective doping concentration of 9e18 cm -3 .

[0151] S9, etching an opening a second time on the backlight side of the silicon wafer 1 to form a first semiconductor opening region W1;

[0152] S10, depositing a transparent conductive film layer 9 on the backlight surface of the silicon wafer 1;

[0153] S11 , etching an opening on the backlight side of the silicon wafer 1 for the third time to form an isolation trench W3 ; after etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 kΩ.

[0154] S12 , forming metal electrodes 10 at the first semiconductor opening region W1 and the second semiconductor opening region W2 on the backlight surface of the silicon wafer 1 .

[0155] Example 2

[0156] The method is carried out in accordance with Example 1, except that the thickness D0 of the oxygen-doped amorphous silicon layer without phosphorus doping is adjusted to 1 nm, and C1 is adjusted to 6.6×10 18 cm -3 The process parameters that need to be adjusted to meet this condition are: reducing the deposition time of the non-phosphorus-doped oxygen-doped amorphous silicon layer by 2 / 3, and reducing the flow rate of 21% phosphine during the deposition of the phosphorus-doped oxygen-doped amorphous silicon layer to meet C1.

[0157] Example 3

[0158] The same method as in Example 1 is used, except that the frequency H0 during the deposition of the non-phosphorus-doped oxygen-doped amorphous silicon layer is adjusted to 400 kHz. The corresponding oxygen concentration of the obtained non-phosphorus-doped oxygen-doped amorphous silicon layer is 4.8×10 18 cm -3 , thickness remains unchanged.

[0159] Example 4

[0160] The process was carried out in accordance with Example 1, except that the power W1 during the deposition of the phosphorus-doped and oxygen-doped amorphous silicon layer was adjusted to 6000W, and the deposition time of the phosphorus-doped and oxygen-doped amorphous silicon layer was extended by 30%. The oxygen concentration of the obtained phosphorus-doped and oxygen-doped amorphous silicon layer was 1×10 18 cm -3 -3.5×10 19 cm -3 , the phosphorus doping concentration is 1×10 18 cm -3 -5.6×10 18 cm -3 , the thickness remains unchanged.

[0161] Example 5

[0162] Refer to Example 1, except that the n5 film thickness of the phosphorus-doped and oxygen-doped amorphous silicon layer is not deposited, that is, it is only deposited to the n4 film thickness of the phosphorus-doped and oxygen-doped amorphous silicon layer; the sum of the thicknesses of the non-phosphorus-doped oxygen-doped amorphous silicon layer and the phosphorus-doped and oxygen-doped amorphous silicon layer is 6.2nm.

[0163] Example 6

[0164] The method is carried out in accordance with Example 1, except that the variation range of the phosphorus doping concentration of the phosphorus doped and oxygen doped amorphous silicon layer is adjusted so that the initial phosphorus doping concentration of the phosphorus doped and oxygen doped amorphous silicon layer remains unchanged, but the corresponding gradient decrease range is different and satisfies the following conditions: in the direction away from the silicon wafer, the absolute value of the difference between adjacent phosphorus doping concentrations of different gradients is 0.1×10 18 cm -3 .

[0165] Example 7

[0166] The process is carried out in accordance with Example 1, except that the oxygen concentration of the phosphorus-doped and oxygen-doped amorphous silicon layer remains the same from the initial concentration in the direction away from the silicon wafer, and increases non-gradiently.

[0167] Example 8

[0168] The process is carried out with reference to Example 1, except that the silicon nitride of the anti-reflection layer is high-refractive-index silicon nitride with the same refractive index, that is, low-refractive-index silicon nitride is not provided.

[0169] Comparative Example 1

[0170] The same procedure is carried out as in Example 1, except that the frequencies during deposition of the oxygen-doped amorphous silicon layer without phosphorus doping and the oxygen-doped amorphous silicon layer with phosphorus doping are the same, that is, H1 is modified to be the same as H0.

[0171] Comparative Example 2

[0172] The process is carried out with reference to Example 1, except that the power during the deposition of the non-phosphorus-doped oxygen-doped amorphous silicon layer and the phosphorus-doped oxygen-doped amorphous silicon layer is the same, that is, W0 is modified to be the same as W1.

[0173] Comparative Example 3

[0174] The same procedure is followed as in Example 1, except that the phosphorus doping concentration of the phosphorus-doped and oxygen-doped amorphous silicon layers is the same in the direction away from the silicon wafer and is C1. To meet this condition, it is sufficient to keep the corresponding inlet gas flow rate unchanged.

[0175] Comparative Example 4

[0176] The method is carried out in accordance with Example 1, except that the phosphorus-doped concentration C1 of the phosphorus-doped and oxygen-doped amorphous silicon layer is 2.5×10 19 cm -3 The process parameters that need to be adjusted to meet this condition are: the initial phosphine flow rate is increased by 3 times.

[0177] Comparative Example 5

[0178] The process is carried out in accordance with Example 1, except that no annealing is performed, and a silicon oxide layer with a thickness of 2 nm is deposited between the light-receiving surface of the silicon wafer and the non-phosphorus-doped oxygen-doped amorphous silicon layer, and a conventional step of hydrogen-doping the silicon nitride in the anti-reflection layer is adopted, that is, hydrogen is also introduced during the deposition of silicon nitride, and the hydrogen flow rate is 4500 sccm.

[0179] Test Case

[0180] The back-contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1. UVID refers to the light-induced attenuation phenomenon produced by a cell under ultraviolet irradiation. The testing method is: use an ultraviolet light box (wavelength range 280-400nm) to continuously irradiate for 2 hours, and evaluate the power attenuation ratio of the cell before and after the cumulative irradiation to determine the light attenuation; the power attenuation ratio is calculated as: (power before irradiation - power after irradiation) / power before irradiation. The smaller the attenuation ratio before and after UVID, the stronger the UVID anti-attenuation ability and the higher the battery stability. Among them, the various performance indicators of each example and comparative example are converted based on Example 1 as a reference benchmark. The data of Example 1 is normalized to 1.000, and the other examples are converted based on Example 1. For example, the UVID power attenuation ratio of Comparative Example 1 / the UVID power attenuation ratio of Example 1 is 33.233.

[0181] Table 1

[0182]

[0183] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention can ensure a higher passivation level by eliminating the need to deposit silicon oxide on the light-receiving surface in advance and the need to incorporate hydrogen into the anti-reflection layer. At the same time, it is beneficial to reduce the UVID power attenuation ratio and improve the battery conversion efficiency.

[0184] Furthermore, according to Example 1 and Examples 2-8, it can be seen that the preferred solution of the present invention is more conducive to improving the passivation level, while further reducing the attenuation of UVID and improving the battery conversion efficiency.

[0185] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, various simple variations of the technical solution of the present invention may be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as disclosed in the present invention and fall within the scope of protection of the present invention.

Claims

1. A method for preparing a low UVID back contact battery, characterized in that: The following steps are involved: S01, forming a first semiconductor layer on the backlight surface of the silicon wafer; and performing a first etching opening to form a second semiconductor opening region; S02. A phosphorus-free oxygen-doped silicon layer and a phosphorus-doped oxygen-doped silicon layer are sequentially deposited on the light-receiving surface of the silicon wafer to form a light-receiving surface passivation layer. The oxygen-doped silicon layer is attached to and in contact with the light-receiving surface of the silicon wafer. The oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer are independently selected from correspondingly doped amorphous silicon or microcrystalline silicon. The phosphorus-free oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer are deposited by continuous coating using tubular PECVD in the continuous presence of glow plasma. The phosphorus doping concentration of the phosphorus-doped oxygen-doped silicon layer decreases gradually in the direction away from the silicon wafer, and the phosphorus doping concentration corresponding to the first gradient and the thickness corresponding to the first gradient are denoted as C1 and D1, respectively. The frequency, power, and deposition thickness of the phosphorus-free oxygen-doped silicon layer during deposition are H0, W0, and D0, respectively. The frequency and power of the phosphorus-doped oxygen-doped silicon layer during deposition are H1 and W1, respectively, and satisfy the following conditions: H0>H1, W0 <W1,C1≤(3D0×10 19 ) / D1, D0 is 1-5nm, D1 is 1-5nm; S03, depositing an anti-reflection layer outside the passivation layer on the light-receiving surface, wherein the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide, and carbon-doped silicon oxide; S04, then annealing; S05. Then, a second semiconductor layer is formed on the backlight surface.

2. The method for preparing a low UVID back contact battery according to claim 1, wherein: H0 is 320KHZ-5MHZ, W0 is 500-6000w, H1 is 40-320KHZ, W1 is 5000-15000w; and / or, C1 is 1.0×10 18 cm -3 -9.9×10 19 cm -3 .

3. The method for preparing a low UVID back contact battery according to claim 1 or 2, characterized in that: The phosphorus doping concentration of the phosphorus-doped and oxygen-doped silicon layer is in the range of 1×10 18 cm -3 -5×10 19 cm -3 and / or, The decrease in the phosphorus concentration gradient of the phosphorus-doped and oxygen-doped silicon layer satisfies the following conditions: in the direction away from the silicon wafer, the absolute value of the difference in the phosphorus concentration of adjacent different gradients is 0.1×10 18 cm -3 -1×10 19 cm -3 .

4. The method for preparing a low UVID back contact battery according to claim 1, wherein: The sum of the thicknesses of the non-phosphorus-doped oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer is 5-15 nm, and / or The oxygen concentration of the phosphorus-doped and oxygen-doped silicon layer is in the range of 1×10 18 cm -3 -1×10 21 cm -3 , and / or, The oxygen concentration of the oxygen-doped silicon layer without phosphorus doping is in the range of 0.5×10 18 cm -3 -8.5×10 19 cm -3 .

5. The method for preparing a low UVID back contact battery according to claim 1 or 4, characterized in that: The oxygen doping concentration of the phosphorus-doped and oxygen-doped silicon layer increases gradually in a direction away from the silicon wafer.

6. The method for preparing a low UVID back contact battery according to claim 5, characterized in that: The oxygen concentration gradient of the phosphorus-doped and oxygen-doped silicon layer satisfies the following requirement: the absolute value of the difference in oxygen concentration between adjacent layers with different gradients is 1×10 18 cm -3 -1×10 19 cm -3 .

7. The method for preparing a low UVID back contact battery according to claim 1, wherein: The conditions for continuous coating include: deposition temperature of 350-600°C and gas pressure of 1200-2000 mtorr; and / or, The deposition conditions for the non-phosphorus-doped oxygen-doped silicon layer include: a silane flow rate of 800-2000 sccm, a nitrous oxide flow rate of 200-1000 sccm; the deposition conditions for the phosphorus-doped oxygen-doped silicon layer include: a silane flow rate of 800-2000 sccm, a nitrous oxide flow rate range of 200-2000 sccm, and a phosphine flow rate range of 200-1000 sccm.

8. The method for preparing a low UVID back contact battery according to claim 1, wherein: The annealing temperature is 400-700°C and the annealing time is 15-60 minutes; and / or, Annealing conditions include: introducing a protective gas, wherein the protective gas includes nitrogen, argon or a nitrogen-argon mixture, and the annealing pressure is 100-900 mbar.

9. The method for preparing a low UVID back contact battery according to claim 1 or 8, characterized in that: The anti-reflection layer includes at least one of silicon nitride, silicon oxynitride, and carbon-doped silicon nitride.

10. The method for preparing a low UVID back contact battery according to claim 9, characterized in that: The anti-reflection layer comprises silicon nitride with a thickness of 50-100 nm. The silicon nitride contains high-refractive-index silicon nitride with a refractive index of 2.0-2.3 and low-refractive-index silicon nitride with a refractive index of 1.9-2.0, which are formed sequentially.

11. The method for preparing a low UVID back contact battery according to claim 10, wherein: The anti-reflection layer further includes carbon-doped silicon oxide disposed outside the silicon nitride. The total thickness of the anti-reflection layer is 80-130 nm, wherein the thickness of the carbon-doped silicon oxide is 30-80 nm, and the refractive index of the carbon-doped silicon oxide is 1.3-1.

7. and / or, The anti-reflection layer is deposited by tubular PECVD, and the deposition conditions include: deposition temperature of 350-600°C, deposition pressure of 1300-2500mtorr, and power of 5kw-20kw.

12. The method for preparing a low UVID back contact battery according to claim 1, wherein: S01 further includes: forming an isolation layer after forming the first semiconductor layer; then performing a first etching opening on the obtained first semiconductor layer and the isolation layer on the backlight side to form a second semiconductor opening area; then performing a texturing cleaning step, and optionally performing a cleaning step to remove the isolation layer outside the second semiconductor opening area on the backlight side of the silicon wafer; and / or, The preparation method further comprises: In S05, the backlight surface coating is first removed and the second semiconductor opening area is cleaned, and then the step of forming the second semiconductor layer is performed; S06, performing a second etching to open a portion of the second semiconductor layer on the backlight side of the silicon wafer, to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S07, depositing a conductive film layer on the backlit surface obtained in S06; S08, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench; S09 , forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

13. A low UVID back contact battery, characterized in that The battery is prepared by the method for preparing a low-UVID back contact battery according to any one of claims 1 to 12.

14. A low UVID back contact solar cell comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the backlight side of the silicon wafer, characterized in that: The invention also includes a phosphorus-free oxygen-doped silicon layer and a phosphorus-doped oxygen-doped silicon layer sequentially arranged on the light-receiving surface of the silicon wafer to form a light-receiving surface passivation layer, and an anti-reflection layer arranged outside the light-receiving surface passivation layer, the oxygen-doped silicon layer is attached to and in contact with the light-receiving surface of the silicon wafer, wherein the oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer are independently selected from correspondingly doped amorphous silicon or microcrystalline silicon, and the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide, and carbon-doped silicon oxide; wherein the light-receiving surface passivation layer is doped with hydrogen, and the phosphorus-doped oxygen-doped silicon layer has a phosphorus doping concentration that decreases in a gradient in a direction away from the silicon wafer, and the phosphorus doping concentration corresponding to the first gradient and the thickness corresponding to the first gradient are respectively recorded as C1 and D1, and the thickness of the oxygen-doped silicon layer without phosphorus doping is recorded as D0, and the following conditions are satisfied: C1≤(3D0×10 19 ) / D1, D0 is 1-5nm, D1 is 1-5nm.

15. The low UVID back contact cell according to claim 14, characterized in that The oxygen concentration of the phosphorus-doped and oxygen-doped silicon layer increases in a gradient in the direction away from the silicon wafer. The increasing amplitude of the oxygen concentration gradient of the phosphorus-doped and oxygen-doped silicon layer satisfies the following requirement: in the direction away from the silicon wafer, the absolute value of the difference between the oxygen concentrations of adjacent different gradients is 1×10 18 cm -3 -1×10 19 cm -3 ; and / or, The anti-reflection layer includes silicon nitride and carbon-doped silicon oxide arranged in sequence. The total thickness of the anti-reflection layer is 80-130nm, the thickness of the silicon nitride is 50-100nm, and the silicon nitride contains high-refractive-index silicon nitride with a refractive index of 2.0-2.3 and low-refractive-index silicon nitride with a refractive index of 1.9-2.0 formed in sequence. The refractive index of carbon-doped silicon oxide is 1.3-1.

7.

16. The low UVID back contact cell according to claim 14 or 15, characterized in that The back contact cell has at least one of the following structures: Structure 1, C1 is 1.0×10 18 cm -3 -9.9×10 19 cm -3 ; Structure 2: The phosphorus concentration of the phosphorus-doped and oxygen-doped silicon layer is in the range of 1×10 18 cm -3 -5×10 19 cm -3 , the oxygen concentration range is 1×10 18 cm -3 -1×10 21 cm -3 ; Structure 3: The phosphorus-doped and oxygen-doped silicon layer has a phosphorus-doped concentration gradient that satisfies the following conditions: In the direction away from the silicon wafer, the absolute value of the difference between adjacent phosphorus-doped concentrations with different gradients is 0.1×10 18 cm -3 -1×10 19 cm -3 ; Structure 4: The sum of the thickness of the non-phosphorus-doped oxygen-doped silicon layer and the phosphorus-doped oxygen-doped silicon layer is 5-15 nm; Structure 5: The oxygen concentration of the oxygen-doped silicon layer without phosphorus doping is in the range of 0.5×10 18 cm -3 -8.5×10 19 cm -3 ; Structure 6. The two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer. A second semiconductor opening area is formed between the adjacent first semiconductor layers. The second semiconductor opening area is spaced apart from the first semiconductor opening area, and the area between them is a spacer area. In the spacer area, an isolation layer is provided between the first semiconductor layer and the second semiconductor layer, or no isolation layer is provided. The back-contact battery also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is provided on the portion of the conductive film layer located in the spacer area. The metal electrode is provided on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area.

17. A photovoltaic module, characterized in that: It comprises the low UVID back contact cell according to claim 13, or comprises the low UVID back contact cell according to any one of claims 14-16.

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