Chip packaging structure based on adapter board, electronic device and preparation method

Abstract

The present invention discloses a chip packaging structure, electronic device and preparation method based on an adapter board, which are applied to the field of chip packaging. The first surface of the adapter board is provided with a first redistribution layer, which includes multiple layers of stacked connection wiring layers, and adjacent connection wiring layers are isolated by a first dielectric layer; each layer of connection wiring layer includes multiple metal wirings, and each metal wiring has at least one corresponding guide hole in the first dielectric layer on the back side; along the direction back to the adapter board, the number of corresponding guide holes in the first dielectric layer outside the outermost connection wiring layer is greater than the number of corresponding guide holes in the first dielectric layer outside the innermost connection wiring layer; the pins are located on the adapter board, and the pins are arranged in an array within the mapping range along the first surface back to the adapter board. The present invention improves the layout density of the pins by preparing a redistribution layer formed by stacking multiple layers of connection wiring layers on the front side of the adapter board.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging, and in particular to a chip packaging structure based on an adapter board, an electronic device, and a preparation method thereof. Background Art

[0002] Existing chip packaging technology cannot meet the massive transfer requirements of MicroLED (micro-light-emitting diode) chips, hindering the further development of electronic products. Traditional chip packaging processes are unable to meet this demand due to the following main issues: limited chip lead density, which cannot achieve high-density interconnection; large package size, which makes it difficult to meet the requirements of thinness and compactness; and complex manufacturing processes and high costs.

[0003] Therefore, there is an urgent need for a new chip packaging structure and a preparation method thereof to solve the problems existing in the prior art and realize the mass transfer of Mircoled chips. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a chip packaging structure, electronic equipment and preparation method based on an adapter board, which solves the problems in the prior art that high-density interconnection cannot be achieved during the chip packaging process, and the chip packaging size is large, the manufacturing process is complex, and the cost is high.

[0005] In order to solve the above technical problems, the present invention provides a chip packaging structure based on an adapter board, comprising an adapter board;

[0006] The first surface of the adapter plate includes electrodes; each of the electrodes is connected to a corresponding pad located on one side of the second surface of the adapter plate through a conductive component provided in a through hole in the corresponding adapter plate;

[0007] A first redistribution layer is provided on the first surface of the adapter board, wherein the first redistribution layer includes multiple stacked connection wiring layers, and adjacent connection wiring layers are isolated by a first dielectric layer; each connection wiring layer includes multiple metal wirings;

[0008] The first dielectric layer is provided with a connecting hole, and a wire is provided in the connecting hole, and the wire is used to connect the corresponding metal wiring in the adjacent connecting wiring layer; each metal wiring is correspondingly provided with at least one connecting hole in the first dielectric layer on the side facing away from the adapter board;

[0009] In a direction facing away from the adapter board, the number of the corresponding guide holes provided in the first dielectric layer outside the outermost connection wiring layer is greater than the number of the corresponding guide holes provided in the first dielectric layer outside the innermost connection wiring layer;

[0010] The outermost connection wiring layer is connected to a pin corresponding to each of the guide holes, and each of the metal wirings in the innermost connection wiring layer is connected to a corresponding electrode; the pins are located on the adapter board, within a mapping range along the first surface facing away from the adapter board;

[0011] The pins connected to the outermost connection wiring layer are arranged in an array, and the pins arranged in the array are correspondingly connected to the chip, and the pins and the chip are encapsulated in a plastic package.

[0012] Optionally, the first redistribution layer includes three stacked connection wiring layers; the three stacked connection wiring layers include a first connection wiring layer, a second connection wiring layer, and a third connection wiring layer sequentially arranged along a direction facing away from the adapter board;

[0013] An extending direction of the metal wiring in the second connection wiring layer is perpendicular to an extending direction of the metal wiring in the third connection wiring layer.

[0014] Optionally, a second redistribution layer is provided on the second surface of the adapter board; the second redistribution layer is a redistribution layer formed by a single-layer connection wiring layer;

[0015] A second dielectric layer is formed on the surface of the second redistribution layer, and an opening is formed in the second dielectric layer to expose the corresponding pad.

[0016] Optionally, an insulating layer is formed on the inner wall of the through hole.

[0017] Optionally, the insulating layer is one of a silicon oxide layer, a silicon nitride layer, and a polyimide layer;

[0018] A metal seed layer is formed on the surface of the insulating layer in the through hole, and a copper metal lead or an aluminum metal lead is formed by electroplating on the surface of the metal seed layer.

[0019] Optionally, the first dielectric layer is a polyimide layer.

[0020] The present invention also provides an electronic device, comprising the above-mentioned chip packaging structure based on the adapter board.

[0021] The present invention also provides a method for preparing a chip packaging structure based on an adapter plate, which is used to prepare the above-mentioned chip packaging structure based on the adapter plate, comprising:

[0022] Providing a substrate, sequentially and cyclically stacking a first dielectric layer and a connection wiring layer on a first surface of the substrate, and connecting a plurality of groups of pins in an array at the outermost connection wiring layer in a direction facing away from the substrate;

[0023] A through hole is formed in the substrate, passing through the first surface to the second surface, and a conductive component is formed in the through hole to connect the electrode corresponding to the pin to the pad located on one side of the second surface of the substrate;

[0024] The pins are connected to the chip respectively, and the pins and the chip are plastic-sealed to complete the preparation of the chip packaging structure based on the adapter board.

[0025] Optionally, preparing a conductive component in the through hole to connect the electrode corresponding to the pin to the pad located on the second surface side of the substrate includes:

[0026] preparing an insulating layer on the inner wall of the through hole, and preparing a metal seed layer on the surface of the insulating layer;

[0027] Metal leads are prepared by electroplating on the surface of the metal seed layer.

[0028] Optionally, the step of sequentially and cyclically stacking a first dielectric layer and a connection wiring layer on the first surface of the substrate includes:

[0029] A first dielectric layer is formed with a connecting hole on the first surface of the substrate to expose a portion of the electrode;

[0030] preparing a connection wiring layer on the surface of the first dielectric layer as a target connection wiring layer;

[0031] The lead hole is formed on the surface of the target connection wiring layer to expose a portion of the first dielectric layer of the target connection wiring layer as the current first dielectric layer;

[0032] A connection wiring layer is prepared again on the surface of the current first dielectric layer as a new target connection wiring layer, and the step of preparing the first dielectric layer with the connection holes formed on the surface of the target connection wiring layer to expose a portion of the target connection wiring layer is performed until the preparation of multiple layers of the connection wiring layer and the first dielectric layer is completed.

[0033] It can be seen that the chip packaging structure based on the adapter board provided by the present invention includes an adapter board; the first surface of the adapter board includes electrodes; each electrode is connected to the corresponding pad on one side of the second surface of the adapter board through a conductive component provided in a through-hole in the corresponding adapter board; the first surface of the adapter board is provided with a first redistribution layer, the first redistribution layer includes a plurality of stacked connection wiring layers, and adjacent connection wiring layers are isolated by a first dielectric layer; each connection wiring layer includes a plurality of metal wirings; a guide hole is provided in the first dielectric layer, and a wire is provided in the guide hole, and the wire is used to connect the corresponding metal wirings in the adjacent connection wiring layers; each metal wiring is on the side facing away from the adapter board. In the first dielectric layer, at least one guide hole is correspondingly provided; in the direction facing away from the adapter plate, the number of guide holes correspondingly provided in the first dielectric layer outside the outermost connection wiring layer is greater than the number of guide holes correspondingly provided in the first dielectric layer outside the innermost connection wiring layer; the outermost connection wiring layer is connected to a pin corresponding to each guide hole, and each metal wiring in the innermost connection wiring layer is connected to an electrode correspondingly; the pins are located on the adapter plate, within the mapping range along the first surface facing away from the adapter plate; the pins connected to the outermost connection wiring layer are arranged in an array, and the pins arranged in the array are connected to the chip correspondingly, and the pins and the chip are encapsulated in a plastic package. By providing an adapter plate, the present invention can reduce the material used for the plastic package, eliminate the need to thin the plastic package, and improve production efficiency. In addition, by preparing a redistribution layer formed by stacking and arranging multiple layers of connection wiring layers on the front side of the adapter plate, the layout density of the pins in the chip packaging structure can be increased, thereby achieving high-density interconnection of the structure. Based on the above structure, the overall size of the chip package can be reduced, the complexity of the chip packaging structure preparation can be reduced, and the chip packaging structure can be made thinner.

[0034] In addition, the present invention also provides an electronic device and a method for preparing a chip packaging structure based on an adapter board, which also have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0036] Figure 1 A schematic structural diagram of a chip packaging structure based on an adapter board provided in an embodiment of the present invention;

[0037] Figure 2 A flowchart of a method for preparing a chip packaging structure based on an adapter board provided in an embodiment of the present invention;

[0038] Figure 3 A schematic cross-sectional view of a chip packaging structure based on an adapter board without a through hole provided in an embodiment of the present invention;

[0039] Figure 4 A schematic top view of a chip packaging structure based on an adapter board provided by an embodiment of the present invention without a through hole;

[0040] Figure 5 A schematic cross-sectional view of an unconnected chip in a chip packaging structure based on an adapter board provided by an embodiment of the present invention;

[0041] Figure 6 A schematic cross-sectional view of a chip packaging structure based on an adapter board provided in an embodiment of the present invention, wherein the chip packaging structure is not plastic-sealed;

[0042] Figure 7 A schematic top view of a chip packaging structure based on an adapter board provided in an embodiment of the present invention before plastic encapsulation;

[0043] The following are the descriptions of the reference numerals:

[0044] 1- adapter board, 2- substrate, 10- connection wiring layer, 20- first dielectric layer, 30- pins, 40- chip, 50- plastic package, 60- conductive component, 61- insulation layer, 70- pad, 80- second dielectric layer. DETAILED DESCRIPTION

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0046] Please refer to Figure 1 , Figure 1 A schematic diagram of a chip packaging structure based on an adapter board provided in an embodiment of the present invention. The chip packaging structure may include an adapter board 1;

[0047] The first surface of the adapter board 1 includes electrodes; each electrode is connected to a corresponding pad 70 located on one side of the second surface of the adapter board 1 through a conductive component 60 provided in a through hole in the corresponding adapter board 1;

[0048] A first redistribution layer is provided on the first surface of the adapter board 1. The first redistribution layer includes multiple stacked connection wiring layers 10. Adjacent connection wiring layers 10 are isolated by a first dielectric layer 20. Each connection wiring layer 10 includes multiple metal wirings.

[0049] The first dielectric layer 20 is provided with a conducting hole, in which a conductor is provided. The conductor is used to connect the corresponding metal wirings in the adjacent connecting wiring layer 10. Each metal wiring is provided with at least one conducting hole in the first dielectric layer 20 on the side facing away from the adapter board 1.

[0050] In the direction away from the adapter board 1, the number of corresponding conductive holes provided in the first dielectric layer 20 outside the outermost connection wiring layer 10 is greater than the number of corresponding conductive holes provided in the first dielectric layer 20 outside the innermost connection wiring layer 10;

[0051] The outermost connection wiring layer 10 is connected to a pin 30 corresponding to each lead hole, and each metal wiring in the innermost connection wiring layer 10 is connected to an electrode correspondingly; the pin 30 is located on the adapter board 1, within the mapping range along the first surface in the direction away from the adapter board 1;

[0052] The pins 30 connected to the outermost connection wiring layer 10 are arranged in an array, and the pins 30 arranged in the array are correspondingly connected to the chip 40 . The pins 30 and the chip 40 are encapsulated in a plastic package 50 .

[0053] In this embodiment, the first redistribution layer located on one side of the adapter board 1 includes at least two layers of connection wiring layers 10. It is clear that, within the upper limit of pin placement density, the greater the number of connection wiring layers 10 in the first redistribution layer, the higher the placement density of the corresponding array-connected pins 30. Therefore, by adjusting the number of first redistribution layers on one side of the adapter board 1, the pin density of the chip 40 can be flexibly adjusted to achieve high-density interconnection. This embodiment is specifically applicable to devices with RGB (RGB represents the three primary colors of light: red, green, and blue) chips. In this case, the spacing between each group of RGB pins 30 can be set to 10 microns to 100 microns, and the number of connection wiring layers 10 in the first redistribution layer can be set to three, thereby achieving high-density interconnection of the chip 40 pins. For ease of description, the side of the adapter board 1 where the first redistribution layer is located is designated as the upper side, and the side closer to the adapter board 1 is designated as the lower side. In this case, the first dielectric layer 20 and the connection wiring layer 10 are stacked vertically from bottom to top. In one feasible embodiment, the first dielectric layer 20 can be configured as a polymer insulating layer, while the connection wiring layer 10 is typically constructed of copper. This improves the thermal expansion coefficient compatibility with the connection wiring layer 10, provides a more compatible polymer insulating layer with greater flexibility, reduces the risk of brittle fracture, and exhibits excellent chemical resistance and environmental stability. The conductive holes provided in the first dielectric layer 20 for connecting different connection wiring layers 10 can be circular, square, or other irregular shapes, preferably circular to reduce stress accumulation, and extend through the first dielectric layer 20. Furthermore, the conductive holes can be fabricated by photolithography and etching, or by laser ablation. In this embodiment, the positions of the conductive holes are determined by the locations of the upper and lower layers of the rewiring. The conductive holes can generally be filled with a metal conductive material to connect adjacent connection wiring layers 10. These holes can be fabricated simultaneously with the fabrication of the connection wiring layers 10, or separately by electroplating, electroless plating, sputtering and electroplating, or filling with a conductive paste to achieve vertical interconnection between layers. It should be noted that the outermost connection wiring layer 10 in this embodiment is the connection wiring layer 10 farthest from the adapter board 1. At the surface of the outermost connection wiring layer 10, the width of the pins 30 can be set to 5 microns to 100 microns.

[0054] In addition, in this embodiment, by setting a multi-layer connection wiring layer 10 on one side of the adapter board 1, while achieving high-density interconnection of the leads of the RGB chip, the position of the chip 40 pad 70 can be redistributed to improve the flexibility of the connection. In this embodiment, a solder paste layer can be prepared on the surface of the outermost connection wiring layer 10 to facilitate welding with the pins 30. For example, a nickel layer, an organic solder-preservative film layer, or a tin layer, a silver layer or other film layer can be prepared on the surface of the outermost connection wiring layer 10. In this embodiment, the multiple groups of pins 30 connected in an array can be arranged in a rectangular array to ensure the regularity of the structure and increase the density of the chip 40. In this embodiment, the pins 30 can be connected to the outermost connection wiring layer 10 by reflow soldering, hot pressing bonding or conductive adhesive bonding, and can be connected to the chip 40 by reflow soldering. In this embodiment, the plastic package 50 can be made of a thermosetting resin material, such as an epoxy resin material. The plastic package 50 wraps all the pins 30 and all the chips 40 to protect the device.

[0055] In this embodiment, the through hole runs through the entire adapter board 1 and is set corresponding to the connection wiring layer 10 closest to the adapter board 1 to connect the pins 30 connected to the array to the pads 70 on the other side of the adapter board 1, forming a one-to-one correspondence between the pins 30 on one side of the adapter board 1 and the pads 70 on the other side. The diameter of the through hole can be set to 10 microns to 100 microns, and the depth can be set to 50 microns to 500 microns. An insulating layer 61 is set on the side wall of the through hole to prevent the device from short-circuiting, and then a conductive component 60 is prepared in the insulating layer 61 to achieve the connection between the connection wiring layer 10 on the first surface and the pads 70 on the second surface. In this embodiment, the pads 70 located on the second surface side of the adapter board 1 can be set directly opposite the pins 30 on the first surface side of the adapter board 1 to further improve the regularity of the device. In a feasible embodiment, the conductive component 60 in the through hole can be directly connected to the pad 70, or the conductive component 60 in the through hole can also be connected to the pad 70 through the redistribution layer located on the second surface of the adapter board 1. In addition, the chip 40 in this embodiment can be connected to the pins 30 in a flip-chip manner.

[0056] Furthermore, in order to ensure the lead wiring density, the first redistribution layer may include three stacked connection wiring layers 10; the three stacked connection wiring layers 10 include a first connection wiring layer, a second connection wiring layer, and a third connection wiring layer sequentially arranged along the back of the adapter board 1;

[0057] An extending direction of the metal wiring in the second connection wiring layer is perpendicular to an extending direction of the metal wiring in the third connection wiring layer.

[0058] It should be noted that the spacing between the pins 30 of the conventional package is generally greater than 150 microns, which makes it difficult to meet the high-density interconnection of the device, thereby increasing the area of ​​the adapter board 1. Directly reducing the spacing between adjacent pins 30 also results in insufficient processing accuracy and signal interference. In this embodiment, based on the multi-layer connection wiring layer 10 arranged on the first surface of the adapter board 1, the connection wiring layer 10 on one side of the first surface of the adapter board 1 is controlled to be a three-layer stacked structure, so as to reduce the spacing between adjacent pins 30 to 10 microns to achieve high-density interconnection of the device, while ensuring that the plastic encapsulation material can fully fill the gap between the pins 30 to avoid the occurrence of voids. In addition, the width of the pins 30 can be set to 5 microns to 100 microns, which can ensure the mechanical strength of the pins 30 and improve the stability of the pins 30. When the spacing between the pins 30 is greater than or equal to 10 microns, it can meet the requirements of high-speed signal transmission, and can reduce the presence of pores when the plastic encapsulation body 50 is filled, avoiding the problem of thermal stress concentration caused by insufficient filling.

[0059] Furthermore, in order to improve the flexibility of the layout of the pads 70, a second redistribution layer may be provided on the second surface of the adapter board 1; the second redistribution layer is a redistribution layer formed by a single-layer connection wiring layer 10;

[0060] A second dielectric layer 80 is formed on the surface of the second redistribution layer. An opening is formed in the second dielectric layer 80 to expose the corresponding pad 70 .

[0061] It should be noted that in this embodiment, a second redistribution layer is formed by setting a single-layer connection wiring layer 10 on the second surface of the adapter board 1, and the second redistribution layer is used to connect the conductive structure in the through-hole to the corresponding pad 70, so as to realize the flexible arrangement of the pad 70 on the second surface of the adapter board 1. In this embodiment, the second redistribution layer can fan out the pad 70 connected to the conductive structure in the through-hole from the position of the projection area of ​​the chip 40 to the edge of the adapter board 1. In this embodiment, the second dielectric layer 80 can be set as a polymer insulating layer, specifically a polyimide layer or an epoxy resin layer, and the opening in the second dielectric layer that exposes the corresponding pad 70 is actually an opening that exposes the connection wiring layer 10 in the second redistribution layer. The size of the exposed connection wiring layer 10 in the second redistribution layer can be set to 100 microns to 500 microns in length and 100 microns to 500 microns in width. It should be further noted that in this embodiment, the side wall of the through hole is inclined during preparation, and the specific inclination angle can be in the range of 80 degrees to 85 degrees.

[0062] In addition, in this embodiment, in order to ensure that other structures are not affected when preparing the second dielectric layer 80, the curing temperature of the second dielectric layer 80 can be set to be lower than the tolerance temperature of the plastic package 50 and the first redistribution layer, so as to avoid the packaged chip 40 and the plastic package 50 from failing due to high temperature. Compared with traditional single-sided wiring, the second redistribution layer of this embodiment realizes double-sided high-density interconnection, and uses the second redistribution layer to adjust the pad 70 from the area directly below the chip 40 to the area not covered by the chip 40, which is convenient for heat dissipation and maintenance during subsequent circuit board assembly.

[0063] Furthermore, in order to prevent the conductive structure provided in the through hole from short-circuiting, an insulating layer 61 may be formed on the inner wall of the through hole.

[0064] In this embodiment, by setting an insulating layer 61 on the inner wall of the through hole, the conductive component 60 on the inner wall of the through hole can be isolated from the substrate 2 material of the adapter board 1, thereby avoiding the problem of current leakage or short circuit. At the same time, the parasitic capacitance between the through hole and the adapter board 1 can be reduced, thereby improving the integrity of the high-frequency signal. It should be noted that when the conductive component 60 in the through hole in this embodiment extends to the second surface of the adapter board 1, when it is connected to the second redistribution layer located on the second surface of the adapter board 1, since the second redistribution layer has an extension structure in a direction parallel to the second surface of the adapter board 1, an insulating layer can be prepared on the entire surface of the second surface of the adapter board 1 to further isolate the above-mentioned conductive component 60 from contacting the adapter board 1 and causing a short circuit. Alternatively, the insulating layer can be precisely prepared only at the position corresponding to the connection wiring layer 10 in the second redistribution layer on the second surface of the adapter board 1.

[0065] Furthermore, in order to ensure that the insulating layer 61 and the conductive component 60 in the through hole are smoothly prepared, the insulating layer 61 can be set to be one of a silicon oxide layer, a silicon nitride layer, and a polyimide layer;

[0066] A metal seed layer is formed on the surface of the insulating layer 61 in the through hole, and a copper metal lead or an aluminum metal lead is formed on the surface of the metal seed layer by electroplating.

[0067] This embodiment does not limit the specific method of preparing the above-mentioned insulating layer 61. For example, the above-mentioned silicon oxide layer or the above-mentioned silicon nitride layer can be prepared by plasma enhanced chemical vapor deposition, and the polyimide layer can be directly prepared by spin coating. It should be further explained that in this embodiment, a silicon oxide layer is used as the above-mentioned insulating layer 61, which is suitable for use in a silicon adapter board 1 that is resistant to high temperatures of 400 degrees Celsius, and the above-mentioned insulating layer 61 is set to a silicon nitride layer, which can ensure the role of a passivation layer and prevent moisture penetration. When the above-mentioned insulating layer 61 is set to a polyimide layer, it is suitable for organic substrates or packaging structures that require stress buffering. In addition, in the present application, which is suitable for the copper metal leads or aluminum metal leads prepared subsequently, the metal seed layer can be set to a titanium-copper alloy seed layer or a titanium-aluminum alloy seed layer.

[0068] Furthermore, in order to ensure the electrical isolation effect of the first dielectric layer 20 and to prevent the first dielectric layer 20 from being damaged by subsequent high-temperature preparation processes, the first dielectric layer 20 may be a polyimide layer.

[0069] In this embodiment, the first dielectric layer 20 is set to a polyimide layer, which can have both high temperature resistance and mechanical flexibility, avoiding the problems of cracking and interface delamination due to thermal stress. Furthermore, in this embodiment, the polyimide layer can be set to a photosensitive polyimide layer, which can be directly patterned by photolithography to simplify the preparation process. In addition, in this embodiment, the polyimide dielectric layer set between adjacent first redistribution layers can be set to a total thickness of 15 microns, and the polyimide dielectric layer can be set to include multiple layers of sub-polyimide dielectric layers, and each layer of sub-polyimide dielectric layers is provided with conductive holes for realizing adjacent vertical conductive interconnections, and the conductive holes in each layer of sub-polyimide dielectric layers are staggered to reduce crosstalk. Specifically, the polyimide dielectric layer can be set to include 3 layers of sub-polyimide dielectric layers.

[0070] The chip 40 packaging structure based on the adapter board 1 provided by the embodiment of the present invention includes an adapter board 1, and the first surface of the adapter board 1 includes electrodes; each electrode is connected to the corresponding pad 70 located on the second surface side of the adapter board 1 through a conductive component 60 set in a through hole in the corresponding adapter board 1; the first surface of the adapter board 1 is provided with a first redistribution layer, and the first redistribution layer includes a multi-layer stacked connection wiring layer 10, and adjacent connection wiring layers 10 are isolated by a first dielectric layer 20; each connection wiring layer 10 includes a plurality of metal wirings; a guide hole is provided in the first dielectric layer 20, and a wire is provided in the guide hole, and the wire is used to connect the corresponding metal wirings in the adjacent connection wiring layers 10; each metal wiring is connected to the first dielectric layer 20 on the side facing away from the adapter board 1. At least one conductive hole is correspondingly provided in the electrical layer 20; in the direction away from the adapter board 1, the number of corresponding conductive holes provided in the first dielectric layer 20 outside the outermost connection wiring layer 10 is greater than the number of corresponding conductive holes provided in the first dielectric layer 20 outside the innermost connection wiring layer 10; each conductive hole of the outermost connection wiring layer 10 is connected to a pin 30, and each metal wiring in the innermost connection wiring layer 10 is connected to an electrode; the pins 30 are located on the adapter board 1, within the mapping range along the first surface in the direction away from the adapter board 1; the pins 30 connected to the outermost connection wiring layer 10 are arranged in an array, and the pins 30 arranged in an array are correspondingly connected to the chip 40, and the pins 30 and the chip 40 are encapsulated in a plastic package 50. By providing an adapter plate 1, the present invention can reduce the material used in the plastic package 50, eliminating the need to thin the plastic package 50, thereby improving production efficiency. In addition, by preparing a redistribution layer formed by stacking and arranging multiple layers of connection wiring layers 10 on the front side of the adapter plate 1, the layout density of the pins 30 in the chip packaging structure can be increased, thereby achieving high-density interconnection of the structure. Based on the above structure, the overall size of the chip package can be reduced, the complexity of the chip packaging structure preparation can be reduced, and the chip packaging structure can be made thinner and lighter.

[0071] In addition, the embodiment of the present invention provides a first redistribution layer including three stacked connection wiring layers 10, and the three stacked connection wiring layers 10 include a first connection wiring layer, a second connection wiring layer and a third connection wiring layer arranged in sequence along the back of the adapter board 1, and the extension direction of the metal wiring in the second connection wiring layer is perpendicular to the extension direction of the metal wiring in the third connection wiring layer, so that the spacing between adjacent pins 30 can be set to 10 microns to 100 microns, and the width of the pins 30 is set to 5 microns to 100 microns, thereby realizing high-density interconnection of devices and ensuring that the plastic packaging material can fully fill the gap between the pins 30 to avoid voids, ensure the mechanical strength of the pins 30, and improve the stability of the pins 30; a second redistribution layer formed by arranging a single-layer connection wiring layer 10 on the second surface of the adapter board 1, and using the second redistribution layer to connect the conductive components in the through-holes 60 is connected to the corresponding pad 70, so that the pad 70 can be flexibly arranged on the side of the second surface of the adapter board 1; by setting the insulating layer 61 on the inner wall of the through hole, the conductive component 60 on the inner wall of the through hole can be isolated from the substrate 2 material of the adapter board 1, avoiding the problem of current leakage or short circuit, and at the same time reducing the parasitic capacitance between the through hole and the adapter board 1, thereby improving the integrity of the high-frequency signal; by setting the insulating layer 61 as one of a silicon oxide layer, a silicon nitride layer, and a polyimide layer, a metal seed layer is formed on the surface of the insulating layer 61 in the through hole, and a copper metal lead or an aluminum metal lead is formed by electroplating on the surface of the metal seed layer, thereby ensuring that the insulating layer 61 in the through hole and the conductive component 60 are successfully prepared; by setting the first dielectric layer 20 as a polyimide layer, it can have both high temperature resistance and mechanical flexibility, avoiding the problem of cracking due to thermal stress and interface delamination.

[0072] An electronic device provided by an embodiment of the present invention is introduced below. The electronic device described below and the chip packaging structure based on the adapter board described above can refer to each other.

[0073] The electronic device provided by the embodiment of the present invention may include the above-mentioned chip packaging structure based on the adapter board.

[0074] The following is an introduction to a method for preparing a chip packaging structure based on an adapter board provided in an embodiment of the present invention. The method for preparing a chip packaging structure based on an adapter board described below is used to prepare a chip packaging structure based on an adapter board as described above, and can be referenced to each other with the chip packaging structure based on an adapter board described above.

[0075] Please refer to Figure 2 , Figure 2 A flowchart of a method for preparing a chip packaging structure based on an adapter board provided in an embodiment of the present invention may include:

[0076] S101: providing a substrate, sequentially and cyclically stacking a first dielectric layer and a connection wiring layer on a first surface of the substrate, and connecting a plurality of groups of pins in an array at the outermost connection wiring layer in a direction facing away from the substrate.

[0077] The execution subject of this embodiment is a chip packaging structure preparation device based on an adapter board. In this embodiment, a metal layer can be deposited on the first dielectric layer below, and then the deposited metal layer can be patterned to obtain a connection wiring layer, or a patterned mask layer can be prepared on the first dielectric layer below, and then a metal layer can be deposited, and then the mask layer can be removed to obtain a connection wiring layer. In this embodiment, upper and lower are directional words introduced for the convenience of description, where upper corresponds to the direction away from the adapter board, and lower corresponds to the direction toward the adapter board. In this embodiment, the specific preparation method of the first dielectric layer is not limited. For example, it can be prepared by any method including spin coating, spray coating, lamination, and chemical vapor deposition. In this embodiment, the substrate can be a silicon substrate, and a polyimide layer and a connection wiring layer can be arranged in a circular manner on the first surface of the silicon substrate to form a plurality of groups of RGB pins, and each group of RGB pins includes a red light pin, a green light pin, and a blue light pin. The structure prepared by the above step S101 can be referred to Figure 3 and Figure 4 , Figure 3 A schematic cross-sectional view of a chip packaging structure based on an adapter board without a through hole provided in an embodiment of the present invention; Figure 4 The schematic top view of a chip packaging structure based on an adapter board without a through hole provided in an embodiment of the present invention. Figure 4 The middle arrangement is provided with R pin, G pin, B pin, and S pin.

[0078] Furthermore, in order to ensure that the above step S101 is successfully completed, the above-mentioned sequentially cyclically stacking the first dielectric layer and the connection wiring layer on the first surface of the substrate may include:

[0079] Step S11: forming a first dielectric layer with a conductive hole on the first surface of the substrate to expose a portion of the electrode;

[0080] Step S12: preparing a connection wiring layer on the surface of the current first dielectric layer as a target connection wiring layer;

[0081] Step S13: forming a lead hole on the surface of the target connection wiring layer to expose a portion of the first dielectric layer of the target connection wiring layer as the current first dielectric layer;

[0082] Step S14: Prepare a connection wiring layer again on the surface of the current first dielectric layer as a new target connection wiring layer, and perform the step of preparing a first dielectric layer with a connecting hole formed on the surface of the target connection wiring layer to expose part of the target connection wiring layer until the preparation of the multi-layer connection wiring layer and the first dielectric layer is completed.

[0083] Specifically, in this embodiment, a first polyimide layer is first formed on a silicon substrate, followed by a first connection wiring layer formed on the polyimide layer. Next, a polyimide layer is formed on the first connection wiring layer, and a second connection wiring layer is formed on the polyimide layer. This process is repeated multiple times, ultimately forming a first redistribution layer formed by stacking multiple connection wiring layers. Each connection wiring layer is interconnected by metal wires, thereby achieving an array arrangement of multiple groups of RGB pins. The pin pitch of each group of RGB pins can be set to 10-100 microns, and the pin width can be set to 5-100 microns.

[0084] S102: A through hole is opened in the substrate, which passes through the first surface to the second surface, and a conductive component is prepared in the through hole to connect the electrode corresponding to the pin to the pad located on one side of the second surface of the substrate.

[0085] In this embodiment, the electrodes corresponding to the RGB pins can be wired to the back pads through TSV (Through-Silicon Via) technology on the back side of the silicon substrate, forming back pads corresponding to the RGB pins. Specifically, the TSV can be prepared on the back side of the silicon substrate by deep reactive ion etching process, with the diameter of the TSV set to 10-100 microns and the depth set to 50-500 microns. The structure prepared in step S102 can be referred to Figure 5 , Figure 5 A schematic cross-sectional view of an unconnected chip in a chip packaging structure based on an adapter board provided in an embodiment of the present invention.

[0086] In this embodiment, a polymer insulation layer is formed on the outermost connection wiring layer on one side of the first surface of the adapter board. Multiple exposed connection wiring layer areas are formed on this polymer insulation layer, serving as patch areas, each corresponding to a group of RGB pins. The polymer insulation layer can be made of a polyimide layer or an epoxy resin layer. The patch areas are 100-500 microns by 100-500 microns in size.

[0087] Furthermore, in order to ensure that the conductive component in the through hole in the substrate is successfully prepared, the above-mentioned preparation of the conductive component in the through hole to connect the electrode corresponding to the pin to the pad located on the second surface side of the substrate may include the following steps.

[0088] Step S21: preparing an insulating layer on the inner wall of the through hole, and preparing a metal seed layer on the surface of the insulating layer;

[0089] Step S22: preparing metal leads by electroplating on the surface of the metal seed layer.

[0090] In this embodiment, an insulating layer is formed on the inner wall of the through-silicon via. The insulating layer can be configured as a silicon oxide layer, a silicon nitride layer, or a polyimide layer. A metal seed layer is then formed on the insulating layer. The metal seed layer can be made of a titanium-copper alloy or a titanium-aluminum alloy. Finally, copper or aluminum is electroplated onto the metal seed layer to form a metal conductor. The metal conductor is electrically connected to the RGB pins on the front side, thereby connecting the electrodes of the RGB pins to the back side of the silicon substrate, and forming pads on the back side of the silicon substrate that correspond one-to-one to the RGB pins.

[0091] S103: Connect the pins to the chip accordingly, and perform plastic packaging on the pins and the chip to complete the preparation of the chip packaging structure based on the adapter board.

[0092] In this embodiment, a Micro-LED chip is mounted on the patch area. The conventional patch process can be used to align the pads of the Micro-LED chip with the pads of the RGB pins on the adapter board and then solidify the pads. The first surface of the adapter board with the Micro-LED chip mounted thereon is then plastic-sealed. The plastic-sealing material can be a thermosetting resin material such as epoxy resin. After the above step S103, the chip packaging structure based on the adapter board prepared in this embodiment is formed. Figure 6 and Figure 7 , Figure 6 A schematic cross-sectional view of a chip packaging structure based on an adapter board provided in an embodiment of the present invention, wherein the chip packaging structure is not plastic-sealed; Figure 7 The following is a schematic top view of a chip packaging structure based on an adapter board without plastic packaging provided by an embodiment of the present invention. Figure 7 It includes R chip, G chip, B chip, and S chip.

[0093] The method for preparing a chip packaging structure based on an adapter board provided by an embodiment of the present invention includes S101: providing a substrate, and preparing a first dielectric layer and a connection wiring layer by stacking them in sequence on the first surface of the substrate, and connecting multiple groups of pins in an array at the outermost connection wiring layer in a direction facing away from the substrate; adjacent connection wiring layers are isolated by a first dielectric layer, and the first dielectric layer is provided with a connection hole for connecting adjacent first redistribution layers; S102: opening a through hole in the substrate that passes through the first surface to the second surface, and preparing a conductive component in the through hole to connect the electrode corresponding to the pin to the pad located on the second surface side of the substrate; S103: connecting the pin to the chip, and plastic-sealing the pin and the chip to complete the preparation of the chip packaging structure based on the adapter board.

[0094] The present invention can reduce the material used for the plastic package by providing an adapter plate, eliminating the need to thin the plastic package, thereby improving production efficiency. Furthermore, by preparing a first redistribution layer formed by stacking and arranging multiple layers of connection wiring layers on the front of the adapter plate, the layout density of the pins in the chip packaging structure can be increased, achieving high-density interconnection of the structure. Based on the above structure, the overall size of the chip package can be reduced, the complexity of preparing the chip packaging structure can be reduced, and the thinness of the chip packaging structure can be achieved. In addition, the embodiment of the present invention prepares the multi-layer connection wiring layer in a cyclic preparation manner, ensuring that the above step S101 is successfully prepared and the preparation efficiency is improved; through the above step S21: preparing an insulating layer on the inner wall of the through hole and preparing a metal seed layer on the surface of the insulating layer; and step S22: preparing metal leads by electroplating on the surface of the metal seed layer, it can ensure that the conductive components in the through hole in the substrate are successfully prepared and the preparation complexity is reduced.

[0095] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0096] In addition, it should be noted that, in this document, relationships such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0097] The above is a detailed introduction to the chip packaging structure, electronic device and preparation method based on the adapter board provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A chip packaging structure based on an adapter board, characterized in that: comprising an adapter plate; the first surface of the adapter plate comprising electrodes; each of the electrodes being connected to a corresponding pad on one side of the second surface of the adapter plate via a corresponding conductive component disposed in a through hole in the adapter plate; A first redistribution layer is provided on the first surface of the adapter board, wherein the first redistribution layer includes multiple stacked connection wiring layers, and adjacent connection wiring layers are isolated by a first dielectric layer; each connection wiring layer includes multiple metal wirings; The first dielectric layer is provided with a connecting hole, and a wire is provided in the connecting hole, and the wire is used to connect the corresponding metal wiring in the adjacent connecting wiring layer; each metal wiring is correspondingly provided with at least one connecting hole in the first dielectric layer on the side facing away from the adapter board; In a direction facing away from the adapter board, the number of the corresponding guide holes provided in the first dielectric layer outside the outermost connection wiring layer is greater than the number of the corresponding guide holes provided in the first dielectric layer outside the innermost connection wiring layer; The outermost connection wiring layer is connected to a pin corresponding to each of the lead holes, and each of the metal wires in the innermost connection wiring layer is connected to one of the electrodes correspondingly; The pins are located on the adapter board, within a mapping range along the first surface facing away from the adapter board; The pins connected to the outermost connection wiring layer are arranged in an array, and the pins arranged in the array are correspondingly connected to the chip, and the pins and the chip are encapsulated in a plastic package.

2. The chip packaging structure based on the adapter board according to claim 1, characterized in that: The first redistribution layer includes three stacked connection wiring layers; the three stacked connection wiring layers include a first connection wiring layer, a second connection wiring layer, and a third connection wiring layer sequentially arranged along a direction facing away from the adapter board; An extending direction of the metal wiring in the second connection wiring layer is perpendicular to an extending direction of the metal wiring in the third connection wiring layer.

3. The chip packaging structure based on the adapter board according to claim 1, characterized in that: The second surface of the adapter board is provided with a second redistribution layer; the second redistribution layer is a redistribution layer formed by a single-layer connection wiring layer; A second dielectric layer is formed on the surface of the second redistribution layer, and an opening is formed in the second dielectric layer to expose the corresponding pad.

4. The chip packaging structure based on the adapter board according to claim 1, characterized in that: An insulating layer is formed on the inner wall of the through hole.

5. The chip packaging structure based on the adapter board according to claim 4, characterized in that: The insulating layer is one of a silicon oxide layer, a silicon nitride layer, and a polyimide layer; A metal seed layer is formed on the surface of the insulating layer in the through hole, and a copper metal lead or an aluminum metal lead is formed by electroplating on the surface of the metal seed layer.

6. The chip packaging structure based on the adapter board according to claim 1, characterized in that: The first dielectric layer is a polyimide layer.

7. An electronic device, characterized in that: The invention comprises a chip packaging structure based on an adapter board as claimed in any one of claims 1 to 6.

8. A method for preparing a chip packaging structure based on an adapter plate, characterized in that: A method for preparing a chip packaging structure based on an adapter plate according to any one of claims 1 to 6, comprising: Providing a substrate, sequentially and cyclically stacking a first dielectric layer and a connection wiring layer on a first surface of the substrate, and connecting a plurality of groups of pins in an array at the outermost connection wiring layer in a direction facing away from the substrate; A through hole is formed in the substrate, passing through the first surface to the second surface, and a conductive component is formed in the through hole to connect the electrode corresponding to the pin to the pad located on one side of the second surface of the substrate; The pins are connected to the chip respectively, and the pins and the chip are plastic-sealed to complete the preparation of the chip packaging structure based on the adapter board.

9. The method for preparing a chip packaging structure based on an adapter plate according to claim 8, wherein: The step of preparing a conductive component in the through hole to connect the electrode corresponding to the pin to the pad located on one side of the second surface of the substrate includes: preparing an insulating layer on the inner wall of the through hole, and preparing a metal seed layer on the surface of the insulating layer; Metal leads are prepared by electroplating on the surface of the metal seed layer.

10. The method for preparing a chip packaging structure based on an adapter plate according to claim 8, wherein: The method of sequentially and cyclically stacking a first dielectric layer and a connection wiring layer on the first surface of the substrate comprises: A first dielectric layer is formed with a connecting hole on the first surface of the substrate to expose a portion of the electrode; preparing a connection wiring layer on the surface of the first dielectric layer as a target connection wiring layer; The lead hole is formed on the surface of the target connection wiring layer to expose a portion of the first dielectric layer of the target connection wiring layer as the current first dielectric layer; A connection wiring layer is prepared again on the surface of the current first dielectric layer as a new target connection wiring layer, and the step of preparing the first dielectric layer with the connection holes formed on the surface of the target connection wiring layer to expose a portion of the target connection wiring layer is performed until the preparation of multiple layers of the connection wiring layer and the first dielectric layer is completed.

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