Test structure and test method for semiconductor devices

Abstract

Embodiments of the present application disclose a test structure and a test method for a semiconductor device, the semiconductor device comprising a substrate, a plurality of gates and a plurality of contact structures, the test structure comprising a plurality of first conductive structures, the substrate comprising a plurality of first active regions arranged at intervals; the plurality of gates are arranged above the substrate, and a projection of each gate on a surface of the substrate overlaps a corresponding first active region; the plurality of contact structures are respectively connected to the corresponding first active regions through vias, and the plurality of contact structures comprise a plurality of first contact structures located between two adjacent gates; the plurality of first contact structures are electrically connected between a first measurement structure and a second measurement structure through the plurality of first conductive structures and the corresponding first active regions, so that an electrical resistance value between the first measurement structure and the second measurement structure represents an electrical detection result of the plurality of first contact structures. The embodiments of the present application improve the test accuracy of process defects of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, and in particular to a test structure and a test method for a semiconductor device. BACKGROUND

[0002] In a complementary metal oxide semiconductor (CMOS) manufacturing process, a non-volatile memory unit (eNVM) is usually integrated. This integration can efficiently store information while effectively reducing the area and cost of a circuit board module. In the layout design of the eNVM, a high-density memory array region usually occupies a large proportion. In order to improve the speed, power consumption and area efficiency of the memory, the periodic cell structure is arranged as densely as possible and is compressed to the minimum size under the premise of meeting the process and performance requirements. In different types of eNVM arrays, there are often densely arranged long strip-shaped gates and highly densely distributed contact structures. When the pattern spacing in the layout design is too small, the pattern density is too high, or the pattern length is too long, it may exceed the allowable range of the process manufacturing, thereby exceeding the limitation of the process window and increasing the risk in the manufacturing process. This can easily lead to defects such as short circuit, open circuit or transistor performance degradation in the process manufacturing. If a single or a small number of memory cells fail due to these defects, it can cause functional abnormalities of the entire chip, thereby causing the chip yield to decrease. Therefore, a test structure such as an Rc chain is usually used to test the electrical detection results of the contact structure of the semiconductor device to monitor the process defects. However, the conventional test structure often fails to fully consider the special structural characteristics of the semiconductor device. SUMMARY

[0003] In view of the above problems, the purpose of the present application is to provide a test structure and a test method for a semiconductor device, which improves the test accuracy of process defects of the semiconductor device by designing a test structure for a first contact structure at a gap position between two adjacent gates arranged densely in the semiconductor device, thereby improving the performance and yield of the semiconductor device.

[0004] According to a first aspect of an embodiment of the present application, a test structure for a semiconductor device is provided, the semiconductor device comprising a substrate, a plurality of gates and a plurality of contact structures, the test structure comprising a plurality of first conductive structures, wherein,

[0005] The substrate comprises a plurality of first active regions arranged at intervals.

[0006] The plurality of gates are disposed over the substrate, and a projection of each of the gates on the substrate surface overlaps with a corresponding first active region;

[0007] The plurality of contact structures are respectively connected to corresponding first active regions through vias, and the plurality of contact structures include a plurality of first contact structures located between two adjacent gates.

[0008] The plurality of first contact structures are electrically connected between a first measurement structure and a second measurement structure through the plurality of first conductive structures and corresponding first active regions, so that an electrical resistance value between the first measurement structure and the second measurement structure represents an electrical detection result of the plurality of first contact structures.

[0009] Optionally, the first contact structure is located on both sides of the first active region, a first end of the first contact structure is connected to the corresponding first conductive structure, and a second end of the first contact structure is connected to the corresponding first active region.

[0010] Optionally, the plurality of first contact structures include 1st to nth first contact structures, the 1st to nth first contact structures are arranged in sequence along a direction parallel to the two adjacent gates, a first one of the first contact structures is connected to the first measurement structure, an i-th one of the first contact structures is connected to an (i+1)-th one of the first contact structures through a corresponding first conductive structure, a j-th one of the first contact structures is connected to a (j+1)-th one of the first contact structures through a corresponding first active region, an n-th one of the first conductive structures is connected to the second measurement structure, n is a positive integer greater than 1, i is an even number greater than or equal to 2, and j is an odd number greater than or equal to 1.

[0011] Optionally, a spacing between the two adjacent gates is greater than a first preset threshold and less than a second preset threshold, the first preset threshold is greater than or equal to a size of the first contact structure, and the second preset threshold is less than or equal to a size of two first contact structures.

[0012] Optionally, a length of the two adjacent gates along a first direction is greater than a third preset threshold, and a first end of each of the two adjacent gates is electrically connected to a third measurement structure.

[0013] Optionally, a width of the first conductive structure along a second direction is greater than the spacing between the two adjacent gates.

[0014] Optionally, the substrate further comprises a second active region, the second active region is spaced apart from the plurality of first active regions, a well region is disposed in the substrate within the second active region, a plurality of second contact structures are disposed on the well region, first ends of the plurality of second contact structures are respectively connected to the well region through a via hole;

[0015] The test structure further comprises:

[0016] a second conductive structure, second ends of the plurality of second contact structures are respectively connected to the second conductive structure, the well region is electrically connected to a fourth measurement structure through the second conductive structure and the plurality of second contact structures.

[0017] Optionally, the first measurement structure is configured to provide a first test voltage, the second measurement structure is configured to provide a second test voltage, the third measurement structure is configured to provide a gate voltage for the adjacent two gates to close the channel current of the device, and the fourth measurement structure is configured to provide a reverse bias voltage for the well region to reduce the leakage current of the device.

[0018] Optionally, the resistance value between the first measurement structure and the second measurement structure is calculated according to a voltage difference between the first test voltage and the second test voltage and a current value flowing through the first measurement structure and the second measurement structure.

[0019] According to a second aspect of the embodiments of the present application, a test method for a semiconductor device is provided, which is used for the test structure as described above, comprising:

[0020] providing a gate voltage for the adjacent two gates through a third measurement structure to close the channel current of the device;

[0021] providing a reverse bias voltage for a well region in the substrate through a fourth measurement structure to reduce the leakage current of the device;

[0022] providing a first test voltage for a plurality of first contact structures located between the adjacent two gates through a first measurement structure, and providing a second test voltage for the plurality of first contact structures located between the adjacent two gates through a second measurement structure;

[0023] testing a current value flowing through the first measurement structure and the second measurement structure;

[0024] calculating a resistance value between the first measurement structure and the second measurement structure according to a voltage difference between the first test voltage and the second test voltage and the current value, the resistance value representing an electrical property detection result of the plurality of first contact structures.

[0025] The unexpected technical effects of the present application are:

[0026] In a semiconductor device, a substrate includes a plurality of first active regions arranged at intervals, a plurality of gates is arranged above the substrate, and a projection of each gate on a surface of the substrate overlaps a corresponding first active region. A first contact structure at a gap position between two adjacent gates arranged in a dense arrangement is extremely sensitive to process defects. The plurality of first contact structures are electrically connected between a first measurement structure and a second measurement structure through a plurality of first conductive structures and the corresponding first active regions, so that an electrical resistance value between the first measurement structure and the second measurement structure represents an electrical detection result of the plurality of first contact structures. By measuring the electrical resistance value between the first measurement structure and the second measurement structure, the electrical detection result of the first contact structure at the gap position between the two adjacent gates arranged in the dense arrangement can be accurately measured, so that the process defects of the first contact structure at the gap position between the two adjacent gates arranged in the dense arrangement in the semiconductor device can be effectively monitored and evaluated, and problems such as abnormal film layer accumulation morphology, etching residue or poor contact are solved, the test accuracy of the process defects of the semiconductor device is improved, and then the performance and yield of the semiconductor device are improved.

[0027] In addition, in the embodiments of the present application, the third measurement structure is used to provide a gate voltage for the two adjacent gates to turn off the channel current of the device, the fourth measurement structure is used to provide a reverse bias voltage for the well region in the substrate to reduce the leakage current of the device, the first measurement structure is used to provide a first test voltage, the second measurement structure is used to provide a second test voltage, the current value flowing through the first measurement structure and the second measurement structure is tested, the electrical resistance value between the first measurement structure and the second measurement structure representing the electrical detection result of the plurality of first contact structures is calculated according to the voltage difference and the current value of the first test voltage and the second test voltage, the precise voltage and current control is used to reduce the interference of the channel current and the leakage current on the electrical detection result in the test process, and thus the test accuracy and reliability of the process defects of the semiconductor device are improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings, in which:

[0029] Figure 1 Fig. 1 shows a layout schematic diagram of a semiconductor device in the related art;

[0030] Figure 2A Fig. 2 shows a layout schematic diagram of a test structure for a semiconductor device in the related art;

[0031] Figure 2B Fig. 3 shows a cross-sectional view of a film layer along line A-A in Fig. 1; Figure 2A

[0032] Figure 3A ​Fig. 1 shows a layout diagram of a test structure for a semiconductor device according to the prior art;

[0033] Figure 3B Fig. 2 shows a cross-sectional view of the test structure along line B-B in Fig. 1; Figure 3A

[0034] Figure 4A Fig. 3 shows a layout diagram of a test structure for a semiconductor device according to an embodiment of the present application;

[0035] Figure 4B Fig. 4 shows a cross-sectional view of the test structure along line C-C in Fig. 3; Figure 4A

[0036] Figure 4C Fig. 5 shows a cross-sectional view of the test structure along line D-D in Fig. 4; Figure 4A

[0037] Fig. 6 shows a flow diagram of a test method for a semiconductor device according to an embodiment of the present application. Figure 5

[0038] Fig. 10 shows a layout diagram of a semiconductor device according to the prior art. DETAILED DESCRIPTION

[0039] The present application will be described in more detail with reference to the drawings, in which:

[0040] The present application can take various forms, some of which will now be described with reference to the drawings.

[0041] It should be noted that, for the sake of simplicity, some layers are omitted in the drawings of the present application. The distances and line widths in the drawings are used to show the relative positions of the components and between the components, and the actual distances and line widths are subject to the process rules.

[0042] Figure 1 Fig. 10 shows a layout diagram of a semiconductor device according to the prior art. Figure 1 ​​​As shown, the semiconductor device (e.g., embedded non-volatile memory) includes a substrate, a plurality of gates 20 and a plurality of contact structures 30. The substrate serves as a reference plane and mechanical support, and includes a plurality of spaced-apart active regions 10, which are separated by shallow trench isolation (STI) regions. The active region 10 refers to an area on the semiconductor substrate for forming a transistor (e.g., NMOS device, PMOS device) or other active device, which is usually subjected to a doping process to form a well region, a source region, a drain region and a channel region. The STI is an isolation technique for isolating different active regions, which is achieved by etching a shallow trench in the substrate and filling the trench with an insulating material (e.g., silicon dioxide) to electrically isolate different active regions. The plurality of gates 20 are disposed on the substrate, and each gate 20 has a projection on the substrate surface that overlaps a corresponding active region 10. The gate 20 can be made of polysilicon (Poly) or metal, and controls the formation of a channel by applying a gate voltage to the gate 20 to control the flow of carriers between the source region and the drain region. The active region 10 is provided with an array of contact structures 30, and the gate 20 is also provided with a contact structure 30. The contact structure 30 is a channel for connecting the front transistor and the back metal wiring, which not only connects the gate, but also connects to the source region and the drain region. The etching quality of the contact structure 30 directly affects the characteristics of the semiconductor device and the yield of the product. The spacing between the gates 20 is related to the type and number of cell devices in the active region 10. For example, Figure 1 As shown, in some cases, the gate 20 is a densely arranged long strip-shaped gate, which can be understood as follows: the spacing between the gates 20 along the Y-axis direction is less than a predetermined threshold value, so that only one contact structure 30 can be arranged between the gates 20, and the length of the gate 20 along the X-axis direction is greater than a predetermined threshold value. In the densely arranged long strip-shaped gate, especially when the spacing between the gates 20 is very small and the contact structures 30 are distributed at a high density, the contact structure located at the gap position between the adjacent gates 20 is extremely sensitive to process defects. For example, abnormal film layer accumulation topography or etching residue problems between the gates 20 can cause poor formation of silicon metal compounds and poor bottom topography of the via. These problems not only increase the resistance of the contact structure, but also further affect the performance of the semiconductor device, resulting in a decrease in the yield of the semiconductor device. Therefore, effective electrical detection of the contact structure at these key structure positions is an important means to improve the reliability and yield of the semiconductor device.

[0043] Figure 2A As shown, a layout diagram of a test structure for a semiconductor device in the related art, Figure 2B As shown, Figure 2A is a cross-sectional view of the film layer along the A-A line. As shown, Figure 2A andFigure 2B As shown in FIG. 1, a semiconductor device in the prior art includes a plurality of active regions 10 arranged at intervals, and the active regions 10 are isolated by shallow trench isolation regions 110. Contact structures 30 are arranged at both ends of the active regions 10. The test structure includes a conductive structure 40, and the plurality of active regions 10 and the conductive structure 40 are connected in series by the contact structures 30 to form a contact resistance chain (Rc chain). The contact structure 30 of the active region 10 at the head end and the contact structure 30 of the active region 10 at the tail end are both connected to a measurement structure. By applying a test voltage to the measurement structure, the current flowing through the connected path of the contact resistance chain is measured, and the resistance value representing the electrical property detection result of the contact structure 30 is calculated according to Ohm's law. The resistance value directly reflects the process defect condition of the contact structure 30 on the active region 10 in a large area.

[0044] Figure 3A As shown in FIG. 2, another test structure of a semiconductor device in the prior art is shown in a layout diagram, Figure 3B As shown in FIG. 3, Figure 3A A cross-sectional view of the structure along the line B-B is shown in FIG. 4. As shown in FIG. 4, Figure 3A and Figure 3B As shown in FIG. 5, a semiconductor device in the prior art includes a plurality of gates 20 arranged at intervals on an active region 10, and contact structures 30 are arranged at both ends of the gates 20. The test structure includes a conductive structure 40, and the plurality of gates 20 and the conductive structure 40 are connected in series by the contact structures 30 to form a contact resistance chain (Rc chain). The contact structure 30 of the gate 20 at the head end and the contact structure 30 of the gate 20 at the tail end are both connected to a measurement structure. By applying a test voltage to the measurement structure, the current flowing through the connected path of the contact resistance chain is measured, and the resistance value representing the electrical property detection result of the contact structure 30 is calculated according to Ohm's law. The resistance value directly reflects the process defect condition of the contact structure 30 on the gate 20.

[0045] It can be understood that the test structure in the prior art mainly focuses on the contact structure 30 on the active region 10 in a large area or the contact structure 30 on the gate 20, and cannot effectively monitor the contact structure at the gap position between the closely arranged gates 20 in the semiconductor device. Therefore, when the test structure in the prior art is applied to a high-density storage array, the process defects of the contact structure at the key structure position of the semiconductor device cannot be effectively monitored, which affects the performance and yield of the semiconductor device.

[0046] Therefore, embodiments of the present application provide a new test structure and test method for a semiconductor device, which accurately test the process defects of the semiconductor device and improve the performance and yield of the semiconductor device by designing a test structure for a first contact structure at a gap position between two adjacent gates arranged closely in the semiconductor device.

[0047] Figure 4A Fig. 4A shows a layout view of an exemplary test structure for a semiconductor device according to embodiments of the present application, Figure 4B Fig. 4B shows a cross-sectional view along the line C-C of Fig. 4A, Figure 4A Fig. 4C shows a cross-sectional view along the line D-D of Fig. 4A. As shown in Fig. 4C, Figure 4A Fig. 4D shows a cross-sectional view along the line E-E of Fig. 4A. As shown in Fig. 4D, Figures 4A to 4C The semiconductor device according to embodiments of the present application includes a substrate, a plurality of gates 20, a plurality of contact structures 30, and a plurality of second contact structures 320. The plurality of contact structures 30 includes a plurality of first contact structures 310. The test structure includes a plurality of first conductive structures 410 and a plurality of second conductive structures 420. The substrate serves as a reference surface and mechanical support, and includes a plurality of first active regions 120 arranged in an array. The first active regions 120 are separated by shallow trench isolation regions 110. It is to be noted that, Figure 4A Only three first active regions 120 are shown. The semiconductor device can include other number of first active regions 120, which is not limited by embodiments of the present application. The plurality of first active regions 120 can be arranged in an array, for example, in 2 rows and 3 columns.

[0048] In some embodiments, the substrate further comprises a second active region 130, which is spaced apart from the plurality of first active regions 120. A well region is disposed in the substrate within the second active region 130. The well region can be formed in the substrate within the second active region 130 by ion implantation or other processes. In high-density memory arrays, it is often desirable to integrate NMOS devices and PMOS devices on the same substrate to implement CMOS logic circuits. To integrate NMOS devices and PMOS devices on the same P-type substrate, an N-type well region (N-well) is formed in the P-type substrate to fabricate PMOS devices, while NMOS devices are fabricated directly in the P-type substrate. To integrate NMOS devices and PMOS devices on the same N-type substrate, a P-type well region (P-well) is formed in the N-type substrate to fabricate NMOS devices, while PMOS devices are fabricated directly in the N-type substrate. In some embodiments, for fabricating NMOS devices, high-concentration N-type doped source and drain regions can be formed in the P-type substrate or P-type well region by ion implantation or other processes. For fabricating PMOS devices, high-concentration P-type doped source and drain regions can be formed in the N-type substrate or N-type well region by ion implantation or other processes. In some embodiments, a plurality of second contact structures 320 is disposed on the well region disposed in the substrate within the second active region 130. First ends of the plurality of second contact structures 320 are respectively connected to the well region through vias. Second ends of the plurality of second contact structures 320 are respectively connected to second conductive structures 420 through vias. The well region is electrically connected to the fourth measurement structure through the second conductive structures 420 and the plurality of second contact structures 320.

[0049] In some embodiments, a plurality of gates 20 is disposed on the substrate, and a projection of each gate 20 on the surface of the substrate overlaps with a corresponding first active region 120. The gate 20 can be made of polysilicon (Poly) or metal, and is disposed between the source region and the drain region, covering a gate oxide layer. The formation of a channel between the source region and the drain region is controlled by applying a gate voltage to the gate 20. When the gate voltage reaches a certain threshold value, a conductive channel is induced on the surface of the substrate, allowing current to flow from the source region to the drain region (or from the drain region to the source region). In some embodiments, a plurality of contact structures 30 is disposed on the first active region 120 in an array arrangement. It should be noted that, Figure 4AOnly one example of the arrangement of the contact structures 30 in the first active region 120 is shown, and other numbers and arrangements of the contact structures 30 in the first active region 120 can be included in the semiconductor device, which are not limited in the embodiments. The contact structure 30 is a channel connecting the front transistor and the back metal wiring, which is connected to the gate, the source region and the drain region, and the etching quality directly affects the characteristics of the semiconductor device and the yield of the product. The spacing between the adjacent gates 20 refers to the distance between the adjacent two gates 20 along the Y-axis direction, which directly affects the size and density of the transistor. Smaller gate spacing means that more transistors can be accommodated in the same chip area, thereby improving the density of the cell device. In some embodiments, the contact structure 30 includes a plurality of first contact structures 310 located between the adjacent two gates 20. The spacing between the adjacent two gates 20 is greater than a first preset threshold and less than a second preset threshold, the first preset threshold is greater than or equal to the size of the first contact structure 310, and the second preset threshold is less than or equal to the size of the two first contact structures 310. In some embodiments, the length of the adjacent two gates 20 along the X-axis direction is greater than a third preset threshold, and the first ends of the adjacent two gates 20 are connected to the third measurement structure 3. In some embodiments, the width of the first conductive structure 410 along the Y-axis direction is greater than the spacing between the adjacent two gates 20.

[0050] In some embodiments, the plurality of first contact structures 310 are electrically connected between the first measurement structure 1 and the second measurement structure 2 through the plurality of first conductive structures 410 and the corresponding first active region 120, so that the resistance value between the first measurement structure 1 and the second measurement structure 2 represents the electrical detection result of the plurality of first contact structures 310. In some embodiments, the first contact structure 310 is located on both sides of the first active region 120, the first end of the first contact structure 310 is connected to the corresponding first conductive structure 410, and the second end of the first contact structure 310 is connected to the corresponding first active region 120. In some embodiments, the plurality of first contact structures 310 include the 1st to nth first contact structures 310, which are arranged in sequence along a direction parallel to the adjacent two gates 20, the first first contact structure 310 is connected to the first measurement structure 1, the ith first contact structure 310 is connected to the i+1th first contact structure 310 through the corresponding first conductive structure 410, the jth first contact structure 310 is connected to the j+1th first contact structure 310 through the corresponding first active region 120, the nth first conductive structure 410 is connected to the second measurement structure 2, n is a positive integer greater than 1, i is an even number greater than or equal to 2, and j is an odd number greater than or equal to 1.

[0051] In some embodiments, the first measurement structure 1 is used to provide a first test voltage, and the second measurement structure 2 is used to provide a second test voltage. The third measurement structure 3 is used to provide a gate voltage for the two adjacent gates 20 to turn off the channel current of the device. The fourth measurement structure is used to provide a reverse bias voltage for the well region to reduce the leakage current of the device. In some embodiments, in the case that the well region is a P-type well region of an NMOS device, the reverse bias voltage is a ground voltage GND. In the case that the well region is an N-type well region of a PMOS device, the reverse bias voltage is a supply voltage VDD. The gate voltage is a ground voltage GND. In some embodiments, by testing the current values flowing through the first measurement structure 1 and the second measurement structure 2, and according to the voltage difference between the first test voltage and the second test voltage and the measured current values, the resistance value between the first measurement structure 1 and the second measurement structure 2, which represents the electrical detection result of the plurality of first contact structures 310, can be calculated according to Ohm's law. The resistance value can directly reflect the process defect condition of the first contact structure 310 at the gap position between the two adjacent gates 20. When the resistance value is greater than a certain threshold value, it can be determined that the first contact structure 310 at the position has defects, such as abnormal film layer accumulation morphology, etching residue, or poor contact, etc. This testing method can accurately measure the electrical detection result of the first contact structure at the gap position between the two adjacent gates arranged densely, thereby effectively monitoring and evaluating the process defects of the first contact structure at the gap position between the two adjacent gates arranged densely in the semiconductor device, solving the problems of abnormal film layer accumulation morphology, etching residue, or poor contact, etc., and improving the testing accuracy of the process defects of the semiconductor device, and further improving the performance and yield of the semiconductor device.

[0052] Figure 5 Fig. 1 shows a flowchart of an exemplary testing method for a semiconductor device according to an embodiment of the present application. The testing method of the present embodiment is used for a testing structure as shown in Fig. 2. Figures 4A to 4C Fig. 2 shows a testing structure according to an embodiment of the present application. As shown in Fig. 2, the testing structure includes a substrate 10, a plurality of first contact structures 310, a plurality of second contact structures 320, a plurality of gates 20, a plurality of third measurement structures 3, a plurality of fourth measurement structures 4, a plurality of first measurement structures 1, and a plurality of second measurement structures 2. Figure 5 Fig. 3 shows a testing method according to an embodiment of the present application. As shown in Fig. 3, the testing method of the present embodiment includes the following steps.

[0053] In step S510, a gate voltage is provided for the two adjacent gates by the third measurement structure to turn off the channel current of the device.

[0054] In step S520, a reverse bias voltage is provided for the well region in the substrate by the fourth measurement structure to reduce the leakage current of the device.

[0055] In step S530, a first test voltage is provided for the plurality of first contact structures located between the two adjacent gates by the first measurement structure, and a second test voltage is provided for the plurality of first contact structures located between the two adjacent gates by the second measurement structure.

[0056] In step S540, a current value flowing through the first measurement structure and the second measurement structure is tested.

[0057] In step S550, according to the voltage difference between the first test voltage and the second test voltage and the current value, a resistance value between the first measurement structure and the second measurement structure is calculated, which represents the electrical detection result of the plurality of first contact structures.

[0058] Since the process of testing the process defects of the contact structures located in the gap position between the densely arranged long strip-shaped gates using the test method of the embodiments of the present application has been described above, it will not be repeated here.

[0059] Finally, it should be noted that the terms "first", "second" and "third" are used only for descriptive purposes and should not be construed as indicating or implying relative importance. In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details and do not limit the present application to only the specific embodiments described. Obviously, many modifications and variations can be made in light of the above description. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A test structure for a semiconductor device, the semiconductor device comprising a substrate, a plurality of gates, and a plurality of contact structures, the test structure comprising a plurality of first conductive structures, wherein: The substrate includes a plurality of first active regions spaced apart from each other; The plurality of gates are disposed on the substrate, and a projection of each gate on the surface of the substrate overlaps with the corresponding first active region; The plurality of contact structures are respectively connected to the corresponding first active regions via through holes, and the plurality of contact structures include a plurality of first contact structures located between two adjacent gates; The multiple first contact structures are electrically connected between the first measurement structure and the second measurement structure through the multiple first conductive structures and the corresponding first active areas, so that the resistance value between the first measurement structure and the second measurement structure represents the electrical detection results of the multiple first contact structures.

2. The test structure according to claim 1, wherein: The first contact structure is located on both sides of the first active region, a first end of the first contact structure is connected to the corresponding first conductive structure, and a second end of the first contact structure is connected to the corresponding first active region.

3. The test structure according to claim 2, wherein: The multiple first contact structures include the 1st to nth first contact structures, and the 1st to nth first contact structures are arranged in sequence along a direction parallel to the extension of the two adjacent gates. The first first contact structure is connected to the first measurement structure, the i-th first contact structure is connected to the i+1-th first contact structure through the corresponding first conductive structure, the j-th first contact structure is connected to the j+1-th first contact structure through the corresponding first active area, and the n-th first conductive structure is connected to the second measurement structure, where n is a positive integer greater than 1, i is an even number greater than or equal to 2, and j is an odd number greater than or equal to 1.

4. The test structure according to claim 1, wherein: The distance between the two adjacent gates is greater than a first preset threshold and less than a second preset threshold, the first preset threshold is greater than or equal to the size of the first contact structure, and the second preset threshold is less than or equal to the size of the two first contact structures.

5. The test structure according to claim 1, wherein: The length of the two adjacent gates along the first direction is greater than a third preset threshold, and the first ends of the two adjacent gates are both electrically connected to the third measurement structure. The test structure according to claim 1 , wherein: The width of the first conductive structure along the second direction is greater than the distance between the two adjacent gates.

7. The test structure according to claim 5, wherein: The substrate further includes a second active region, the second active region being spaced apart from the plurality of first active regions, a well region being provided in the substrate within the second active region, a plurality of second contact structures being provided on the well region, and first ends of the plurality of second contact structures being connected to the well region via through holes, respectively; The test structure also includes: The second conductive structure, the second ends of the plurality of second contact structures are respectively connected to the second conductive structure through through holes, and the well region is electrically connected to the fourth measurement structure through the second conductive structure and the plurality of second contact structures.

8. The test structure according to claim 7, wherein: The first measurement structure is used to provide a first test voltage, the second measurement structure is used to provide a second test voltage, the third measurement structure is used to provide a gate voltage for the two adjacent gates to shut down the channel current of the device, and the fourth measurement structure is used to provide a reverse bias voltage for the well region to reduce the leakage current of the device.

9. The test structure according to claim 8, wherein: The resistance value between the first measuring structure and the second measuring structure is calculated according to the voltage difference between the first test voltage and the second test voltage and the current value flowing through the first measuring structure and the second measuring structure.

10. A method for testing a semiconductor device, used in the test structure according to claim 9, comprising: providing a gate voltage to two adjacent gates through a third measurement structure to shut down a channel current of the device; providing a reverse bias voltage to the well region in the substrate through the fourth measurement structure to reduce leakage current of the device; providing a first test voltage to the plurality of first contact structures located between the two adjacent gates through a first measurement structure, and providing a second test voltage to the plurality of first contact structures located between the two adjacent gates through a second measurement structure; Testing current values ​​flowing through the first measurement structure and the second measurement structure; A resistance value between the first measurement structure and the second measurement structure, which represents an electrical property detection result of the plurality of first contact structures, is calculated based on a voltage difference between the first test voltage and the second test voltage and the current value.

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