Threshold voltage detection circuit and detection device

Abstract

The application provides a threshold voltage detection circuit and a detection device, and relates to the technical field of semiconductor testing. The threshold voltage detection circuit comprises a first pulse output circuit, a second pulse output circuit, a first switch circuit, a second switch circuit, a third switch circuit and a detection circuit. The first pulse output circuit is used for receiving a first positive voltage and a first negative voltage. The second pulse output circuit is used for receiving a second positive voltage and a second negative voltage. The first end of the first switch circuit is connected with the output end of the first pulse output circuit and the output end of the second pulse output circuit respectively. The second end of the first switch circuit is connected with the first end of the second switch circuit and the first end of the third switch circuit respectively. The second end of the second switch circuit is connected with the first end of the detection circuit. The second end of the third switch circuit is connected with the second end of the detection circuit. The application can realize accurate detection of the threshold voltage of a semiconductor device to be detected.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, and in particular to a threshold voltage detection circuit and a detection device. BACKGROUND

[0002] Wide bandgap semiconductor (for example, silicon carbide (SiC) and gallium nitride (GaN)) power devices achieve higher energy efficiency and power density in high temperature, high frequency and high voltage scenarios, are the core of the third generation semiconductor technology, are widely used in new energy vehicle main drive inverters, vehicle chargers and direct current converters and other key electric drive electric control components, and help to realize light weight and high efficiency of new energy vehicle electric drive electric control components.

[0003] However, as the use time increases, the wide bandgap semiconductor power device may have reliability problems such as threshold voltage drift, leakage current increase, and bipolar degradation. Dynamic gate bias stress (DGB) can simulate the degradation trend of the wide bandgap semiconductor power device in 20 years of life cycle within 1000 hours by applying stress much higher than the actual working condition. At present, in the dynamic gate bias stress of the wide bandgap semiconductor power device, the detection of the threshold voltage during the dynamic gate bias stress is not accurate enough. SUMMARY

[0004] Embodiments of the present application provide a threshold voltage detection circuit and a detection device for improving the detection accuracy of the threshold voltage during the dynamic gate bias stress.

[0005] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a threshold voltage detection circuit is provided. The threshold voltage detection circuit includes a first pulse output circuit, a second pulse output circuit, a first switch circuit, a second switch circuit, a third switch circuit, and a detection circuit. The first input terminal of the first pulse output circuit is used to receive a first positive voltage, and the second input terminal of the first pulse output circuit is used to receive a first negative voltage; the first input terminal of the second pulse output circuit is used to receive a second positive voltage, and the second input terminal of the second pulse output circuit is used to receive a second negative voltage. The first terminal of the first switch circuit is connected to the output terminal of the first pulse output circuit and the output terminal of the second pulse output circuit, respectively; the second terminal of the first switch circuit is connected to the first terminal of the second switch circuit and the first terminal of the third switch circuit, respectively. The second terminal of the second switch circuit is connected to the first terminal of the detection circuit, and the second terminal of the third switch circuit is connected to the second terminal of the detection circuit. The first terminal of the first switch is used to connect to the control terminal of the semiconductor device under test, the second terminal of the first switch circuit is used to connect to the first controlled terminal of the semiconductor device under test, and the second terminal of the third switch circuit is used to connect to the second controlled terminal of the semiconductor device under test.

[0007] In the embodiments of the present application, the first pulse output circuit can apply dynamic gate bias stress to the semiconductor device under test, and the second pulse output circuit can apply a second positive voltage (positive prestress) or a second negative voltage (negative prestress) to the semiconductor device under test. The timing of the dynamic gate bias stress test and the threshold voltage detection is controlled by turning the first, second, and third switching circuits on or off, as well as the operating states of the first and second pulse output circuits, thereby enabling the detection circuit to accurately detect the threshold voltage of the semiconductor device under test.

[0008] In some possible implementations, a control circuit is further included, and the control circuit is connected to the first pulse output circuit, the second pulse output circuit, the first switch circuit, the second switch circuit, and the third switch circuit, respectively. The control circuit is configured to: during the dynamic stress application phase, control the first pulse output circuit to output a square wave pulse, wherein the first level of the square wave pulse is a first positive voltage, and the second level of the square wave pulse is a first negative voltage. During the preprocessing phase of the first detection phase, the second pulse output circuit is controlled to output a second positive voltage. During the preprocessing phase of the second detection phase, the second pulse output circuit is controlled to output a second negative voltage. The dynamic stress application phase is before the first detection phase and the second detection phase.

[0009] The embodiment of the present application can measure the threshold voltage after positive prestress (i.e., the second positive voltage) and the threshold voltage after negative prestress (i.e., the second negative voltage) in one test cycle of the semiconductor device to be tested, thereby evaluating the threshold voltage hysteresis effect of the semiconductor device to be tested.

[0010] In some possible implementation manners, the control circuit is configured to control the third switch circuit to be turned on and the first switch circuit to be turned off in the dynamic stress application stage.

[0011] In some possible implementation manners, the control circuit is configured to control the first switch circuit to be turned on and the third switch circuit to be turned off in the pre-processing stage of the first detection stage, and control the first switch circuit to be turned on and the third switch circuit to be turned off in the pre-processing stage of the second detection stage.

[0012] In some possible implementation manners, the control circuit is configured to control the first switch circuit to be turned on, the second switch circuit to be turned on and the third switch circuit to be turned off in the threshold voltage detection stage of the first detection stage, and detect the first threshold voltage of the semiconductor device to be tested by controlling the detection circuit to output a pulse current. The threshold voltage detection stage is after the pre-processing stage.

[0013] In some possible implementation manners, the control circuit is configured to control the first switch circuit to be turned on, the second switch circuit to be turned on and the third switch circuit to be turned off in the threshold voltage detection stage of the second detection stage, and detect the second threshold voltage of the semiconductor device to be tested by controlling the detection circuit to output a pulse current. The threshold voltage detection stage is after the pre-processing stage.

[0014] In some possible implementation manners, the control circuit is configured to control the first switch circuit to be turned on, the second switch circuit to be turned on and the third switch circuit to be turned on between the pre-processing stage and the threshold voltage detection stage.

[0015] In some possible implementation manners, the control circuit is configured to control the second switch circuit to be turned off and the third switch circuit to be turned on between the first detection stage and the second detection stage.

[0016] In the second aspect, a detection device is provided. The detection device comprises a test machine and the threshold voltage detection circuit in the first aspect, and the threshold voltage detection circuit is arranged in the test machine.

[0017] In some possible implementation manners, the detection device further comprises a temperature control device arranged in the test machine, and the temperature control device is configured to control the working temperature of the semiconductor device to be tested and the temperature of the working environment of the semiconductor device to be tested.

[0018] It should be understood that the technical effects of the second aspect can refer to the technical effects of the first aspect and any of the implementation manners thereof, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 A circuit structure schematic diagram of a transistor test circuit is provided for the embodiments of the present application.

[0020] Figure 2 A circuit structure schematic diagram of a threshold voltage detection circuit provided for an embodiment of the present application;

[0021] Figure 3 A voltage waveform schematic diagram of a control terminal of a semiconductor device under test in a test provided for an embodiment of the present application;

[0022] Figure 4 A state schematic diagram of each switch in a threshold voltage detection circuit in a dynamic stress application stage provided for an embodiment of the present application;

[0023] Figure 5 A state schematic diagram of each switch in a threshold voltage detection circuit in a pre-processing stage of a first detection stage provided for an embodiment of the present application;

[0024] Figure 6 A state schematic diagram of each switch in a threshold voltage detection circuit in a threshold voltage detection stage of a first detection stage provided for an embodiment of the present application;

[0025] Figure 7 A state schematic diagram of each switch in a threshold voltage detection circuit between a pre-processing stage and a threshold voltage detection stage of a first detection stage provided for an embodiment of the present application;

[0026] Figure 8 A state schematic diagram of each switch in a threshold voltage detection circuit in a pre-processing stage of a second detection stage provided for an embodiment of the present application;

[0027] Figure 9 A state schematic diagram of each switch in a threshold voltage detection circuit in a threshold voltage detection stage of a second detection stage provided for an embodiment of the present application;

[0028] Figure 10 A state schematic diagram of each switch in a threshold voltage detection circuit between a pre-processing stage and a threshold voltage detection stage of a second detection stage provided for an embodiment of the present application;

[0029] Figure 11 A state schematic diagram of each switch in a threshold voltage detection circuit between a dynamic stress application stage and a first detection stage provided for an embodiment of the present application.

[0030] Reference signs: 110, bipolar pulse signal generation circuit; 120, test sub-circuit; 130, control circuit; 140, test table; 210, first pulse output circuit; 220, second pulse output circuit; 230, first switch circuit; 240, second switch circuit; 250, third switch circuit; 260, detection circuit. DETAILED DESCRIPTION

[0031] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0032] The terms "first", "second", etc. used in the embodiments of the present application are only used for distinguishing the same type of features, and should not be understood as indicating relative importance, quantity, order, etc.

[0033] The terms "exemplary" or "for example" used in the embodiments of the present application are used to represent an example, illustration or description. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design solutions. In fact, the terms "exemplary" or "for example" are used in the sense of presenting a related concept in a specific manner.

[0034] The terms "coupling", "connection" used in the embodiments of the present application should be interpreted in a broad sense, for example, can refer to a physical direct connection or an indirect connection through electronic devices, such as a connection through resistors, inductors, capacitors or other electronic devices.

[0035] Figure 1 A circuit structure schematic diagram of a transistor test circuit is provided. As shown in the figure, Figure 1 The test circuit includes a bipolar pulse signal generating circuit 110, a test sub-circuit 120, a control circuit 130 and a test table 140. The control circuit 130 is connected with the bipolar pulse signal generating circuit 110 and the test sub-circuit 120 respectively. The bipolar pulse signal generating circuit 110 is used to generate a bipolar pulse signal under the control of the control circuit 130, and the output of the bipolar pulse signal generating circuit 110 is connected to the control end of the transistor to be tested. The control circuit 130 controls the test sub-circuit 120, which is used to short the control end and the input end of the transistor to be tested, or short the input end and the output end of the transistor to be tested. The test table 140 is connected to the ground GND and the transistor to be tested, and is used to measure the threshold voltage of the transistor to be tested.

[0036] However, the interface and oxide layer defects of the wide bandgap semiconductor power device (hereinafter referred to as semiconductor device) make the measurement of its threshold voltage extremely susceptible to history effect, hysteresis effect and charge instability. Figure 1 The test circuit shown in the figure is difficult to accurately reflect the threshold voltage of the semiconductor device to be tested, and the continuous measurement results of the same semiconductor device to be tested can be very different.

[0037] The present application provides a threshold voltage detection circuit, as shown in the figure, Figure 2As shown, the threshold voltage detection circuit includes a first pulse output circuit 210, a second pulse output circuit 220, a first switch circuit 230, a second switch circuit 240, a third switch circuit 250, and a detection circuit 260.

[0038] In some embodiments, the first switch circuit 230 includes a first switch K1, the second switch circuit 240 includes a second switch K2, and the third switch circuit 250 includes a third switch K3. In some examples, the first switch K1, the second switch K2, and the third switch K3 can all be relays.

[0039] In some embodiments, the first pulse output circuit 210 includes an upper bridge transistor T1 and a lower bridge transistor T2; wherein the upper bridge transistor T1 and the lower bridge transistor T2 can be integrated into a half-bridge driving chip. An input end of the upper bridge transistor T1 is connected with a first input end of the first pulse output circuit 210, for receiving a first positive voltage DC1+. An input end of the lower bridge transistor T2 is connected with a second input end of the first pulse output circuit 210, for receiving a first negative voltage DC1-. Output ends of the upper bridge transistor T1 and the lower bridge transistor T2 are both connected with an output end of the first pulse output circuit 210.

[0040] In some embodiments, the second pulse output circuit 220 includes a first resistor R1, a second resistor R2, a fourth switch K4, and a fifth switch K5; wherein the fourth switch K4 and the fifth switch K5 can also be relays. One end of the first resistor R1 is connected with a first input end of the second pulse output circuit 220, for receiving a second positive voltage DC2+, and the other end of the first resistor R1 is connected with a first end of the fourth switch K4, a second end of the fourth switch K4 being connected with an output end of the second pulse output circuit 220. One end of the second resistor R2 is connected with a second input end of the second pulse output circuit 220, for receiving a second negative voltage DC2-, and the other end of the second resistor R2 is connected with a first end of the fifth switch K5, a second end of the fifth switch K5 being connected with the output end of the second pulse output circuit 220.

[0041] A first end of the first switch K1 is connected with the output end of the upper bridge transistor T1 and the output end of the lower bridge transistor T2 (i.e., the output end of the first pulse output circuit 210) respectively, and is connected with the second end of the fourth switch K4 and the second end of the fifth switch K5 (i.e., the output end of the second pulse output circuit 220) respectively. A second end of the first switch K1 is connected with a first end of the second switch K2 and a first end of the third switch K3 respectively. A second end of the second switch K2 is connected with a first end of the detection circuit 260, and a second end of the third switch K3 is connected with a second end of the detection circuit 260, and grounded GND.

[0042] The first end of the first switch K1 is used to connect to the control terminal (e.g., gate (G)) of the semiconductor device under test (DUT). The second end of the first switch K1 is used to connect to the first controlled terminal (e.g., drain (D)) of the semiconductor device under test (DUT). The second end of the third switch K3 is used to connect to the second controlled terminal (e.g., source (S)) of the semiconductor device under test (DUT). In other words, the first switch K1 can control whether the drain and gate of the semiconductor device under test (DUT) are at the same potential. The third switch K3 can control whether the drain and source of the semiconductor device under test (DUT) are at the same potential.

[0043] In some embodiments, the threshold voltage detection circuit further includes a control circuit (not shown in the drawings), which is respectively connected to the first pulse output circuit 210, the second pulse output circuit 220, the first switch K1, the second switch K2, and the third switch K3.

[0044] Figure 3 The figure shows the voltage waveform of the control terminal of the semiconductor device under test DUT during the test. Figure 3 As shown, the threshold voltage detection of the semiconductor device DUT under test in the embodiment of the present application includes a dynamic stress application stage, a first detection stage and a second detection stage; wherein, the dynamic stress application stage is before the first detection stage and the second detection stage, the detection stage includes a preprocessing stage and a threshold voltage detection stage, and the threshold voltage detection stage is after the preprocessing stage.

[0045] like Figure 3 and Figure 4 As shown, during the dynamic stress application phase, the control circuit controls the upper bridge transistor T1 and the lower bridge transistor T2 to be turned on at different times. That is, when the upper bridge transistor T1 is turned on, the lower bridge transistor T2 is turned off, and the first pulse output circuit 210 applies a first positive voltage DC1+ to the control terminal of the semiconductor device under test DUT. When the lower bridge transistor T2 is turned on, the upper bridge transistor T1 is turned off, and the first pulse output circuit 210 applies a first negative voltage DC1- to the control terminal of the semiconductor device under test DUT.

[0046] The control circuit controls the upper bridge transistor T1 and the lower bridge transistor T2 to periodically alternately conduct, thereby controlling the first pulse output circuit 210 to apply square wave pulses to the control terminal of the semiconductor device under test (DUT). The first level (also called the high level) of the square wave pulse is a first positive voltage DC1+ (e.g., +20V), and the second level (also called the low level) of the square wave pulse is a first negative voltage DC1- (e.g., -10V). This provides the dynamic gate bias stress required for DGB testing of the semiconductor device under test (DUT). In some embodiments, the frequency of the square wave pulse is greater than 50kHz.

[0047] As shown in FIG. 1 1, during the dynamic stress application stage, the control circuit controls the third switch K3 to be on, and controls the first switch K1, the fourth switch K4 and the fifth switch K5 to be off. In some embodiments, the control circuit can control the second switch K2 to be on. In other embodiments, the control circuit can also control the second switch K2 to be off. Figure 4

[0048] When the control circuit controls the upper bridge transistor T1 and the lower bridge transistor T2 to be off at the same time; that is, the output of the first pulse output circuit 210 is in a high resistance state, the dynamic stress application stage ends, and the voltage at the control terminal of the semiconductor device under test DUT is 0V.

[0049] As shown in FIG. 12, during the pre-processing stage of the first detection stage, the control circuit controls the fourth switch K4 to be on, and controls the fifth switch K5 to be off, so as to control the second pulse output circuit 220 to apply a second positive voltage DC2+ to the control terminal of the semiconductor device under test DUT. And the control circuit also controls the first switch K1 to be on, controls the second switch K2 to be off, and controls the third switch K3 to be off; wherein the control circuit controls the third switch K3 to be off first, and then controls the fourth switch K4 to be on. In other embodiments, the control circuit can also control the second switch K2 to be on. Figure 3 Figure 5 In some embodiments, the duration of the pre-processing stage of the first detection stage is 100ms. When the control circuit controls the fourth switch K4 and the fifth switch K5 to be off at the same time, the pre-processing stage of the first detection stage ends, and the voltage at the control terminal of the semiconductor device under test DUT is 0V.

[0050] As shown in FIG. 13, during the threshold voltage detection stage of the first detection stage, the control circuit controls the first switch K1 to be on, controls the second switch K2 to be on, and controls the third switch K3 to be off. After the third switch K3 is off, the control circuit controls the direct current power supply in the detection circuit 260 to apply a pulse current to the gate of the semiconductor device under test DUT. When the gate-source voltage of the semiconductor device under test DUT is stable, the gate-source voltage is read out, which is the first threshold voltage of the semiconductor device under test DUT.

[0051] As shown in FIG. 14, between the pre-processing stage and the threshold voltage detection stage of the first detection stage, the control circuit controls the first switch K1 to be on, controls the second switch K2 to be on, and controls the third switch K3 to be on. Figure 3 Figure 6

[0052] As shown in FIG. 15, during the pre-processing stage of the second detection stage, the control circuit controls the fourth switch K4 to be on, and controls the fifth switch K5 to be off, so as to control the second pulse output circuit 220 to apply a second positive voltage DC2+ to the control terminal of the semiconductor device under test DUT. And the control circuit also controls the first switch K1 to be on, controls the second switch K2 to be off, and controls the third switch K3 to be off; wherein the control circuit controls the third switch K3 to be off first, and then controls the fourth switch K4 to be on. In other embodiments, the control circuit can also control the second switch K2 to be on. Figure 3 Figure 7 In some embodiments, the duration of the pre-processing stage of the second detection stage is 100ms. When the control circuit controls the fourth switch K4 and the fifth switch K5 to be off at the same time, the pre-processing stage of the second detection stage ends, and the voltage at the control terminal of the semiconductor device under test DUT is 0V.

[0053] ​​​​​The embodiment of the present application can greatly weaken the influence of short-time stress on threshold voltage by applying the second positive voltage DC2+ to the control terminal of the DUT in the pre-processing stage, and thus the measurement result can more effectively reflect the actual situation of gate oxide degradation.

[0054] As shown in Figure 3 and Figure 8 in the pre-processing stage of the second detection stage, the control circuit controls the fourth switch K4 to be off and the fifth switch K5 to be on, so as to control the second pulse output circuit 220 to apply the second negative voltage DC2- to the control terminal of the DUT. In addition, the control circuit controls the first switch K1 to be on, the second switch K2 to be off, and the third switch K3 to be off; wherein the control circuit controls the third switch K3 to be off first, and then controls the fifth switch K5 to be on. In other embodiments, the control circuit can also control the second switch K2 to be on.

[0055] When the control circuit controls the fourth switch K4 and the fifth switch K5 to be off at the same time, the pre-processing stage of the second detection stage ends, and at this time, the voltage of the control terminal of the DUT is 0V.

[0056] As shown in Figure 3 and Figure 9 in the threshold voltage detection stage of the second detection stage, the control circuit controls the first switch K1 to be on, the second switch K2 to be on, and the third switch K3 to be off. After the third switch K3 is off, the control circuit controls the direct current power supply in the detection circuit 260 to apply a pulse current to the gate of the DUT, and when the gate-source voltage of the DUT is stable, the gate-source voltage is read out, which is the second threshold voltage of the DUT.

[0057] Similarly, as shown in Figure 3 and Figure 10 between the pre-processing stage and the threshold voltage detection stage of the second detection stage, the control circuit controls the first switch K1 to be on, the second switch K2 to be on, and the third switch K3 to be on.

[0058] The embodiment of the present application can greatly weaken the influence of short-time stress on threshold voltage by applying the second positive voltage DC2+ to the control terminal of the DUT in the pre-processing stage, and thus the measurement result can more effectively reflect the actual situation of gate oxide degradation.

[0059] Moreover, the embodiment of the present application can measure the first threshold voltage after positive prestress (i.e., the second positive voltage DC2+) and the second threshold voltage after negative prestress (i.e., the second negative voltage DC2-) in one test cycle of the semiconductor device DUT under test. The threshold voltage hysteresis effect of the semiconductor device DUT under test can be evaluated through the first threshold voltage and the second threshold voltage.

[0060] It should be understood that Figure 3 The embodiment in which the first detection phase precedes the second detection phase is merely an example. In other embodiments, the first detection phase may be performed after the second detection phase; that is, the second threshold voltage after negative prestress (i.e., the second negative voltage DC2-) is first measured, and then the first threshold voltage after positive prestress (i.e., the second positive voltage DC2+) is measured.

[0061] like Figure 3 and Figure 11 As shown, between the dynamic stress application phase and the first detection phase, the control circuit controls the fourth switch K4 and the fifth switch K5 to be disconnected, the second switch K2 to be disconnected, the first switch K1 to be turned on, and the third switch K3 to be turned on. Similarly, between the first detection phase and the second detection phase, the control circuit also controls the fourth switch K4 and the fifth switch K5 to be disconnected, the second switch K2 to be disconnected, the first switch K1 to be turned on, and the third switch K3 to be turned on.

[0062] In the embodiment of the present application, the states of some switches are switched between the dynamic stress application stage and the first detection stage, and between the first detection stage and the second detection stage, thereby reducing the switching operations in the detection stage and facilitating the rapid acquisition of the threshold voltage.

[0063] The present application also provides a detection device. The detection device includes a test machine and Figure 2 The threshold voltage detection circuit is arranged in a test machine.

[0064] Furthermore, the testing equipment may also include a temperature control device, which is arranged in the machine and is used to control the operating temperature of the semiconductor device to be tested (for example, controlling the junction temperature of the semiconductor device to be tested at 175°) and the temperature of the working environment of the semiconductor device to be tested, thereby realizing high temperature dynamic gate bias stress (HDGB) testing.

[0065] The embodiment of the present application provides a threshold voltage detection circuit and a detection device. The first pulse output circuit 210 in the threshold voltage detection circuit can apply stress to a dynamic gate bias stress of a to-be-detected semiconductor device DUT, and the second pulse output circuit 220 can apply a second positive voltage DC2+ (positive pre-stress) or a second negative voltage DC2- (negative pre-stress) to the to-be-detected semiconductor device DUT. The timing of the dynamic gate bias stress test and the threshold voltage detection is controlled through the conduction or disconnection of the first switch circuit 230, the second switch circuit 240 and the third switch circuit 250 and the working state of the first pulse output circuit 210 and the second pulse output circuit 220, so that the detection circuit 260 can realize accurate detection of the threshold voltage of the to-be-detected semiconductor device DUT.

[0066] In several embodiments provided in the present application, it should be understood that the disclosed threshold voltage detection circuit and detection device can be implemented in other manners. For example, the above-described device embodiments are merely schematic, for example, the division of the modules is merely a logical function division, and actual implementation can be in another manner, for example, a plurality of modules or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the modules shown or discussed can be indirect coupling or communication connection through some interfaces, devices or modules, and can be electrical, mechanical or other forms.

[0067] The modules described as separate components can or can not be physically separate, and the components shown as modules can or can not be physical modules, that is, can be located in one device or can be distributed to multiple devices. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment.

[0068] In addition, the functional modules in each embodiment of the present application can be integrated in one device, or each module can be physically present alone, or two or more modules can be integrated in one device.

[0069] The above is merely a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A threshold voltage detection circuit, characterized in that: It includes a first pulse output circuit, a second pulse output circuit, a first switch circuit, a second switch circuit, a third switch circuit, a detection circuit and a control circuit; wherein, The first input terminal of the first pulse output circuit is used to receive a first positive voltage, and the second input terminal of the first pulse output circuit is used to receive a first negative voltage; the first input terminal of the second pulse output circuit is used to receive a second positive voltage, and the second input terminal of the second pulse output circuit is used to receive a second negative voltage; The first end of the first switch circuit is connected to the output end of the first pulse output circuit and the output end of the second pulse output circuit respectively; the second end of the first switch circuit is connected to the first end of the second switch circuit and the first end of the third switch circuit respectively; The second end of the second switch circuit is connected to the first end of the detection circuit, and the second end of the third switch circuit is connected to the second end of the detection circuit; Wherein, the first end of the first switch circuit is used to connect to the control end of the semiconductor device under test, the second end of the first switch circuit is used to connect to the first controlled end of the semiconductor device under test, and the second end of the third switch circuit is used to connect to the second controlled end of the semiconductor device under test; The control circuit is connected to the first pulse output circuit, the second pulse output circuit, the first switch circuit, the second switch circuit, and the third switch circuit respectively; the control circuit is configured as follows: During the dynamic stress application phase, controlling the first pulse output circuit to output a square wave pulse, wherein a first level of the square wave pulse is the first positive voltage, and a second level of the square wave pulse is the first negative voltage; In a preprocessing stage of the first detection stage, controlling the second pulse output circuit to output the second positive voltage; In a preprocessing stage of the second detection stage, controlling the second pulse output circuit to output the second negative voltage; Wherein, the dynamic stress application stage is before the first detection stage and the second detection stage; The control circuit is configured to: during the dynamic stress application phase, control the third switch circuit to be turned on and control the first switch circuit to be turned off.

2. The threshold voltage detection circuit according to claim 1, wherein: The control circuit is configured to: In a preprocessing stage of the first detection stage, controlling the first switch circuit to be turned on, and controlling the third switch circuit to be turned off; In a preprocessing stage of the second detection stage, the first switch circuit is controlled to be turned on, and the third switch circuit is controlled to be turned off.

3. The threshold voltage detection circuit according to any one of claims 1 to 2, characterized in that: The control circuit is configured to: During a threshold voltage detection phase of the first detection phase, controlling the first switch circuit to be turned on, controlling the second switch circuit to be turned on, and controlling the third switch circuit to be turned off; as well as, Detecting a first threshold voltage of the semiconductor device to be tested by controlling the detection circuit to output a pulse current; The threshold voltage detection stage follows the pre-processing stage.

4. The threshold voltage detection circuit according to any one of claims 1 to 2, characterized in that: The control circuit is configured to: In the threshold voltage detection phase of the second detection phase, controlling the first switch circuit to be turned on, controlling the second switch circuit to be turned on, and controlling the third switch circuit to be turned off; as well as, Detecting a second threshold voltage of the semiconductor device to be tested by controlling the detection circuit to output a pulse current; The threshold voltage detection stage follows the pre-processing stage.

5. The threshold voltage detection circuit according to claim 3, wherein: The control circuit is configured to: Between the pre-processing stage and the threshold voltage detection stage, the first switch circuit is controlled to be turned on, the second switch circuit is controlled to be turned on, and the third switch circuit is controlled to be turned on.

6. The threshold voltage detection circuit according to claim 1, wherein: The control circuit is configured to: Between the first detection phase and the second detection phase, the second switch circuit is controlled to be disconnected, and the third switch circuit is controlled to be connected.

7. A detection device, characterized in that: The device comprises a test machine and the threshold voltage detection circuit according to any one of claims 1 to 6, wherein the threshold voltage detection circuit is arranged in the test machine.

8. The detection device according to claim 7, characterized in that It also includes a temperature control device, which is arranged in the machine and is used to control the working temperature of the semiconductor device to be tested and the temperature of the working environment where the semiconductor device to be tested is located.

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