Chip testing circuit, chip and testing method

Abstract

The application relates to the technical field of chip testing, and discloses a chip testing circuit, a chip and a testing method, the circuit comprises a plurality of test module groups and corresponding logic calculation modules, the test module group comprises a plurality of test modules; a test vector input end and a test vector output end of two adjacent test modules are connected, and an expected value input end and an expected value output end of the two adjacent test modules are connected; the test vector input end is connected with a test vector, the expected value input end is connected with an expected test vector value, a control end is connected with a control signal, the test vector and the expected test vector value are compared by a comparison unit, and a comparison result is output to the logic calculation module; and the logic calculation module is used for outputting a sequence value according to the comparison result. When the chip with a plurality of same circuit modules inside is tested, the same modules are grouped, each group of test modules can be tested and compared at the same time, the failed module can be quickly located, and the testing efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a chip testing circuit, a chip and a testing method. Background Art

[0002] As various industries enter a critical period of artificial intelligence upgrades, market demand for high-performance computing and AI chips is rapidly increasing, and the integration of integrated circuits is correspondingly increasing. This has led to increasing requirements for DFT (Design for Test) SCAN testing. Factors such as test time and power consumption can significantly impact the overall DFT testing cost. Against this backdrop, this invention can reduce test time and accelerate the detection of failed dies when performing DFT SCAN testing on multiple identical modules.

[0003] Existing DFT SCAN testing uses offsets to determine the input and output ports of each scan chain. However, at a fixed test frequency, test time depends on the length of the scan chain. For very large chips with many identical modules, this consumes a significant amount of I / O resources, requiring repeated testing of the same modules, significantly wasting resources.

[0004] Therefore, the existing technology still needs to be improved and developed. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a chip test circuit, chip and test method to solve the problem that the existing DFT SCAN test solution requires a large amount of IO resources and the same module needs to be tested repeatedly, which greatly wastes resources.

[0006] The technical solutions of the present invention are as follows:

[0007] In a first aspect, the present invention provides a chip test circuit, comprising a plurality of test module groups and corresponding logic calculation modules, wherein the test module groups include a plurality of test modules;

[0008] The test module includes a test vector input terminal, an expected value input terminal, a test vector output terminal, an expected value output terminal, a control terminal, a comparison result output terminal, a comparison circuit and a data acquisition and storage circuit;

[0009] The test vector input terminal and the test vector output terminal of two adjacent test modules are connected, and the expected value input terminal and the expected value output terminal of two adjacent test modules are connected;

[0010] The test vector input terminal is connected to the test vector, the expected value input terminal is connected to the expected test vector value, and the control terminal is connected to the control signal;

[0011] The comparison circuit is connected to the data acquisition and storage circuit, and is connected to the clock signal, the control signal, the test vector, and the expected test vector value. The comparison circuit is used to compare the test vector with the expected test vector value when the control signal is at a high level, and output the comparison result to the data acquisition and storage circuit;

[0012] The data acquisition and storage circuit is connected to the comparison result output terminal, and is used to store the comparison result and output the comparison result to the logic calculation module through the comparison result output terminal;

[0013] The logic calculation module is connected to the comparison result output end of each test module, and the logic calculation module is used to output a sequence value according to the comparison result; wherein, 0 in the sequence value indicates that the corresponding test module is qualified, and 1 in the sequence value indicates that the corresponding test module is unqualified.

[0014] According to a further configuration of the present invention, the comparison circuit includes a register group, a first AND gate circuit, a second AND gate circuit and an XOR gate circuit;

[0015] The input end of the register group is connected to the test vector input end;

[0016] A first input terminal of the first AND gate circuit is connected to a clock signal, a second input terminal of the first AND gate circuit is connected to the control terminal, and an output terminal of the first AND gate circuit is connected to the clock terminal of the register group;

[0017] The first input terminal of the second AND gate circuit is connected to the output terminal of the register group, the second input terminal of the second AND gate circuit is connected to the control terminal, and the output terminal of the second AND gate circuit is connected to the first input terminal of the XOR gate circuit;

[0018] The second input end of the XOR gate circuit is connected to the expected value input end, and the output end of the XOR gate circuit is connected to the data acquisition and storage circuit.

[0019] According to a further configuration of the present invention, the register group includes a plurality of flip-flops, and the output end and the input end of two adjacent flip-flops are connected.

[0020] According to a further configuration of the present invention, the data acquisition and storage circuit is a status register group.

[0021] According to a further configuration of the present invention, the trigger is a D trigger.

[0022] According to a further configuration of the present invention, the logic calculation module is an OR gate circuit.

[0023] In a second aspect, the present invention provides a chip comprising the chip testing circuit as described above.

[0024] In a third aspect, the present invention provides a chip testing method for testing the aforementioned chip, comprising:

[0025] The test modules of the chip are grouped, wherein each test module group includes several test modules;

[0026] Control the control signal input to the test module to be high level, so that the test vector connected to the test module is shifted through the scan chain for testing;

[0027] Compare the test vector output by the test module scan chain with the expected test vector value and output the comparison result;

[0028] Collecting and storing comparison results;

[0029] Perform logic operations based on the comparison results and output a sequence value, and determine whether the current module to be tested is qualified based on the sequence value.

[0030] The present invention is further configured such that, in the step of controlling the control signal input to the test module to be at a high level so that the test vector connected to the test module is shift tested through the scan chain, each test module group is individually connected to the test vector and the control signal.

[0031] The present invention provides a chip test circuit, chip and test method, wherein the chip test circuit includes several test module groups and corresponding logic calculation modules, wherein the test module group includes several test modules; the test vector input end of two adjacent test modules is connected to the test vector output end, and the expected value input end of two adjacent test modules is connected to the expected value output end; the test vector input end is connected to the test vector, the expected value input end is connected to the expected test vector value, and the control end is connected to the control signal; after the test vector and the expected test vector value are compared by the comparison circuit, the obtained comparison result is stored in the data acquisition and storage circuit and output to the logic calculation module via the data acquisition and storage circuit; the logic calculation module is connected to the comparison result output end of each test module, and the logic calculation module is used to output a sequence value according to the comparison result; wherein 0 in the sequence value indicates that the corresponding test module is qualified, and 1 in the sequence value indicates that the corresponding test module is unqualified. When testing a chip with many identical circuit modules inside, the present invention groups the identical circuit modules so that each group of test modules can be tested and compared simultaneously. This not only enables rapid location of failed modules and selection of bad chips, but also reduces the number of IO ports, avoids repeated testing of identical modules, improves test efficiency, and reduces resource waste. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary personnel in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0033] Figure 1 It is a schematic diagram of grouping test modules in one embodiment of the present invention.

[0034] Figure 2 It is a circuit principle diagram of a chip testing circuit in one embodiment of the present invention.

[0035] Figure 3 1 is a circuit diagram of a comparison unit in one embodiment of the present invention.

[0036] Figure 4 It is a timing control diagram in one embodiment of the present invention.

[0037] Figure 5 It is a flowchart of a chip testing method in one embodiment of the present invention.

[0038] The symbols in the accompanying drawings are: 100, test module; 110, comparison unit; 111, comparison circuit; 112, data acquisition and storage circuit; 113, register group; 200, logic calculation module. DETAILED DESCRIPTION

[0039] The present invention provides a chip test circuit, chip, and test method. To make the objectives, technical solutions, and effects of the present invention more clear and explicit, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0040] In the embodiments and patent claims, unless otherwise specified herein, the words "a," "an," "the," and "the" may include plural forms. If the embodiments of the present invention include descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly specifying the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features.

[0041] It should be further understood that the term "comprising" used in the description of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" as used herein can include wireless connections or wireless couplings. The term "and / or" as used herein includes all or any units and all combinations of one or more of the items listed in association.

[0042] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0043] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0044] The inventors discovered that Design for Testability (DFT) is an integrated circuit design technique that embeds special structures into the circuit during the design phase so that it can be tested after the design is complete. Because many internal node signals of a circuit are difficult to control and observe externally, by adding DFT structures, such as scan chains, internal signals can be exposed to the outside of the circuit, which can improve test efficiency during the testing phase. However, if the chip is very large and has many identical modules inside, the existing DFT SCAN test solution requires a large amount of IO resources, and the same modules need to be tested repeatedly, which greatly wastes resources.

[0045] To address the above technical issues, the present invention provides a chip test circuit, chip, and test method. This design addresses the drawbacks of large-scale chip multi-module testing, which is limited by I / O number constraints and requires repeated testing of the same modules. The present invention utilizes a grouping algorithm for comparison, which can control the designated modules that require testing (or omit testing for modules that do not require testing). Furthermore, the present invention can quickly and accurately locate failed modules based on the comparison output results of each test module, ultimately selecting bad chips to meet design and testing requirements. By grouping identical circuit modules, each group of test modules can be tested and compared simultaneously. This not only allows for rapid location of failed modules and selection of bad chips, but also reduces the number of I / O ports, avoiding repeated testing of the same modules, improving test efficiency, and reducing resource waste.

[0046] Please also see Figures 1 to 4 , the present invention provides a preferred embodiment of a chip testing circuit.

[0047] In some embodiments, as Figures 1 to 3As shown, the present invention provides a chip test circuit, which includes several test module groups and corresponding logic calculation modules 200, the test module group includes several test modules 100; the test module 100 includes a test vector input terminal, an expected value input terminal, a test vector output terminal, an expected value output terminal, a control terminal, a comparison result output terminal and a comparison unit 110; the test vector input terminal of two adjacent test modules 100 is connected to the test vector output terminal, and the expected value input terminal of two adjacent test modules 100 is connected to the expected value output terminal; the test vector input terminal is connected to the test vector, the expected value input terminal is connected to the expected test vector value, and the control terminal is connected to the control signal. The test vector and the expected test vector value are compared by the comparison unit 110 and the comparison result is output to the logic calculation module 200; the logic calculation module 200 is connected to the comparison result output terminal of each test module 100, and the logic calculation module 200 is used to output a sequence value according to the comparison result; wherein, 0 in the sequence value indicates that the corresponding test module 100 is qualified, and 1 in the sequence value indicates that the corresponding test module 100 is unqualified.

[0048] In this embodiment, the test module 100 refers to a module with the same circuit structure in the chip. When performing a DFT SCAN test, the same modules can be grouped and then tested. Figure 1 PE0-PE15 can be grouped into 4x4 groups, with PE0-PE3 forming a test module group, or 8x2 groups, with PE0-PE1 forming a test module group. The specific grouping can be based on the number of registers and logic gates in each PE. In this embodiment, the grouping is 4x4. Each group of test modules 100 corresponds to a logic calculation module 200. The logic calculation module 200 outputs the comparison results of each group as a sequence value.

[0049] See also Figure 2The test module 100 includes a test vector input terminal SI, an expected value input terminal SO_ref, a test vector output terminal SI_x, an expected value output terminal SO, a control terminal, a comparison result output terminal SO_CMP, and a comparison unit 110. The control terminals of each test module in the first group of test modules are represented by SEN[0], SEN[1], SEN[2], and SEN[3], SEN[3:0] represents the control signal of the first group of test modules, and the comparison result output terminals are represented by SO_CMP[0], SO_CMP[1], SO_CMP[2], and SO_CMP[3]. The test vector input terminal of the first test module 100 in each group of test modules 100 is connected to the test vector, and the expected value input terminal is connected to the expected test vector value. The test vector and the expected test vector value are provided by the automatic test pattern generation tool (ATPG) of the automatic test equipment (ATE), and the automatic test equipment also provides a clock signal. The test vector output terminals of the upper and lower test modules 100 are connected to the test vector input terminals, and the expected value output terminals are connected to the expected value input terminals. This allows the test vectors and expected test vector values ​​provided by the automatic test equipment to be provided to the test vector input terminals and expected value input terminals of the test module 100 at the next level. The control terminal can receive a control signal, provided by the chip under test, which is an enable signal that controls whether to test the test module 100. The comparison result output terminals of each group of test modules 100 are connected to the logic calculation module 200.

[0050] In specific implementation, when the control signal SEN of the current module is 0, that is, the control signal is at a low level, the current module to be tested is not tested directly. When the control signal SEN of the current module is 1, that is, the control signal is at a high level, the current test module 100 will perform a shift scan test process, that is, the test vector passes through the scan chain inside the test module 100, and is compared with the expected test vector value through the comparison unit 110, and 0 or 1 is output from the comparison result output terminal of the test module 100 to determine whether the current test module 100 is wrong. For example, when the output comparison result is 0, it means that the current test module 100 is qualified, and when the output comparison result is 1, it means that the current test module 100 is unqualified. If the control signal of the test module 100 of the next level is also at a high level, the comparison and judgment operation is consistent with the working principle of the previous level, and will not be repeated here. It should be noted that when testing the chip, the test can be performed before the chip is packaged, or after the chip is packaged.

[0051] In this way, test vectors for each group of test modules 100 can be input simultaneously without affecting each other. For example, in this embodiment, 16 PE modules are grouped into 4 groups, allowing all 16 PE modules to be tested simultaneously. Furthermore, the test results of each test module 100 are affected by the previous test module 100, so simply reading the data of a single test module 100 can reveal the test results of the corresponding PE module. Therefore, when testing a chip with many identical circuit modules, the present invention groups the identical circuit modules and allows for simultaneous testing and comparison of each group of test modules 100. This not only allows for rapid location of failed modules and selection of bad chips, but also reduces the number of IO ports, avoiding repeated testing of identical modules, improving test efficiency, and reducing resource waste.

[0052] In some embodiments, as Figure 2 and Figure 3 As shown, the comparison unit 110 includes a comparison circuit 111 and a data acquisition and storage circuit 112; the comparison circuit 111 is connected to the data acquisition and storage circuit 112, and the comparison circuit 111 is connected to the clock signal, the control signal, the test vector and the expected test vector value. The comparison circuit 111 is used to compare the test vector with the expected test vector value when the control signal is at a high level, and output the comparison result to the data acquisition and storage circuit 112; the data acquisition and storage circuit 112 is connected to the comparison result output end, and the data acquisition and storage circuit 112 is used to store the comparison result and output the comparison result to the logic calculation module 200 through the comparison result output end.

[0053] In this embodiment, the comparison circuit 111 receives the control signal, the test vector, the expected test vector value, and the clock signal. When the control signal is at a low level, the test module 100 does not receive a clock signal, and the corresponding test module 100 participates in the test. When the control signal is at a high level, the comparison circuit 111 compares the received test vector with the expected test vector value and outputs the comparison result to the data acquisition and storage circuit 112. The data acquisition and storage circuit 112 can collect and store the comparison result output by the comparison unit 110, and then output it to the logic calculation module 200 via the comparison result output terminal of the test module 100.

[0054] In some embodiments, as Figure 3As shown, the comparison circuit 111 includes a register group 113, a first AND gate circuit AND_1, a second AND gate circuit AND_2, and an exclusive OR gate circuit XOR_1; the input end of the register group 113 is connected to the test vector input end; the first input end of the first AND gate circuit AND_1 is connected to the clock signal, the second input end of the first AND gate circuit AND_1 is connected to the control end, and the output end of the first AND gate circuit AND_1 is connected to the clock end of the register group 113; the first input end of the second AND gate circuit AND_2 is connected to the output end of the register group 113, the second input end of the second AND gate circuit AND_2 is connected to the control end, and the output end of the second AND gate circuit AND_2 is connected to the first input end of the exclusive OR gate circuit XOR_1; the second input end of the exclusive OR gate circuit XOR_1 is connected to the expected value input end, and the output end of the exclusive OR gate circuit XOR_1 is connected to the data acquisition and storage circuit 112.

[0055] In this embodiment, the test vector input of the test module 100 is connected to the input and test vector output of the register bank 113, respectively, enabling the test vector to be simultaneously transmitted to the register bank 113 and the next-level test module 100. The first AND gate AND_1 receives a clock signal and a control signal. When the control signal is high, the clock signal is input to the corresponding test module 100. The second AND gate AND_2 receives the test vector and the control signal after shifting by the register bank 113, and inputs the test vector to the XOR gate XOR_1. The expected value input is connected to the XOR gate XOR_1 and the expected value output, respectively, enabling the expected test vector value to be input to the XOR gate XOR_1 and simultaneously output to the next-level test module 100 via the expected value output. The XOR gate XOR_1 operates on the input test vector and the expected test vector value, and outputs the comparison result to the data acquisition and storage circuit 112.

[0056] In some embodiments, as Figure 3 As shown, the register group 113 includes a plurality of flip-flops SET, and the output terminals and input terminals of two adjacent flip-flops SET are connected.

[0057] In this embodiment, the register group 113 includes a plurality of flip-flops connected in series, the number of which corresponds to the number of bits of the test vector data, that is, each flip-flop corresponds to one bit. In some embodiments, the flip-flop may be a D flip-flop.

[0058] In some embodiments, the data acquisition and storage circuit 112 is a status register group.

[0059] In this embodiment, the data acquisition and storage circuit 112 may be composed of a plurality of status registers.

[0060] In some embodiments, as Figure 3 As shown, the logic calculation module 200 is an OR gate circuit.

[0061] In this embodiment, the logic calculation module 200 may be an OR gate circuit OR_N, and the comparison results (SO_CMP[0], SO_CMP[1], SO_CMP[2], SO_CMP[3]) output by each group of test modules are input into the logic calculation module 200. When the sequence values ​​output by the logic calculation module 200 are all low, the logic calculation module outputs the result PE_FALL_DONE at a low level, indicating that all PE modules in the current group are qualified. When one of the output results is high, the logic calculation module outputs the result PE_FALL_DONE at a high level, indicating that there is a problem with the PE module in the group and that one PE module is unqualified. By observing the comparison result output ports of each PE module, if the comparison result output port of a test module shows a value of 1, the corresponding PE module can be accurately located as unqualified.

[0062] like Figure 4 As shown in the figure, when the third PE module and the fourth PE module in one group of PE modules are tested, it can be found that the third PE module is normal and the fourth PE module is abnormal, wherein ScanEn represents the scan enable signal. TEST_CLK represents the clock signal, ScanIn[0] represents the test vector of the first test module, SEN[3] represents the control signal of the fourth test module, PE_ScanOunt[0] represents the expected test vector value output by the fourth test module, SO_Ref represents the expected test vector value, PE3_SO_CMP represents the comparison result output by the fourth test module, SEN[2] represents the control signal of the third test module, PE2_SO_CMP represents the comparison result output by the third test module, and PE_FALL_DONE represents the output result of the logic calculation module.

[0063] In some embodiments, the present invention provides a chip including the chip test circuit described above, which is described in detail in an embodiment of a chip test circuit and will not be described in detail here.

[0064] In some embodiments, as Figure 5 As shown, the present invention provides a chip testing method for testing the chip described above, which comprises the steps of:

[0065] S100, grouping the test modules of the chip, wherein each test module group includes a plurality of test modules;

[0066] S200, controlling the control signal input to the test module to be high level, so that the test vector connected to the test module is shifted through the scan chain for testing;

[0067] S300, comparing the test vector output by the test module scan chain with the expected test vector value and outputting the comparison result;

[0068] S400, collecting and storing comparison results;

[0069] S500 , performing a logical operation based on the comparison result and outputting a sequence value, and judging whether the current test module is qualified based on the sequence value.

[0070] In this embodiment, when performing a DFT SCAN test, identical modules are grouped and then tested. Each group of test modules corresponds to a logic calculation module. The logic calculation module outputs the comparison results of each group in the form of a sequence value.

[0071] When the control signal SEN of the current module is 0, that is, the control signal is at a low level, the current test module will not be tested directly. When the control signal SEN of the current module is 1, that is, the control signal is at a high level, the current test module will be tested. In specific implementation, the control signal of the test module to be tested is at a high level, and the current test module will perform a shift scan test process, that is, after the test vector passes through the scan chain inside the test module, it is compared with the expected test vector value through the comparison unit, and 0 or 1 is output from the comparison result output terminal of the test module to determine whether the current module to be tested is incorrect. For example, when the output comparison result is 0, it means that the current module to be tested is qualified, and when the output comparison result is 1, it means that the current module to be tested is unqualified. By observing the comparison result output port of each test module, if the comparison result output port SO_CMP output port of a test module shows a value of 1, the corresponding PE module can be accurately located as unqualified. If a PE module has been judged as unqualified, the control signal SEN of the PE module only needs to be set to 0, and the PE module will enter the bypass state and will not be tested, thereby not affecting other PE modules that pass.

[0072] In this embodiment, each of the test module groups is independently connected to a test vector and a control signal, so that the test modules that need to be tested can be controlled or the test modules that do not need to be tested can be processed.

[0073] In summary, the chip testing circuit, chip, and testing method provided by the present invention have the following beneficial effects:

[0074] When testing chips with many identical circuit modules, by grouping the identical circuit modules and testing and comparing each group of test modules simultaneously, not only can the failed module be quickly located and bad chips be sorted out, but the number of IO ports can also be reduced, avoiding repeated testing of the same module, thus improving test efficiency and reducing resource waste.

[0075] The test vectors of each test module can be input simultaneously without affecting each other. The test results of each test module are affected by the previous test module. The test results of the corresponding PE module can be obtained by directly reading the data of a single test module.

[0076] You can control the PE modules that need to be tested, or process the PE modules that do not need to be tested.

[0077] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A chip testing circuit, characterized in that: The system comprises several test module groups and corresponding logic calculation modules, wherein the test module groups include several test modules; wherein the test modules refer to modules with the same circuit structure in the chip; The test module includes a test vector input terminal, an expected value input terminal, a test vector output terminal, an expected value output terminal, a control terminal, a comparison result output terminal, a comparison circuit and a data acquisition and storage circuit; The test vector input terminal and the test vector output terminal of two adjacent test modules are connected, and the expected value input terminal and the expected value output terminal of two adjacent test modules are connected; The test vector input terminal is connected to the test vector, the expected value input terminal is connected to the expected test vector value, and the control terminal is connected to the control signal; the control terminal can be connected to the control signal, the control signal is provided by the chip under test, and the control signal is an enable signal that controls whether the test module needs to be tested; The comparison circuit is connected to the data acquisition and storage circuit, and is connected to the clock signal, the control signal, the test vector, and the expected test vector value. The comparison circuit is used to compare the test vector with the expected test vector value when the control signal is at a high level, and output the comparison result to the data acquisition and storage circuit; The data acquisition and storage circuit is connected to the comparison result output terminal, and is used to store the comparison result and output the comparison result to the logic calculation module through the comparison result output terminal; The logic calculation module is connected to the comparison result output terminal of each test module, and the logic calculation module is used to output a sequence value according to the comparison result; wherein 0 in the sequence value indicates that the corresponding test module is qualified, and 1 in the sequence value indicates that the corresponding test module is unqualified; The comparison circuit includes a register group, a first AND gate circuit, a second AND gate circuit and an XOR gate circuit; The input end of the register group is connected to the test vector input end; A first input terminal of the first AND gate circuit is connected to a clock signal, a second input terminal of the first AND gate circuit is connected to the control terminal, and an output terminal of the first AND gate circuit is connected to the clock terminal of the register group; The first input terminal of the second AND gate circuit is connected to the output terminal of the register group, the second input terminal of the second AND gate circuit is connected to the control terminal, and the output terminal of the second AND gate circuit is connected to the first input terminal of the XOR gate circuit; The second input end of the XOR gate circuit is connected to the expected value input end, and the output end of the XOR gate circuit is connected to the data acquisition and storage circuit; the XOR gate circuit can operate on the connected test vector and the expected test vector value, and output the comparison result to the data acquisition and storage circuit.

2. The chip testing circuit according to claim 1, characterized in that: The register group includes a plurality of flip-flops, and the output terminals and input terminals of two adjacent flip-flops are connected.

3. The chip testing circuit according to claim 1, wherein: The data acquisition and storage circuit is a status register group.

4. The chip testing circuit according to claim 2, characterized in that: The trigger is a D trigger.

5. The chip testing circuit according to claim 1, wherein: The logic calculation module is an OR gate circuit.

6. A chip, characterized in that: The chip test circuit comprises the chip test circuit according to any one of claims 1 to 5.

7. A chip testing method for testing the chip according to claim 6, characterized in that: include: The test modules of the chip are grouped, wherein each test module group includes several test modules; Control the control signal input to the test module to be high level, so that the test vector connected to the test module is shifted through the scan chain for testing; Compare the test vector output by the test module scan chain with the expected test vector value and output the comparison result; Collecting and storing comparison results; Perform logical operations based on the comparison results and output sequence values, and determine whether the current test module is qualified based on the sequence values.

8. The chip testing method according to claim 7, characterized in that: In the step of controlling the control signal input to the test module to be at a high level so that the test vector connected to the test module is shifted through the scan chain, each test module group is individually connected to the test vector and the control signal.

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