Memory management method and memory controller

Abstract

The invention provides a memory management method and a memory controller. The method comprises the following steps: judging whether the processing time of each input / output request exceeds a corresponding preset time threshold value or not; when the target processing time of the target input / output request exceeds a corresponding target preset time threshold value, obtaining a currently executed target storage device event; adjusting the target preset time threshold based on the target storage device event to obtain an adjusted target time threshold; applying the adjusted target time threshold, and monitoring whether the target storage device event is completed; and if the target storage device event has been completed, restoring the adjusted target time threshold to the original target preset time threshold. According to the technical scheme, the accuracy of performance monitoring of the storage device can be improved, and system interference or false alarm caused by frequent triggering of overtime warning is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data storage and management, and in particular to a memory management method and a memory controller for dynamically adjusting an input / output request processing time threshold based on storage device events. Background Art

[0002] With the rapid development of storage device technology, storage capacity is getting larger and larger, read and write speeds are getting faster and faster, and the scope of application is becoming wider and wider. However, with long-term use, storage devices may cause performance degradation or command timeouts due to various reasons (such as hardware failure, software defects, improper configuration, device aging, etc.), thereby affecting the stability and efficiency of the entire storage device.

[0003] Traditional storage device testing methods often provide only limited performance data, making it difficult to conduct in-depth analysis and locate the root cause of problems. Under high storage device load, instruction or data transmission may be delayed. However, the fixed processing time thresholds set by storage devices are overly strict, resulting in excessive false positives for normal operations, which in turn fail to fully reflect the storage device's accurate performance status.

[0004] For example, storage device performance may temporarily decrease due to storage device usage but then return to normal. If the processing time threshold is fixed, the storage device may not be able to adjust to this performance change in a timely manner. For example, if a video is being recorded and a threshold is set based on the video write speed, a write timeout may occur. Alternatively, reading the relevant logs may reveal that the device is frequently performing garbage collection, or the device temperature is high, resulting in insufficient free space and overheating on the storage device. This may cause the current write rate to decrease, the load to increase, and the input / output request processing time to increase, thus exceeding the preset processing time threshold. Summary of the Invention

[0005] In view of this, the present disclosure provides a memory management method and a memory controller for dynamically adjusting the input / output request processing time threshold based on storage device events. By monitoring the processing time of the input / output requests received by the storage device and the storage device events that affect the processing time, when the processing time exceeds the preset time threshold, the time threshold is dynamically adjusted based on the currently executed storage device event, and the original threshold is restored after the event is completed, thereby solving the problem of false alarms caused by traditional fixed timeout thresholds.

[0006] One or more embodiments of the present disclosure provide a memory management method applicable to a storage device configured with a memory module. The method comprises: determining, based on a processing time of an input / output request, whether the processing time exceeds a preset time threshold; obtaining a target storage device event currently being executed when a target processing time of a target input / output request exceeds the target preset time threshold; adjusting the target preset time threshold based on the target storage device event to obtain an adjusted target time threshold; applying the adjusted target time threshold and monitoring whether the target storage device event is completed; and restoring the adjusted target time threshold to the original target preset time threshold if the target storage device event is completed.

[0007] In one or more embodiments of the present disclosure, before adjusting the target preset time threshold based on the target storage device event to obtain the adjusted target time threshold, it also includes: within a predetermined time, determining that the same storage device target event in the storage device event reaches a preset trigger number of times; and wherein, adjusting the target preset time threshold based on the target storage device event to obtain the adjusted target time threshold includes: when the same target storage device event in the storage device event reaches a preset trigger number of times, adjusting the target preset time threshold to obtain the adjusted target time threshold.

[0008] In one or more embodiments of the present disclosure, adjusting the target preset time threshold based on the target storage device event to obtain the adjusted target time threshold includes: obtaining corresponding threshold adjustment parameters from a preset time threshold adjustment table based on the event type of the target storage device event and the request type of the target input / output request; the threshold adjustment table records multiple threshold adjustment parameters corresponding to storage device events of different event types and input / output requests of different request types; extending the target preset time threshold based on the threshold adjustment parameters to obtain the adjusted target time threshold; and applying the adjusted target time threshold to subsequent input / output requests related to the target input / output request type.

[0009] In one or more embodiments of the present disclosure, restoring the adjusted target time threshold to the original target preset time threshold includes: when the target storage device event is completed, triggering a progressive recovery program for the adjusted target time threshold, the progressive recovery program including: presetting multiple recovery time points, and gradually reducing the adjusted target time threshold based on the multiple recovery time points until the adjusted target time threshold is restored to the original target preset time threshold.

[0010] In one or more embodiments of the present disclosure, the method further includes: obtaining one or more target temperature values from one or more temperature sensors of the storage device; determining whether the one or more target temperature values exceed the corresponding one or more target preset temperature thresholds; and when the one or more target temperature values exceed the corresponding one or more target preset temperature thresholds, based on the one or more target temperature values, extending the target preset time threshold to obtain an adjusted target time threshold.

[0011] In one or more embodiments of the present disclosure, the method further includes: determining whether the one or more target temperature values have fallen below the corresponding target preset temperature threshold; and if the one or more target temperature values have fallen below the corresponding target preset temperature threshold, triggering a progressive recovery program for the adjusted target time threshold, the progressive recovery program including: presetting multiple recovery time points, and gradually reducing the adjusted target time threshold based on the multiple recovery time points until the adjusted target time threshold is restored to the original target preset time threshold.

[0012] In one or more embodiments of the present disclosure, applying the adjusted target time threshold includes: processing another input / output request corresponding to the adjusted target time threshold, and confirming another processing time of the another input / output request; and determining whether the another processing time of the another input / output request exceeds the corresponding adjusted target time threshold.

[0013] In one or more embodiments of the present disclosure, a memory controller is provided for controlling a storage device configured with a memory module. The memory controller includes:

[0014] a memory interface control circuit for electrically connecting to the memory module; and

[0015] a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the storage device to electrically connect to the host system,

[0016] wherein the processor is configured to:

[0017] Determining, based on a processing time of an input / output request, whether the processing time exceeds a preset time threshold;

[0018] When a target processing time of a target input / output request exceeds a target preset time threshold, obtaining a currently executed target storage device event;

[0019] Adjusting the target preset time threshold based on the target storage device event to obtain an adjusted target time threshold;

[0020] applying the adjusted target time threshold and monitoring whether the target storage device event is completed; and

[0021] If the target storage device event has been completed, the adjusted target time threshold is restored to the original target preset time threshold.

[0022] Based on the above, the present disclosure realizes the dynamic adjustment of the input / output request processing time threshold based on the storage device event, improves the accuracy of the storage device performance monitoring and reduces false alarms. By real-time monitoring and recording the events of the storage device, different processing time thresholds can be set for commands such as read, write, and synchronization, and the current event is recorded when the processing time exceeds the preset threshold. When a processing time timeout occurs, the threshold can be dynamically adjusted according to the current event to reduce system interference or false alarms caused by frequent triggering of timeout warnings. When the tasks performed by the storage device are mostly large data volumes or complex operations, since these tasks themselves may take a long time to complete, by dynamically adjusting the time threshold, the memory controller can be prevented from triggering unnecessary timeout alarms and error handling processes during these events, thereby avoiding frequent interruptions of ongoing storage operations, reducing the additional resource overhead caused by retry operations, and ensuring the response efficiency of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present disclosure;

[0024] Figure 2 is a flowchart of a memory management method according to an embodiment of the present disclosure;

[0025] Figure 3 FIG1 is a timing diagram of dynamically adjusting an input / output request processing time threshold value with a memory controller as a main judgment component according to an embodiment of the present disclosure;

[0026] Figure 4 is another flow chart of a memory management method according to an embodiment of the present disclosure;

[0027] Figure 5A 、 Figure 5B The present invention is a timing diagram of dynamically adjusting the input / output request processing time threshold with the host system processor as the main judgment component according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0029] Figure 1 FIG is a block diagram of a host system and a storage device according to an embodiment of the present disclosure. Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, a server, or a smart mobile device. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120 (also referred to as a host memory), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 can be disposed on a motherboard of the host system 10.

[0030] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0031] In this embodiment, the host system 10 is electrically connected to the storage device 20 via the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0032] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless method. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low-power Bluetooth memory storage device (e.g., iBeacon), etc., based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a display, and a speaker via the system bus.

[0033] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0034] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0035] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 can be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present disclosure is not limited to this, and the host memory 120 can also be other suitable memories. In addition, the host memory 120 also stores temporary data related to the disclosed solution, including processing time records of input / output requests, target preset time thresholds, adjusted target time thresholds, information related to multiple storage device events affecting various input / output requests, event timeout association count data, time threshold adjustment tables, and recovery time point data required for the progressive recovery process. This data is frequently accessed and updated during the process of the processor 110 executing the dynamic adjustment of the input / output request processing time threshold, in accordance with the memory management method of the present disclosure.

[0036] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading, and erasing data in the memory module 220 according to instructions from the host system 10 .

[0037] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities that controls the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with a plurality of control instructions / program codes, and when the storage device 20 is operating, these control instructions / program codes are executed to perform operations such as writing, reading, and erasing data. Furthermore, the processor 211 is configured to execute the memory management method provided herein.

[0038] In other embodiments, the control instructions / program codes corresponding to the data reading method may be further implemented as a circuit unit in the form of hardware to realize the memory management method provided by the present disclosure.

[0039] It is worth noting that in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing unit (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar circuit components, but the present disclosure is not limited thereto. In one embodiment, the processor 110 and the processor 211 can operate in conjunction to implement the memory management method provided by the present disclosure.

[0040] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 may also be considered as operations performed by the memory controller 210.

[0041] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is configured to receive instructions from the processor 211 to transmit data. For example, the data management circuit 212 reads data from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213 (e.g., performing corresponding write operations based on various write instructions from the host system 10). For another example, the data management circuit 212 performs a read operation based on a read instruction from the host system 10, reads data from one or more physical units of the memory module 220 (the data may be read from one or more storage cells in the one or more physical units) via the memory interface control circuit 213, and writes the read data to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230. In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0042] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also known as programming) operation, a read operation, or an erase operation on the memory module 220 .

[0043] In addition, the data to be written to the memory module 220 will be converted into a format acceptable to the memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the memory module 220, the processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include a write instruction sequence instructing to write data, a read instruction sequence instructing to read data, an erase instruction sequence instructing to erase data, and corresponding instruction sequences for instructing various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, and a physical address will be included.

[0044] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationships between the logical addresses of the logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of the physical units (e.g., physical erase units / physical blocks, physical pages) configured in the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also referred to as the logical-to-physical mapping table) to look up the physical unit to which a logical unit is mapped (e.g., to look up the physical page to which a logical page is mapped; to look up the physical address to which a logical address is mapped). Furthermore, the memory controller 210 can use the physical-to-logical address mapping table (also referred to as the physical-to-logical mapping table) to look up the logical unit to which a physical unit is mapped (e.g., to look up the logical page to which a physical page is mapped; to look up the logical address to which a physical address is mapped).

[0045] The buffer memory 214 is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the memory module 220, and various system data used to manage the storage device 20. When the processor 211 is the primary execution component, the buffer memory 214 also stores data related to dynamically adjusting the input / output request processing time threshold, including input / output request processing time records, information related to multiple storage device events that affect various input / output requests, currently executed storage device event information (such as garbage collection, ECC error correction, mapping table refresh, etc.), preset time thresholds corresponding to various input / output requests, adjusted time thresholds, timed-out input / output request information, event completion status, event timeout associated count data, time threshold adjustment table, and recovery time point data required for the progressive recovery process. This information is recorded in log form or registers to facilitate the processor 211 to implement the memory management method provided by the present disclosure.

[0046] The memory module 220 is electrically connected to the memory controller 210 (specifically, to the memory interface control circuit 213) and is used to store user data sent by the host system 10. In one embodiment, the memory module 220 also stores firmware and program code modules executed by the processor 211, as well as statistical data or historical data related to the operation of the storage device 20 (e.g., information related to various storage device events that affect various input / output requests, preset time thresholds corresponding to various types of input / output requests, and threshold adjustment parameters corresponding to various storage device events).

[0047] In addition, each physical block in the memory module 220 further includes a plurality of physical pages, each physical page including a plurality of memory cells. It should be noted that the present disclosure is not limited to the size of each physical page and logical page.

[0048] Figure 2 The flowchart of the memory management method according to the embodiment of the present disclosure is shown.

[0049] In one embodiment, the processor 211 continuously monitors the processing time of each input / output request received by the storage device, and continuously monitors a plurality of storage device events that affect the processing time.

[0050] In this embodiment, the input / output request refers to a request sent by the host system 10 to the storage device 20 for reading data, writing data, or performing synchronization operations. Specifically, the input / output request mainly includes the following three types: a read request (Read Command), which is used to read data from the storage device 20; a write request (Write Command), which is used to write data to the storage device 20; and a synchronization request (Sync Command), which is used to ensure data consistency and complete the persistent storage of cached data. These input / output requests are different from the management instructions (such as formatting instructions, secure erase instructions, etc.) or status query instructions (such as temperature query, health status query, etc.) of the storage device 20. The input / output request directly involves data access operations, and the processing time is usually affected by the internal state of the storage device 20 and the storage device events being executed. For example, when the storage device 20 is performing a garbage collection operation, the processing time of the input / output request may be significantly extended, thereby affecting the user experience.

[0051] In this embodiment, the processor 211 can record the start time and completion time of the input / output request to calculate the processing time. At the same time, the processor 211 also monitors the storage device events currently being executed through the task status register, such as garbage collection (GC), mapping table refresh, background data sorting, wear leveling, and other events that may affect the processing time. The task status register can be implemented, for example, via the following hardware: buffer memory 214, read-only memory (ROM), or a special storage circuit unit (not shown) additionally provided in the storage device. For example, for a garbage collection event, the processor 211 can determine whether the garbage collection event is being executed through the GC_STATUS flag in the task status register (e.g., a corresponding value of 1 indicates that the garbage collection event is being executed).

[0052] In this embodiment, the multiple storage device events that affect the processing time specifically include but are not limited to: garbage collection (GC) start event, garbage collection (GC) end event, page table garbage collection (PTE GC) start event, page table garbage collection (PTE GC) end event, new virtual block (VB) creation event, L2 refresh operation event, waiting for free block event, read disturb refresh (read disturb refresh) event, pre-erase virtual block creation event, background pre-erase virtual block event, task abort (abort) event, flash block optimization (FBO) event, ECC error correction event and refresh operation event of reinitializing the target virtual block after unexpected power interruption. These events usually occupy the computing and storage resources of the storage device, resulting in extended processing time of input / output requests, especially under high load conditions. The processor 211 records the occurrence status and impact of these events to provide a basis for subsequent time threshold adjustment.

[0053] In another embodiment, processor 211 can autonomously determine and learn storage device events that affect processing time, rather than being limited to pre-set event types. Specifically, processor 211 implements autonomous learning through the following steps: First, during the initial use phase of the storage device, the processing time of all input / output requests is recorded and a benchmark performance database is established. Second, when the processing time of a particular input / output request significantly deviates from the benchmark performance, processor 211 records all system status parameters at that point in time, including but not limited to the current task queue, resource usage, and internal operating status. Next, processor 211 uses statistical analysis to identify system status parameters that are highly correlated with extended processing time and identifies them as potential impacting events (for example, "Processor 211 uses a linear regression-based statistical model to analyze the correlation between historical IO latency data and system status parameters"). Finally, by continuously accumulating and updating this correlated data, processor 211 gradually establishes and refines a dynamic event-performance impact model. Through this autonomous learning mechanism, processor 211 can adapt to performance changes under different workloads and usage patterns, identify emerging influencing factors, and adjust time threshold policies accordingly, thereby achieving more accurate performance monitoring and management.

[0054] Reference Figure 2First, in step S210, based on the processing time of the input / output request, it is determined whether the processing time exceeds a preset time threshold. In this embodiment, different types of input / output requests (such as read, write, synchronization, etc.) may have different or the same preset time thresholds, which may be stored in a configuration register. For example, the preset time threshold for a read request may be set to 500 milliseconds, while the preset time threshold for a write request may be set to 800 milliseconds. The configuration register may be implemented, for example, via the following hardware: a buffer memory 214, a ROM, or a special storage circuit unit (not shown) additionally provided in the storage device.

[0055] Specifically, processor 211 monitors the entire processing cycle of each I / O request received by the storage device, from start to completion, records the processing time, and compares this time with a pre-set time threshold. In one embodiment, processor 211 accurately measures the processing time using an internal high-precision timer or system clock to ensure the accuracy of the comparison. Specifically, processor 211 records a timestamp when the I / O request begins and again when the request completes. The difference between the two timestamps is then calculated as the actual processing time.

[0056] When it is found that the target processing time of the target input / output request exceeds the target preset time threshold, the system proceeds to step S220 to obtain the currently executed target storage device event.

[0057] In step S220, when the processing time (also referred to as the target processing time) of a certain I / O request (also referred to as the target I / O request) exceeds the corresponding target preset time threshold, the processor 211 obtains the currently executing storage device event (one of the multiple storage device events, also referred to as the target storage device event). In other words, only when the processing time of a certain I / O request exceeds the corresponding preset time threshold will the processor 211 initiate an additional program to begin analyzing the currently executing storage device event to further determine whether the preset time threshold should be adjusted.

[0058] In one embodiment, when the processing time of a specific I / O request exceeds a corresponding preset time threshold, the processor 211 obtains information corresponding to the target I / O request (also referred to as target information). The target information may include the request type (such as read, write, or synchronization operation), request time, and request size. The target storage device event may be an ongoing event such as garbage collection, ECC error correction, or mapping table refresh. This information is recorded in the buffer memory 214 for subsequent analysis and processing.

[0059] In one embodiment, the processor 211 checks the status bits in the task status register to identify the storage device events currently being executed, such as garbage collection (GC), ECC error correction, mapping table refresh, etc. These events are usually the main reason for the extended processing time. The processor 211 can also obtain detailed information about the event, including the event type identifier, event start time, event completion progress, etc. In detail, in the process of obtaining the target storage device event, the processor 211 may need to access multiple internal registers or status bits, such as the GC_STATUS bit (a value of 1 indicates that garbage collection is being executed, and a value of 0 indicates that it is not being executed), the ECC_STATUS bit (indicating the ECC error correction status), etc., to fully understand the internal status of the current storage device.

[0060] Subsequently, in step S230, based on the target storage device event, the target preset time threshold is adjusted to obtain an adjusted target time threshold. Specifically, the processor 211 obtains the corresponding threshold adjustment parameter from the preset time threshold adjustment table based on the identified target storage device event type and target input / output request type, and applies it to the original preset time threshold to calculate a new adjusted time threshold. For example, for garbage collection events, the original threshold may be extended by 50%; for ECC error correction events, the original threshold may be extended by 100%. In detail, the processor 211 may use a multiplication factor (such as 1.5 times or 2 times) or an addition factor (such as adding 300 milliseconds) to adjust the threshold, or may apply different degrees of adjustment according to the severity or progress stage of the event. Among them, the adjusted target time threshold will be greater than the target preset time threshold.

[0061] In one embodiment, when one or more of the multiple storage device events are executed and the processing time of an input / output request exceeds the corresponding preset time threshold, the processor 211 records this phenomenon as the one or more storage devices causing the input / output request to time out and calculates the timeout associated count for each of the one or more storage devices. For example, the processor 211 may record the number of timeout requests associated with garbage collection events within the last 10 minutes. This statistical method helps avoid frequent adjustments to time thresholds due to brief or infrequent events, thereby reducing system burden and improving stability.

[0062] In one embodiment, processor 211 employs an adjustment mechanism directly triggered by a single event. Upon detecting a target storage device event (e.g., garbage collection) and a target I / O request timeout, processor 211 immediately performs a threshold adjustment operation. For example, upon detecting a garbage collection event occurring simultaneously with a read request timeout, processor 211 may directly adjust the preset time threshold for read requests from 500 milliseconds to 750 milliseconds (increasing the time threshold by 50%). Upon detecting an ECC error correction event occurring simultaneously with a write request timeout, processor 211 may directly adjust the preset time threshold for write requests from 800 milliseconds to 1600 milliseconds (increasing the time threshold by 100%).

[0063] However, this adjustment mechanism directly triggered by a single event may have technical problems. First, occasional timeouts and event coincidences may be caused by random factors, rather than an inevitable causal relationship. If the threshold is adjusted immediately every time a single timeout event is detected, it may lead to excessively frequent threshold adjustments, increasing system fluctuations and resource consumption. Secondly, although certain storage device events may cause short-term performance fluctuations, such fluctuations may be normal and acceptable, and the threshold does not need to be adjusted every time. In addition, frequent threshold adjustments will increase the system burden and affect the efficiency of normal operations, especially in high-load environments.

[0064] To solve the above technical problems, in another embodiment, the processor 211 implements an adjustment trigger mechanism based on a timeout association count. Specifically, the processor 211 counts the timeout association count of target storage device events in the case of input / output request timeouts within a predetermined time window, and performs threshold adjustment only when the timeout association count exceeds a preset count threshold. For example, the processor 211 may set a timeout threshold to be adjusted only when the number of timeout requests associated with a specific event (such as garbage collection) exceeds 2 times (preset count threshold) within the last 10 minutes; for events with a greater impact (such as ECC error correction), the timeout association count threshold may be set to 1 time, while for events with a smaller impact (such as mapping table refresh), the timeout association count threshold may be set to 3 times.

[0065] Through this judgment mechanism based on timeout correlation counts, the system can more accurately identify the actual correlation between storage device events and performance impacts, avoid unnecessary adjustments caused by accidental factors, and ensure timely threshold adjustments when they are really needed, thereby improving system stability and resource utilization efficiency.

[0066] In one embodiment, in the specific implementation of adjusting the time threshold, the processor 211 retrieves the corresponding threshold adjustment parameter from a preset time threshold adjustment table based on the event type of the target storage device event and the request type of the target input / output request. The threshold adjustment table records multiple threshold adjustment parameters corresponding to different event types of storage device events and different request types of input / output requests. For example, for a combination of a garbage collection event and a read request, the threshold adjustment parameter may be 1.5, indicating that the preset time threshold is extended by 50%. For a combination of an ECC error correction event and a write request, the threshold adjustment parameter may be 2.0, indicating that the preset time threshold is extended by 100%. For another example, for a combination of a garbage collection event and a read request, if the preset time threshold is 500 milliseconds, the threshold adjustment parameter is 250 milliseconds, which means that the preset time threshold can be extended to 750 milliseconds. For a combination of a mapping table refresh event and a synchronization request, if the preset time threshold is 800 milliseconds, the threshold adjustment parameter of 800 milliseconds can extend it to 1600 milliseconds to accommodate the increased processing time for such events. Specifically, different event types may require different time extension amounts, and these specific time values may be pre-set based on actual performance characteristics of the storage device.

[0067] Based on the obtained threshold adjustment parameter, processor 211 extends the target preset time threshold to obtain an adjusted target time threshold. For example, if the original preset time threshold for a read request is 500 milliseconds and the threshold adjustment parameter is 1.5, the adjusted target time threshold is 750 milliseconds. Processor 211 then applies the adjusted target time threshold to subsequent I / O requests of the target I / O request type, ensuring that all requests of the same type use the adjusted target time threshold during the current event.

[0068] In another embodiment, when the temperature of processor 211 exceeds a specific temperature, processor 211 may automatically reduce its operating frequency to protect the hardware, resulting in an average increase in I / O processing time. To address this type of input / output delay, processor 211 also obtains one or more temperature values from one or more temperature sensors (not shown) of the storage device, such as the controller temperature and / or the NAND flash memory temperature. Processor 211 determines whether these temperature values exceed corresponding preset temperature thresholds, such as a controller temperature threshold of 70°C or a NAND flash memory temperature threshold of 85°C. When the one or more temperature values exceed the corresponding one or more preset temperature thresholds, processor 211 extends the target preset time threshold based on the one or more temperature values to obtain an adjusted target time threshold. For example, when the controller temperature exceeds the 70°C threshold, processor 211 may extend the target preset time threshold from 500 milliseconds to 650 milliseconds; when the NAND flash memory temperature exceeds the 85°C threshold, processor 211 may extend the target preset time threshold from 500 milliseconds to 700 milliseconds; and when both temperatures exceed their respective thresholds, processor 211 may extend the target preset time threshold from 500 milliseconds to 800 milliseconds. This temperature-based dynamic adjustment mechanism enables the storage device to maintain stable performance monitoring parameters in high-temperature operating environments, reducing unnecessary timeout alarms. It should be noted that the above-mentioned time extensions are all exemplary and the present disclosure is not limited thereto.

[0069] In another embodiment, the processor 211 may further extend the target preset time threshold based on the target storage device event and temperature. For example, if both a garbage collection event occurs and the temperature exceeds the threshold, the threshold, which was originally extended by 50% due to the garbage collection, may be extended by an additional 30% to accommodate the further performance degradation of the storage device caused by the high temperature and the execution of the target storage device event.

[0070] In step S240, the adjusted target time threshold is applied and the target storage device event is monitored for completion. Specifically, processor 211 processes another I / O request corresponding to the adjusted target time threshold; monitors another processing time of the other I / O request; and determines whether the other processing time of the other I / O request exceeds the corresponding adjusted target time threshold. While applying the adjusted time threshold, processor 211 continues to use this threshold to evaluate newly received requests of the same type as the target I / O request, effectively reducing potential false alarms during event execution.

[0071] At the same time, the processor 211 continuously monitors the execution status of the target storage device event to check whether the event has been completed. Specifically, the processor 211 may periodically query the relevant status bits in the task status register or set an event completion interrupt notification mechanism to promptly obtain the event completion status.

[0072] At the same time, the processor 211 continuously monitors whether the target storage device event is completed. For example, for a garbage collection event, the processor 211 can determine whether the event is completed by checking the GC_STATUS flag in the task status register (e.g., changing from 1 to 0). For other events, there are also corresponding status flags for monitoring.

[0073] Finally, in step S250, if the target storage device event has been completed, the adjusted target time threshold is restored to the original target preset time threshold. Specifically, once the processor 211 confirms that the target storage device event has ended (such as garbage collection is completed, ECC error correction is completed, etc.), the threshold recovery process is started to gradually adjust the adjusted time threshold back to the original setting value. In detail, this recovery process can be an immediate one-time recovery or a gradual multi-stage recovery. In the gradual recovery implementation, the processor 211 may gradually reduce the threshold value at multiple preset recovery time points, or determine the recovery progress based on the number of successfully executed non-timeout requests, to ensure that the system smoothly transitions back to normal state and avoid performance fluctuations caused by threshold mutations. In this embodiment, when the target storage device event has been completed, the processor 211 triggers a gradual recovery program for the adjusted target time threshold. The gradual recovery program gradually reduces the adjusted target time threshold at multiple preset recovery time points until it is restored to the original target preset time threshold.

[0074] For example, if the adjusted target time threshold for garbage collection completion is 750 milliseconds (originally 500 milliseconds), processor 211 will gradually recover as follows: at T+1 second, reduce the threshold from 750 milliseconds to 650 milliseconds; at T+2 seconds, reduce the threshold from 650 milliseconds to 550 milliseconds; and at T+3 seconds, reduce the threshold from 550 milliseconds to the original 500 milliseconds. This gradual recovery avoids performance fluctuations or false alarms caused by sudden threshold changes.

[0075] Similarly, for temperature-related threshold adjustments, processor 211 determines whether one or more temperature values have fallen below the corresponding preset temperature thresholds. If the temperature has fallen, processor 211 also triggers a progressive recovery process, gradually reducing the adjusted target time threshold based on multiple recovery time points until it returns to the original target preset time threshold. This temperature-sensitive threshold adjustment mechanism enables the storage device to better adapt to performance fluctuations caused by temperature changes.

[0076] In another embodiment, if the target processing time exceeds the corresponding target preset time threshold but no target storage device event is detected, the processor 211 triggers a data cleanup operation. This situation may be due to performance degradation caused by data fragmentation or improper data layout. The data cleanup operation reorganizes the data layout in the storage device through data block adjustment operations, such as through FBO (Flash Blocks Optimization) or XCOPY operations, to improve read speed and overall performance.

[0077] Through the above steps, the memory management method provided by the present disclosure can dynamically adjust the input / output request processing time threshold based on storage device events, improve the accuracy of storage device performance monitoring, and reduce system interference or false alarms caused by frequent triggering of timeout warnings.

[0078] It is worth mentioning that the above steps are mainly executed by the processor 211, but the present disclosure is not limited thereto. The technical solution of the present disclosure has a diversified implementation architecture, allowing for flexible configuration of the execution subject. Specifically, Figure 2 The memory management method process shown can be independently executed by the memory controller 210 (processor 211) on the storage device side, or can be led by the second processor 110 of the host system 10, or completed by the collaborative interaction of the two. In the architecture where the memory controller 210 is the main execution subject, the memory controller 210 independently completes the entire process from monitoring the processing time to judging timeouts, obtaining event information, adjusting thresholds and performing recovery, and only reports necessary status information to the host system 10; in the architecture where the host system 10 is the main execution subject, the second processor 110 judges the timeout situation and calculates the threshold adjustment parameters by reading the log information of the storage device 20, and then sends the adjusted threshold configuration to the storage device 20 through a specific command; in the collaborative execution architecture, the storage device 20 is responsible for basic data collection and threshold application, while the host system 10 is responsible for complex judgment logic and adjustment strategy formulation. This flexible execution subject configuration enables the technical solution disclosed in this disclosure to adapt to different hardware capabilities and system architecture requirements, improving the versatility and adaptability of technical applications.

[0079] Figure 3 FIG. 1 is a timing diagram of dynamically adjusting an input / output request processing time threshold with a memory controller as a main determination component according to an embodiment of the present disclosure.

[0080] In one embodiment, referring to Figure 3 First, in step S301, the host system 10 sends an input / output request to the processor 211. These requests can be different types of operation instructions such as read requests, write requests, or synchronization requests. After receiving these requests, the processor 211 starts to execute the corresponding processing flow.

[0081] Next, in step S302, processor 211 continuously monitors the processing time of the I / O requests. Specifically, processor 211 within processor 211 records the start and completion time of each I / O request and calculates the difference between them, which is the processing time. This continuous monitoring process ensures that the processing time of each I / O request is accurately recorded.

[0082] At the same time, in step S303, processor 211 continuously monitors multiple storage device events that affect processing time. Processor 211 obtains information about various currently executing storage device events, such as garbage collection (GC), ECC error correction, and mapping table refresh, through its internal task status register. These storage device events typically occupy processor 211's computing resources and may extend the processing time of input / output requests. It should be noted that the present disclosure does not limit the order of steps S302 and S303.

[0083] Subsequently, in step S304, the processor 211 sends the received input / output request to the memory module 220 for actual processing, such as performing a data read or write operation. After the memory module 220 completes the corresponding operation, it returns the operation result to the processor 211 in step S305. When the processor 211 receives the operation result, it immediately records the current system time as the completion timestamp and subtracts it from the previously recorded start timestamp to obtain the actual processing time of the input / output request. The processor 211 can use a high-precision internal timer or system clock to record these timestamps to ensure the accuracy of the measurement. For different types of input / output requests (such as reading, writing or synchronization), the processor 211 may use different timing logic to adapt to the characteristics of each type of operation.

[0084] In step S306, the processor 211 determines whether the processing time of the input / output request exceeds the corresponding preset time threshold. The processor 211 compares the calculated processing time with the corresponding threshold preset in the configuration register to determine whether a timeout occurs.

[0085] When the judgment result shows that the target processing time of the target input / output request exceeds the corresponding target preset time threshold, the processor 211 enters the branch process (alt). In step S307, the processor 211 obtains the target information of the corresponding target input / output request. The target information of the target input / output request includes but is not limited to the following information: (1) Request type: such as read request (Read Command), write request (Write Command), synchronization request (Sync Command); (2) Request size: data transfer volume, such as 4KB, 8KB, 16KB, etc.; (3) Request priority: identifies the importance of the request, such as high priority, standard priority or low priority; (4) Request identifier (Request ID): a number used to uniquely identify each request; (5) Request timestamp: records the time when the request is initiated; (6) Request logical address range: logical address information of the read or write operation; (7) Request target location: such as the target storage area, NAND chip number, block number, page number, etc.; and (8) Request context information: such as whether it is part of a batch operation, whether it is a critical system operation, etc.

[0086] Next, in step S308, the processor 211 obtains the event information of the target storage device currently being executed, such as the ongoing garbage collection operation or ECC error correction process. The processor 211 reads the detailed status information of these events from the task status register. The detailed status information of the event may include but is not limited to: (1) event type identifier: such as EVENT_GC_START (0x02), EVENT_GC_END (0x03), etc.; (2) current status of the event: such as in progress (1), completed (0); (3) event start time: the timestamp of the event start; (4) event expected completion time: the system estimated end time of the event; (5) event completion percentage: the progress of the event execution; (6) event impact area: such as the affected storage block, chip or channel information; (7) event priority: indicating the urgency of the event; (8) event resource occupancy: the proportion of system resources occupied by the event; (9) event historical statistics: such as the recent frequency of the event, average execution time, etc.; and (10) event correlation information: other parallel events related to the current event, etc.

[0087] In another embodiment, the event detailed status information may also include specific event parameters, for example, for garbage collection (GC): the source blocks and target blocks involved, the amount of valid data, and the amount of migrated data; for ECC error correction: the number of error bits, the position of the error correction codeword, and the type of error correction algorithm; for mapping table refresh: refresh range, the number of completed entries, and the total number of entries; for temperature-related events: the current temperature value, temperature trend, and heat dissipation status.

[0088] In step S309, the processor 211 records the acquired target information and target storage device events into the buffer memory 214, ROM, or a specific storage circuit unit to form a system log for subsequent analysis and processing. These system log records help understand performance bottlenecks and optimize system operations.

[0089] If the target storage device event is determined to be one of the multiple storage device events, processor 211 enters another conditional branch process. In step S310, processor 211 adjusts the target preset time threshold based on the target storage device event. Specifically, processor 211 retrieves the corresponding adjustment parameter from the preset time threshold adjustment table based on the currently executing event type, applies it to the original preset time threshold, and calculates a new adjusted target time threshold.

[0090] In step S311, processor 211 applies the adjusted target time threshold. Processor 211 stores the new adjusted target time threshold in a configuration register for use in determining the processing time of subsequent I / O requests. This allows a more reasonable time threshold standard to be used during the execution of target storage device events.

[0091] Subsequently, in step S312, processor 211 continuously monitors whether the target storage device event has completed. Processor 211 determines whether the event has ended by checking the status flag of the corresponding event in the task status register. For example, for a garbage collection event, processor 211 may check whether the GC_STATUS flag has changed from 1 to 0 (since the target time threshold is changed in response to the target storage device event, monitoring the target time threshold is necessary).

[0092] When the target storage device event is detected to have completed, the processor 211 restores the adjusted target time threshold to the original target preset time threshold in step S313. This restoration process can be immediate or a gradual restoration strategy can be used, that is, the adjusted target time threshold is gradually reduced at multiple restoration time points until it is fully restored to the original value.

[0093] Through the above-mentioned timing process, the processor 211 realizes the function of dynamically adjusting the input / output request processing time threshold based on storage device events, reducing system interference or false alarms caused by frequent triggering of timeout warnings, especially during events that affect performance such as garbage collection performed by the storage device, and can more accurately reflect the actual performance status of the storage device.

[0094] Figure 4 FIG. 4 is another flow chart of a memory management method according to an embodiment of the present disclosure.

[0095] Reference Figure 4 In one embodiment, Figure 4 Another flow chart of the memory management method disclosed herein for dynamically adjusting input / output request processing time thresholds based on storage device events is shown, showing more detailed processing logic and branching structure.

[0096] In this embodiment, the processor 211 first executes two monitoring tasks in parallel, as shown in steps S410 and S411. In step S410, the processor 211 continuously monitors the processing time of each input / output request received by the storage device. Specifically, the processor 211 records the start time and completion time of each input / output request and obtains accurate processing time data by calculating the time difference. At the same time, in step S411, the processor 211 continuously monitors multiple storage device events that affect the processing time, such as garbage collection, mapping table refresh, ECC error correction, and other system internal activities that may cause the processing time to be extended.

[0097] The parallel execution design of these two monitoring steps enables the processor 211 to simultaneously focus on the performance of the input / output request and the internal state of the system. This design also ensures the continuity of monitoring, and the execution of one monitoring task will not interrupt another monitoring task.

[0098] Next, in step S420, processor 211 determines whether the processing time of each I / O request exceeds a corresponding preset time threshold. In this embodiment, different types of I / O requests may have different preset time thresholds. For example, a read request may be set to 500 milliseconds, a write request may be set to 800 milliseconds, and a synchronization request may be set to 1000 milliseconds. Processor 211 selects the corresponding preset time threshold based on the request type for comparison and determination.

[0099] If the judgment result is "no," meaning the processing time of the current I / O request has not exceeded the corresponding preset time threshold, the processor 211 returns to steps S410 and S411 to continue monitoring subsequent I / O requests and storage device events. If the judgment result is "yes," indicating that the target processing time of the currently processed target I / O request has exceeded the corresponding target preset time threshold, the processor 211 proceeds to step S430. In step S430, the processor 211 obtains the currently executed target storage device event. Specifically, the processor 211 obtains detailed information about the target I / O request by accessing the internal request queue, including data such as the request type, request size, and request identifier. For the currently executed target storage device event, the processor 211 obtains detailed information by accessing the task status register. In this embodiment, the task status register may be configured with multiple status bits, each corresponding to a specific storage device event. For example, the GC_STATUS bit is used to indicate the garbage collection status. When the value is 1, it means that garbage collection is being executed, and when the value is 0, it means that it is not being executed. The ECC_STATUS bit is used to indicate the ECC error correction status. The REFRESH_STATUS bit is used to indicate the mapping table refresh status, etc. By reading the values of these status bits, the processor 211 can accurately determine the currently executing storage device event and obtain detailed information such as its execution stage and impact range.

[0100] Subsequently, in step S440, processor 211 determines whether the target storage device event is one of the multiple storage device events. This determination is intended to confirm whether the currently executing event is a type of event known to affect processing time, such as garbage collection, mapping table refresh, etc. If the determination result is "no," indicating that although the input / output request has timed out, no known events affecting performance have been detected, processor 211 returns to steps S410 and S411 to continue monitoring. In another embodiment, when processor 211 determines that the input / output request has timed out but no known events affecting performance have been detected, processor 211 may perform a data cleanup operation to improve the overall performance of the storage device.

[0101] In another embodiment, when the processor 211 determines that an input / output request has timed out, but no known event that affects performance is currently detected, the processor 211 will record the timeout event and increase the value of the corresponding counter. When the timeout count of such unassociated clear events reaches a preset threshold (for example, more than 10 times in total within an hour), the processor 211 will automatically schedule a data sorting operation during the system idle period. The data sorting operation reorganizes the data layout in the storage device through data block adjustment operations, optimizes data distribution, reduces fragmentation, and thus improves the performance of subsequent read and write operations. By arranging the data sorting operation to be executed during the system idle period, it is possible to avoid further aggravating the current system load, while solving potential performance problems and providing a better execution environment for subsequent input / output requests.

[0102] If the result of step S440 is "yes," indicating that the currently timed-out I / O request is associated with the detected storage device event, the processor 211 proceeds to step S450. In step S450, the processor 211 adjusts the target preset time threshold based on the target storage device event to obtain an adjusted target time threshold, and applies the adjusted target time threshold. The processor 211 applies the adjusted target time threshold to the system configuration, so that subsequent I / O requests of the same type can be judged using the new adjusted target time threshold.

[0103] In this embodiment, the processor 211 uses a preset time threshold adjustment table to obtain corresponding threshold adjustment parameters. The threshold adjustment table records multiple threshold adjustment parameters corresponding to storage device events of different event types and input / output requests of different request types, forming a two-dimensional mapping relationship. For example, the table may include behavioral storage device event types (such as garbage collection, ECC error correction, mapping table refresh, etc.) and columns as input / output request types (such as read, write, synchronization, etc.), with each cell in the table storing the adjustment parameter corresponding to the combination.

[0104] In a specific implementation, the threshold adjustment table can be stored in the ROM of processor 211 as a fixed configuration, or it can be stored in a read-write memory (such as buffer memory 214) to support dynamic updates. In an adaptive implementation, processor 211 will periodically update the parameters in the threshold adjustment table based on historical performance data to adapt to changes in performance characteristics caused by storage device aging or workload changes.

[0105] Processor 211 searches the threshold adjustment table to obtain corresponding adjustment parameters based on the currently detected target storage device event type and target I / O request type, and then applies the parameters to adjust the target preset time threshold. For example, the parameter in the intersection cell of the garbage collection event row and the read request column in the table might be 1.5 or "+250ms," indicating that the preset read request time threshold is extended by 50%, or by 250 milliseconds.

[0106] Next, in step S460, the processor 211 determines whether the target storage device event has been completed. For example, the processor 211 determines whether the event has ended by checking a related flag or status value in a task status register.

[0107] If the determination result of step S460 is “No”, indicating that the target storage device event is still in progress, the processor 211 maintains the adjusted time threshold, continues to monitor the completion status of the target storage device event, and periodically returns to execute step S460.

[0108] If the result of step S460 is "yes," indicating that the target storage device event has completed, processor 211 proceeds to step S470. In step S470, processor 211 restores the adjusted target time threshold to the original target preset time threshold. This restoration can be immediate or gradual, depending on the system configuration. In a gradual restoration strategy, processor 211 gradually reduces the adjusted target time threshold at multiple preset restoration time points until it is fully restored to its original value, thereby preventing system performance fluctuations caused by sudden threshold changes.

[0109] In this embodiment, processor 211 employs a progressive recovery strategy based on the number of successful executions. Specifically, after a target storage device event is completed, processor 211 does not immediately restore the adjusted target time threshold to its original value. Instead, processor 211 sets multiple recovery stages, each associated with a specific number of successful non-timeout I / O request executions. For example, in the first stage, processor 211 reduces the adjusted target time threshold from 800 milliseconds to 700 milliseconds after successfully executing 10 non-timeout I / O requests of the same type. In the second stage, processor 211 further reduces the threshold from 700 milliseconds to 600 milliseconds after successfully executing 15 non-timeout I / O requests of the same type. Finally, in the third stage, processor 211 fully restores the threshold to its original value of 500 milliseconds after successfully executing 20 non-timeout I / O requests of the same type.

[0110] This progressive recovery strategy based on the number of successful executions has several advantages: First, it ensures system stability after the event ends, avoiding a short-term increase in false positives that could result from abruptly restoring the original threshold. Second, by monitoring the number of successful, non-timeout executions, the system can more accurately determine whether storage device performance has truly returned to normal. Finally, this strategy can adapt to system performance fluctuations under different workloads, providing a more adaptive threshold adjustment mechanism. Processor 211 implements this progressive recovery strategy by setting a successful execution counter and updating the counter value each time a non-timeout input / output request is successfully completed.

[0111] After completing the threshold restoration, the processor 211 returns to steps S410 and S411 to continue monitoring new input / output requests and storage device events, forming a complete monitoring-judgment-adjustment-recovery cycle.

[0112] Reference Figure 5A and Figure 5B In one embodiment, the present disclosure provides an implementation scheme that uses the host system processor as the main execution and judgment subject. In the aforementioned embodiment, the processor 211 in the memory controller 210 is used as the main execution subject to implement the function of dynamically adjusting the input / output request processing time threshold based on the storage device event. However, the technical solution of the present disclosure is not limited to this implementation method, and can also be implemented by using the second processor 110 in the host system 10 as the main execution and judgment subject. Figure 5A and Figure 5B Detailed description.

[0113] In this implementation, storage device 20 is primarily responsible for executing input / output requests and recording related performance data and event information, while second processor 110 of host system 10 is responsible for monitoring, determining, and adjusting processing time thresholds. This architectural design is suitable for system environments requiring greater computing power or more flexible control strategies, fully utilizing the host system's computing resources and implementing more complex threshold adjustment algorithms.

[0114] Reference Figure 5A In one embodiment, first, in step S501, the second processor 110 sends initial preset time thresholds for various types of input / output requests to the first processor 211. These initial preset time thresholds may be set to different values according to different types of input / output requests (e.g., read, write, synchronization, etc.). For example, a read request may be set to 500 milliseconds, a write request may be set to 800 milliseconds, and a synchronization request may be set to 1000 milliseconds.

[0115] Next, in step S502, the first processor 211 stores and applies these initial preset time thresholds. The first processor 211 stores these thresholds in an internal configuration register for subsequent determination of whether the input / output request processing time has timed out.

[0116] Then, in step S503, the second processor 110 starts sending actual input / output requests to the first processor 211. These requests may be specific operation instructions such as reading data, writing data, or performing synchronization operations.

[0117] When the first processor 211 receives the input / output request, in step S504, the first processor 211 records the start time of the input / output request. The first processor 211 uses an internal high-precision timer or a system clock to record the precise timestamp of the start of the request processing.

[0118] In step S505, the first processor 211 sends the input / output request to the memory module 220 for processing, such as performing a data read or write operation. After the memory module 220 completes the corresponding operation, it returns the operation result to the first processor 211 in step S506.

[0119] After receiving the operation result, the first processor 211 records the completion time of the input / output request in step S507 and calculates the processing time, ie, the difference between the completion time and the start time, in step S508.

[0120] In step S509, the first processor 211 records the processing time and currently executing storage device events in the buffer memory 214. These records include not only the processing time data of the input / output request, but also various events executed within the storage device during the processing, such as garbage collection, ECC error correction, and mapping table refresh. This information can be saved in log form to provide a data basis for subsequent analysis and adjustment.

[0121] Then, in step S510 , the first processor 211 returns the execution result of the input / output request to the second processor 110 , completing a complete flow of request processing.

[0122] At the same time, the second processor 110 performs two continuous monitoring tasks. In step S511, the second processor 110 continuously monitors the processing time of the input / output request, and in step S512, continuously monitors multiple storage device events that affect the processing time. These monitoring tasks are based on data collected from the storage device.

[0123] To obtain this data, in step S513, the second processor 110 sends a request to the first processor 211 to read the processing time and event information from the buffer memory. After receiving the request, the first processor 211 retrieves the relevant information from the buffer memory 214 in step S514 and returns this information to the first processor 211 in step S515. Finally, in step S516, the first processor 211 transmits the processing time and event information to the second processor 110. It should be noted that steps S511-S515 should be considered a continuous, looping process. That is, the storage device 20 continuously provides processing time and storage device event information to the host system 10, allowing the host system 10 to continuously monitor it.

[0124] Through the above steps, the host system can continuously monitor the performance status and internal events of the storage device, providing necessary data support for subsequent judgment and adjustment.

[0125] Reference Figure 5B In one embodiment, Figure 5B This diagram shows the determination and adjustment phase of dynamically adjusting the input / output request processing time threshold based on the host system processor. Figure 5A The complete process of threshold adjustment based on monitoring data is described in detail.

[0126] In this embodiment, first, in step S517, the second processor 110 determines whether the processing time of the input / output request exceeds the corresponding preset time threshold based on the data obtained from the storage device. The second processor 110 compares the received processing time data with the previously set preset time threshold to determine whether a timeout has occurred.

[0127] If the target processing time of the target I / O request exceeds the corresponding target preset time threshold, the second processor 110 enters a branch process. In step S518, the second processor 110 obtains target information of the target I / O request, such as the request type, request size, request identifier, and other detailed data.

[0128] Next, in step S519, the second processor 110 obtains event information of the target storage device currently being executed, such as an ongoing garbage collection operation or an ECC error correction process, which is obtained from event records previously obtained from the storage device.

[0129] In step S520, the second processor 110 records the target information and target storage device events in the host memory 120 to form a local log record for subsequent analysis and processing. In one embodiment, the specific uses and implementation methods of the host system maintaining these logs include:

[0130] (1) Identifying performance anomaly patterns: The second processor 110 can identify patterns and precursors of storage device performance anomalies by analyzing the temporal patterns, event distribution, and timeout characteristics in the log data. For example, it may be discovered that the frequency of garbage collection events increases significantly after a specific sequence of operations, or that the processing time of a certain type of request is generally longer during a specific time period.

[0131] (2) Adaptive Threshold Optimization: Based on historical log data, the second processor 110 can build mathematical models to predict the impact of different event types on the processing time of different request types. These models can be simple statistical regression models or more complex machine learning algorithms to calculate the optimal threshold adjustment parameters.

[0132] (3) Storage device health status monitoring: By tracking ECC error correction events, read retry times and other indicators over a long period of time, the second processor 110 can evaluate the overall health status of the storage device and predict possible performance degradation or failure risks.

[0133] (4) Workload feature analysis: Log data reveals the system's access patterns and data locality characteristics, and the second processor 110 can optimize the prefetch strategy, cache management, and data layout based on this to improve the overall storage performance.

[0134] (5) Threshold adjustment strategy evaluation: By comparing the timeout rate, false alarm rate and system throughput under different threshold adjustment strategies, the second processor 110 can quantitatively evaluate the effects of various strategies and continuously improve the adjustment algorithm.

[0135] If the target storage device event is determined to be one of the predefined storage device events, the second processor 110 proceeds to another branch of the process. In step S521, the second processor 110 adjusts the target preset time threshold based on the target storage device event. Specifically, the second processor 110 uses a predefined adjustment algorithm to calculate a new target preset time threshold that best suits the current situation, taking into account various factors such as the input / output request type, storage device event type, historical performance data, and system load.

[0136] In step S522, the second processor 110 sends the adjusted target time threshold to the first processor 211. Then, in step S523, the first processor 211 applies the adjusted target time threshold and stores it in the configuration register for use in processing time determination of subsequent input / output requests.

[0137] Next, in step S524, the second processor 110 continuously monitors whether the target storage device event is complete. To obtain the latest event status, in step S525, the second processor 110 sends a request to the first processor 211 to query the target storage device event status. The first processor 211 processes the request and returns the target storage device event status in step S526.

[0138] When it is detected that the target storage device event has been completed, the second processor 110 enters the last branch process.

[0139] In step S527, the second processor 110 formulates a progressive recovery plan for gradually restoring the adjusted target time threshold to the original target preset time threshold. Specifically, the second processor 110 calculates multiple recovery stages and the intermediate threshold corresponding to each stage based on the event completion status, the current system load, and historical performance data. For example, if the current adjusted target time threshold is 800 milliseconds and the original target preset time threshold is 500 milliseconds, the second processor 110 may design three recovery stages: the first stage is restored to 700 milliseconds, the second stage is restored to 600 milliseconds, and the final stage is restored to the original 500 milliseconds.

[0140] In step S528, the second processor 110 sends a phased recovery instruction to the first processor 211, sending only the threshold value for the current phase each time. Specifically, the second processor 110 first sends the intermediate threshold value for the first phase (e.g., 700 milliseconds), then waits for a predetermined condition to be met (e.g., successfully processing 10 non-timed-out requests), and then sends the intermediate threshold value for the second phase (e.g., 600 milliseconds), and so on, until all phases are completed. This phased transmission mechanism ensures that the system can stably adapt to each threshold adjustment.

[0141] In step S529, the first processor 211 receives the intermediate thresholds for each stage and applies them gradually, rather than restoring the system to its original value all at once. After receiving each new intermediate threshold, the first processor 211 updates the time threshold settings in its configuration registers and applies them to subsequent I / O requests. This gradual adjustment mechanism allows the storage device to smoothly transition to its original performance state, avoiding performance fluctuations and false alarms caused by sudden threshold changes.

[0142] It should be noted that steps S527 to S529 are actually executed in a loop multiple times, corresponding to each stage of progressive recovery, until the original target preset time threshold is fully recovered.

[0143] This implementation led by the host system 10 can have multiple advantages: first, the host system usually has stronger computing power and can execute more complex threshold adjustment algorithms; second, in some cases, the host system 10 can integrate performance data from multiple storage devices to achieve global optimization.

[0144] In one embodiment, the present disclosure provides a communication protocol and operational process for setting and adjusting time thresholds between a host system 10 and a storage device 20. Specifically, the second processor 110 sends configuration commands to the first processor 211 via a specific instruction sequence, enabling flexible control of input / output request processing time thresholds. The following details the relevant embodiments.

[0145] In one embodiment, the threshold setting process between the second processor 110 and the first processor 211 includes a specific command sequence and control mechanism. Specifically, the second processor 110 configures the enabled state of the threshold setting function by sending a write cache command.

[0146] Reference Figure 5A When second processor 110 needs to send an initial preset time threshold or an adjusted time threshold to first processor 211, second processor 110 first sends a write cache command containing the control word "Enable threshold set = 0x01." This control word instructs first processor 211 to enter threshold setting mode, preparing to receive and apply subsequently transmitted threshold parameters. In this mode, first processor 211 interprets the received data as time threshold configuration information rather than ordinary data content.

[0147] After receiving the control word "Enable threshold set = 0x01", the first processor 211 switches its internal state to threshold configuration mode and monitors the subsequent received data stream. In this state, subsequent write cache commands will be parsed into specific threshold configuration parameters, such as the processing time threshold for read, write, or synchronization operations.

[0148] After the threshold configuration is complete, the second processor 110 sends a write cache command containing the control word "Enable threshold set = 0x00" to instruct the first processor 211 to exit the threshold setting mode and resume normal command processing. After exiting the configuration mode, subsequent write cache commands will revert to regular data transmission commands instead of threshold configuration commands.

[0149] In another embodiment, if the second processor 110 inserts other non-threshold configuration-related write buffer commands between sending "Enable threshold set = 0x01" and "Enable threshold set = 0x00," it may cause confusion in the internal state of the first processor 211. Specifically, these inserted Write Buffer commands may overwrite the opcodes cached by the first processor 211, causing the threshold configuration command sequence to be interrupted or incorrectly parsed.

[0150] To address this issue, if the second processor 110 needs to send a non-configuration-related write cache command after enabling threshold setting mode, it must first send the control word "Enable threshold set = 0x00" to exit configuration mode. After completing normal command operations, it must resend the control word "Enable threshold set = 0x01" to enter configuration mode. This strict mode switching mechanism ensures the integrity and consistency of the configuration command sequence.

[0151] In one embodiment, the first processor 211 maintains multiple timeout counters to record the timeout times of different types of input / output requests, such as read, write, and synchronization. The values of these counters range from 0x00 to 0xFF and stop increasing when the upper limit of 0xFF is reached.

[0152] When the second processor 110 needs to reset these counters, it can send a control command with the value "Clear timeout count = 0x01." Upon receiving this command, the first processor 211 resets all timeout counters to 0x00 and restarts the timeout count for each request type from zero. This clearing mechanism enables the second processor 110 to obtain accurate timeout statistics at specific points in time (such as a system reset, workload change, or the start of a performance analysis cycle), preventing the accumulation of historical data from affecting analysis accuracy.

[0153] In another embodiment, the Clear timeout count command can carry additional parameters to specify the specific type of request counters to be cleared. For example, parameter 0x01 clears only read request timeout counters, 0x02 clears only write request timeout counters, 0x03 clears only synchronization request timeout counters, and 0xFF clears all types of timeout counters. This refined control mechanism enables the second processor 110 to perform independent performance analysis for specific request types.

[0154] In one embodiment, the second processor 110 may set different processing time thresholds for different types of input / output requests via a write cache command. Specifically, the second processor 110 may configure parameters for a write processing time threshold, a read processing time threshold, and a synchronization processing time threshold, respectively, to set independent timeout thresholds for write, read, and synchronization requests.

[0155] The valid range of these threshold parameter values is 0x00 to 0x7F, with each unit representing a 500-millisecond interval. For example, setting Readthreshold = 0x01 means that the processing time threshold for read requests is 500 milliseconds; setting Writethreshold = 0x02 means that the processing time threshold for write requests is 1000 milliseconds; and setting Syncthreshold = 0x04 means that the processing time threshold for sync requests is 2000 milliseconds. This design supports a wide range of thresholds, for example, from 500 milliseconds (0x01) to 63,500 milliseconds (0x7F), to accommodate different workloads and performance requirements.

[0156] In another embodiment, the second processor 110 may consider the operating status and performance characteristics of the storage device when setting the threshold parameters. For example, for read-intensive applications, a lower read processing time threshold may be set to ensure read performance; for write-intensive applications, a higher write processing time threshold may be set to accommodate performance fluctuations that may occur when writing large amounts of data.

[0157] Specifically, the second processor 110 may adopt the following threshold configuration strategy according to the application scenario:

[0158] 1. For high-performance read applications (such as database queries):

[0159] -Read threshold = 0x01 (500 milliseconds)

[0160] -Write threshold=0x04 (2000 milliseconds)

[0161] -Sync threshold = 0x03 (1500 milliseconds)

[0162] 2. For high-density write applications (such as logging or data backup):

[0163] -Read threshold = 0x02 (1000 milliseconds)

[0164] -Write threshold=0x06 (3000 milliseconds)

[0165] -Sync threshold = 0x04 (2000 milliseconds)

[0166] 3. For mixed-load applications (such as general file systems):

[0167] -Read threshold = 0x02 (1000 milliseconds)

[0168] -Write threshold=0x03 (1500 milliseconds)

[0169] -Sync threshold = 0x03 (1500 milliseconds)

[0170] This targeted threshold configuration can optimize the system's processing strategy for different request types and improve the accuracy and effectiveness of performance monitoring.

[0171] In one embodiment, the communication protocol between the second processor 110 and the first processor 211 includes a specific mechanism to ensure the integrity of the threshold setting instruction sequence. Because the read cache operation depends on the operation code (opcode) issued by the previous write cache command, and different opcodes correspond to different read cache behaviors, the integrity of the instruction sequence is crucial for the correct execution of the threshold setting.

[0172] Specifically, after the second processor 110 sends Enable threshold set = 0x01 to enter threshold setting mode, if a read cache operation is required to retrieve storage device status or configuration results, it must ensure that no other write cache commands are inserted in the middle. If other write cache commands are inserted, they may overwrite the opcode cached by the first processor 211, causing subsequent read cache operations to perform unexpectedly.

[0173] To address this issue, when an interruption in the instruction sequence is detected, the second processor 110 must resend the write cache (Enable threshold set = 0x00) command to update the opcode cached by the first processor 211, ensuring that subsequent read cache operations can be executed correctly. This mechanism ensures state consistency and operational correctness during the execution of complex instruction sequences.

[0174] In another embodiment, the second processor 110 uses atomic operations when sending command sequences related to threshold configuration, ensuring that the entire configuration process is not interrupted by other commands. Specifically, before initiating threshold configuration, the second processor 110 suspends all non-critical input / output requests until the configuration sequence is complete. While this exclusive operation may temporarily affect system performance, it effectively avoids configuration errors caused by interrupted command sequences.

[0175] In one embodiment, the second processor 110 performs a complete threshold configuration process including the following steps:

[0176] 1. Send the Write Buffer (Enable threshold set = 0x01) command to enter the threshold setting mode

[0177] 2. Send the Write Buffer (Clear timeout count = 0x01) command to clear the historical timeout statistics

[0178] 3. Send the Write Buffer (Read threshold = 0x02) command and set the read request threshold to 1000 milliseconds

[0179] 4. Send the Write Buffer (Write threshold = 0x04) command and set the write request threshold to 2000 milliseconds

[0180] 5. Send the Write Buffer (Sync threshold = 0x03) command and set the synchronization request threshold to 1500 milliseconds

[0181] 6. Send the Write Buffer (Enable threshold set = 0x00) command to exit the threshold setting mode

[0182] 7. Send a read cache command to retrieve the current threshold configuration and timeout statistics

[0183] During this process, second processor 110 ensures that no other irrelevant write cache commands are inserted between steps 1 to 6, thus ensuring the integrity of the instruction sequence. If the configuration process needs to be interrupted to perform other write cache operations, second processor 110 will first complete step 6 to exit configuration mode, perform other operations, and then restart from step 1.

[0184] After the configuration process is complete, the first processor 211 will use the newly set threshold parameters to monitor the processing time of various input / output requests and record relevant information when a timeout is detected. This information can be retrieved through subsequent read cache commands for performance analysis and fault diagnosis.

[0185] Through this complete and flexible threshold configuration mechanism, the memory management method provided by the present disclosure can accurately adapt to different application scenarios and performance requirements.

[0186] In one embodiment, the first processor 211 implements a basic error checking mechanism when processing write cache and read cache commands. When the first processor 211 detects a command parameter error (e.g., an invalid threshold setting) or a buffer offset error, it immediately terminates the current operation and returns a check condition status along with the corresponding sense key information. For example, a parameter error returns ILLEGAL REQUEST (sense key 0x05), while a buffer out-of-bounds error returns DATAPROTECT (sense key 0x07).

[0187] After receiving the error notification, the second processor 110 can diagnose the cause of the problem based on the returned perception code information and take corresponding measures, such as correcting the parameter value and resending the command. This simple and effective error handling mechanism ensures the accuracy of the system configuration.

[0188] In another embodiment, the first processor 211 maintains a basic performance event log system that records the processing time of input / output requests and related storage device events. The log adopts a circular buffer design and automatically overwrites the oldest record when the space is exhausted.

[0189] The second processor 110 retrieves this log information by issuing a standard read cache command. Specifically, the second processor 110 specifies a specific opcode and buffer offset, and the first processor 211 responds by returning the corresponding log content. The log data contains basic information such as the input / output request type, processing time, and related event identifiers. The second processor 110 analyzes this data to assess the suitability of the current threshold settings and determine whether adjustments are needed.

[0190] This embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code is executed in a processor, the processor performs the steps of the above-mentioned memory management method. The computer program product can be implemented in hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK).

[0191] Through the above solution, the present disclosure implements a memory management method for dynamically adjusting input / output request processing time thresholds based on storage device events, providing the following multiple technical effects.

[0192] First, this disclosure addresses the inadequacy of traditional fixed-threshold monitoring mechanisms in the face of dynamic changes in storage device performance. By monitoring storage device events (such as garbage collection, mapping table refreshes, and ECC error correction) in real time and adjusting processing time thresholds accordingly, it effectively reduces false alarm rates, avoids unnecessary alerts caused by short-term performance fluctuations, and improves the reliability of storage performance monitoring.

[0193] Secondly, the disclosed progressive threshold recovery mechanism ensures a smooth transition back to normal operation after an event. By gradually reducing the adjusted time threshold at multiple recovery points, or performing phased recovery based on the number of successful executions, performance fluctuations caused by sudden threshold changes are avoided, enhancing the stability of the storage system.

[0194] Furthermore, the decision-making mechanism based on event timeout association counting provided by this disclosure ensures the rationality and necessity of threshold adjustments. By counting the number of event association timeouts within a predetermined time window and comparing it with a preset threshold, adjustment decisions are made, avoiding frequent adjustments caused by occasional events.

[0195] In addition, the technical solution disclosed in the present invention can additionally adjust the time threshold according to temperature monitoring data to adapt to performance changes that may occur in storage devices in high-temperature environments, further enhancing the system's adaptability to environmental changes.

[0196] Finally, this disclosure allows for flexible configuration of the host system and storage device implementation entities. Monitoring, judgment, and adjustment can be performed independently by the storage device processor, or the entire process can be led by the host system processor. This flexible architectural design makes this technical solution widely applicable to different system architectures and application scenarios.

[0197] In summary, the present disclosure implements accurate monitoring of storage device performance, reduces false alarms, and improves system stability through a method for dynamically adjusting the input / output request processing time threshold.

[0198] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, applicable to a storage device equipped with a memory module, characterized in that: The method comprises: Determining, based on a processing time of an input / output request, whether the processing time exceeds a preset time threshold; When a target processing time of a target input / output request exceeds a target preset time threshold, obtaining a currently executed target storage device event; Adjusting the target preset time threshold based on the target storage device event to obtain an adjusted target time threshold; applying the adjusted target time threshold and monitoring whether the target storage device event is completed; and If the target storage device event has been completed, the adjusted target time threshold is restored to the original target preset time threshold.

2. The memory management method according to claim 1, wherein: Before adjusting the target preset time threshold based on the target storage device event and obtaining the adjusted target time threshold, the method further includes: Determining that the same storage device target event in the storage device events reaches a preset triggering number within a predetermined time; and The step of adjusting the target preset time threshold based on the target storage device event to obtain the adjusted target time threshold includes: When the same target storage device event in the storage device events reaches a preset triggering number, the target preset time threshold is adjusted to obtain the adjusted target time threshold.

3. The memory management method according to claim 1, wherein: The step of adjusting the target preset time threshold based on the target storage device event and obtaining the adjusted target time threshold includes: Based on the event type of the target storage device event and the request type of the target input / output request, obtaining a corresponding threshold adjustment parameter from a preset time threshold adjustment table; The threshold adjustment table records a plurality of threshold adjustment parameters corresponding to storage device events of different event types and input / output requests of different request types; Based on the threshold adjustment parameter, extending the target preset time threshold to obtain the adjusted target time threshold; and The adjusted target time threshold is applied to subsequent input / output requests associated with the target input / output request type.

4. The memory management method according to claim 1, wherein: Restoring the adjusted target time threshold to the original target preset time threshold includes: When the target storage device event is completed, triggering a progressive recovery procedure for the adjusted target time threshold, the progressive recovery procedure comprising: A plurality of restoration time points are preset, and the adjusted target time threshold is gradually reduced according to the plurality of restoration time points until the adjusted target time threshold is restored to the original target preset time threshold. The memory management method according to claim 1 , wherein: The method further comprises: obtaining one or more target temperature values from one or more temperature sensors of the storage device; determining whether the one or more target temperature values exceed corresponding one or more target preset temperature thresholds; and When the one or more target temperature values exceed the corresponding one or more target preset temperature thresholds, the target preset time threshold is extended based on the one or more target temperature values to obtain an adjusted target time threshold. The memory management method according to claim 5 , wherein: The method further comprises: Determining whether the one or more target temperature values have fallen below the corresponding target preset temperature threshold; and If the one or more target temperature values have fallen below the corresponding target preset temperature threshold, triggering a progressive recovery procedure for the adjusted target time threshold, the progressive recovery procedure comprising: A plurality of restoration time points are preset, and the adjusted target time threshold is gradually reduced according to the plurality of restoration time points until the adjusted target time threshold is restored to the original target preset time threshold.

7. The memory management method according to claim 1, wherein: Applying the adjusted target time threshold includes: processing another input / output request corresponding to the adjusted target time threshold, and determining another processing time for the another input / output request; and It is determined whether the another processing time of the another input / output request exceeds the corresponding adjusted target time threshold.

8. A memory controller for controlling a storage device equipped with a memory module, characterized in that: The memory controller comprises: a memory interface control circuit for electrically connecting to the memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the storage device to electrically connect to the host system, wherein the processor is configured to: Determining, based on a processing time of an input / output request, whether the processing time exceeds a preset time threshold; When a target processing time of a target input / output request exceeds a target preset time threshold, obtaining a currently executed target storage device event; Adjusting the target preset time threshold based on the target storage device event to obtain an adjusted target time threshold; applying the adjusted target time threshold and monitoring whether the target storage device event is completed; and If the target storage device event has been completed, the adjusted target time threshold is restored to the original target preset time threshold.

9. The memory controller according to claim 8, wherein: Before adjusting the target preset time threshold based on the target storage device event and obtaining the adjusted target time threshold, the processor is further configured to: Determining that the same storage device target event in the storage device events reaches a preset triggering number within a predetermined time; as well as The step of adjusting the target preset time threshold based on the target storage device event to obtain the adjusted target time threshold includes: When the same target storage device event in the storage device events reaches a preset triggering number, the target preset time threshold is adjusted to obtain the adjusted target time threshold.

10. The memory controller according to claim 8, wherein: The processor is further configured to: obtaining one or more target temperature values from one or more temperature sensors of the storage device; determining whether the one or more target temperature values exceed corresponding one or more target preset temperature thresholds; as well as When the one or more target temperature values exceed the corresponding one or more target preset temperature thresholds, the target preset time threshold is extended based on the one or more target temperature values to obtain an adjusted target time threshold.

11. The memory controller according to claim 10, wherein: The processor is further configured to: Determining whether the one or more target temperature values have fallen below the corresponding target preset temperature threshold; and If the one or more target temperature values have fallen below the corresponding target preset temperature threshold, triggering a progressive recovery procedure for the adjusted target time threshold, the progressive recovery procedure comprising: A plurality of restoration time points are preset, and the adjusted target time threshold is gradually reduced according to the plurality of restoration time points until the adjusted target time threshold is restored to the original target preset time threshold.

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