Calculation unit and data processing method

Abstract

The invention provides a calculation unit and a data processing method, and the method comprises the steps: splitting first data, second data and third data according to the bit width, and obtaining a plurality of pieces of first sub-data, a plurality of pieces of second sub-data and a plurality of pieces of third sub-data; and multiplying the first sub-data and the second sub-data which meet the preset relationship to obtain corresponding product terms, and calculating the product terms and the corresponding third sub-data in a summation manner to obtain calculation results. According to the method, the input data is flexibly split according to the bit width to obtain the corresponding sub-data, and the input data does not need to be additionally preprocessed or converted, so that the universality and the applicability of data processing are improved. According to the embodiment of the invention, the split sub-data is processed in parallel, the first sub-data and the second sub-data which meet the preset relation are multiplied, and summation operation is performed on the multiplied data and the third sub-data, so that the calculation time can be shortened, and the data processing speed and efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the fields of data processing and artificial intelligence technology, and in particular to a computing unit and a data processing method. Background Art

[0002] The development of AI (Artificial Intelligence) algorithms has placed higher demands on data processing capabilities, requiring the processor's ALU (Arithmetic Logic Unit) to be compatible with a wide range of data formats to meet the needs of diverse business scenarios. In high-precision scenarios, floating-point data types are widely used; in performance-focused scenarios, short-bit-width integer data (e.g., 8 bits) is favored due to its low resource consumption. Therefore, making the ALU compatible with both floating-point and integer data to achieve the desired PPA (Performance, Power, Area) performance of high-quality circuits remains a pressing technical challenge.

[0003] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to solve one of the technical problems in the related art at least to a certain extent.

[0005] To achieve the above objectives, the first embodiment of the present application provides a computing unit, including:

[0006] a gating module, configured to split the first data, the second data, and the third data according to their bit widths, respectively, to obtain a plurality of first sub-data corresponding to the first data, a plurality of second sub-data corresponding to the second data, and a plurality of third sub-data corresponding to the third data, wherein the bit width of the first sub-data is less than or equal to the bit width of the first data, the bit width of the second sub-data is less than or equal to the bit width of the second data, and the third sub-data is less than or equal to the bit width of the third data;

[0007] a calculation module, configured to respectively multiply the first sub-data and the second sub-data satisfying a preset relationship to obtain corresponding product terms, and respectively calculate the product terms and the corresponding third sub-data in a summation manner;

[0008] An output module is used to output the calculation result.

[0009] To achieve the above-mentioned purpose, a second embodiment of the present application proposes a data processing method, including:

[0010] Splitting the first data, the second data, and the third data according to their bit widths to obtain a plurality of first sub-data corresponding to the first data, a plurality of second sub-data corresponding to the second data, and a plurality of third sub-data corresponding to the third data, wherein the bit width of the first sub-data is less than or equal to the bit width of the first data, the bit width of the second sub-data is less than or equal to the bit width of the second data, and the third sub-data is less than or equal to the bit width of the third data;

[0011] The first sub-data and the second sub-data satisfying the preset relationship are respectively multiplied to obtain corresponding product terms, and the product terms and the corresponding third sub-data are respectively calculated in a summation manner to obtain calculation results.

[0012] To achieve the above objectives, a third embodiment of the present application provides a data processing device, including:

[0013] an acquisition module, configured to split the first data, the second data, and the third data according to bit widths to obtain a plurality of first sub-data corresponding to the first data, a plurality of second sub-data corresponding to the second data, and a plurality of third sub-data corresponding to the third data, wherein the bit width of the first sub-data is less than or equal to the bit width of the first data, the bit width of the second sub-data is less than or equal to the bit width of the second data, and the third sub-data is less than or equal to the bit width of the third data;

[0014] The calculation module is used to respectively multiply the first sub-data and the second sub-data that satisfy a preset relationship to obtain corresponding product terms, and respectively calculate the product terms and the corresponding third sub-data in a summation manner to obtain a calculation result.

[0015] To achieve the above-mentioned purpose, the fourth embodiment of the present application proposes an electronic device, comprising: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement the data processing method proposed in the second embodiment of the present application.

[0016] To achieve the above-mentioned purpose, the fifth aspect embodiment of the present application proposes a non-temporary computer-readable storage medium. When the instructions in the storage medium are executed by the processor of an electronic device, the electronic device can execute the data processing method proposed in the second aspect embodiment of the present application.

[0017] To achieve the above-mentioned purpose, the sixth embodiment of the present application proposes a computer program product, including a computer program, which implements the data processing method proposed in the second embodiment of the present application when executed by a processor in a communication device.

[0018] To achieve the above-mentioned purpose, the seventh aspect embodiment of the present application proposes a chip, which includes the computing unit proposed in the first aspect embodiment of the present application; or the chip includes a processing circuit and an interface circuit, wherein the interface circuit is used to obtain instructions and send the instructions to the processing circuit, and the processing circuit is used to execute the instructions to implement the data processing method proposed in the second aspect embodiment of the present disclosure.

[0019] The present application provides a computing unit and a data processing method.

[0020] In the embodiment of the present application, by flexibly splitting the input data according to the bit width to obtain the corresponding sub-data, it is possible to process data inputs of different bit widths without the need for additional preprocessing or conversion of the input data, thereby improving the versatility and applicability of data processing. By processing the split sub-data in parallel, multiplying the first sub-data and the second sub-data that satisfy the preset relationship, and performing a summation operation with the third sub-data, the calculation time can be shortened and the speed and efficiency of data processing can be improved. Since it can process the smaller bit width data after splitting, the computing unit can have the advantages of smaller area and lower power consumption. Compared with the traditional full-bit width processing method, it can effectively utilize hardware resources, reduce power consumption and cost. By performing multiplication and summation operations on the split sub-data, the computing unit can support a variety of complex operations, thus having a wider range of usage scenarios. By splitting large data into small data for processing, the calculation error caused by the excessive data bit width can be reduced, and since multiple sub-data can be processed in parallel, the delay is effectively reduced, and a higher frequency pipeline can be achieved, making it easier to achieve high-precision calculations.

[0021] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0023] Figure 1 A schematic diagram of the structure of a computing unit provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of the structure of a gating module and a calculation module provided according to an embodiment of the present application;

[0025] Figure 3 A flowchart of a data processing method provided in an embodiment of the present application;

[0026] Figure 4A flowchart of another data processing method provided in an embodiment of the present application;

[0027] Figure 5 A flowchart of another data processing method provided in an embodiment of the present application;

[0028] Figure 6 A schematic diagram of obtaining an accumulated value in a first low-order data interval according to an embodiment of the present application;

[0029] Figure 7 A schematic diagram of obtaining an accumulated value in a first high-order data interval according to an embodiment of the present application;

[0030] Figure 8 A schematic diagram of obtaining an accumulated value in the second low-order data interval according to an embodiment of the present application;

[0031] Figure 9 A schematic diagram of obtaining an accumulated value in the second high-order data interval according to an embodiment of the present application;

[0032] Figure 10 A schematic diagram of multiplying two signed 24-bit integers to obtain an accumulated value according to an embodiment of the present application;

[0033] Figure 11 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0034] Figure 12 A schematic structural diagram of an electronic device provided according to an embodiment of the present application;

[0035] Figure 13 The figure is a schematic diagram of the structure of a chip provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numbers in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible implementations consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0037] The terms used in the embodiments of this application are for the purpose of describing specific embodiments only and are not intended to limit the embodiments of this application. The singular forms "a" and "the" used in the embodiments of this application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0038] It should be understood that although the terms first, second, third, etc. may be used to describe various information in the embodiments of the present application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein may be interpreted as "at the time of" or "when" or "in response to a determination."

[0039] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0040] According to the IEEE standard, the structure of floating-point data includes a sign bit, an exponent bit, and a mantissa bit, where the sign bit is fixed to 1 bit, and different data formats have different exponent bits and mantissa bits. For example, for a 32-bit floating-point number, its structure includes a 1-bit sign bit (sign), an 8-bit exponent bit (exp), and a 23-bit mantissa bit (mantissa). For a 16-bit floating-point number, it includes a 1-bit sign bit, a 5-bit exponent bit, and a 10-bit mantissa bit. The numerical expression of a floating-point number follows a specific formula:

[0041] (-1) sign ×2 Exp-bias ×1.Mantissa

[0042] Among them, (-1) sign It is the sign bit of the floating point number, indicating whether the floating point number is positive or negative. A sign of 0 indicates a positive number, and a sign of 1 indicates a negative number. Exp-biasIt is the exponent part of the floating-point number, which represents the power of the floating-point number. It is usually an exponent with base 2. The exponent needs to subtract a bias value from the value of the exponent code Exp to get the actual exponent value. This bias value is 127 for 32-bit floating-point numbers and 15 for 16-bit floating-point numbers. 1.Mantissa is the mantissa part of the floating-point number. It is a binary decimal used to represent the valid digit part of the floating-point number. The mantissa part actually stored only contains the binary decimal after the most significant bit is 1.

[0043] The floating-point multiplication process is complex and sophisticated, consisting of three stages: sign calculation, exponent calculation, and mantissa calculation. Mantissa calculation requires the implementation of an unsigned integer multiplier with a bit width equal to the mantissa width plus 1. For example, for a 32-bit floating-point number, its mantissa calculation requires a 24-bit unsigned multiplier. In current floating-point multiplication and addition calculations, such as a × b + c, the hardware floating-point calculation process typically follows these steps: the mantissa multiplication of a and b is performed in parallel with the exponential operation of the addend c. The multiplication and exponential results are then added together, and then normalized and rounded to produce a floating-point result that complies with IEEE standards. This process demonstrates the efficiency and accuracy of modern hardware in processing complex floating-point operations.

[0044] Typically, when implementing floating-point multiplication and 32-bit integer multiplication, the ALU can use a single 32-bit multiplier to handle both floating-point mantissa multiplication and integer multiplication. However, directly implementing a single 32-bit multiplier is not very beneficial to the circuit's PPA performance and is difficult to achieve compatibility with other shorter bit-width data formats.

[0045] The following describes a computing unit and a data processing method thereof according to an embodiment of the present application with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic diagram of the structure of a computing unit provided in an embodiment of the present application. Figure 1 As shown, the calculation unit 100 includes: a gating module 10 , a calculation module 20 and an output module 30 .

[0047] The selection module 10 is used to split the input first data, second data and third data into multiple sub-data according to the bit width of the data, and the bit width of these sub-data is less than or equal to the bit width of the input data (including the first data, the second data and the third data). Specifically, the first data is split into multiple first sub-data, the second data is split into multiple second sub-data, and the third data is split into multiple third sub-data.

[0048] The calculation module 20 performs two key operations. First, the calculation module 20 multiplies the first sub-data and the second sub-data that satisfy the preset relationship to obtain corresponding product terms. Second, these product terms are added with the corresponding third sub-data to complete a calculation process.

[0049] The output module 30 is responsible for outputting the calculation results obtained by the calculation module. The calculation unit 100 realizes data splitting through the selection module 10, uses the calculation module 20 to perform parallel multiplication and addition operations, and outputs the results through the output module, forming an efficient and flexible data processing flow.

[0050] It should be noted that, if the first data, the second data and the third data are all floating-point numbers, the bit width of the first sub-data is equal to the first data, the bit width of the second sub-data is equal to the second data, and the bit width of the third sub-data is equal to the third data; if the first data, the second data and the third data are all 32-bit integers (including unsigned 32-bit integers and signed 32-bit integers), the bit widths of the first sub-data, the second sub-data, and the third sub-data that meet the preset relationship can be 24 bits, 9 bits, 8 bits, etc., and the appropriate bit width should be selected according to specific needs.

[0051] Alternatively, as an example, Figure 2 Schematic diagram of the structure of the gating module and the calculation module provided according to the embodiment of the present application.

[0052] like Figure 2 As shown, the input module 10 of the computing unit 100 includes: at least one first multiplexer 101, wherein the first multiplexer 101 is used to split the input first data, second data and third data according to the bit width based on the selection operation. It should be noted that the first multiplexer 101 can select a sub-data from the input data and forward it, and can output different selected sub-data to the same output line. Each first multiplexer 101 can be controlled by an instruction decoder (the instruction decoder is not in the Figure 2 ), wherein the instruction decoder can interpret the operation code in the computer instruction into a corresponding control signal, and the control signal controls the selection operation of each first multiplexer 101.

[0053] In some embodiments, the input module may further employ a data selector, wherein the data selector may select one or more sub-data from a plurality of input data for output for data transmission.

[0054] As an example, the calculation module 20 of the calculation unit includes at least one calculation sub-module, wherein at least one calculation sub-module is used to multiply the first sub-data and the second sub-data in a preset combination to obtain a product term; or, at least one calculation sub-module is used to multiply the first sub-data and the second sub-data in a corresponding combination to obtain a product term, and to calculate in a summation manner based on the product terms obtained by each calculation sub-module in the calculation module and at least two of the required third sub-data.

[0055] It should be noted that the bit widths of the first sub-data, the second sub-data, and the third sub-data can be 24 bits, 9 bits, 8 bits, etc. The preset combination method may include but is not limited to 24 bits × 24 bits, 9 bits × 8 bits, 8 bits × 8 bits, etc. In the present application, the bit widths of the first sub-data, the second sub-data, and the third sub-data are selected according to the input bit widths of the first data, the second data, and the third data. After determining the bit widths of the first sub-data, the second sub-data, and the third sub-data, the bit widths of the first sub-data and the second sub-data can be used to determine the combination method of the product term of the first sub-data and the second sub-data from the preset combination method. For example, if the bit width of the first sub-data is 24 and the bit width of the second sub-data is 24, a 24-bit × 24-bit combination method can be selected. For another example, if the bit width of the first sub-data is 9 and the bit width of the second sub-data is 8, a 9-bit × 8-bit combination method can be selected.

[0056] Furthermore, if Figure 2 As shown, at least one calculation submodule includes a first calculation submodule 210, a second calculation submodule 220, and a third calculation submodule 230, wherein the first calculation submodule 210 generates a first product term based on the data type and the calculation precision; the second calculation submodule 220 generates a second product term based on the data type and the calculation precision; and the third calculation submodule 230 generates a third product term based on the data type and the calculation precision. The first calculation submodule 210 is further configured to, when the first data, the second data, and the third data are all integers, sum the first product term, the second product term, and the third product term to obtain a first sum value, and calculate the first sum value and the required third sub-data in a summation manner;

[0057] And / or, the first calculation submodule 210 is further used to calculate the first product term and the required third sub-data in a summation manner when at least one of the first data, the second data and the third data is a floating-point number, and the second calculation submodule 220 calculates the second product term and the required third sub-data in a summation manner, wherein the bit width of the first sub-data is equal to the first data, the bit width of the second sub-data is equal to the second data, and the bit width of the third sub-data is equal to the third data.

[0058] Furthermore, if Figure 2As shown, the first calculation submodule 210 includes: a first multiplier 211 and a first adder 212, wherein the input end of the first multiplier 211 is connected to the output end of the corresponding first multiplexer 101 in the selection module 10, for generating a first product term; the input end of the first adder 212 is connected to the output end of the first multiplier, the corresponding first multiplexer 101 in the selection module 10, the second calculation submodule 220 and the third calculation submodule 230, wherein the selection module 10 is used to provide the required third sub-data.

[0059] Furthermore, if Figure 2 As shown, the second calculation submodule 220 includes: a second multiplier 221, a second adder 222, a second multiplexer 223 and a first product correction device 224, wherein the input end of the second multiplier 221 is connected to the output end of the corresponding first multiplexer 101 in the gating module 10, for generating a second product term; the input end of the second adder 222 is connected to the first multiplier and the output end of the corresponding first multiplexer 101 in the gating module 10; the first product correction device 224 is used to The second multiplexer 223 converts the unsigned integer multiplication result into a signed multiplication result, or converts the signed integer multiplication result into an unsigned multiplication result; the input end of the second multiplexer 223 is connected to the output end of the first multiplier and the first product correction device 224. When the first data, the second data and the third data are all integers, the second multiplexer 223 transmits the converted integer multiplication result to the first calculation submodule 210. Further, the integer multiplication result is transmitted to the input end of the first adder 212.

[0060] Furthermore, if Figure 2 As shown, the third calculation submodule 230 includes: a third multiplier 231, a third multiplexer 232 and a second product correction unit 233, wherein the input end of the third multiplier 231 is connected to the output end of the corresponding first multiplexer 101 in the selection module 10 to generate a third product term; the second product correction unit 233 is used to convert an unsigned integer multiplication result into a signed multiplication result, or convert a signed integer multiplication result into an unsigned multiplication result; the input end of the third multiplexer 232 is connected to the output ends of the third multiplier 231 and the second product correction unit 233. When the first data, the second data and the third data are all integers, the third multiplexer 232 transmits the converted integer multiplication result to the first calculation submodule 210, and further, the integer multiplication result is transmitted to the input end of the first adder 212.

[0061] It should be noted that the computing unit of the embodiment of the present application can also use a hardware description language for function setting (based on the hardware description language, set the interface, functional logic, connection relationship, timing, frequency, data throughput, etc. of the configuration unit, command parsing unit and first generation unit, and then convert the configuration unit, command parsing unit and first generation unit into a combination of actual circuits, which are converted into a gate-level circuit netlist through an automatic synthesis tool, and then use a dedicated integrated circuit or field programmable gate array automatic layout and routing tool to convert the netlist into a specific circuit wiring structure to be implemented). It can also use an IP core (IP core stands for Intellectual Property, which is a general term for integrated circuit cores with intellectual property cores. It is an integrated circuit design macro module (logic or functional unit) that is gradually separated from the chip design link, repeatedly verified, has specific functions, can be reused, and contains specific core elements (instruction set, functional description, code, etc.). It can be understood as a partially reusable "chip design module") for function setting. It can also use an application-specific integrated circuit (Application Specific Integrated Circuit) An ASIC (Application Specific Integrated Circuit) is a proprietary application program chip designed and manufactured for specific user requirements and specific electronic systems. Its computing power and efficiency can be customized according to algorithm requirements. Any configuration of computing units is applicable, and is not limited to this embodiment, as long as the first data, the second data, and the third data can be split according to bit width to obtain corresponding sub-data, and the first sub-data and the second sub-data corresponding to the bit width are multiplied to obtain corresponding product terms, and the product terms are respectively calculated and summed with the corresponding third sub-data to output the calculation results.

[0062] In particular, according to an embodiment of the present application, the functions described in the above reference structural diagram can be implemented as a chip, which includes a computing unit provided in an embodiment of the present application, and obtains corresponding sub-data by splitting the input data according to the bit width, and obtains product terms by multiplying the sub-data of different bit widths according to the data type and calculation accuracy to perform the required function calculation.

[0063] Figure 3 This is a flow chart of a data processing method provided in an embodiment of the present application. Figure 3 As shown, the data processing method includes but is not limited to the following steps:

[0064] S301, split the first data, the second data and the third data according to the bit width to obtain multiple first sub-data corresponding to the first data, multiple second sub-data corresponding to the second data and multiple third sub-data corresponding to the third data, wherein the bit width of the first sub-data is less than or equal to the bit width of the first data, the bit width of the second sub-data is less than or equal to the bit width of the second data, and the third sub-data is less than or equal to the bit width of the third data.

[0065] In a feasible implementation, first clarify the type and bit width of each input data (including the first data, the second data, and the third data), which usually involves the storage format of the data and the limitations of the hardware platform. Then, according to the requirements of the calculation accuracy, the first data is split into a number of first sub-data. The bit width of each first sub-data should be less than or equal to the bit width of the input first data. The splitting method may involve separating the high bit from the low bit, or performing uneven splitting according to a specific algorithm. As an example, if the first data is a 32-bit unsigned integer, it can be split into two 16-bit sub-data, or four 8-bit sub-data. Similar to the splitting of the first data, the second data is split into a number of second sub-data, and the third data is split into a number of third sub-data.

[0066] It should be noted that the splitting strategy depends on the specific application scenario and requirements. For example, in some cases, the high and low bits may be processed separately; in other cases, the data may need to be split into sub-data with the same bit width. The split sub-data may need to be stored or transmitted in a specific format for subsequent processing. When performing the splitting work, it is necessary to pay attention to data type conversion and overflow issues, especially when the input data is a signed integer, the split sub-data may need to maintain its signedness. The splitting process has a wide range of applications in fields such as data processing, signal processing, and machine learning. For example, in image processing, image data can be split into smaller blocks for processing; in signal processing, signal data can be split into different frequency bands for analysis; in machine learning, feature data can be split into smaller feature subsets for training. The process of splitting the first data, second data, and third data according to bit width should be customized and optimized according to specific needs.

[0067] S302: Multiply the first sub-data and the second sub-data that satisfy a preset relationship to obtain corresponding product terms, and calculate the product terms and the corresponding third sub-data in a summation manner to obtain calculation results.

[0068] In a feasible embodiment, a multiplication operation is performed on each pair of first sub-data and second sub-data with matching bit widths obtained by splitting. If the bit widths of the first sub-data and the second sub-data are the same, they are directly multiplied; if they are different, bit expansion or truncation may be required to match the bit widths, and then the multiplication operation is performed, and the result of the multiplication operation is the product term. Each product term is added to the corresponding third sub-data, where the correspondence generally refers to matching in a certain order or rule. The result of the addition operation is the intermediate result of the function calculation. All intermediate results are added (or combined according to a specific algorithm) to obtain the final function calculation result.

[0069] In summary, the data processing method provided by the embodiment of the present application obtains corresponding sub-data by flexibly splitting the input data according to the bit width, so that data inputs of different bit widths can be processed without additional preprocessing or conversion of the input data, thereby improving the versatility and applicability of data processing. By processing the split sub-data in parallel, multiplying the first sub-data and the second sub-data that satisfy the preset relationship, and performing a sum operation with the third sub-data, the calculation time can be shortened and the speed and efficiency of data processing can be improved. Since it can process smaller bit width data after splitting, the computing unit can have the advantages of smaller area and lower power consumption. Compared with the traditional full-bit width processing method, it can effectively utilize hardware resources, reduce power consumption and cost. By performing multiplication and summation operations on the split sub-data, the computing unit can support a variety of complex mathematical function operations, and thus has a wider range of usage scenarios. By splitting large data (including first data, second data, and third data) into small data (including first sub-data, second sub-data, and third sub-data) for processing, the calculation error caused by excessive data bit width can be reduced. Since multiple sub-data can be processed in parallel, the latency is effectively reduced, and a higher-frequency pipeline can be achieved, making it easier to achieve high-precision calculations. For example, the split sub-data may be more suitable for utilizing existing computing resources. For example, smaller sub-data can more easily adapt to the processor's cache size, thereby reducing the number of cache misses.

[0070] Figure 4 This is a flow chart of another data processing method provided in the embodiment of the present application. Figure 4 As shown, the data processing method includes but is not limited to the following steps:

[0071] S401, if the first data, the second data and the third data are all floating-point numbers, the first data, the second data and the third data are split according to the bit width, and based on the splitting, first sub-data having a bit width equal to the first data, second sub-data having a bit width equal to the second data and third sub-data having a bit width equal to the third data are obtained.

[0072] In a feasible embodiment, if at least one of the first data, the second data, and the third data is a floating-point number, the multiplication and addition result thereof is a floating-point type. Floating-point numbers are typically represented in computers using the IEEE-754 standard, and direct bitwise splitting has no direct mathematical meaning for floating-point numbers. This is because the storage format of floating-point numbers includes a sign bit, an exponent bit, and a mantissa bit, and the float.to_bytes() method in a computer is capable of accurately processing the byte representation of floating-point numbers. Therefore, the bit width of the obtained first sub-data is still equal to the bit width of the first data, the bit width of the obtained second sub-data is still equal to the bit width of the second data, and the bit width of the obtained third sub-data is still equal to the bit width of the third data.

[0073] S402: Determine a product term of the first sub-data and the second sub-data.

[0074] In a feasible implementation, the mantissas of the first sub-data and the second sub-data are first multiplied to obtain a product term. This step can be completed by a multiplier that receives the mantissas of the first sub-data and the second sub-data and outputs their product term.

[0075] S403: Calculate the product term and the corresponding third sub-data in a summation manner to obtain a calculation result.

[0076] In one feasible implementation, the exponent bits of the third sub-data are aligned with the exponent bits of the product of the first and second sub-data before the subsequent addition operation. This alignment process is called addend alignment. The addend alignment and mantissa multiplication are performed in parallel to improve computational efficiency.

[0077] Figure 5 This is a flow chart of another data processing method provided in the embodiment of the present application. Figure 5 As shown, the data processing method includes but is not limited to the following steps:

[0078] S501, if the first data, the second data and the third data are all integers, based on the splitting, a plurality of first sub-data with a smaller bit width than the first data, a plurality of second sub-data with a smaller bit width than the second data and a plurality of third sub-data with a smaller bit width than the third data are obtained.

[0079] For further details on step S501, please refer to the relevant contents in the above embodiment, which will not be repeated here.

[0080] S502 , converting the multiplication operation of the first data and the second data into accumulation of a plurality of product terms, and obtaining an accumulated value, wherein the product terms are obtained by multiplying the first sub-data and the second sub-data that satisfy a preset relationship.

[0081] In a feasible implementation, the multiplication operation of two large data (i.e., first data and second data with relatively large bit widths) is converted into the accumulation of product terms of multiple small data (including multiple first sub-data with a smaller bit width than the first data and multiple second sub-data with a smaller bit width than the second data), and the accumulated value is calculated, including: multiplying each split sub-data one by one and accumulating the results. The key here is to correctly handle the sign bit and carry.

[0082] In a feasible implementation, if the first data, the second data, and the third data are all signed integers, a first low-order data interval corresponding to the multiplication of the first data and the second data can be obtained. As an example, if the first data, the second data, and the third data are all signed 32-bit integers, the first low-order data interval is a low-order 32-bit data interval. It should be noted that the word length of the CPU in a computer is 8 bits, 16 bits, 32 bits, and 64 bits, which refers to the number of binary bits that can be processed at one time. With the development of technology, 8 bits and 16 bits have been eliminated, and the commonly used word lengths today are 32 bits and 64 bits. Therefore, the signed 32-bit integer is related to the word length of the CPU.

[0083] Next, within the first low-order data interval, the first sub-data and the second sub-data satisfying a preset relationship are multiplied to obtain a first product term, a second product term, and a third product term. The first product term is obtained by multiplying two unsigned integers of the first bit width; the second product term and the third product term are both obtained by multiplying an unsigned integer of the second bit width by a signed integer of the third bit width. For example, the first bit width can be 24 bits; the second bit width can be 9 bits; and the third bit width can be 8 bits.

[0084] The first, second, and third product terms are then summed to obtain a first intermediate value; and first reference data is filtered out from the first intermediate value, wherein the first reference data is located within a first high-order data interval obtained by multiplying the first and second data. It should be noted that the sum of the first, second, and third product terms contains a carry, and the multiplication of the first and second data results in a 64-bit data interval. The 33rd bit of data can be filtered out from the first intermediate value and used as the first reference data, wherein the 33rd bit of data is located within the 64-bit data interval.

[0085] It should be supplemented that the first reference data is used to correct the accumulated result of the product terms of the sub-data in the first high-order data interval, wherein the first high-order data interval is obtained by multiplying the first data and the second data.

[0086] Furthermore, if the first data, the second data, and the third data are all signed integers, a first high-order data interval corresponding to the multiplication of the first data and the second data is obtained. As an example, if the first data, the second data, and the third data are all signed 32-bit integers, the first high-order data interval is the high-order 32-bit data interval.

[0087] Within the first upper 32-bit data interval, the first sub-data and the second sub-data satisfying a preset relationship are multiplied to obtain a fourth product term, a fifth product term, and a sixth product term. The fourth product term is obtained by multiplying two signed integers of the fourth bit width; the fifth product term and the sixth product term are both obtained by multiplying a signed integer of the fifth bit width by an unsigned integer of the sixth bit width. As an example, the fourth bit width can be 24 bits; the fifth bit width can be 9 bits; and the sixth bit width can be 8 bits.

[0088] Then, based on the fourth product term, the fifth product term, and the sixth product term, the first operation result is obtained. Furthermore, the fourth product term, the fifth product term, and the sixth product term can be summed to obtain a second intermediate value; then, the inverted value of the first reference data is summed with the second intermediate value to obtain a third intermediate value; and the first high-order component is obtained from the third intermediate value; and then the first reference data and the first high-order component are concatenated to obtain the first operation result. It should be noted that the first high-order component is located within the upper 32-bit data interval, and the bit width of the first high-order component can be 31, that is, the upper 31-bit component of the upper 32-bit data interval.

[0089] It should be noted that since the second intermediate value obtained by summing the fourth product term, the fifth product term, and the sixth product term may lack some low-bit results, resulting in the result of the second intermediate value in the upper 32-bit data interval being 1 less than the correct value, it is possible to obtain first reference data in the lower 32-bit data interval while calculating the upper 32-bit data interval. The second intermediate value is corrected by taking the inverted value of the first reference data, so that the correction process is synchronized with the calculation process of the upper 32-bit data interval, which can avoid the series connection of the calculation logic and the correction logic, thereby reducing the data processing delay. The specific correction method is as follows:

[0090] The first correction method is: if the lowest bit of the upper 32-bit data interval obtained from the second intermediate value is an integer 0, and the first reference data is also an integer 0, that is, the calculation result of the second intermediate value is the same as the actual result of the upper 32-bit data interval, and the first reference data is inverted (to obtain an integer 1) and summed with the second intermediate value to obtain a third intermediate value; from the third intermediate value, obtain the upper 31-bit component; splice the upper 31-bit component with the first reference data to obtain the first calculation result.

[0091] The second correction method is: if the lowest bit of the upper 32-bit data interval obtained from the second intermediate value is the integer 0, and the first reference data is also the integer 1, that is, the calculation result of the second intermediate value is different from the actual result of the upper 32-bit data interval; at this time, the upper 31-bit component of the second intermediate value is the correct value; then the first reference data is inverted (to obtain the integer 0) and summed with the second intermediate value to obtain the third intermediate value; and the upper 31-bit component of the third intermediate value is obtained; the upper 31-bit component of the third intermediate value is spliced with the first reference data to obtain the first calculation result.

[0092] The third correction method is: if the lowest bit of the upper 32-bit data interval obtained from the second intermediate value is the integer 1, and the first reference data is also the integer 0, that is, the calculation result of the second intermediate value is different from the actual result of the upper 32-bit data interval; at this time, the upper 31-bit component of the second intermediate value is missing the carry from the integer 1 to the integer 0; the first reference data can be inverted (to obtain the integer 1) and summed with the second intermediate value to compensate for the missing carry part to obtain the third intermediate value; and the upper 31-bit component of the third intermediate value is obtained; the upper 31-bit component of the third intermediate value is spliced with the first reference data to obtain the first calculation result.

[0093] The fourth correction method is: if the lowest bit of the high 32-bit data interval obtained from the second intermediate value is an integer 1, and the first reference data is also an integer 1, that is, the calculation result of the second intermediate value is the same as the actual result of the high 32-bit data interval; and the first reference data is inverted (to obtain the integer 0) and summed with the second intermediate value to obtain a third intermediate value; and the high 31-bit component of the third intermediate value is obtained; the high 31-bit component of the third intermediate value is spliced with the first reference data to obtain the first calculation result.

[0094] After obtaining the first operation result, the multiplication operation of the first data and the second data is converted into the accumulation of the first product term, the second product term, the third product term and the first operation result, and the accumulated value is obtained.

[0095] As an example, the first data can be represented as int32(a), and the second data can be represented as int32(b), where int is a signed integer. Split int32(a)×int32(b) into the lower 32-bit data interval part and the upper 32-bit data interval split part, respectively. Figure 6 This is a schematic diagram of obtaining the accumulated value in the first low-order data interval according to the embodiment of the present application. Figure 6 As shown, the first low-order data interval, that is, the low 32-bit data interval is split as follows:

[0096] int32(a)×int32(b)={int8(a[31:24]), uint24(a[23:0])}×{int8(b[31:24]), uint24(b[23:0])}

[0097] =uint24(a[23:0])×uint24(b[23:0])+uint24(a[23:0])×int8(b[31:24])<<24+ uint24(b[23:0])×int8(a[31:24])<<24+int8(a[31:24])×int8(b[31:24])<<48

[0098] =uint24(a[23:0])×uint24(b[23:0])+uint9(a[8:0])×int8(b[31:24])<<24+uint15(a[23:9])×int8(b[31:24])<<33+ uint9(b[8:0])×int8(a[31:24])<<24+uint15(b[23:9])×int8(a[31:24])<<33+int8(a[31:24])×int8(b[31:24])<<48

[0099] =uint24(a[23:0])×uint24(b[23:0])+uint9(a[8:0])×int8(b[31:24])<<24+uint9(b[8:0])×int 8(a[31:24])<<24+uint15(a[23:9])×int8(b[31:24])<<33+int23(b[31:9])×int8(a[31:24])<<33

[0100] Among them, uint24(a[23:0])×uint24(b[23:0]) is the first product term, and the first product term is Figure 6 The yellow parallelogram part in the middle; uint9(a[8:0])×int8(b[31:24])<<24 is the second product term, the second product term is Figure 6 The blue parallelogram part in the middle; uint9(b[8:0])×int8(a[31:24])<<24 is the third product term, and the third product term is Figure 6 The green parallelogram part in the middle; uint15(a[23:9])×int8(b[31:24])<<33 and int23(b[31:9])×int8(a[31:24])<<33 are error terms, and the error term is as follows Figure 6The largest parallelogram in the blank area.

[0101] like Figure 6 As shown, the first product term, the second product term and the third product term are summed to obtain a first intermediate value; and the first reference data is screened out from the first intermediate value, wherein the first reference data is the 33rd bit data.

[0102] Furthermore, Figure 7 This is a schematic diagram of obtaining the accumulated value in the first high-order data interval according to the embodiment of the present application. Figure 7 As shown, the first high-order data interval, that is, the high 32-bit data interval is split as follows:

[0103] int32(a)×int32(b)={int24(a[31:8]), uint8(a[7:0])}×{int24(b[31:8]), uint8(b[7:0])}

[0104] =int24(a[31:8])×int24(b[31:8])<<16+int24(a[31:8])×uint8(b[7:0])<<8+int24(b[31:8])×uint8(a[7:0])<<8+uint8(a[7:0])×uint8(b[7:0])

[0105] =int24(a[31:8])×int24(b[31:8])<<16+int9(a[31:23])×uint8(b[7:0])<<23+uint15(a[22:8])

[0106] ×uint8(b[7:0])<<8+int9(b[31:23])×uint8(a[7:0])<<23+uint15(b[22:8])×uint8(a[7:0])<<8+uint8(a[7:0])×uint8(b[7:0])

[0107] =int24(a[31:8])×int24(b[31:8])<<16+int9(a[31:23])×uint8(b[7:0])<<23+int9(b[31:23] )×uint8(a[7:0])<<23+uint15(a[22:8])×uint8(b[7:0])<<8+uint23(b[22:0])×uint8(a[7:0])

[0108] Among them, int24(a[31:8])×int24(b[31:8])<<16 is the fourth product term, and the fourth product term is Figure 7 The orange parallelogram part in the middle; int9(a[31:23])×uint8(b[7:0])<<23 is the fifth product term, and the fifth product term is Figure 7 The blue parallelogram part in the middle; int9(b[31:23])×uint8(a[7:0])<<23 is the sixth product term, and the seventh product term is Figure 7 The green parallelogram part in the middle; uint15(a[22:8])×uint8(b[7:0])<<8 and uint23(b[22:0])×uint8(a[7:0]) are error terms, which are as follows Figure 7 The largest parallelogram in the blank area.

[0109] like Figure 7 As shown, the fourth product term, the fifth product term and the sixth product term are summed to obtain a second intermediate value; the inverted value of the first reference data and the second intermediate value are summed to obtain a third intermediate value; the upper 31-bit component is obtained from the third intermediate value; Figure 6 The obtained first reference data and the high 31-bit component are concatenated to obtain a first operation result.

[0110] Furthermore, if Figure 6 and Figure 7 As shown, int32(a)×int32(b) is converted into the accumulation of the first product term, the second product term, the third product term and the first operation result, and the accumulated value is obtained.

[0111] In another feasible implementation, if the first data, the second data, and the third data are all unsigned integers, a second low-order data interval corresponding to the multiplication of the first data and the second data can be obtained. For example, if the first data, the second data, and the third data are all unsigned 32-bit integers, the second low-order data interval is the low-order 32-bit data interval.

[0112] Next, within the second low-order data interval, the first sub-data and the second sub-data that satisfy a preset relationship are multiplied to obtain a seventh product term, an eighth product term, and a ninth product term. The seventh product term is obtained by multiplying two unsigned integers with a width of the seventh bit; the eighth product term and the ninth product term are both obtained by multiplying an unsigned integer with a width of the eighth bit and an unsigned integer with a width of the ninth bit. For example, the first bit width can be 24 bits; the eighth bit width can be 9 bits; and the ninth bit width can be 8 bits.

[0113] The seventh, eighth, and ninth product terms are then summed to obtain a fourth intermediate value; second reference data is selected from the fourth intermediate value, wherein the second reference data is within the second highest-order data interval obtained by multiplying the first and second data. It should be noted that the sum of the seventh, eighth, and ninth product terms contains a carry, and the multiplication of the first and second data results in a 64-bit data interval. The 33rd bit of data can be selected from the fourth intermediate value and used as the second reference data, wherein the 33rd bit of data is within the 64-bit data interval.

[0114] It should be supplemented that the second reference data is used to correct the accumulated result of the sub-data product terms in the second high-order data interval, wherein the second high-order data interval is obtained by multiplying the first data and the second data.

[0115] Furthermore, if the first data, the second data, and the third data are all unsigned integers, a second high-order data interval corresponding to the multiplication of the first data and the second data is obtained. As an example, as an example, if the first data, the second data, and the third data are all unsigned 32-bit integers, the second high-order data interval is the high-order 32-bit data interval.

[0116] In the second high-order data interval, the first sub-data and the second sub-data satisfying a preset relationship are multiplied to obtain a tenth product term, an eleventh product term, and a twelfth product term, respectively. The tenth product term is obtained by multiplying two unsigned integers with a width of tenth bit; the eleventh product term and the twelfth product term are both obtained by multiplying an unsigned integer with a width of eleventh bit and an unsigned integer with a width of twelfth bit. As an example, the tenth bit width can be 24 bits; the eleventh bit width can be 9 bits; and the twelfth bit width can be 8 bits.

[0117] Then, the second operation result is obtained by multiplying the tenth product term, the eleventh product term, and the twelfth product term. Furthermore, the tenth product term, the eleventh product term, and the twelfth product term can be summed to obtain a fifth intermediate value; then, the inverted value of the second reference data and the fifth intermediate value are summed to obtain a sixth intermediate value; and the second high-order component is obtained from the sixth intermediate value; and then, the second reference data and the second high-order component are concatenated to obtain the second operation result. It should be noted that the second high-order component is located within the upper 32-bit data interval, and the bit width of the second high-order component can be 31, that is, the upper 31-bit component of the upper 32-bit data interval.

[0118] It should be noted that, since the fifth intermediate value obtained by summing the tenth product term, the eleventh product term and the twelfth product term may be missing some low-bit results, resulting in the result of the fifth intermediate value in the upper 32-bit data interval being 1 less than the correct value, before calculating the upper 32-bit data interval, the second reference data is obtained from the lower 32-bit data interval, and the fifth intermediate value is corrected by the inverted value of the second reference data. This operation is the same as the correction process of the second intermediate value by the inverted value of the first reference data, and will not be repeated here.

[0119] After obtaining the second operation result, the multiplication operation of the first data and the second data is converted into the accumulation of the seventh product term, the eighth product term, the ninth product term and the second operation result, and the accumulated value is obtained.

[0120] As an example, the first data can be represented as uint32(a), and the second data can be represented as uint32(b), where uint is an unsigned integer. Split uint32(a)×uint32(b) into the lower 32-bit data interval part and the upper 32-bit data interval split part, respectively. Figure 8 This is a schematic diagram of obtaining an accumulated value in the second low-order data interval according to an embodiment of the present application.

[0121] like Figure 8 As shown, the second low-order data interval, that is, the low 32-bit data interval is split as follows:

[0122] uint32(a)×uint32(b)={uint8(a[31:24]), uint24(a[23:0])}×{uint8(b[31:24]), uint24(b[23:0])}

[0123] =uint24(a[23:0])×uint24(b[23:0])+uint24(a[23:0])×uint8(b[31:24])<<24+u int24(b[23:0])×uint8(a[31:24])<<24+uint8(a[31:24])×uint8(b[31:24])<<48

[0124] =uint24(a[23:0])×uint24(b[23:0])+uint9(a[8:0])×uint8(b[31:24])<<24+uint15(a[23:9])×uint8(b[31:24])<<33+ uint9(b[8:0])×uint8(a[31:24])<<24+uint15(b[23:9])×int8(a[31:24])<<33+uint8(a[31:24])×uint8(b[31:24])<<48

[0125] =uint24(a[23:0])×uint24(b[23:0])+uint9(a[8:0])×uint8(b[31:24])<<24+uint9(b[8:0])×uint8 (a[31:24])<<24+uint15(a[23:9])×uint8(b[31:24])<<33+uint23(b[31:9])×uint8(a[31:24])<<33

[0126] Among them, uint24(a[23:0])×uint24(b[23:0]) is the seventh product term, and the seventh product term is Figure 8 The yellow parallelogram part in the middle; uint9(a[8:0])×uint8(b[31:24])<<24 is the eighth product term, and the eighth product term is Figure 8 The blue parallelogram part in the middle; uint9(b[8:0])×uint8(a[31:24])<<24 is the ninth product term, and the ninth product term is Figure 8 The green parallelogram part in the middle; uint15(a[23:9])×uint8(b[31:24])<<33 and uint23(b[31:9])×uint8(a[31:24])<<33 are error terms, and the error term is as follows Figure 8 The largest parallelogram in the blank area.

[0127] like Figure 8 As shown, the seventh product term, the eighth product term and the ninth product term are summed to obtain a fourth intermediate value; and the second reference data is screened out from the fourth intermediate value, wherein the second reference data is the 33rd bit data.

[0128] Furthermore, Figure 9 This is a schematic diagram of obtaining the accumulated value in the second high-order data interval according to the embodiment of the present application. Figure 9 As shown, the second high-order interval, that is, the high 32-bit data interval is split as follows:

[0129] uint32(a)×uint32(b)={uint24(a[31:8]), uint8(a[7:0])}×{uint24(b[31:8]), uint8(b[7:0])}

[0130] ==uint24(a[31:8])×uint24(b[31:8])<<16+uint24(a[31:8])×uint8(b[7:0])<<8+uint24(b[31:8])×uint8(a[7:0])<<8+uint8(a[7:0])×uint8(b[7:0])

[0131] =uint24(a[31:8])×uint24(b[31:8])<<16+uint9(a[31:23])×uint8(b[7:0])<<23+uint15(a[22:8])×uint8(b[7:0] )<<8+uint9(b[31:23])×uint8(a[7:0])<<23+uint15(b[22:8])×uint8(a[7:0])<<8+uint8(a[7:0])×uint8(b[7:0])

[0132] =uint24(a[31:8])×uint24(b[31:8])<<16+uint9(a[31:23])×uint8(b[7:0])<<23+uint9(b[31:2 3])×uint8(a[7:0])<<23+uint15(a[22:8])×uint8(b[7:0])<<8+uint23(b[22:0])×uint8(a[7:0])

[0133] Among them, uint24(a[31:8])×uint24(b[31:8])<<16 is the tenth product term, and the tenth product term is Figure 9 The orange parallelogram part in the middle; uint9(a[31:23])×uint8(b[7:0])<<23 is the eleventh product term, and the eleventh product term is Figure 9 The blue parallelogram part in the middle; uint9(b[31:23])×uint8(a[7:0])<<23 is the twelfth product term, the twelfth product term is Figure 9 The green parallelogram part in the middle; uint15(a[22:8])×uint8(b[7:0])<<8 and uint23(b[22:0])×uint8(a[7:0]) are error terms, which are as follows Figure 9The largest parallelogram in the blank area.

[0134] like Figure 9 As shown, the tenth product term, the eleventh product term, and the twelfth product term are summed to obtain a fifth intermediate value; the inverted value of the second reference data and the fifth intermediate value are summed to obtain a sixth intermediate value; the upper 31-bit component is obtained from the sixth intermediate value; Figure 8 The obtained second reference data and the high 31-bit component are concatenated to obtain a second operation result.

[0135] Furthermore, if Figure 8 and Figure 9 As shown, uint32(a)×uint32(b) is converted into the accumulation of the seventh product term, the eighth product term, the ninth product term and the second operation result, and the accumulated value is obtained.

[0136] In another feasible embodiment, if the first data, the second data, and the third data are all integers (including signed integers and unsigned integers), the first sub-data and the second sub-data that satisfy a predetermined relationship are multiplied together to obtain a thirteenth product term, a fourteenth product term, and a fifteenth product term, respectively. The thirteenth product term is obtained by multiplying two signed integers with a width of thirteen bits; the fourteenth product term and the fifteenth product term are obtained by multiplying two integers with a width of fourteen bits. For example, the width of the thirteenth bit may be 24 bits; the width of the fourteenth bit may be 8 bits.

[0137] The thirteenth product term is then split into a sixteenth product term and a seventeenth product term, and the fourteenth product term, the fifteenth product term, the sixteenth product term, and the seventeenth product term are multiplied to obtain an accumulated value, wherein the sixteenth product term is obtained by multiplying two fifteenth-bit-wide unsigned integers; and the seventeenth product term is obtained by multiplying two sixteenth-bit-wide signed integers. As an example, the fifteenth bit width may be 8 bits; and the sixteenth bit width may be 8 bits.

[0138] Furthermore, the bit width of the thirteenth product term is divided into a seventeenth-bit width interval, an eighteenth-bit width interval, and a nineteenth-bit width interval. Then, based on the seventeenth-bit width interval, the eighteenth-bit width interval, and the nineteenth-bit width interval, the thirteenth product term is split to obtain a first sub-term, a second sub-term, and two third sub-terms, wherein the first sub-term is the multiplication of two integers in the seventeenth-bit width interval, the second sub-term is the multiplication of two integers in the nineteenth-bit width interval, and the third sub-term is the multiplication of an unsigned integer in the seventeenth-bit width interval and a signed integer in the nineteenth-bit width interval. As an example, the seventeenth-bit width, the eighteenth-bit width, and the nineteenth-bit width can all be 8 bits. Then, the first sub-term is converted to an unsigned integer to obtain the sixteenth product term; the second sub-term is converted to a signed integer to obtain the seventeenth product term. It should be noted that the accumulation of the two third sub-terms may result in a carry, which may cause an error.

[0139] Furthermore, the first low-order data is filtered out from the first third sub-item and used as the third reference data; the second low-order data is filtered out from the second third sub-item and used as the fourth reference data; and the third reference data and the fourth reference data are then ANDed together to obtain the fifth reference data. As an example, the first low-order data and the second low-order data can be bit 1 data.

[0140] Furthermore, the first third sub-item and the second third sub-item are summed to obtain the seventh intermediate value; the inverted value of the fifth reference data and the seventh intermediate value are summed to obtain the eighth intermediate value; then the third high-order component is obtained from the eighth intermediate value, and the fifth reference data and the third high-order component are spliced to obtain the third operation result, wherein the third high-order component can be the high 15-bit component.

[0141] Next, the multiplication operation of the first data and the second data is converted into the accumulation of the fourteenth product term, the fifteenth product term, the sixteenth product term, the seventeenth product term and the third operation result to obtain an accumulated value.

[0142] As an example, the thirteenth product term is based on the multiplication of two signed 24-bit integers and is expressed as follows:

[0143] int24(a 0 uint <<16+a 1 uint )×int24(b 0 uint <<16+b 1 uint )

[0144] =a 1 uint ×b 1 uint +a 0 int ×b 0 int <<32+(b 0 int ×a 1 uint +a 0 int ×b 1 uint )<<16

[0145] Among them, the 24-bit integer is divided into the high 8-bit interval (i.e. the 17th-bit wide interval), the middle 8-bit interval (i.e. the 18th-bit wide interval) and the 8th-bit interval (i.e. the 19th-bit wide interval); a 0 uint <<16, b0 uint <<16 is in the upper 8-bit range; a 1 uint 、b 1 uint Located in the lower 8-bit range; a 0 int ×b 0 int <<32 by a 0 uint <<16 and b 0 uint <<16 is multiplied. Since the sign is usually involved in the high 8-bit interval, the product result is signed; a 0 int ×b 0 int <<32 is the first sub-item; a 1 uint ×b 1 uint is the second sub-item; b 0 int ×a 1 uint <<16 and a 0 int ×b 1 uint <<16 is the third sub-item.

[0146] In the above expression, a 1 uint ×b 1 uint 、a 0 int ×b 0 int <<32 may not meet the requirements of the calculation result, and product correction is required, that is, converting the signed multiplication result into an unsigned multiplication result, or converting the unsigned multiplication result into a signed multiplication result. Furthermore, the multiplication bit width is 8, and we get a 0 int ×b 0 int +[a [7] ×b [6:0] +b [7] ×a [6:0] ]<<8=a 0 uint ×b 0 uint ;a 0 int is an 8-bit interval array, a [7] with a [6:0] is an element of an 8-bit interval array; b 0int is an 8-bit interval array, b [7] with b [6:0] is an element of an 8-bit interval array. The multiplication bit width is 8, and we get a 1 uint ×b 1 uint -[a [7] ×b [6:0] +b [7] ×a [6:0] ]<<8=a 1 int ×b 1 int .

[0147] In the above expression, (b 0 int ×a 1 uint +a 0 int ×b 1 uint )<<16, the bit width of the accumulated item is 17. If the accumulated item is a positive number, it will not affect a 0 int ×b 0 int The result of <<32 will interfere; if the accumulated item is negative, the sign bit of the accumulated item will be 0 int ×b 0 int The result of <<32 will produce an error, so it is necessary to (b 0 int ×a 1 uint +a 0 int ×b 1 uint )<<16 for correction: from b 0 int ×a 1 uint <<16 and a 0 int ×b 1 uint <<16, filter out the first low-order data and the second low-order data; use the first low-order data as the third reference data; use the second low-order data as the fourth reference data; then perform an AND operation on the third reference data and the fourth reference data to obtain the fifth reference data; according to (b 0 int ×a 1 uint +a 0 int ×b 1uint )<<16 to obtain a seventh intermediate value; sum the inverted value of the fifth reference data and the seventh intermediate value to obtain an eighth intermediate value; then obtain the upper 15-bit component from the eighth intermediate value; concatenate the fifth reference data and the upper 15-bit component to obtain a third operation result. Furthermore, the multiplication operation of the first data and the second data is converted into the accumulation of the fourteenth product term, the fifteenth product term, the sixteenth product term, the seventeenth product term, and the result of the third operation to obtain an accumulated value.

[0148] Furthermore, Figure 10 Schematic diagram of multiplying two signed 24-bit integers to obtain an accumulated value according to an embodiment of the present application. Figure 10 As shown, the result of multiplying two signed 24-bit integers is 48 bits wide, where a 0 int ×b 0 int <<32 is the high 16-bit multiplication result. The high 16-bit multiplication result is Figure 10 The yellow parallelogram part in the middle; (b 0 int ×a 1 uint +a 0 int ×b 1 uint )<<16 is the multiplication result of the middle bit, and the multiplication result of the middle bit is Figure 10 The two green parallelogram parts in a 1 uint ×b 1 uint The multiplication result of the lower 16 bits is Figure 10 Medium blue parallelogram part.

[0149] S503: Calculate the accumulated value and the corresponding third sub-data in a summation manner to obtain a calculation result.

[0150] For further introduction to step S503, please refer to the relevant contents in the above embodiment, which will not be repeated here.

[0151] In summary, the data processing method provided by the embodiment of the present application obtains corresponding sub-data by flexibly splitting the input data according to the bit width, so that data inputs of different bit widths can be processed without additional preprocessing or conversion of the input data, thereby improving the versatility and applicability of data processing. By processing the split sub-data in parallel, multiplying the first sub-data and the second sub-data that satisfy the preset relationship, and performing a sum operation with the third sub-data, the calculation time can be shortened and the speed and efficiency of data processing can be improved. Since it can process smaller bit width data after splitting, the computing unit can have the advantages of smaller area and lower power consumption. Compared with the traditional full-bit width processing method, it can effectively utilize hardware resources, reduce power consumption and cost. By performing multiplication and summation operations on the split sub-data, the computing unit can support a variety of complex mathematical operations, and thus has a wider range of usage scenarios. By splitting large data (including first data, second data, and third data) into small data (including first sub-data, second sub-data, and third sub-data) for processing, the calculation error caused by excessive data bit width can be reduced. Since multiple sub-data can be processed in parallel, the latency is effectively reduced, and a higher-frequency pipeline can be achieved, making it easier to achieve high-precision calculations. For example, the split sub-data may be more suitable for utilizing existing computing resources. For example, smaller sub-data can more easily adapt to the processor's cache size, thereby reducing the number of cache misses.

[0152] Figure 11 This is a structural diagram of a data processing device provided in an embodiment of the present application. Figure 11 As shown, the data processing device 1100 includes:

[0153] An acquisition module 1101 is configured to split the first data, the second data, and the third data according to their bit widths to obtain a plurality of first sub-data corresponding to the first data, a plurality of second sub-data corresponding to the second data, and a plurality of third sub-data corresponding to the third data, wherein the bit width of the first sub-data is less than or equal to the bit width of the first data, the bit width of the second sub-data is less than or equal to the bit width of the second data, and the third sub-data is less than or equal to the bit width of the third data;

[0154] The calculation module 1102 is used to respectively multiply the first sub-data and the second sub-data that satisfy a preset relationship to obtain corresponding product terms, and respectively calculate the product terms and the corresponding third sub-data in a summation manner to obtain a calculation result.

[0155] Figure 12 The figure is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present application. Figure 12 The electronic device shown is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0156] like Figure 12 As shown, the electronic device 1200 includes a processor 1201, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1202 or the program loaded from the memory 1206 to the random access memory (RAM) 1203. Various programs and data required for the operation of the electronic device 1200 are also stored in the RAM 1203. The processor 1201, ROM 1202 and RAM 1203 are connected to each other via a bus 1204. An input / output (I / O) interface 1205 is also connected to the bus 1204.

[0157] The following components are connected to the I / O interface 1205: a memory 1206 including a hard disk, etc.; and a communication part 1207 including a network interface card such as a LAN (Local Area Network) card, a modem, etc., and the communication part 1207 performs communication processing via a network such as the Internet; a drive 1208 is also connected to the I / O interface 1205 as needed.

[0158] In particular, according to an embodiment of the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, an embodiment of the present application includes a computer program carried on a computer-readable medium, which contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 1207. When the computer program is executed by the processor 1201, the above-mentioned functions defined in the method of the present application are performed.

[0159] In an exemplary embodiment, a storage medium including instructions is further provided, such as a memory including instructions, and the instructions can be executed by the processor 1201 of the electronic device 1200 to perform the above method. Alternatively, the storage medium can be a non-transitory computer-readable storage medium, such as a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0160] In this application, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. Furthermore, in this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination thereof.

[0161] The present application also proposes a chip, which can be found in Figure 13 Schematic diagram of the chip structure shown. Figure 13 The chip shown includes a processor 1301 and an interface circuit 1302. There may be one or more processors 1301, and one or more interface circuits 1302.

[0162] Optionally, the chip also includes a memory 1303, which is used to store necessary computer programs and data; the interface circuit 1302 is used to receive signals from the memory 1303 and send signals to the processor 1301, and the signals include computer instructions stored in the memory 1303. When the processor 1301 executes the computer instructions, the electronic device executes the data processing method described in the above embodiments of the present disclosure.

[0163] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0164] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A computing unit, characterized in that: include: a gating module, configured to split the first data, the second data, and the third data according to their bit widths, respectively, to obtain a plurality of first sub-data corresponding to the first data, a plurality of second sub-data corresponding to the second data, and a plurality of third sub-data corresponding to the third data, wherein the bit width of the first sub-data is less than or equal to the bit width of the first data, the bit width of the second sub-data is less than or equal to the bit width of the second data, and the third sub-data is less than or equal to the bit width of the third data; a calculation module, configured to respectively multiply the first sub-data and the second sub-data satisfying a preset relationship to obtain corresponding product terms, and respectively calculate the product terms and the corresponding third sub-data in a summation manner; An output module is used to output the calculation result.

2. The calculation unit according to claim 1, characterized in that The input module includes: at least one first multiplexer; The first multiplexer is configured to split the input first data, the second data, and the third data according to bit widths based on a strobe operation.

3. The calculation unit according to claim 1, characterized in that The calculation module includes: at least one calculation submodule; Wherein, at least one of the calculation submodules is configured to multiply the first sub-data and the second sub-data in a preset combination manner to obtain the product term; Alternatively, at least one of the calculation submodules is used to multiply the first sub-data and the second sub-data in a preset combination to obtain a product term, and to perform calculations based on the product terms obtained by each of the calculation submodules in the calculation module and at least two of the required third sub-data in a summation manner.

4. The calculation unit according to claim 3, characterized in that The at least one calculation submodule includes a first calculation submodule, a second calculation submodule, and a third calculation submodule, wherein the first calculation submodule generates a first product term based on the data type and the calculation precision; the second calculation submodule generates a second product term based on the data type and the calculation precision; and the third calculation submodule generates a third product term based on the data type and the calculation precision; The first calculation submodule is further configured to, when the first data, the second data, and the third data are all integers, sum the first product term, the second product term, and the third product term to obtain a first sum value, and calculate the first sum value and the required third sub-data in a summation manner; and / or, The first calculation submodule is further used to calculate the first product term and the required third subdata in a summation manner when the first data, the second data and the third data are all floating-point numbers, and the second calculation submodule calculates the second product term and the required third subdata in a summation manner, wherein the bit width of the first subdata is equal to the first data, the bit width of the second subdata is equal to the second data, and the bit width of the third subdata is equal to the third data.

5. The calculation unit according to claim 4, characterized in that The first calculation submodule includes: a first multiplier and a first adder, wherein the first multiplier is used to generate the first product term; the first adder is connected to the first multiplier, the selection module, the second calculation submodule and the third calculation submodule, wherein the selection module is used to provide the required third sub-data. The calculation unit according to claim 4 , wherein: The second calculation submodule includes: a second multiplier, a second adder, a second multiplexer and a first product correction device, wherein the second multiplier is used to generate the second product term; the second adder is connected to the first multiplier and the selection module; the first product correction device is used to convert an unsigned integer multiplication result into a signed multiplication result, or convert a signed integer multiplication result into an unsigned multiplication result; the second multiplexer is connected to the first multiplier and the first product correction device, and when the first data, the second data and the third data are all integers, the second multiplexer transmits the converted integer multiplication result to the first calculation submodule.

7. The calculation unit according to claim 4, characterized in that The third calculation submodule includes: a third multiplier, a third multiplexer and a second product correction unit, wherein the third multiplier generates the third product term; the second product correction unit is used to convert an unsigned integer multiplication result into a signed multiplication result, or convert a signed integer multiplication result into an unsigned multiplication result; the third multiplexer is connected to the third multiplier and the second product correction unit, and when the first data, the second data and the third data are all integers, the third multiplexer transmits the converted integer multiplication result to the first calculation submodule.

8. A data processing method, characterized in that: include: Splitting the first data, the second data, and the third data according to their bit widths to obtain a plurality of first sub-data corresponding to the first data, a plurality of second sub-data corresponding to the second data, and a plurality of third sub-data corresponding to the third data, wherein the bit width of the first sub-data is less than or equal to the bit width of the first data, the bit width of the second sub-data is less than or equal to the bit width of the second data, and the third sub-data is less than or equal to the bit width of the third data; The first sub-data and the second sub-data satisfying the preset relationship are respectively multiplied to obtain corresponding product terms, and the product terms and the corresponding third sub-data are respectively calculated in a summation manner to obtain calculation results.

9. The data processing method according to claim 8, characterized in that: include: If the first data, the second data, and the third data are all floating-point numbers, first sub-data having a bit width equal to the first data, second sub-data having a bit width equal to the second data, and third sub-data having a bit width equal to the third data are obtained based on the splitting; determining a product term of the first sub-data and the second sub-data; The product term and the corresponding third sub-data are calculated in a summation manner.

10. The data processing method according to claim 8, characterized in that: include: If the first data, the second data, and the third data are all integers, a plurality of first sub-data having a smaller bit width than the first data, a plurality of second sub-data having a smaller bit width than the second data, and a plurality of third sub-data having a smaller bit width than the third data are obtained based on the splitting; converting the multiplication operation of the first data and the second data into accumulation of a plurality of product terms, and obtaining an accumulated value, wherein the product terms are obtained by multiplying the first sub-data and the second sub-data that satisfy a preset relationship; The accumulated value and the corresponding third sub-data are calculated in a summation manner.

11. The data processing method according to claim 10, characterized in that: The converting the multiplication operation of the first data and the second data into accumulation of a plurality of product terms and obtaining an accumulated value includes: If the first data, the second data, and the third data are all signed integers, obtaining a first low-order data interval corresponding to the multiplication of the first data and the second data; In the first low-order data interval, first sub-data and second sub-data satisfying a preset relationship are multiplied to obtain a first product term, a second product term, and a third product term, respectively, wherein the first product term is obtained by multiplying two unsigned integers of the first bit width; the second product term and the third product term are both obtained by multiplying an unsigned integer of the second bit width by a signed integer of the third bit width; summing the first product term, the second product term, and the third product term to obtain a first intermediate value; First reference data is filtered out from the first intermediate values.

12. The data processing method according to claim 11, characterized in that: Also includes: If the first data, the second data, and the third data are all signed integers, obtaining a first high-order data interval corresponding to the multiplication of the first data and the second data; In the first upper 32-bit data interval, the first sub-data and the second sub-data satisfying a preset relationship are multiplied to obtain a fourth product term, a fifth product term, and a sixth product term, respectively. The fourth product term is obtained by multiplying two signed fourth-bit-width integers; and the fifth product term and the sixth product term are both obtained by multiplying a signed fifth-bit-width integer and an unsigned sixth-bit-width integer. A first operation result is obtained according to the fourth product term, the fifth product term, and the sixth product term.

13. The data processing method according to claim 12, characterized in that: Obtaining a first operation result according to the fourth product term, the fifth product term, and the sixth product term includes: summing the fourth product term, the fifth product term, and the sixth product term to obtain a second intermediate value; Summing the inverted value of the first reference data and the second intermediate value to obtain a third intermediate value; Obtaining a first high-order component from the third intermediate value; The first reference data and the first high-order component are concatenated to obtain a first operation result.

14. The data processing method according to claim 12 or 13, characterized in that: Also includes: The multiplication operation of the first data and the second data is converted into the accumulation of a first product term, a second product term, a third product term and a first operation result, and an accumulated value is obtained.

15. The data processing method according to claim 10, characterized in that: The converting the multiplication operation of the first data and the second data into accumulation of a plurality of product terms and obtaining an accumulated value includes: If the first data, the second data, and the third data are all unsigned integers, obtaining a second low-order data interval corresponding to the multiplication of the first data and the second data; In the second low-order data interval, the first sub-data and the second sub-data satisfying a preset relationship are multiplied to obtain a seventh product term, an eighth product term, and a ninth product term, respectively. The seventh product term is obtained by multiplying two unsigned integers of the seventh bit width; the eighth product term and the ninth product term are both obtained by multiplying an unsigned integer of the eighth bit width and an unsigned integer of the ninth bit width. summing the seventh product term, the eighth product term, and the ninth product term to obtain a fourth intermediate value; Second reference data is screened out from the fourth intermediate value.

16. The data processing method according to claim 15, characterized in that: Also includes: If the first data, the second data and the third data are all unsigned integers, obtain a second high-order data interval corresponding to the multiplication of the first data and the second data; In the second high-order data interval, the first sub-data and the second sub-data satisfying a preset relationship are respectively multiplied to obtain a tenth product term, an eleventh product term, and a twelfth product term, wherein the tenth product term is obtained by multiplying two unsigned tenth-bit-wide integers; the eleventh product term and the twelfth product term are both obtained by multiplying an unsigned eleventh-bit-wide integer by an unsigned twelfth-bit-wide integer; A second operation result is obtained by multiplying the tenth product term, the eleventh product term, and the twelfth product term.

17. The data processing method according to claim 16, characterized in that: Obtaining a second operation result according to the tenth product term, the eleventh product term, and the twelfth product term includes: summing the tenth product term, the eleventh product term, and the twelfth product term to obtain a fifth intermediate value; Summing the inverted value of the second reference data and the fifth intermediate value to obtain a sixth intermediate value; Obtaining a second high-order component from the sixth intermediate value; The second reference data and the second high-order component are concatenated to obtain a second operation result.

18. The data processing method according to claim 17, characterized in that: Also includes: The multiplication operation of the first data and the second data is converted into the accumulation of a seventh product term, an eighth product term, a ninth product term and a second operation result, and an accumulated value is obtained.

19. The data processing method according to claim 10, characterized in that: The converting the multiplication operation of the first data and the second data into accumulation of a plurality of product terms and obtaining an accumulated value further includes: If the first data, the second data, and the third data are all integers, the first sub-data and the second sub-data satisfying a preset relationship are multiplied together to obtain a thirteenth product term, a fourteenth product term, and a fifteenth product term, respectively, wherein the thirteenth product term is obtained by multiplying two signed thirteenth-bit wide integers; the fourteenth product term and the fifteenth product term are obtained by multiplying two fourteenth-bit wide integers, wherein the types of the integers include signed integers and unsigned integers; The thirteenth product term is split into a sixteenth product term and a seventeenth product term, and the accumulated value is obtained based on the fourteenth product term, the fifteenth product term, the sixteenth product term, and the seventeenth product term, wherein the sixteenth product term is obtained by multiplying two fifteen-bit-wide unsigned integers, and the seventeenth product term is obtained by multiplying two sixteenth-bit-wide signed integers.

20. The data processing method according to claim 19, characterized in that: The splitting of the thirteenth product term into a sixteenth product term and a seventeenth product term comprises: dividing the bit width of the thirteenth product term into a seventeenth bit width interval, an eighteenth bit width interval, and a nineteenth bit width interval; The thirteenth product term is split based on the seventeenth bit-width interval, the eighteenth bit-width interval, and the nineteenth bit-width interval to obtain a first sub-term, a second sub-term, and two third sub-terms, wherein the first sub-term is the multiplication of two integers in the seventeenth bit-width interval, the second sub-term is the multiplication of two integers in the nineteenth bit-width interval, and the third sub-term is the multiplication of an unsigned integer in the seventeenth bit-width interval and a signed integer in the nineteenth bit-width interval; Perform an unsigned conversion on the first sub-item to obtain the sixteenth product term; perform a signed conversion on the second sub-item to obtain the seventeenth product term.

21. The data processing method according to claim 20, characterized in that: Also includes: Filtering out the first lowest-order data from the first third sub-item, and using the first lowest-order data as the third reference data; Filter out the second lowest-order data from the second and third sub-items, and use the second lowest-order data as the fourth reference data; The third reference data and the fourth reference data are ANDed together to obtain fifth reference data.

22. The data processing method according to claim 21, characterized in that: Also includes: Sum the first third subterm and the second third subterm to get the seventh middle value; summing the inverted value of the fifth reference data and the seventh intermediate value to obtain an eighth intermediate value; Obtaining a third high-order component from the eighth intermediate value; The fifth reference data and the third high-order component are concatenated to obtain a third operation result.

23. The data processing method according to claim 22, characterized in that: Also includes: The multiplication operation of the first data and the second data is converted into the accumulation of a fourteenth product term, a fifteenth product term, a sixteenth product term, a seventeenth product term and a third operation result, and an accumulated value is obtained.

24. A data processing device, characterized in that: include: an acquisition module, configured to split the first data, the second data, and the third data according to bit widths to obtain a plurality of first sub-data corresponding to the first data, a plurality of second sub-data corresponding to the second data, and a plurality of third sub-data corresponding to the third data, wherein the bit width of the first sub-data is less than or equal to the bit width of the first data, the bit width of the second sub-data is less than or equal to the bit width of the second data, and the third sub-data is less than or equal to the bit width of the third data; The calculation module is used to respectively multiply the first sub-data and the second sub-data that satisfy a preset relationship to obtain corresponding product terms, and respectively calculate the product terms and the corresponding third sub-data in a summation manner to obtain a calculation result.

25. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the data processing method according to any one of claims 8 to 23.

26. A non-transitory computer-readable storage medium, characterized in that When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the data processing method according to any one of claims 8 to 23.

27. A computer program product, characterized in that The invention comprises a computer program, which implements the data processing method according to any one of claims 8 to 23 when executed by a processor.

28. A chip, characterized in that: The chip includes a computing unit as described in any one of claims 1 to 7; or the chip includes one or more interface circuits and one or more processors; the interface circuit is used to receive a signal from a memory of an electronic device and send the signal to the processor, the signal including a computer instruction stored in the memory, and when the processor executes the computer instruction, the electronic device executes the data processing method described in any one of claims 8 to 23.

Images