Instruction scheduling method and device, chip and storage medium

Abstract

The invention discloses an instruction scheduling method and device, a chip and a storage medium, and is applied to the technical field of instruction scheduling. The method comprises the following steps: acquiring an instruction packet, wherein the instruction packet comprises a plurality of instructions; a current instruction is decoded to determine the instruction type of the current instruction, and the current instruction is any instruction in the instruction packet; and under the condition that the instruction type is a mode switching instruction, switching an instruction scheduling mode to enable the instruction scheduling mode to be matched with the mode switching instruction. Dynamic switching of different instruction scheduling modes can be achieved, the most suitable instruction scheduling mode is intelligently determined according to the current processor state and the characteristics of the instruction to be executed, and balance between execution efficiency and energy consumption is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of instruction scheduling, and more specifically, to an instruction scheduling method, device, chip, and non-volatile computer-readable storage medium based on multiple instruction scheduling modes. Background Art

[0002] As one of the key technologies to improve computer performance, instruction scheduling has been widely used in compiler optimization and operating system task scheduling.

[0003] Existing instruction scheduling methods either have excellent programming flexibility and low energy consumption, but have low parallelism in data-intensive task processing, resulting in low execution efficiency, such as the sequential superscalar mode; or have high parallelism in instruction execution, but high programming complexity, poor flexibility and high energy consumption, and cannot effectively balance the execution efficiency and energy consumption of instruction execution, such as the very long instruction word mode. Summary of the Invention

[0004] The embodiments of the present application provide an instruction scheduling method, device, chip and non-volatile computer-readable storage medium based on multiple instruction scheduling modes, which can intelligently switch the most suitable instruction scheduling mode according to the current processor state and the characteristics of the instructions to be executed, so that each instruction is scheduled and executed under a more appropriate instruction scheduling mode, achieving a balance between execution efficiency and energy consumption.

[0005] The instruction scheduling method based on multiple instruction scheduling modes of the embodiment of the present application includes obtaining an instruction package, which includes multiple instructions; decoding a current instruction to determine the instruction type of the current instruction, and the current instruction is any instruction in the instruction package; when the instruction type is a mode switching instruction, switching the instruction scheduling mode so that the instruction scheduling mode matches the mode switching instruction.

[0006] In some embodiments, the instruction scheduling mode includes an in-order superscalar mode and a very long instruction word mode.

[0007] In some embodiments, the switching instruction scheduling mode includes: modifying the value of the instruction scheduling mode field of the control and status register corresponding to the instruction scheduling mode so that the value corresponds to the operand of the mode switching instruction; wherein the instruction scheduling mode field is used to control the current instruction scheduling mode.

[0008] In some embodiments, the instruction scheduling mode includes a first scheduling mode and a second scheduling mode. When the value of the instruction scheduling mode field is a first preset value, the current instruction scheduling mode is the first scheduling mode. When the value of the instruction scheduling mode field is a second preset value, the current instruction scheduling mode is the second scheduling mode.

[0009] In some embodiments, the first scheduling mode includes an in-order superscalar mode, and the second scheduling mode includes a very long instruction word mode.

[0010] In some embodiments, each code segment corresponds to an instruction portion in the instruction stream, and the mode switching instruction exists. The mode switching instruction corresponding to the code segment is generated based on the instruction scheduling mode corresponding to the code segment.

[0011] In some embodiments, decoding the current instruction to determine the instruction type of the current instruction includes: decoding the current instruction to determine the various fields in the current instruction; matching the various fields of the current instruction with various preset instruction formats to determine the target instruction format corresponding to the current instruction, the target instruction format being any of the preset instruction formats, and the preset instruction format corresponding to the instruction type; determining the instruction type of the current instruction based on the target instruction format.

[0012] In some embodiments, the instruction scheduling mode includes a sequential superscalar mode, and the method further includes: before distributing the target instruction of the current processing cycle, determining whether the target register corresponding to the target instruction is locked; if so, delegating the target instruction to the next processing cycle for processing, and re-entering the step of determining whether the register corresponding to the target instruction is locked before distributing the target instruction of the current processing cycle; if not, distributing the target instruction and locking the target register.

[0013] In some embodiments, each register has a corresponding lock flag, and locking the target register includes: updating the lock flag corresponding to the target register to a target value, where the target value is determined based on an execution cycle of the target instruction.

[0014] In some implementations, the method further includes: updating a lock flag corresponding to each of the registers when the current processing cycle ends.

[0015] In some embodiments, each of the registers has a corresponding lock identifier, and determining whether the target register corresponding to the target instruction is locked includes: determining whether the lock identifier corresponding to the target register is a third preset value; wherein, if the lock identifier corresponding to the target register is the third preset value, the target register is not locked; and if the lock identifier corresponding to the target register is not the third preset value, the target register is locked.

[0016] In some embodiments, the instruction scheduling mode includes a very long instruction word mode. In the very long instruction word mode, the functions corresponding to each instruction in the instruction package are matched with each preset functional unit, and each instruction is distributed to each preset functional unit for parallel execution.

[0017] In some embodiments, the instruction scheduling mode includes a very long instruction word mode, and the method further includes:

[0018] Obtain the function corresponding to each instruction in the instruction package, each function corresponding to one or more preset functional units; based on the function corresponding to each instruction, divide each instruction into one or more instruction groups, and the functions corresponding to each instruction in the same instruction group are the same; fetch instructions in each instruction group to obtain multiple instructions to be distributed, and the number of instructions to be distributed corresponding to each instruction group is less than or equal to the number of preset functional units corresponding to the instruction group; and distribute each instruction to be distributed to its corresponding preset functional unit.

[0019] The instruction scheduling device for multiple instruction scheduling modes of the embodiment of the present application includes an acquisition module, a decoding module, and a switching module. The acquisition module is used to acquire an instruction packet, wherein the instruction packet includes multiple instructions; the decoding module is used to decode the current instruction to determine the instruction type of the current instruction, wherein the current instruction is any instruction in the instruction packet; and the switching module is used to switch the instruction scheduling mode when the instruction type is a mode switching instruction, so that the instruction scheduling mode matches the mode switching instruction.

[0020] The chip of the embodiment of the present application can be used to execute instructions of the instruction scheduling method based on multiple instruction scheduling modes described in any of the above embodiments.

[0021] The non-volatile computer-readable storage medium of an embodiment of the present application includes a computer program. When the computer program is executed by a processor, the processor executes the instruction scheduling method based on multiple instruction scheduling modes described in any of the above embodiments.

[0022] The instruction scheduling method, scheduling device, chip, and computer-readable storage medium based on multiple instruction scheduling modes disclosed in the present application insert a mode switching instruction into an instruction packet and execute the mode switching instruction to switch the instruction scheduling mode. This allows subsequent instructions to select an appropriate instruction scheduling mode for scheduling and execution based on the instruction type and characteristics. Different instruction scheduling modes have different trade-offs between execution efficiency and energy consumption. Therefore, dynamically switching instruction scheduling modes based on instruction type and characteristics can achieve a balance between instruction execution efficiency and energy consumption.

[0023] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0025] Figure 1 is a first flow chart of an instruction scheduling method based on multiple instruction scheduling modes in certain embodiments of the present application;

[0026] Figure 2 is a second flow chart of an instruction scheduling method based on multiple instruction scheduling modes in certain embodiments of the present application;

[0027] Figure 3 is a third flow chart of an instruction scheduling method based on multiple instruction scheduling modes in certain embodiments of the present application;

[0028] Figure 4 is a fourth flow chart of an instruction scheduling method based on multiple instruction scheduling modes in certain embodiments of the present application;

[0029] Figure 5 is a fifth flow chart of an instruction scheduling method based on multiple instruction scheduling modes in certain embodiments of the present application;

[0030] Figure 6 is a sixth flow chart of an instruction scheduling method based on multiple instruction scheduling modes in certain embodiments of the present application;

[0031] Figure 7 is a seventh flow chart of an instruction scheduling method based on multiple instruction scheduling modes in certain embodiments of the present application;

[0032] Figure 8 Schematic diagram of a sequential superscalar instruction scheduling mechanism of an instruction scheduling method based on multiple instruction scheduling modes in certain embodiments of the present application;

[0033] Figure 9 is an eighth flow chart of an instruction scheduling method based on multiple instruction scheduling modes in certain embodiments of the present application;

[0034] Figure 10 is a ninth flow chart of an instruction scheduling method based on multiple instruction scheduling modes in certain embodiments of the present application;

[0035] Figure 11 Schematic diagram of a very long instruction word mode instruction scheduling mechanism of an instruction scheduling method based on multiple instruction scheduling modes in certain embodiments of the present application;

[0036] Figure 12 is a schematic diagram of a module of a scheduling device according to certain embodiments of the present application;

[0037] Figure 13 It is a schematic diagram of the connection status of a non-volatile computer-readable storage medium and a processor in certain embodiments of the present application. DETAILED DESCRIPTION

[0038] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of the present application, and should not be understood as limiting the embodiments of the present application.

[0039] To facilitate understanding of this application, the following are explanations of the terms that appear in this application:

[0040] 1. Instruction Scheduling: Instruction scheduling is the process of sequencing operations within a program block or procedure to efficiently utilize processor resources. The goal of instruction scheduling is to improve instruction-level parallelism by rearranging instructions, allowing programs to run more efficiently on CPUs with an instruction pipeline. A prerequisite for optimizing instruction scheduling is that the CPU hardware supports instruction parallelism; otherwise, instruction scheduling is meaningless.

[0041] Current instruction execution typically relies solely on sequential superscalar scheduling or very long instruction words (VLIWs). Sequential superscalar scheduling accurately utilizes hardware, resulting in lower energy consumption, but suffers from limited parallelism. VLIWs, on the other hand, increase parallelism and execution efficiency by increasing software complexity. However, they suffer from high energy consumption, strong assembler dependency, poor compatibility, and difficulty in program development. A single instruction scheduling model cannot effectively balance execution efficiency, energy optimization, and programming flexibility.

[0042] In order to solve the above technical problems, an embodiment of the present application provides an instruction scheduling method based on multiple instruction scheduling modes.

[0043] The following is a detailed description of the instruction scheduling method based on multiple instruction scheduling modes of the present application:

[0044] See also Figure 1 , an embodiment of the present application provides an instruction scheduling method based on multiple instruction scheduling modes, the instruction scheduling method based on multiple instruction scheduling modes includes:

[0045] Step 011: Obtain an instruction packet, which includes multiple instructions;

[0046] As you can understand, the program execution process is generally divided into five stages: preprocessing, compilation, assembly, linking, and execution. Assembly is the process of translating the assembly code files generated during the compilation stage into target machine instructions. The assembler converts the assembly instructions into machine code that can be directly executed by the machine.

[0047] Specifically, when executing instruction scheduling, the first step is to fetch instructions. To improve execution efficiency, multiple instructions can be fetched at once to generate an instruction packet. Based on the instructions in the instruction packet, each instruction in the instruction packet is scheduled so that each instruction is executed in parallel as much as possible to improve instruction execution efficiency.

[0048] Step 012: Decode the current instruction to determine the instruction type of the current instruction, where the current instruction is any instruction in the instruction packet;

[0049] Optionally, decoding may be decoding and analyzing the instruction to obtain key information such as the type, operand, and operation code of the instruction, and generating a corresponding control signal based on the decoding result of the instruction.

[0050] Optionally, the instruction type includes basic instruction types such as R-type (register-to-register operation), I-type (short immediate and memory load operation), S-type (memory store operation), B-type (conditional jump operation), U-type (long immediate operation), and J-type (unconditional operation). In addition to the basic instruction types, extended instructions can also be added, and the newly added extended instructions can be customized based on the instruction format.

[0051] Specifically, during instruction execution, after completing the instruction fetch operation, the current instruction needs to be decoded. After decoding the current instruction, information such as the function code, operands, and operation code of the current instruction can be obtained through decoding analysis. Based on the combination of the operands and function code, the instruction type of the current instruction can be determined.

[0052] Step 013: When the instruction type is a mode switching instruction, switch the instruction scheduling mode so that the instruction scheduling mode matches the mode switching instruction.

[0053] Optionally, the mode switch instruction may be a newly added extended instruction. When the mode switch instruction is executed, the instruction scheduling mode may be switched, for example, switching the original instruction scheduling mode from sequential superscalar mode to very long instruction word mode, or vice versa.

[0054] Specifically, when it is determined that the current instruction type is a mode switch instruction, it indicates that the instruction scheduling mode needs to be switched, and the scheduling of subsequent instructions is based on the switched instruction scheduling mode. The current mode switch instruction is executed to switch the instruction scheduling mode, and the switched instruction scheduling mode matches the mode switch instruction.

[0055] For example, if the original instruction scheduling mode is sequential superscalar mode, and the current instruction is a mode switch instruction, and the target instruction scheduling mode of the mode switch instruction is VLIW mode, then the mode switch instruction is executed to switch the instruction scheduling mode from sequential superscalar mode to VLIW mode. Instructions following the mode switch instruction are then scheduled based on VLIW mode.

[0056] Optionally, the instruction scheduling mode may include a sequential superscalar mode and a very long instruction word mode. In the sequential superscalar mode, programming is flexible, but dependencies between instructions and data hazards may prevent some instructions from being executed in parallel, thereby limiting the performance improvement of the superscalar processor. Energy consumption is lower, but the execution efficiency is relatively low. In the very long instruction word mode, the operations of multiple instructions are packaged into a very long instruction word, and multiple operation fields can be executed in parallel, which improves the parallel processing capability of the processor. However, there are also problems such as complex programming, poor flexibility, and high power consumption.

[0057] The embodiment of the present application inserts a mode switching instruction into the instruction packet, and switches the instruction scheduling mode through the mode switching instruction, so that the scheduling of the instruction can select the appropriate instruction scheduling mode according to the type and characteristics of the instruction. For example, when the execution efficiency of the instruction is not high but the energy consumption is low, the instruction scheduling mode can be switched to the sequential superscalar mode through the mode switching instruction. When the execution efficiency of the instruction is high but the energy consumption is not high, the instruction scheduling mode can be switched to the very long instruction word mode through the mode switching instruction. In this way, based on the type and characteristics of the instruction, the instruction scheduling mode is dynamically switched through the mode switching instruction, achieving a balance between instruction efficiency and energy consumption.

[0058] In some embodiments, the instruction scheduling modes include an in-order superscalar mode and a very long instruction word mode.

[0059] Optionally, the instruction scheduling mode allocates operations in processes or program blocks in the ready state to the processor for execution according to a certain strategy. Instruction scheduling mode plays an important role in the computer field, especially in improving instruction-level parallelism and computer processing efficiency.

[0060] Optionally, the sequential superscalar mode increases the execution speed of instructions by repeatedly setting multiple functional components and allowing these functional components to work simultaneously. In fact, it increases processor performance at the expense of increased hardware resources. A processor using superscalar technology can issue multiple instructions in one clock cycle.

[0061] Optionally, the VLIW mode improves processor execution efficiency by packing the operations of multiple instructions into a very long instruction word. A VLIW contains multiple operation fields, each of which can correspond to a corresponding functional component. These operation fields include multiple arithmetic unit control instruction fields that can be executed in parallel, several memory control instruction fields, and other operation control fields.

[0062] Specifically, the instruction scheduling mode includes a sequential superscalar mode and a very long instruction word mode, and the mode switching instruction can switch the instruction scheduling mode to the sequential superscalar mode or the very long instruction word mode.

[0063] See also Figure 2 In some embodiments, step 013 "when the instruction type is a mode switching instruction, switching the instruction scheduling mode so that the instruction scheduling mode matches the mode switching instruction" is implemented by step 0131, which is described in detail below.

[0064] Step 0131: Modify the value of the instruction scheduling mode field of the control and status register corresponding to the instruction scheduling mode so that the value corresponds to the operand of the mode switching instruction; wherein the instruction scheduling mode field is used to control the current instruction scheduling mode.

[0065] Optionally, the Control and Status Register (CSR) is a set of special registers within the processor that reflect and control the processor's current state and execution mechanism. The CSR can be modified using dedicated instructions following the copy-modify-writeback principle. The Control and Status Register stores an instruction dispatch mode field, which identifies the currently running instruction dispatch mode. The instruction dispatch mode can be switched by changing the preset value in the status register.

[0066] Specifically, to specify the instruction scheduling mode, an instruction scheduling mode field is stored in a preset control and status register to identify the current instruction scheduling mode. When a mode switch instruction is executed, the value of the instruction scheduling mode field in the control and status register is modified based on the operand and opcode of the mode switch instruction so that the value of the scheduling mode field corresponds to the instruction scheduling mode to be switched. During the subsequent instruction dispatch process, the instruction scheduling mode of the subsequent instruction is determined based on the value stored in the control and status register.

[0067] For example, in some embodiments, if the value of the instruction scheduling mode field in the control and status register is 0, it indicates that the current instruction scheduling mode is the sequential superscalar mode. If the value of the instruction scheduling mode field in the control and status register is 1, it indicates that the current instruction scheduling mode is the very long instruction word mode.

[0068] If the value of the instruction scheduling mode field in the current control and status register is 0, and the current instruction type is a mode switch instruction, and based on the operand and opcode of the mode switch instruction, the value of the mode switch instruction that needs to be modified is 1, then the value of the instruction scheduling mode field in the control and status register is modified to 1. When subsequent instructions are distributed, based on the value of the scheduling mode field in the control and status register being 1, it is determined that the scheduling mode to be executed by the subsequent instructions is the very long instruction word mode. Until the value of the scheduling mode field in the control and status register is modified, the subsequent instructions reselect the instruction scheduling mode to be executed.

[0069] In this way, a field representing the instruction scheduling mode is stored in the control and status register, and the field of the instruction scheduling mode is modified through the mode switching instruction to realize dynamic switching of the instruction scheduling mode, so that each instruction can be scheduled and executed according to the corresponding instruction scheduling mode, combining the advantages of different instruction scheduling modes to achieve a balance between energy consumption and execution efficiency.

[0070] In some embodiments, the instruction scheduling mode includes a first scheduling mode and a second scheduling mode. When the value of the instruction scheduling mode field is a first preset value, the current instruction scheduling mode is the first scheduling mode. When the value of the instruction scheduling mode field is a second preset value, the current instruction scheduling mode is the second scheduling mode.

[0071] Specifically, when scheduling instructions, the instruction scheduling mode includes a first scheduling mode and a second scheduling mode, and the instruction scheduling mode is determined according to the instruction scheduling mode field in the control and status register. To determine the current instruction scheduling mode, the instruction scheduling mode field in the control and status register can be read. If the value of the instruction scheduling mode field is a first preset value, the current instruction scheduling mode is determined to be the first scheduling mode, and the instruction scheduling mode is switched to the first scheduling mode; if the value of the instruction scheduling mode field is a second preset value, the current instruction scheduling mode is determined to be the second scheduling mode, and the instruction scheduling mode is switched to the second scheduling mode.

[0072] In some embodiments, the first scheduling mode comprises an in-order superscalar mode and the second scheduling mode comprises a very long instruction word mode.

[0073] Optionally, the sequential superscalar mode can be a technology that divides an instruction into several cycles to achieve overlapping processing of multiple instructions, thereby improving the utilization of processor components, supporting instruction-level parallelism, and can execute multiple instructions without mutual dependencies simultaneously in a single clock cycle.

[0074] Optionally, VLIW mode can bundle the operations of multiple instructions into a single, very long instruction to reduce memory accesses. VLIW mode divides the instruction word into multiple independent control fields, each of which directly and independently controls a corresponding functional component, allowing the processor to execute multiple instructions within a single clock cycle, thereby achieving parallel execution of instructions.

[0075] Specifically, the first scheduling mode can be a sequential superscalar mode. When the instruction scheduling mode field in the control and status register is a first preset value, the current scheduling mode is determined to be a sequential superscalar mode. When the instruction scheduling mode field in the control and status register is a second preset value, the current scheduling mode is determined to be a very long instruction word mode.

[0076] For example, see Figure 3 , a schematic diagram of an instruction scheduling mode in some embodiments, wherein the preprocessing includes inserting a mode switch instruction into the instruction packet, and the mode switch instruction can switch the instruction scheduling mode to a sequential superscalar mode or a very long instruction word mode.

[0077] In some embodiments, the instruction packet is obtained by fetching instructions from an instruction stream generated when a program is running. The program includes multiple code segments, and each code segment has a corresponding instruction scheduling mode.

[0078] Alternatively, an instruction stream can be a sequence of instructions generated during program execution. Program execution goes through various stages, including preprocessing, compilation, assembly, and linking. After the compilation and assembly stages, the program's code segments are translated into instructions that can be directly executed by the machine. The sequence of instructions formed by these instructions is the instruction stream.

[0079] Optionally, the instruction packet can be obtained by fetching one or more instructions from the instruction stream. During the execution of the instruction stream, first, an instruction is fetched from the instruction stream, and one or more instructions are fetched from the instruction stream to generate the instruction packet.

[0080] Specifically, during program execution, a program goes through stages such as compilation and assembly to generate an assembly language program file, which contains multiple code segments. To improve operational efficiency, a corresponding instruction scheduling mode is selected based on the function and type of each code segment for scheduling and execution. Each code segment generates an instruction stream during execution. During instruction scheduling, instructions are fetched from the instruction stream, which can be one or more. Each instruction fetched generates an instruction packet, and each instruction in the instruction packet is scheduled for execution according to the corresponding instruction scheduling mode.

[0081] In some embodiments, each code segment corresponds to an instruction portion in the instruction stream, and a mode switching instruction exists. The mode switching instruction corresponding to the code segment is generated based on the instruction scheduling mode corresponding to the code segment.

[0082] Optionally, the mode switching instruction may be an instruction generated according to the instruction scheduling mode required by the code segment, and executing the mode switching instruction may switch the instruction scheduling mode to the instruction scheduling mode required by the code segment.

[0083] Specifically, since each code segment has a corresponding instruction scheduling mode, a mode switching instruction is included in the instruction stream corresponding to each code segment to ensure that the instructions corresponding to each code segment are scheduled and executed according to the corresponding instruction scheduling mode. The mode switching instruction is generated based on the instruction scheduling mode required by the code segment. After the mode switching instruction is executed, the instruction scheduling mode is switched to the instruction scheduling mode required by the code segment.

[0084] For example, the instruction scheduling modes corresponding to code segment A and code segment B are sequential superscalar mode and very long instruction word mode respectively. Based on the mode switching instruction generated by code segment A, the instruction scheduling mode can be switched to sequential superscalar mode, and the instruction stream corresponding to code segment A can be scheduled and executed in sequential superscalar mode; based on the mode switching instruction generated by code segment B, the instruction scheduling mode can be switched to very long instruction word mode, and the instruction stream corresponding to code segment B can be scheduled and executed in very long instruction word mode.

[0085] In this way, the instruction scheduling mode is switched according to the generated mode switching instruction, so that each code segment can be scheduled and executed according to the corresponding instruction scheduling mode, thereby improving the operation efficiency.

[0086] See also Figure 4 In some embodiments, step 012 “decoding the current instruction to determine the instruction type of the current instruction” is implemented by steps 0121 to 0123, which are described in detail below.

[0087] Step 0121: Decode the current instruction and determine each field in the current instruction;

[0088] Step 0122: Matching each field of the current instruction with each preset instruction format to determine a target instruction format corresponding to the current instruction, where the target instruction format is any preset instruction format corresponding to the instruction type.

[0089] Step 0123: Based on the target instruction format, determine the instruction type of the current instruction.

[0090] Optionally, decoding may be parsing and translating instructions so that a computer can correctly execute these instructions. During the decoding process, the instructions may be broken down into multiple parts, such as an operation code, an address, a register number, etc.

[0091] Optionally, the instruction format may be the basic structure and function of the instruction, typically including operands, operation codes, operation function codes, source operand registers and destination registers, etc. Different instruction types correspond to different instruction formats.

[0092] Specifically, each instruction type corresponds to a different instruction format, and the instruction type of the current instruction can be determined based on the instruction format of the current instruction. The current instruction is decoded to determine various fields in the current instruction, such as the instruction code, function code, and operation code.

[0093] Based on the location and function of each field in the instruction, the instruction format is matched with the preset instruction format to determine the instruction format that matches the current instruction. The matching instruction format is the target instruction format. The preset instruction format corresponds to the instruction type. Therefore, when the target instruction format of the current instruction is determined, the instruction type of the current instruction can be determined based on the target instruction format.

[0094] For example, see Figure 5 , diagram of instruction formats corresponding to different instruction types. Instruction formats can have register-register operations (R type (such as Figure 5 R-type)) instructions, register-immediate operations (I-type (such as Figure 5 I-type)) instructions, data storage operations (S-type (such as Figure 5S-type)) instructions, immediate operations (U-type (such as Figure 5 The U-type)) instruction in .

[0095] Among them, opcode represents the operation code, funct represents the function code, rs represents the source operand register, rd represents the destination register, and imm represents the immediate value.

[0096] If the fields of the current instruction include an immediate value, an operation code, and a destination register, and the positions of the fields are the same as those of a U-type instruction, then it can be determined that the instruction type of the current instruction is a U-type instruction.

[0097] In this way, by decoding the current instruction, obtaining the instruction code, function code, operation code and other information of the current instruction, and matching them with the preset instruction format, the instruction type of the current instruction can be determined.

[0098] See also Figure 6 In some embodiments, the instruction scheduling mode includes a sequential superscalar mode, and the scheduling method further includes steps 014 to 016, which are described in detail below.

[0099] Step 014: Before distributing the target instruction of the current processing cycle, determine whether the target register corresponding to the target instruction is locked;

[0100] Step 015: If yes, the target instruction is transferred to the next processing cycle for processing, and the process again enters the step of determining whether the register corresponding to the target instruction is locked before distributing the target instruction of the current processing cycle;

[0101] Step 016: If not, dispatch the target instruction and lock the target register.

[0102] Optionally, instruction distribution may be a process of performing instruction scheduling in a sequential superscalar mode, in which instructions in a ready state are allocated to different execution units to achieve parallel execution of instructions.

[0103] Specifically, before dispatching the target instruction of the current processing cycle, it is first necessary to obtain the resource status and determine resource availability. Dependencies may also exist between instructions. For example, the execution result of one instruction needs to be used as input for the next instruction. For example, if instruction A stores the result in register X, and instruction B reads data from register X, instruction B depends on instruction A. Dependencies limit the parallel execution of instructions and the efficiency of pipeline design. When there are dependencies between instructions, these instructions must be executed in a specific order. Ignoring the dependencies between instructions may cause the program to produce incorrect results or abnormal behavior.

[0104] Before dispatching the target instruction of the current processing cycle, the target registers required by the target instruction, including operand registers and destination registers, are known based on the decoded information. A determination is made as to whether the target register corresponding to the target instruction is locked. If the target register is locked, it indicates that the target register is occupied by another instruction. If the target register is unlocked, it indicates that the target register is not occupied by another instruction and can be allocated to the current target instruction.

[0105] If the target register is locked (that is, occupied), it means that the target register cannot be allocated to the target instruction in the current cycle, and therefore the target instruction cannot be dispatched in the current cycle. The target instruction is then processed in the next processing cycle. Before dispatching the target instruction in the next processing cycle, the target register of the target instruction is checked again to determine whether the target register is locked. The target instruction is dispatched only when the target register is unlocked.

[0106] If the target register is not locked, it means that the target register is not occupied, so the target instruction can be dispatched in the current processing cycle. To dispatch the target instruction, the target register of the target instruction is locked to indicate the target instruction's occupation of the target register and avoid read-write conflicts. The locked target registers include the operand register and destination register corresponding to the target instruction.

[0107] For example, dependencies between instructions can be determined using a register lock flag method. A lock flag is set for each register. When an instruction is in the execution phase, the target register of the instruction is locked. When the target instruction is dispatched, the number of cycles required to execute the target instruction is stored as the lock flag of the target register, and the target register is locked. If the lock flag of the target register is a non-zero positive integer, it means that the target register is locked. If the lock flag of the target register is 0, the target register is not locked.

[0108] In this way, by judging whether the target register of the target instruction is locked and determining whether the target register can be distributed, the dependency judgment between instructions is realized, and the dependency relationship between instructions is resolved, so that each instruction can be executed in sequence and the execution efficiency is improved.

[0109] See also Figure 7 In some embodiments, each register has a corresponding lock flag, and step 016 "locking the target register" is implemented by step 0161, which is described in detail below.

[0110] Step 0161: Update the lock flag corresponding to the target register to a target value, where the target value is determined based on the execution cycle of the target instruction.

[0111] Optionally, the lock flag may be a flag indicating a lock state of a register, and each register has a corresponding lock flag for indicating the lock state of each register.

[0112] Specifically, if the target instruction can be dispatched in the current processing cycle, the target register of the target instruction is locked to ensure the normal execution of the target instruction. However, the number of cycles required for the execution of each instruction is different. During the instruction execution cycle, the target register should be in a locked state by the target instruction. The number of cycles required for instruction execution is the number of cycles required for the instruction register. Therefore, when the target register is locked, the target value of the lock flag is determined to be the number of execution cycles required for the target instruction based on the execution cycle required by the target instruction, and the lock flag of the target register is updated to the target value.

[0113] For example, see Figure 8 , an embodiment of an instruction scheduling mechanism in sequential superscalar mode.

[0114] Among them, R0 to Rn are all registers, and a lock tag (Lock-Tag) is set for each register from R0 to Rn. When the value of Lock_Tag is zero, it means that the corresponding register is unlocked. The instruction packet decoding module can decode the instruction, obtain the source register and destination register corresponding to the instruction, and determine the source register and destination register corresponding to the instruction as the target register. The detection module can detect the lock tag corresponding to the target register to determine whether the target register is locked.

[0115] Before dispatching instruction 1, the lock flag corresponding to the target register corresponding to instruction 1 is first detected. If the lock flag corresponding to the target register corresponding to instruction 1 is not zero, it means that the target register corresponding to instruction 1 is locked and instruction 1 cannot be dispatched. If the lock flag corresponding to the target register corresponding to instruction 1 is zero, it means that the target register corresponding to instruction 1 is not locked and instruction 1 can be dispatched. Instruction 1 enters the dispatch unit, and then instruction 2 is detected to determine whether instruction 2 can be dispatched.

[0116] When instruction 1 is dispatched, the target register corresponding to instruction 1 is locked, and the Lock-Tag corresponding to the target register of instruction 1 is updated to the number of cycles required to execute instruction 1. All lock flags are updated at the end of each cycle. If the lock flag value is non-zero, the lock flag is decremented by 1 each cycle. When the lock flag value is zero, it indicates that the corresponding register is unlocked and the lock flag remains unchanged. When the register is locked, the lock flag is updated.

[0117] In this way, the lock status of the target register is indicated by the lock flag, so that the target register of the target instruction is not occupied by other instructions during the execution cycle, thereby ensuring the normal execution of the instruction.

[0118] Please refer again Figure 7 In some embodiments, step 0162 is also included, which is described in detail below.

[0119] Step 0162: When the current processing cycle ends, the lock flags corresponding to the respective registers are updated.

[0120] Specifically, each register has a corresponding lock flag. The target register of the instruction that can be dispatched needs to be locked, and the lock flag corresponding to the target register is determined as the number of execution cycles required for the instruction. The lock flags corresponding to registers other than the target register also need to be updated. Therefore, at the end of the current processing cycle, the lock flags of all registers are updated to maintain the correctness of the lock flags corresponding to all registers.

[0121] Optionally, at the end of each execution cycle of the target instruction, the lock flag corresponding to each register is updated, and the lock flag with a value other than 0 is decremented by 1, while the lock flag with a value of 0 remains 0.

[0122] Specifically, after the execution of the instruction is completed, it is necessary to unlock the locked state of each locked target register, that is, to mark each target register as unlocked. Therefore, for the target register in the locked state, its lock mark is a non-zero positive integer. At the end of each cycle, the target register is occupied by one cycle, that is, the lock mark number is reduced by 1. For the register that is not in the locked state, its lock mark is 0. If it is still not locked at the end of the cycle, its lock mark remains. In this way, after the execution of the instruction is completed, the lock mark of the corresponding target register is 0, and the lock mark of 0 indicates that the register is in the unlocked state.

[0123] In this way, at the end of each cycle, the lock flag corresponding to each register is updated, which can better maintain the lock status of each register and is beneficial to the register lock status judgment in the instruction distribution stage.

[0124] See also Figure 9 In some embodiments, each register has a corresponding lock flag. Step 014 "before distributing the target instruction of the current processing cycle, determining whether the target register corresponding to the target instruction is locked" is implemented by steps 0141 to 0142, which are described in detail below.

[0125] Step 0141: Determine whether the lock flag corresponding to the target register is a third preset value;

[0126] Step 0142: When the lock flag corresponding to the target register is a third preset value, the target register is not locked; when the lock flag corresponding to the target register is not the third preset value, the target register is locked.

[0127] Optionally, the third preset value is used to indicate that the corresponding register is in an unlocked state.

[0128] Specifically, based on the target register corresponding to the target instruction, a lock flag corresponding to the target register is obtained, and it is determined whether the lock flag corresponding to the target register is a third preset value.

[0129] When the lock flag corresponding to the target register is the third preset value, it indicates that the target register is not locked. When the lock flag corresponding to the target register is not the third preset value, it indicates that the target register is locked.

[0130] For example, when the lock flag is updated to the number of instruction execution cycles during instruction distribution, the third preset value may be 0. If the lock flag is 0, it indicates that the target register is not occupied, that is, in an unlocked state. If the lock flag is not 0, it indicates that the target register is locked.

[0131] In some embodiments, the instruction scheduling mode includes a very long instruction word mode. In the very long instruction word mode, the functions corresponding to each instruction in the instruction package are matched with each preset functional unit respectively, and each instruction is distributed to each preset functional unit for parallel execution.

[0132] Optionally, the preset functional unit may be a preset hardware unit that can execute different functions, and corresponding instructions may be executed through the preset functional unit.

[0133] Specifically, in the very long instruction word mode, register dependency check is not performed, each instruction in the instruction packet corresponds to a different function, and each instruction packet is distributed to the corresponding functional unit for execution according to the function corresponding to each instruction, and each functional unit is executed in parallel.

[0134] See also Figure 10 In some embodiments, the instruction scheduling mode includes a very long instruction word mode, and the instruction scheduling method further includes steps 017 to 020, which are described in detail below.

[0135] Step 017: Obtain the function corresponding to each instruction in the instruction packet, each function corresponds to one or more preset functional units;

[0136] Step 018: Based on the functions corresponding to the instructions, the instructions are divided into one or more instruction groups, and the instructions in the same instruction group have the same functions;

[0137] Step 019: fetch instructions from each instruction group to obtain a plurality of instructions to be dispatched, wherein the number of instructions to be dispatched corresponding to each instruction group is less than or equal to the number of preset functional units corresponding to the instruction group;

[0138] Step 020: Distribute each instruction to be distributed to its corresponding preset functional unit.

[0139] Optionally, the preset functional unit is a hardware unit that performs different operating functions, such as an integer calculation functional unit, a floating-point calculation functional unit, a conditional jump functional unit, etc.

[0140] Specifically, an instruction packet is obtained by fetching instructions from the instruction stream. The instruction packet contains multiple instructions, each of which has a corresponding function that is executed by a corresponding preset functional unit. Based on the function of each instruction, the instructions in the instruction packet are grouped. Instructions with the same function are grouped into the same instruction group, while instructions with different functions are not grouped into the same instruction group.

[0141] Since there are various types of preset functional units and the number of preset functional units of each type is fixed, when distributing instructions, instructions should be taken from each instruction group according to the type and number of preset functional units to obtain multiple instructions to be distributed, so as to maximize the parallelism of multiple preset functional units.

[0142] The number of instructions extracted from each instruction group should be less than or equal to the number of pre-set functional units corresponding to the instruction group. If the number of instructions in an instruction group is less than the number of pre-qualified functional units, all instructions in the instruction group may be extracted as instructions to be distributed. If the number of instructions in an instruction group is greater than the number of pre-qualified functional units, instructions equal to the number of pre-qualified functional units may be extracted from the instruction group as instructions to be distributed.

[0143] For example, the preset functional units are an integer calculation functional unit, a floating-point calculation functional unit, and a conditional jump functional unit, and the number of each functional unit is two. In the instruction packet, there are two integer calculation instructions, two floating-point calculation instructions, and two conditional jump instructions, so there are three instruction groups. Two instructions are taken from each of the integer calculation instruction group, the floating-point calculation instruction group, and the conditional jump instruction group, for a total of six instructions to be distributed. The six instructions to be distributed are distributed to the corresponding preset functional units, so that the six preset functional units are executed in parallel.

[0144] For another example, if the instruction packet contains three integer calculation instructions, two floating-point calculation instructions, and one conditional jump instruction, then two instructions are taken from the integer calculation instruction group, two instructions are taken from the two floating-point calculation instruction groups, and one instruction is taken from the floating-point calculation instruction group, for a total of five instructions to be dispatched. The five instructions to be dispatched are respectively dispatched to the corresponding preset functional units, so that the five preset functional units are executed in parallel, and one floating-point calculation functional unit is idle.

[0145] For another example, see Figure 11 , a very long instruction word mode instruction scheduling mechanism in one embodiment.

[0146] Among them, the parallelism detection module and the functional unit detection module can detect each instruction in the instruction packet, obtain the function corresponding to each instruction, and obtain the type and quantity of each preset functional unit. The preset functional units include the integer unit (A), the floating point unit (F), and the memory access unit (D). For most applications, the number of integer instructions is the largest, followed by floating point instructions, memory access instructions, and jump instructions are relatively small. In other words, it is more likely to distribute more instructions in one cycle in the order of A, F, and D to achieve greater instruction parallelism, so two functional units of A, F, and D are preset. The distribution unit can select instructions corresponding to the type and quantity of the preset functional unit type from the instruction packet as instructions to be distributed, and distribute each instruction to be distributed to each preset functional unit.

[0147] In this way, by obtaining the function of each instruction in the instruction packet and combining it with the type and number of pre-set functional units, the instructions to be distributed are selected. This ensures that each pre-set functional unit is as idle as possible, increases the parallelism of multiple pre-set functional units, and thus improves the utilization rate of each pre-set functional unit and significantly improves the execution efficiency of instructions.

[0148] See also Figure 12 In order to better implement the instruction scheduling method based on multiple instruction scheduling modes according to the embodiment of the present application, the embodiment of the present application further provides an instruction scheduling device 10. The instruction scheduling device 10 may include an acquisition module 11, a decoding module 12, and a switching module 13. The acquisition module 11 is used to acquire an instruction packet, which includes multiple instructions; the decoding module 12 is used to decode the current instruction to determine the instruction type of the current instruction; and the switching module 13 is used to switch the instruction scheduling mode when the instruction type is a mode switching instruction, so that the instruction scheduling mode matches the mode switching instruction.

[0149] In some embodiments, the switching module 13 is also used to change the value of the instruction scheduling mode field of the control and status register corresponding to the instruction scheduling mode so that the value corresponds to the operand of the mode switching instruction; wherein the instruction scheduling mode field is used to control the current instruction scheduling mode.

[0150] In some embodiments, the decoding module 12 is also used to decode the current instruction and determine the various fields in the current instruction; match the various fields of the current instruction with various preset instruction formats to determine the target instruction format corresponding to the current instruction, the target instruction format is any preset instruction format, and the preset instruction format corresponds to the instruction type; based on the target instruction format, determine the instruction type of the current instruction.

[0151] In some embodiments, the instruction scheduling mode includes a sequential superscalar mode, and the instruction scheduling device 10 also includes a locking module 14, which is used to determine whether the target register corresponding to the target instruction is locked before distributing the target instruction of the current processing cycle; if so, the target instruction is delegated to the next processing cycle for processing, and the step of determining whether the register corresponding to the target instruction is locked before distributing the target instruction of the current processing cycle is entered again; if not, the target instruction is distributed and the target register is locked.

[0152] In some embodiments, the locking module 14 is further configured to update the locking flag corresponding to the target register to a target value, where the target value is determined based on an execution cycle of the target instruction.

[0153] In some embodiments, the instruction scheduling device 10 further includes an updating module 15 for updating the lock flag corresponding to each register when the current processing cycle ends.

[0154] In some embodiments, the locking module 14 is further used to determine whether the locking identifier corresponding to the target register is a third preset value; wherein, when the locking identifier corresponding to the target register is the third preset value, the target register is not locked; when the locking identifier corresponding to the target register is not the third preset value, the target register is locked.

[0155] In some embodiments, the instruction scheduling device 10 further includes a distribution module 16, which is used to obtain the function corresponding to each instruction in the instruction package, each function corresponding to one or more preset functional units; based on the function corresponding to each instruction, each instruction is divided into one or more instruction groups, and each instruction in the same instruction group has the same function; fetch instructions in each instruction group to obtain multiple instructions to be distributed, and the number of instructions to be distributed corresponding to each instruction group is less than or equal to the number of preset functional units corresponding to the instruction group; and distribute each instruction to be distributed to its corresponding preset functional unit.

[0156] The above text describes the scheduling device 10 from the perspective of functional modules in conjunction with the accompanying drawings. The functional modules can be implemented in hardware form, can be implemented by instructions in software form, or can be implemented by a combination of hardware and software modules. Specifically, the steps of the method embodiments in the embodiments of the present application can be completed by hardware integrated logic circuits and / or software instructions in the processor. The steps of the method disclosed in the embodiments of the present application can be directly reflected as being executed by a hardware encoding processor, or can be executed by a combination of hardware and software modules in the encoding processor. Optionally, the software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps in the above method embodiments in combination with its hardware.

[0157] The embodiments of the present application also provide a chip that can implement the steps of the instruction scheduling method based on multiple instruction scheduling modes in any of the above embodiments. For the sake of brevity, they are not repeated here.

[0158] See also Figure 13 The embodiment of the present application also provides a computer-readable storage medium 300 on which a computer program 310 is stored. When the computer program 310 is executed by the processor 320, the steps of the instruction scheduling method based on multiple instruction scheduling modes of any of the above-mentioned embodiments are implemented. For the sake of brevity, they are not repeated here.

[0159] In the description of this specification, the reference terms "certain embodiments", "in an example", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are mutually inconsistent.

[0160] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0161] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An instruction scheduling method based on multiple instruction scheduling modes, characterized in that: include: Obtaining an instruction packet, wherein the instruction packet includes multiple instructions; Decoding a current instruction to determine an instruction type of the current instruction, where the current instruction is any instruction in the instruction packet; In a case where the instruction type is a mode switching instruction, the instruction scheduling mode is switched so that the instruction scheduling mode matches the mode switching instruction.

2. The instruction scheduling method based on multiple instruction scheduling modes according to claim 1, characterized in that: The instruction scheduling mode includes a sequential superscalar mode and a very long instruction word mode.

3. The instruction scheduling method based on multiple instruction scheduling modes according to claim 1, characterized in that: The switching instruction scheduling mode includes: Modifying a value of an instruction scheduling mode field of a control and status register corresponding to the instruction scheduling mode so that the value corresponds to an operand of the mode switching instruction; The instruction scheduling mode field is used to control the current instruction scheduling mode.

4. The instruction scheduling method based on multiple instruction scheduling modes according to claim 3, characterized in that: The instruction scheduling mode includes a first scheduling mode and a second scheduling mode. When the value of the instruction scheduling mode field is a first preset value, the current instruction scheduling mode is the first scheduling mode. When the value of the instruction scheduling mode field is a second preset value, the current instruction scheduling mode is the second scheduling mode.

5. The instruction scheduling method based on multiple instruction scheduling modes according to claim 4, characterized in that: The first scheduling mode includes an in-order superscalar mode, and the second scheduling mode includes a very long instruction word mode.

6. The instruction scheduling method based on multiple instruction scheduling modes according to claim 1, characterized in that: The instruction packet is obtained by fetching instructions from an instruction stream generated when a program is running. The program includes multiple code segments, and each of the code segments has a corresponding instruction scheduling mode.

7. The instruction scheduling method based on multiple instruction scheduling modes according to claim 6, characterized in that: Each code segment corresponds to an instruction part in the instruction stream, and the mode switching instruction exists. The mode switching instruction corresponding to the code segment is generated based on the instruction scheduling mode corresponding to the code segment.

8. The instruction scheduling method based on multiple instruction scheduling modes according to claim 1, characterized in that: Decoding the current instruction to determine the instruction type of the current instruction includes: Decoding the current instruction to determine each field in the current instruction; Matching each field of the current instruction with each preset instruction format to determine a target instruction format corresponding to the current instruction, where the target instruction format is any of the preset instruction formats corresponding to the instruction type; An instruction type of the current instruction is determined based on the target instruction format.

9. The instruction scheduling method based on multiple instruction scheduling modes according to claim 1, characterized in that: The instruction scheduling mode includes a sequential superscalar mode, and the method further includes: Before distributing a target instruction of a current processing cycle, determining whether a target register corresponding to the target instruction is locked; If yes, the target instruction is devolved to the next processing cycle for processing, and the step of determining whether the register corresponding to the target instruction is locked before distributing the target instruction of the current processing cycle is entered again; If not, the target instruction is dispatched and the target register is locked.

10. The instruction scheduling method based on multiple instruction scheduling modes according to claim 9, characterized in that: Each of the registers has a corresponding lock flag, and locking the target register includes: The lock flag corresponding to the target register is updated to a target value, where the target value is determined based on an execution cycle of the target instruction.

11. The instruction scheduling method based on multiple instruction scheduling modes according to claim 10, characterized in that: Also includes: When the current processing cycle ends, the lock flags corresponding to the registers are updated.

12. The instruction scheduling method based on multiple instruction scheduling modes according to claim 9, characterized in that: Each of the registers has a corresponding lock flag, and determining whether the target register corresponding to the target instruction is locked includes: Determining whether the lock flag corresponding to the target register is a third preset value; Wherein, when the lock flag corresponding to the target register is a third preset value, the target register is not locked; when the lock flag corresponding to the target register is not the third preset value, the target register is locked.

13. The instruction scheduling method based on multiple instruction scheduling modes according to claim 1, characterized in that: The instruction scheduling mode includes a very long instruction word mode. In the very long instruction word mode, the functions corresponding to the instructions in the instruction package are matched with the preset functional units respectively, and the instructions are distributed to the preset functional units for parallel execution.

14. The instruction scheduling method based on multiple instruction scheduling modes according to claim 1, characterized in that: The instruction scheduling mode includes a very long instruction word mode, and the method further includes: Obtaining a function corresponding to each instruction in the instruction packet, where each function corresponds to one or more preset functional units; Based on the functions corresponding to the instructions, the instructions are divided into one or more instruction groups, and the functions corresponding to the instructions in the same instruction group are the same; fetching instructions from each of the instruction groups to obtain a plurality of instructions to be distributed, wherein the number of the instructions to be distributed corresponding to each of the instruction groups is less than or equal to the number of preset functional units corresponding to the instruction group; Distribute each of the to-be-distributed instructions to the corresponding preset functional units respectively.

15. An instruction scheduling device based on multiple instruction scheduling modes, characterized in that: include: An acquisition module, configured to acquire an instruction packet, wherein the instruction packet includes a plurality of instructions; a decoding module, configured to decode a current instruction to determine an instruction type of the current instruction, wherein the current instruction is any instruction in the instruction packet; The switching module is used to switch the instruction scheduling mode when the instruction type is a mode switching instruction, so that the instruction scheduling mode matches the mode switching instruction.

16. A chip, characterized in that: Used to execute the instruction scheduling method based on multiple instruction scheduling modes as described in any one of claims 1 to 14.

17. A non-volatile computer-readable storage medium containing a computer program, wherein when the computer program is executed by a processor, the processor executes the instruction scheduling method based on multiple instruction scheduling modes according to any one of claims 1 to 14.

Images