Layout verification method and related product

Abstract

The invention provides a layout verification method and a related product. The layout verification method comprises the following steps: acquiring a target layout, and extracting a plurality of blocks from the target layout; a hierarchical tree is constructed, the hierarchical tree comprises a parent tree and a plurality of child trees, the parent tree takes the target layout as a root node, each child tree is used for representing a connection relationship between the block units in each block in a one-to-one correspondence manner, and the root nodes of all child trees are connected with the root node of the parent tree in parallel; and based on the hierarchical tree, performing connectivity relation operation on the target layout through a distributed operation strategy to obtain layout connectivity information. According to the layout verification method provided by the invention, a strategy of carrying out partitioning processing on the input layout is adopted, so that the calculation efficiency of the graph connectivity of the cross-level layout can be effectively improved, the performance of a calculation photoetching platform is further improved, and the market competitiveness of products is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a layout verification method and a computer program product, a computer-readable storage medium, and a computer device for implementing the same. Background Art

[0002] For layouts dominated by mature nodes and simple graphics, standard connectivity calculation methods typically use a single-threaded operation mode that traverses all inverse-order trees from the bottom up. Currently, as process nodes in the layout continue to shrink, the integration of transistors in the process nodes is also increasing, the graphics per unit area are becoming more and more dense, and the layout hierarchical structure is becoming more and more complex, making the layout more and more complex. However, for more complex layouts, this single-threaded operation mode has significant limitations. For example, as the number of nodes in the hierarchical tree increases, the time consumed by the single-threaded operation becomes longer and longer, resulting in inefficient layout connectivity calculations.

[0003] Specifically, with the continuous development of semiconductor technology and the continuous reduction of feature sizes, the role of computational lithography in chip manufacturing processes has become increasingly significant. Since computational lithography requires mask optimization of the entire chip pattern, it also requires process error compensation for different target patterns based on process capabilities. The amount of computation required to achieve both of these requirements is very large. Before implementing specific mask optimization and process error compensation, the system needs to obtain complete single-layer graphic information (single-layer cross-level graphic connectivity) or metal layer connection information (multi-layer cross-level graphic connectivity) from the complex layout structure. The traditional standard connectivity calculation method uses a bottom-up, single-threaded operation mode that traverses all hierarchical trees. It can efficiently complete the task in mature nodes or simple layout designs. However, as process nodes continue to shrink, the transistor integration of advanced nodes is getting higher and higher, the graphics per unit area are becoming more and more dense, and the layout hierarchical structure is becoming more and more complex. Single-threaded operations can no longer meet performance requirements. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a layout verification method that overcomes the above problems or at least partially solves the above problems.

[0005] One purpose of the present invention is to solve the problem of low efficiency in computing connectivity of complex layouts and to achieve the goal of improving the computing efficiency of layout connectivity.

[0006] Specifically, according to one aspect of the present invention, a layout verification method is provided, which includes:

[0007] Acquire a target layout, and extract a plurality of tiles from the target layout, each of the tiles corresponding to a different area on the target layout;

[0008] Constructing a hierarchical tree, the hierarchical tree including a parent tree and multiple subtrees, the parent tree having the target layout as a root node, each of the subtrees being used to represent a one-to-one correspondence between connection relationships between tile units within each tile, and the root nodes of all subtrees being connected in parallel to the root node of the parent tree;

[0009] Based on the hierarchical tree, a connectivity relationship operation is performed on the target layout through a distributed computing strategy to obtain layout connectivity information.

[0010] Optionally, based on the hierarchical tree, a connectivity relationship operation is performed on the target layout through a distributed computing strategy, including:

[0011] generating a plurality of subtree computing tasks corresponding one-to-one to each of the image blocks;

[0012] Based on each of the subtrees, all the subtree computing tasks are computed using the distributed computing strategy to obtain a plurality of block connectivity information.

[0013] Optionally, after obtaining the connectivity information of the plurality of blocks, the method further includes:

[0014] All the block connectivity information is integrated based on the target layout to obtain the layout connectivity information.

[0015] Optionally, the step of extracting a plurality of tiles from the target layout includes:

[0016] According to a preset block threshold, a virtual grid for segmenting the target layout is determined, and the number of cells in the virtual grid is equal to or less than the block threshold.

[0017] Optionally, the step of determining a virtual grid for segmenting the target layout includes:

[0018] Generating an initial virtual grid for segmenting the target layout according to cells of a preset size;

[0019] Determining whether the number of cells in the initial virtual grid is less than or equal to the block threshold;

[0020] If it is not less than or equal to, the size of the cell is increased, and the virtual grid for dividing the target layout is regenerated.

[0021] Optionally, the step of extracting a plurality of tiles from the target layout includes:

[0022] Dividing the target layout into a plurality of layout regions of equal area;

[0023] Based on the multiple layout areas, multiple blocks are extracted from the target layout.

[0024] Optionally, extracting a plurality of the tiles from the target layout based on the plurality of layout areas includes:

[0025] Determining whether an intersection of a boundary of the layout area and an outline of a layout unit is located on a layout grid point, wherein the layout unit is a layout graphic or a cell instance;

[0026] If located, the graphics in the layout area are used as the block; or

[0027] If not, the graphic in the layout unit is used as the block

[0028] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned layout verification methods are implemented.

[0029] According to another aspect of the present invention, a computer program product is provided, which includes a computer program. When the computer program is executed by a processor, the steps of any one of the above-mentioned layout verification methods are implemented.

[0030] According to another aspect of the present invention, a computer device is provided, which includes a memory, a processor, and a computer program stored in the memory, and the processor executes the computer program to implement the steps of any one of the layout verification methods.

[0031] In the layout verification method of the present invention, since multiple blocks are extracted from the target layout, and each block corresponds to a different area on the target layout, and the connectivity information within each block itself is first obtained through a distributed computing strategy, and then the connectivity information of the entire layout is obtained based on the entire target layout, that is, the strategy of block processing of the input layout is adopted, which can effectively improve the computational efficiency of cross-level layout graphic connectivity, thereby improving the performance of the computational lithography platform and enhancing the market competitiveness of the product.

[0032] Based on the following detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings, those skilled in the art will become more aware of the above and other objects, advantages and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0034] Figure 1 It is a schematic structure diagram of the traditional hierarchical tree for the design layout;

[0035] Figure 2 It is about the changes of leaf nodes when computing connectivity of traditional hierarchical trees; Figure 2 The solid nodes in the are new nodes generated, and the dotted box nodes are the leaf nodes that are stripped off;

[0036] Figure 3 is a schematic flow chart of a layout verification method according to an embodiment of the present invention;

[0037] Figure 4 is a block diagram of a target layout in a layout verification method according to an embodiment of the present invention;

[0038] Figure 5 This is a schematic structural diagram of a novel hierarchical tree in a layout verification method according to an embodiment of the present invention, which breaks the traditional thinking framework that the integrity of layout graphics must be preserved;

[0039] Figure 6 is a partial schematic flow chart of a layout verification method according to an embodiment of the present invention;

[0040] Figure 7 is a schematic flow chart of a layout verification method according to an embodiment of the present invention;

[0041] Figure 8 is a schematic diagram of a layout pattern being cut in a layout verification method according to an embodiment of the present invention;

[0042] Figure 9 is a schematic diagram of a cell instance being cut in a layout verification method according to an embodiment of the present invention;

[0043] Figure 10 is a schematic diagram of integrating block connectivity information in a layout verification method according to an embodiment of the present invention;

[0044] Figure 11 is a schematic diagram of the implementation effect of a layout verification method according to an embodiment of the present invention;

[0045] Figure 12 is a schematic diagram of a computer program product according to one embodiment of the present invention;

[0046] Figure 13 is a schematic diagram of a computer-readable storage medium according to one embodiment of the present invention; and

[0047] Figure 14 is a schematic diagram of a computer device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0048] Based on the traditional hierarchical tree, such as Figure 1 and Figure 2As shown, the multi-threaded computing mode developed by the inventor in the early stage also adopts a bottom-up computing process, and transforms the leaf node of each hierarchical tree into a thread starting point. When the calculation of the leaf node is completed, the leaf node is stripped to generate a new node, and the new node will become a new thread starting point, thereby realizing multi-threaded connectivity calculation. However, this multi-threaded computing method is very susceptible to the influence of the hierarchical tree structure of the layout. For example, the closer the node calculation is to the top, the fewer the number of effective threads will be due to the fewer nodes, resulting in poor overall linearity. For example, if the top node is a separate node, it can only be a single-threaded calculation even if a multi-threaded mode is used. Similarly, if the number of graphics in the top node is large (no cluster classification is done), the time consumption of the top node will also be very slow. Therefore, if this multi-threaded solution is used on the hole layer layout, it can produce the expected effect, but when encountering the metal layer layout, the improvement effect is greatly reduced, and it may even appear that as the number of threads increases, the computing efficiency decreases. In other words, based on the traditional hierarchical tree structure, the multi-threaded computing mode developed by the inventor in the early stage still cannot effectively improve the computing efficiency of the layout connectivity. The implementation effect is as follows. Figure 11 As shown by the dotted line in .

[0049] Therefore, the following reference Figures 3 to 14 To describe the layout verification method and related products of the embodiments of the present invention.

[0050] Figure 3 FIG. 1 is a schematic flow chart of a layout verification method according to an embodiment of the present invention. The layout verification method may generally include:

[0051] Step S100: Obtain the target layout and extract multiple tiles from the target layout, each tile corresponding to a different area on the target layout. Figure 4 As shown in the figure, without considering the internal relationship of the graphics in the target layout, the target layout can be physically cut directly to extract multiple blocks, breaking the traditional thinking framework that the layout graphics must retain their integrity. Figure 4 As shown, 6 tiles can be extracted from the target layout, namely tile A, tile B, tile C, tile D, tile E, and tile F.

[0052] Step S200: construct a hierarchical tree. The hierarchical tree includes a parent tree 50 and multiple subtrees 51. The parent tree 50 takes the target layout as the root node. Each subtree 51 is used to represent the connection relationship between the tile units within each tile in a one-to-one correspondence. The root nodes of all subtrees 51 are connected to the root node of the parent tree 50 in parallel. Figure 5As shown, the subtree 51 is used to represent the connection relationship between the tile units in tile A, tile B, tile C, tile D, tile E, and tile F in a one-to-one correspondence. The root nodes of all subtrees 51 are connected in parallel to the root node of the parent tree 50. In this step, the tile units in each tile can be sorted to obtain the connection relationship between the tile units and the tile units, which is used to calculate the connectivity relationship. The hierarchical tree constructed in the embodiment of the present invention is as follows: Figure 5 As shown, it is completely different from the traditional hierarchical tree. In the traditional hierarchical tree, the closer to the top node, the fewer nodes there are. The computing efficiency is affected by the number of nodes, and it is easy to encounter performance bottlenecks. In the hierarchical tree constructed by the embodiment of the present invention, the number of top nodes is determined by the number of divided tiles, which can give full play to computing resources and make the size and area of each tile equal, with comparable computing efficiency and less likely to cause performance bottlenecks. Of course, the size and area of each tile can also be determined according to actual needs.

[0053] Step S300 , based on the hierarchical tree, a connectivity relationship operation is performed on the target layout through a distributed computing strategy to obtain layout connectivity information.

[0054] The layout verification method of an embodiment of the present invention, from the perspective of layout task distribution, proposes a new method for calculating the connectivity of cross-level layout graphics. This method breaks the traditional thinking framework that layout graphics must maintain integrity. By block-based layout planning of the input layout, it can fully utilize distributed computing resources without being restricted by the traditional hierarchical tree, greatly improving computing efficiency and ensuring good linearity. In this embodiment, block processing not only increases the number of task units, but also indirectly plays a role in clustering the top graphics.

[0055] The calculation of connectivity is essentially performed on the entire layout, and its computing efficiency is greatly affected by the top-level graphics to a certain extent. That is, if there is a graphics with a large span and a large number of vertices in the top level, the traditional computing method will encounter a performance bottleneck when calculating the connectivity relationship of the top-level graphics. At the same time, the traditional computing method has a prerequisite when calculating, that is, the top-level graphics must be complete. The layout verification method of the embodiment of the present invention first breaks the "top-level graphics integrity" restriction and allows the top-level graphics to be disconnected. Then, based on this, the hierarchical tree structure of the original layout is reconstructed. The purpose of reconstruction is to achieve distributed computing, that is, a complex top graphics can be dispersed in different tasks for parallel computing, thereby improving efficiency. Finally, by integrating the computing results of each task and waiting for the complete connectivity relationship, the computing efficiency is significantly improved.

[0056] In some embodiments of the present invention, Figure 6As shown, step S300 is to perform connectivity relationship calculation on the target layout based on the hierarchical tree through a distributed computing strategy, including:

[0057] Step S310 : generating a plurality of subtree computing tasks corresponding one-to-one to each tile.

[0058] Step S320 : Based on each subtree, all subtree computing tasks are computed using a distributed computing strategy to obtain connectivity information of multiple tiles.

[0059] Step S330 , integrating all block connectivity information based on the target layout to obtain layout connectivity information.

[0060] In an embodiment of the present invention, all subtree computing tasks can be calculated based on a distributed computing strategy, that is, each tile is first calculated to obtain the connectivity information of each tile, that is, the tile connectivity information, and then all the tile connectivity information is integrated to obtain the layout connectivity information. When performing distributed computing, the number of computing tasks will not decrease as it approaches the top, and the number of transportation tasks is equivalent to the number of physical blocks. It will not happen that the closer the node calculation is to the top, the fewer the number of effective threads will be due to the decrease in the number of nodes, resulting in poor overall linearity. For example, the top node of a traditional hierarchical tree is a separate node, and even if a multi-threaded mode is used, it can only be a single-threaded calculation. Similarly, it will not happen that if the number of graphics in the top node is large (not clustered), the time consumption of the top node will also be very slow. It will not happen that when encountering a metal layer layout, the computing efficiency improvement effect will be greatly reduced, and it may even happen that as the number of threads increases, the computing efficiency decreases.

[0061] The implementation effect of the layout verification method of the embodiment of the present invention is as follows: Figure 11 As shown by the solid line in the figure, the layout verification method of the present invention not only achieves the desired effect on hole-layer layouts, but also significantly improves computational efficiency when applied to metal-layer layouts. This method successfully addresses the performance bottlenecks and linearity issues encountered by traditional hierarchical tree multithreading, demonstrating excellent performance and reducing computation time as computational resources increase.

[0062] In the layout verification method of the embodiment of the present invention, after completing the block layout planning operation of the input layout, distributed computing can be implemented, and each block layout, that is, a block, is a computing task unit. That is to say, under the condition of sufficient resources, the layout can be divided into a large number of small task units, because the smaller the layout area input to the calculation, the fewer the number of top graphics that affect the computing efficiency, and thus the higher the computing efficiency; when the computing resources are not very sufficient, you can still try to divide multiple task units, but in order to balance the performance, the more task units at this time, the better. In other words, the number of task units and computing resources can be perfectly matched to make full use of computing resources, thereby improving the computing efficiency of connectivity.

[0063] In some embodiments of the present invention, Figure 7 As shown, the step of extracting multiple blocks from the target layout in step S100 includes:

[0064] Step S110 , determining a virtual grid for segmenting the target layout according to a preset segmentation threshold, wherein the number of cells in the virtual grid is equal to or less than the segmentation threshold.

[0065] The block threshold is designed to match computational resources. Therefore, the number of separated tiles, and therefore the number of subtree computation tasks established, must match the computational resources. This prevents the task load from exceeding the resource load, which would cause the system's frequent sending and receiving of tasks to become significantly time-consuming. Therefore, the number of cells in the virtual grid should be less than or equal to the block threshold to balance computational resources and the number of tiles. Preferably, the number of cells in the virtual grid is equal to the separation threshold.

[0066] In some embodiments of the present invention, the step of determining a virtual grid for segmenting the target layout includes:

[0067] Generate an initial virtual grid for segmenting the target layout based on cells of a preset size;

[0068] Determine whether the number of cells in the initial virtual grid is less than or equal to the block threshold;

[0069] If it is not less than or equal to, the size of the cell is increased and the virtual grid for segmenting the target layout is regenerated.

[0070] The subtree computation tasks of distributed computing depend on the total resources available or available on the client side. Computing resources usually refer to CPU cores. Typically, the number of resources does not exceed 200 CPU cores.

[0071] In some specific embodiments of the present invention, the preset size of the block area is less than 200 μm by 200 μm. Here, 200 μm is used as an example to describe how to determine the number of blocks:

[0072] First, obtain the boundary lengths of the input target layout, x and y. Then, divide x and y by 200 to obtain a and b, respectively: a = x / 200, b = y / 200. If a or b is less than 1, the x or y corresponding to a or b is directly used as the corresponding length in a certain direction of the block. In this case, the length is less than 200 μm. If a or b is greater than 1, x or y is divided into a or b parts. Therefore, the final number of blocks is a times b.

[0073] Considering that the input target layout can be very large, resulting in a large number of tiles, for example, a 10mm side can be divided into 50 200um tiles. This means that a 10mm x 10mm layout would generate 2500 tiles. At this point, the workload far outweighs the resource requirements, and the system's frequent send and receive tasks become particularly significant. Increasing the tile size can suppress the excessive workload and ultimately achieve better performance. Therefore, building on the aforementioned tile strategy, we add a constraint: the tile threshold. This threshold can be set to 400, meaning that a multiplied by b must be less than 400. This threshold represents an acceptable balance point for the test system. Therefore, if a multiplied by b ≤ 400, the current partitioning method is used. If a multiplied by b > 400, the values of a or b are dynamically adjusted. For example, if a = 5 and b = 100, then a = 5 and b = 80. This increases the cell size and regenerates the virtual grid used to partition the target layout. The block strategy used by the 200 CPU cores can generate up to 400 block areas, which can meet the needs of conventional applications. That is, the operation of 200 CPU cores also means that the linearity of the operation within 400 computing resources can be guaranteed, which significantly improves the computing efficiency.

[0074] In some embodiments of the present invention, Figure 7 As shown, the step of extracting multiple blocks from the target layout in step S100 also includes:

[0075] Step S120 , dividing the target layout into a plurality of layout regions of equal area.

[0076] Step S130 : extracting a plurality of tiles from the target layout based on the plurality of layout regions.

[0077] In an embodiment of the present invention, the layout areas are in the form of equal areas, so that the number of graphics, etc. in each layout area is as equal as possible, ensuring that the computational amount of each subtree operation task is as equal as possible, thereby improving the computational efficiency of the layout connectivity information.

[0078] Specifically, the target layout can be divided into multiple layout regions of equal area based on a virtual grid used to segment the target layout. Since each cell of the virtual grid has a consistent shape and equal area, multiple layout regions of equal area can be divided on the target layout using each cell of equal area in the virtual grid. In some embodiments of the present invention, other methods can also be used to divide the target layout into multiple layout regions of equal area.

[0079] In some embodiments of the present invention, step S130, extracting a plurality of tiles from the target layout based on the plurality of layout regions, includes:

[0080] Determines whether the intersection of the layout region boundary and the outline of a layout unit lies on a layout grid point. A layout unit is a layout shape or cell instance.

[0081] If located, the graphics in the layout area are used as tiles; or,

[0082] If it is not located, the graphics within the layout unit will be used as the block.

[0083] In an embodiment of the present invention, if the outline of a layout unit is completely inside the boundary of the layout area, the graphics within the layout unit are used as tiles. If the outline of a layout unit is completely outside the boundary of the layout area, the layout unit is not included in the tile. If there is an intersection between the boundary of the layout area and the outline of the layout unit, and the intersection is located at a layout grid point, it means that the graphics contained in the layout unit need to be separated into two layout areas, that is, part of the graphics of the separated and cut layout unit is in one layout area, and the other part is in another layout area, so that the tile units in the tile can be various graphics in the tile, including the part of the layout graphics after cutting or the part of the cell instance.

[0084] Specifically, the input layout is divided into blocks, that is, the layout is divided and planned into multiple areas of similar size. In the specific cutting process, two types of processing objects will be encountered, layout graphics (shape) and cell instances (instance). For layout graphics, it will be determined whether the intersection of the cutting line (i.e. the boundary of the layout area) and the graphic (i.e. the outline of the layout unit) is located on the layout grid. If it is located on the layout grid, the layout graphic is cut along the cutting line so that part of the graphic of the separated and cut layout unit is in one layout area, that is, in block A, and the other part is in another layout area, that is, in block B, such as Figure 8As shown. If it is not on the layout grid, the complete layout graphic is retained. Similarly, for the cell instance, the operation of instantiating the cell is taken, and the graphic in the cell is placed in the corresponding parent cell. At the same time, if there is a graphic in the cell instance that intersects with the cutting line, and the intersection is on the layout grid, the same cutting processing method as the layout graphic is adopted, so that part of the graphic in the cell instance is in one layout area, that is, in block C, and the other part of the graphic is in another layout area, that is, in another block D, as shown in FIG. Figure 9 shown.

[0085] In some embodiments of the present invention, step S330 integrates the connectivity information of all tiles based on the target layout to obtain layout connectivity information. That is to say, after all subtree operation tasks are completed, the master server (Master) collects all results and integrates and corrects the top graphic results. In simple terms, each task unit has completed the connectivity relationship calculation within its own calculation range, and the connectivity relationship will be transmitted back to the master server. The master server uses additional algorithm processing to identify those truncated graphics, and finally integrates the connectivity information of the truncated graphics calculated in different task units to obtain the final result.

[0086] like Figure 10 As shown, for example, a complete core function layer or basic design layer (layer main) includes tile units Pa+Pb+Pd, and the tile unit Pa can be calculated to have a connection relationship with the reference layer in tile A, while the tile units Pb and Pd do not have a connection relationship with the reference layer in their corresponding tiles B and D. Therefore, when the main server performs graphic diffusion, integration, and correction, the connection relationship between the tile unit Pa and the reference layer will be diffused to the tile units Pb and Pd, and finally the correct relationship result is obtained, that is, the tile units Pa, Pb, and Pd have a connection relationship with the reference layer.

[0087] The flowchart provided in this embodiment is not intended to indicate that the operations of the method will be performed in any particular order, or that all operations of the method are included in all every case. In addition, the method may include additional operations. Within the scope of the technical ideas provided by the method of this embodiment, additional changes can be made to the above method.

[0088] It should be understood that in some embodiments, each part can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system.

[0089] This embodiment also provides a computer program product 10 , a computer-readable storage medium 20 , and a computer device 30 . Figure 12 is a schematic diagram of a computer program product 10 according to one embodiment of the present invention, Figure 13 is a schematic diagram of a computer-readable storage medium 20 according to one embodiment of the present invention, Figure 14 is a schematic diagram of a computer device 30 according to one embodiment of the present invention. Computer program product 10 includes a computer program 11. When executed by a processor 32, computer program 11 implements the steps of any of the aforementioned layout verification methods. Computer-readable storage medium 20 stores computer program 11. When executed by processor 32, computer program 11 implements the steps of any of the aforementioned layout verification methods. Computer device 30 may include memory 31, processor 32, and computer program 11 stored in memory 31 and executed by processor 32.

[0090] The computer program 11 for performing the operations of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages and procedural programming languages. The computer program 11 can be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or can be connected to an external computer. In some embodiments, to perform various aspects of the present invention, an electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuit.

[0091] In the description of this embodiment, the computer program product 10 is a related product including the computer program 11 .

[0092] For the purposes of the description of this embodiment, the computer-readable storage medium 20 is a tangible device capable of retaining and storing the computer program 11, and can be any device that can contain, store, communicate, propagate, or transmit the program 11 for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable storage medium 20 include the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, and any suitable combination of the foregoing.

[0093] The computer device 30 can be, for example, a server, a desktop computer, a laptop computer, a tablet computer, or a smartphone. In some examples, the computer device 30 can be a cloud computing node. The computer device 30 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. The computer device 30 can be implemented in a distributed cloud computing environment where remote processing devices linked via a communication network perform tasks. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media, including storage devices.

[0094] The computer device 30 may include a processor 32 adapted to execute stored instructions, and a memory 31 that provides temporary storage for the instructions during operation. The processor 32 may be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. The memory 31 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.

[0095] The computer device 30 may also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows data to be input and output with external devices that can be connected to the computer device. The network adapter / interface can provide communication between the computer device and a network, which is generally shown as a communication network.

[0096] At this point, those skilled in the art will recognize that, although a number of exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications consistent with the principles of the present invention may be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and deemed to cover all such other variations or modifications.

Claims

1. A layout verification method, characterized in that: include: Acquire a target layout, and extract a plurality of tiles from the target layout, each of the tiles corresponding to a different area on the target layout; Constructing a hierarchical tree, the hierarchical tree including a parent tree and multiple subtrees, the parent tree having the target layout as a root node, each of the subtrees being used to represent a one-to-one correspondence between connection relationships between tile units within each tile, and the root nodes of all subtrees being connected in parallel to the root node of the parent tree; Based on the hierarchical tree, a connectivity relationship operation is performed on the target layout through a distributed computing strategy to obtain layout connectivity information.

2. The layout verification method according to claim 1, wherein: Based on the hierarchical tree, a connectivity relationship operation is performed on the target layout through a distributed computing strategy, including: generating a plurality of subtree computing tasks corresponding one-to-one to each of the image blocks; Based on each of the subtrees, all the subtree computing tasks are computed using the distributed computing strategy to obtain a plurality of block connectivity information.

3. The layout verification method according to claim 2, characterized in that: After obtaining the connectivity information of the plurality of blocks, the method further includes: All the block connectivity information is integrated based on the target layout to obtain the layout connectivity information.

4. The layout verification method according to claim 2, wherein: The step of extracting a plurality of blocks from the target layout includes: According to a preset block threshold, a virtual grid for segmenting the target layout is determined, and the number of cells in the virtual grid is equal to or less than the block threshold.

5. The layout verification method according to claim 4, characterized in that: The step of determining a virtual grid for segmenting the target layout includes: Generating an initial virtual grid for segmenting the target layout according to cells of a preset size; Determining whether the number of cells in the initial virtual grid is less than or equal to the block threshold; If it is not less than or equal to, the size of the cell is increased, and the virtual grid for dividing the target layout is regenerated.

6. The layout verification method according to claim 1, wherein: The step of extracting a plurality of blocks from the target layout includes: Dividing the target layout into a plurality of layout regions of equal area; Based on the multiple layout areas, multiple blocks are extracted from the target layout.

7. The layout verification method according to claim 6, characterized in that: Extracting a plurality of the blocks from the target layout based on the plurality of layout areas includes: Determining whether an intersection of a boundary of the layout area and an outline of a layout unit is located on a layout grid point, wherein the layout unit is a layout graphic or a cell instance; If located, the graphics in the layout area are used as the block; or If not, the graphic within the layout unit is used as the block.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the layout verification method according to any one of claims 1 to 7 are implemented.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the layout verification method according to any one of claims 1 to 7 are implemented.

10. A computer device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the layout verification method according to any one of claims 1 to 7.

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