System-on-chip standardized interconnection substrate implementation method and interconnection structure

Abstract

The invention belongs to the technical field of semiconductor packaging, and particularly relates to a system-on-chip standardized interconnection substrate implementation method and an interconnection structure. Comprising the following steps: arranging and combining core particles integrated in a system on chip to form a plurality of different functional units; different micro-module-level interconnection substrates with standardized PAD distribution at the bottoms are mounted to the corresponding core particles according to the different functional units respectively, so that various different functional unit micro-modules are formed; providing a wafer-level interconnection substrate with a standardized PAD distribution array at the top, and finishing wiring design shaping of the wafer-level interconnection substrate according to an interconnection communication demand, an external communication demand and a power supply demand; and mounting different functional unit micro modules on the wafer-level interconnection substrate so as to realize standardized interconnection. According to the method, a system-on-chip customization framework can be broken, complex and time-consuming wafer-level interconnection substrate design and processing caused by core particle type selection change are reduced, and the design efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor packaging technology, and in particular relates to a method for realizing a standardized interconnection substrate and an interconnection structure for an on-chip system. The on-chip system is mainly used in fields such as high-performance computing and signal processing. Background Art

[0002] High-performance computing (HPC) has experienced rapid growth in recent years, finding widespread application in fields such as the Internet of Things, big data, blockchain, and artificial intelligence. However, its assembly methods and system architectures are no longer able to meet the form factor requirements of the next generation of miniaturized and portable electronic systems. The development of miniaturized, lightweight, and high-performance HPC systems for this new generation of electronic systems is urgently needed. However, with the slowdown of Moore's Law and the approaching physical limits of semiconductor feature sizes, doubling performance through feature size reduction is becoming unsustainable due to the dual pressures of technical difficulty and economic cost.

[0003] The emergence of System on Wafer (SoW) has opened up a highly innovative and feasible technological path for the development of high-performance computing. This type of wafer-level, high-density integrated computing system has emerged in recent years both domestically and internationally. It primarily addresses the application needs of high computing power combined with miniaturization in specific industries. Based on 2.5D / 3D wafer-level advanced packaging processes, SoW interconnects a large number of pre-designed, functional cores at high density. These cores are equipped with intelligent software systems, achieving a wafer-level, extremely high-density computing system through the collaborative work of hardware and software.

[0004] On-wafer systems require the integration of dozens or even hundreds of chips within a limited space. The design of their interconnect substrates is exponentially more complex than that of traditional multi-chip integrated systems. Currently, on-wafer systems primarily rely on customized architectures to achieve multi-chip integration, requiring a customized substrate design for each chip selection. This necessitates complex and time-consuming repeated substrate design and verification, severely restricting the sustainable development of on-wafer systems. To break down integration barriers between different vendors, accelerate design cycles, and improve the first-time success rate of on-wafer system interconnect substrates, there is an urgent need to develop a standardized wafer interconnect substrate implementation method suitable for on-wafer systems. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for implementing a standardized interconnection substrate for a wafer system. The method provided by the present invention can break the customized design of the wafer system interconnection substrate and use a universal and standardized wafer interconnection substrate design to meet the needs of arbitrary replacement of main control core particles, storage core particles, etc. in various application scenarios, thereby greatly reducing the time and value cost of redesigning the wafer interconnection substrate caused by changing the core particle selection.

[0006] To solve the above technical problems, the present invention provides a method for implementing a standardized interconnect substrate for an on-wafer system, comprising: Step 1: Arrange and combine the core particles integrated in the on-wafer system to form a variety of different functional units; Step 2: providing different micro-module-level interconnect substrates with standardized PAD distribution on the bottom; Step 3: Attach different micro-module-level interconnect substrates with standardized PAD distribution on the bottom to the corresponding core particles according to the above-mentioned different functional units to form a variety of different functional unit micro-modules; Step 4: Provide a wafer-level interconnect substrate with a standardized PAD distribution array on the top, and complete the wiring design of the wafer-level interconnect substrate based on the interconnection communication requirements, external communication requirements, and power supply requirements; Step 5: Based on application requirements, different types and quantities of functional unit micromodules are mounted on the wafer-level interconnect substrate to achieve standardized interconnection.

[0007] Preferably, in step 1, the functional unit is composed of a main control chip and a storage chip, the main control chip includes a CPU, an FPGA, a DSP and an AI; the storage chip includes a DDRx and a FLASH.

[0008] Preferably, in step 2, the standardized PAD distribution includes a standardized signal pin array, a standardized power pin array, and a standardized ground pin array.

[0009] Preferably, through the standardized signal pin array, the intra-chip interconnection communication requirements and the extra-chip communication requirements between multiple different functional units are combined to provide a maximized communication quantity; through the standardized power pin array, the power supply requirements of multiple different functional units are combined to provide a maximized power rail quantity.

[0010] Preferably, in the step 2, the micro-module-level interconnection substrate interconnects the corresponding master control core particles and storage core particles within the substrate.

[0011] Preferably, in step three, the different functional unit micromodules are interconnected at the micromodule level via a substrate having a standardized PAD distribution at the bottom thereof, so as to achieve compatibility of pin definitions between different functional units.

[0012] Preferably, in the step 4, the manner of distributing the standardized PAD array on the top of the wafer-level interconnect substrate is determined according to the wafer size and application requirements.

[0013] Preferably, in step four, the communication paths in the wafer-level interconnect substrate need to be subjected to signal integrity simulation optimization according to the highest communication rate to ensure the communication requirements of all functional units; the power supply planes in the wafer-level interconnect substrate need to be subjected to power integrity simulation optimization according to the maximum power supply level and current to ensure the power supply requirements of all functional units.

[0014] Preferably, in step five, the type and quantity of the functional units to be mounted are arbitrarily selected according to application requirements, and different functional units can be mounted on any standardized PAD distribution on the wafer interconnect substrate.

[0015] The present invention further provides an on-wafer system standardized interconnection structure, which adopts the on-wafer system standardized interconnection substrate implementation method as described above, comprising: There are multiple functional unit micromodules; each of the functional unit micromodules includes a functional unit and a micromodule-level interconnect substrate, on which the functional unit is mounted; each of the functional units is composed of a main control chip and a storage chip, the main control chip includes a CPU, FPGA, DSP and AI; the storage chip includes DDRx and FLASH; A wafer-level interconnect substrate is provided, wherein a plurality of different functional unit micromodules are mounted on the wafer-level interconnect substrate.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a method for implementing a standardized interconnect substrate for on-wafer systems. By combining various types of master control cores with various types of storage cores to form multiple functional units, the intra-wafer signal interconnection requirements, extra-wafer communication requirements, and maximum power supply requirements between all functional units are fully analyzed. A standard PAD distribution is defined by taking and merging, thereby forming a batch of functional unit micromodules with a standard PAD distribution. Then, any type and number of functional unit micromodules are selected according to application requirements and arbitrarily mounted on a wafer-level interconnect substrate with a standard PAD distribution array to form an on-wafer system. The proposed method for implementing a standardized interconnect substrate for on-wafer systems can break the customized architecture, classify cores into multiple levels, and form a functional unit micromodule design library with a standard PAD distribution. According to application requirements, any micromodule can be selected and mounted on a wafer-level standard interconnect substrate. Even if the chip selection exceeds the design library, only the micromodule-level interconnect substrate design is required. This significantly reduces the design difficulty and design cycle, improves design efficiency and the first-time design success rate, and promotes the construction of an on-wafer system design ecosystem. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Flowchart of a method for implementing a standardized interconnection substrate for an on-wafer system in an embodiment of the present invention.

[0018] Figure 2 Schematic diagram of the standardized interconnection structure of the on-chip system in an embodiment of the present invention.

[0019] Figure 3 Schematic diagram of simplified PAD distribution [A] in an embodiment of the present invention.

[0020] Figure 4 Schematic diagram of PAD distribution on top of wafer-level interconnect substrate in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0022] like Figure 1 As shown, an embodiment of the present invention provides a method for implementing a standardized interconnect substrate for an on-wafer system, comprising the following steps: Step 1: Arrange and combine the core particles integrated in the on-wafer system to form multiple functional units; Step 2: Design micro-module-level interconnect substrates with the same PAD distribution at the bottom for different functional units to form a standardized PAD distribution; Step 3: After attaching corresponding chips according to the above-mentioned different functional units on the different micro-module-level interconnect substrates with standardized PAD distribution at the bottom, a variety of functional unit micro-modules are formed; Step 4: Design a wafer-level interconnect substrate with a standardized PAD distribution array on top. Finalize the wiring design in the wafer-level interconnect substrate based on interconnection communication requirements, external communication requirements, and power supply requirements. Step 5: Based on application requirements, different types and quantities of functional unit micromodules are mounted on the wafer-level interconnect substrate to achieve standardized interconnection.

[0023] like Figure 2 As shown, an embodiment of the present invention provides a standardized interconnection structure of an on-chip system, which can be specifically divided into three levels. Level one is a number of functional units composed of main control core particles and storage core particles, level two is a number of micro-module-level interconnection substrates, and level three is a wafer-level interconnection substrate, wherein the main control core particles include but are not limited to CPU, FPGA, DSP, AI, and the storage core particles include but are not limited to DDRx and FLASH. Level one and level two constitute a number of functional unit micro-modules.

[0024] Continue reading Figure 2As shown, the first level is a functional unit group consisting of main control core particles and storage core particles, such as functional unit A [CPU+DDRx+FLASH], functional unit B [FPGA+DDRx+FLASH], functional unit C [AI+DDRx+FLASH], and functional unit D [DSP+DDRx+FLASH]. The second level is a micro-module-level interconnection substrate with the same PAD distribution [A] at the bottom. Each functional unit realizes the standardized lead-out of the substrate internal interconnection, external communication, and power supply signals through the micro-module-level interconnection substrate, forming a standardized micro-module group. The third level is a wafer-level interconnection substrate with a standardized PAD distribution [A] array at the top. The wafer interconnection substrate is designed with standard intra-wafer interconnection communication paths, standard extra-wafer communication paths, and standard power supply paths. Various micro-modules can be mounted on any PAD distribution [A] of the wafer-level interconnection substrate, and realize intra-wafer interconnection, extra-wafer communication, and power supply requirements through the wafer-level interconnection substrate.

[0025] Continue reading Figure 3 The figure shows a simplified schematic diagram of the PAD distribution [A] described in an embodiment of the present invention. First, by taking the union of the intra-chip interconnection communication and extra-chip communication requirements between the four functional units A, B, C, and D described in the embodiment of the present invention and reasonably distributing them, a standard signal pin array is formed. Second, by taking the union of the power supply requirements of the four functional units A, B, C, and D and reasonably distributing them, a maximum number of power rails is provided to meet the communication requirements of all functional units. Finally, a PAD distribution [A] is formed, consisting of three standardized pin arrays: signal, power, and ground.

[0026] Continue reading Figure 4 Figure 2 shows a schematic diagram of the PAD distribution on top of a wafer-level interconnect substrate, described in an embodiment of the present invention. Based on the dimensions of the wafer-level interconnect substrate and the dimensions of each functional unit micromodule, several PADs [A] are arranged on top of the wafer-level interconnect substrate. Each functional unit micromodule can be mounted to any PAD [A] on the wafer-level interconnect substrate, achieving intra-wafer interconnection, extra-wafer communication, and power supply requirements.

[0027] In summary, this method combines several master control and storage cores integrated within an on-wafer system for various application scenarios into a number of functional units. A standard PAD distribution [A] is defined by combining and rationally distributing the intra-wafer signal interconnection, extra-wafer communication, and power supply requirements of all functional units. This standard PAD distribution [A] maximizes both communication requirements and the number of power rails, thus forming a cluster of functional unit micromodules with a standard PAD distribution [A]. Several PADs [A] are arranged on top of a wafer-level interconnect substrate. Any type and number of functional unit micromodules can be selected based on application requirements and mounted on the wafer-level interconnect substrate with a standard PAD distribution array to form an on-wafer system. This method breaks the custom architecture of on-wafer systems, reduces the complex and time-consuming wafer-level interconnect substrate design and processing required by changing core selection, improves design efficiency and first-time design success rate, breaks down integration barriers between different vendors, and promotes the development of an on-wafer system design ecosystem.

[0028] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for implementing a standardized interconnection substrate for an on-wafer system, characterized in that: include: Step 1: Arrange and combine the core particles integrated in the on-wafer system to form a variety of different functional units; Step 2: providing different micro-module-level interconnect substrates with standardized PAD distribution on the bottom; Step 3: Attach different micro-module-level interconnect substrates with standardized PAD distribution on the bottom to the corresponding core particles according to the above-mentioned different functional units to form a variety of different functional unit micro-modules; Step 4: Provide a wafer-level interconnect substrate with a standardized PAD distribution array on the top, and complete the wiring design of the wafer-level interconnect substrate based on the interconnection communication requirements, external communication requirements, and power supply requirements; Step 5: Based on application requirements, different types and quantities of functional unit micromodules are mounted on the wafer-level interconnect substrate to achieve standardized interconnection.

2. The method for implementing a standardized interconnection substrate for an on-wafer system according to claim 1, wherein: In step 1, the functional unit is composed of a main control chip and a storage chip. The main control chip includes a CPU, an FPGA, a DSP, and an AI; and the storage chip includes a DDRx and a FLASH.

3. The method for implementing a standardized interconnection substrate for an on-wafer system according to claim 1, wherein: In the step 2, the standardized PAD distribution includes a standardized signal pin array, a standardized power pin array, and a standardized ground pin array.

4. The method for implementing a standardized interconnection substrate for an on-wafer system according to claim 3, wherein: Through the standardized signal pin array, the intra-chip interconnection communication requirements and the extra-chip communication requirements between multiple different functional units are combined to provide a maximized communication quantity; through the standardized power pin array, the power supply requirements of multiple different functional units are combined to provide a maximized power rail quantity.

5. The method for implementing a standardized interconnection substrate for an on-wafer system according to claim 1, wherein: In the step 2, the micro-module-level interconnection substrate interconnects the corresponding master chiplets and storage chiplets within the substrate.

6. The method for implementing a standardized interconnection substrate for an on-wafer system according to claim 1, wherein: In the step three, the different functional unit micromodules are interconnected via a micromodule-level substrate with a standardized PAD distribution at the bottom thereof, so as to achieve compatibility of pin definitions between different functional units.

7. The method for implementing a standardized interconnection substrate for an on-wafer system according to claim 1, wherein: In step 4, the manner of distributing the standardized PAD array on top of the wafer-level interconnect substrate is determined according to the wafer size and application requirements.

8. The method for implementing a standardized interconnection substrate for an on-wafer system according to claim 1, wherein: In step four, the communication paths in the wafer-level interconnect substrate must be optimized for signal integrity simulation according to the maximum communication rate to ensure the communication requirements of all functional units; the power supply planes in the wafer-level interconnect substrate must be optimized for power integrity simulation according to the maximum power level and current to ensure the power supply requirements of all functional units.

9. The method for implementing a standardized interconnection substrate for an on-wafer system according to claim 1, wherein: In the step five, the type and quantity of the functional units to be mounted are arbitrarily selected according to application requirements, and different functional units can be mounted on any standardized PAD distribution on the wafer interconnect substrate.

10. A standardized interconnect structure for a system on a wafer, comprising: a method for implementing a standardized interconnect substrate for a system on a wafer as claimed in any one of claims 1 to 9; include: There are multiple functional unit micromodules; each of the functional unit micromodules includes a functional unit and a micromodule-level interconnect substrate, on which the functional unit is mounted; each of the functional units is composed of a main control chip and a storage chip, the main control chip includes a CPU, FPGA, DSP and AI; the storage chip includes DDRx and FLASH; A wafer-level interconnect substrate is provided, wherein a plurality of different functional unit micromodules are mounted on the wafer-level interconnect substrate.

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