Simulation configuration method and device of chip, storage medium and electronic device

Abstract

The invention discloses a chip simulation configuration method and device, a storage medium and an electronic device.The method comprises the steps that multiple subsystems included in a to-be-configured chip and associated information and operation information of the to-be-configured chip are detected, the associated information is used for indicating the degree of association between configuration operations of all the subsystems, and the operation information is used for indicating the degree of association between configuration operations of all the subsystems; the operation information is used for indicating an operation sequence of configuration operations of which the association degrees are greater than or equal to an association degree threshold value, and the configuration operations are used for controlling the corresponding subsystems to enter a system state corresponding to the simulation test; the subsystems are divided into one or more subsystem sets with a configuration sequence according to the association information and the operation information, and each subsystem set comprises the subsystems with the association degree between the corresponding configuration operations smaller than an association degree threshold value; and configuring the subsystems in each subsystem set according to the configuration sequence, and by adopting the technical scheme, the problem of relatively low simulation configuration efficiency of the chip in the related technology is solved.

Description

Technical Field

[0001] The present application relates to the field of testing, and more specifically, to a chip simulation configuration method and device, a storage medium, and an electronic device. Background Art

[0002] As chips continue to grow in size and complexity, system-level verification is facing corresponding challenges. Chip system-level verification suffers from long simulation times, significantly reducing chip verification efficiency. One of the phases that most impacts simulation efficiency is the simulation configuration phase. For larger chips, the conventional approach of configuring each subsystem of the chip one by one according to the startup sequence is time-consuming and inefficient.

[0003] With respect to the problem of low chip simulation configuration efficiency in related technologies, no effective solution has been proposed yet. Summary of the Invention

[0004] The embodiments of the present application provide a chip simulation configuration method and device, a storage medium, and an electronic device to at least solve the problem of low chip simulation configuration efficiency in related technologies.

[0005] According to one embodiment of the present application, a chip simulation configuration method is provided, which is applied to a simulation configuration tool. The method includes: detecting multiple subsystems included in the chip to be configured and association information and operation information of the chip to be configured, wherein the chip to be configured is a chip to be simulated tested, the association information is used to indicate the degree of association between configuration operations of each subsystem, the operation information is used to indicate the operation sequence of configuration operations with a degree of association greater than or equal to a correlation degree threshold, and the configuration operation is used to control the corresponding subsystem to enter a system state corresponding to the simulation test;

[0006] Dividing the plurality of subsystems into one or more subsystem sets having a configuration order according to the association information and the operation information, wherein each subsystem set includes subsystems whose corresponding configuration operations have a degree of association less than a threshold value of the degree of association;

[0007] Configure the subsystems in each subsystem collection in the order in which they are configured.

[0008] Optionally, multiple subsystems are divided into one or more subsystem sets with a configuration order based on association information and operation information, including: establishing a target number of initial sets based on the association information, wherein the target number is the maximum number of subsystems with an association relationship, and subsystems whose association degree indicated by the association information is greater than or equal to an association degree threshold have an association relationship; allocating multiple subsystems to each initial set based on the operation information and determining the configuration order of the target number of initial sets to obtain the target number of subsystem sets with a configuration order, wherein the subsystems in each subsystem set do not have an association relationship and are located in the same arrangement position in each configuration chain, and the configuration chain includes subsystems with an association relationship arranged in an operation order.

[0009] Optionally, an initial set of target quantities is established based on the association information, including: dividing multiple subsystems into one or more reference sets based on the association information, wherein the subsystems in each reference set have an association relationship; extracting a target set with the largest number of included subsystems from one or more reference sets; determining the number of subsystems included in the target set as the target quantity; and establishing an empty set of the target quantity to obtain the initial set of the target quantity.

[0010] Optionally, multiple subsystems are allocated to each initial set according to operation information and the configuration order of the target number of initial sets is determined to obtain the target number of subsystem sets with the configuration order, including: converting one or more reference sets into one or more configuration chains according to the operation information; dividing the subsystems located at the same arrangement position in each configuration chain into the same initial set, and establishing a configuration order to obtain the target number of subsystem sets with the configuration order, wherein the arrangement position of each initial set in the configuration order is the arrangement order of the target subsystems included in each initial set in the target configuration chain, and the target configuration chain is the configuration chain converted by the target set.

[0011] Optionally, a control environment and multiple subsystem environments are established in the simulation configuration tool, and the multiple subsystem environments correspond one-to-one to the multiple subsystems. Each subsystem environment is used to configure the corresponding subsystem, and the subsystems in each subsystem set are configured according to the configuration order, including: the control environment extracts subsystem sets one by one from one or more subsystem sets as target subsystem sets according to the configuration order; the control environment searches for subsystem environments corresponding to subsystems included in the target subsystem set from multiple subsystem environments to obtain one or more target subsystem environments; the control environment simultaneously controls one or more target subsystem environments to configure the corresponding subsystems, until one or more target subsystem environments complete the configuration of the corresponding subsystems.

[0012] Optionally, the control environment simultaneously controls one or more target subsystem environments to configure corresponding subsystems until one or more target subsystem environments complete the configuration of the corresponding subsystems, including: the control environment simultaneously sends a configuration start signal to one or more target subsystem environments, wherein each target subsystem environment is used to configure the corresponding subsystem in response to the configuration start signal; and the control environment detects the configuration status of each target subsystem environment until the detected configuration status indicates that the corresponding target subsystem environment has completed the configuration of the corresponding subsystem.

[0013] Optionally, the control environment detects the configuration status of each target subsystem environment until it is detected that the configuration status is used to indicate that the corresponding target subsystem environment has completed the configuration of the corresponding subsystem, including: the control environment receives the configuration end signal returned by each target subsystem environment within the target time period after sending the configuration start signal, wherein each target subsystem environment is used to send a configuration end signal to the control environment when the corresponding subsystem is successfully configured; when the control environment receives the configuration end signal returned by all target subsystem environments within the target time period, it is determined that it is detected that the configuration status is used to indicate that the corresponding target subsystem environment has completed the configuration of the corresponding subsystem; when the control environment does not receive the configuration end signal returned by all target subsystem environments within the target time period, it stops executing the step of extracting subsystem sets one by one from one or more subsystem sets as target subsystem sets in the configuration order.

[0014] According to another embodiment of the present application, a chip simulation configuration device is provided, which is applied to a simulation configuration tool. The device includes:

[0015] a detection module, configured to detect multiple subsystems included in a chip to be configured, as well as association information and operation information of the chip to be configured, wherein the chip to be configured is a chip to be simulated and tested, the association information is used to indicate the degree of association between configuration operations of the subsystems, the operation information is used to indicate the operation sequence of configuration operations with a degree of association greater than or equal to a threshold value of the degree of association, and the configuration operations are used to control the corresponding subsystem to enter a system state corresponding to the simulation test;

[0016] a partitioning module, configured to partition the plurality of subsystems into one or more subsystem sets having a configuration order according to the association information and the operation information, wherein each subsystem set includes subsystems whose corresponding configuration operations have a degree of association less than a threshold value of the degree of association;

[0017] The configuration module is used to configure the subsystems in each subsystem set according to the configuration order.

[0018] According to another aspect of the embodiments of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the simulation configuration method of the chip when running.

[0019] According to another aspect of an embodiment of the present application, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the simulation configuration method of the chip through the computer program.

[0020] In an embodiment of the present application, by detecting multiple subsystems included in a chip to be configured and the associated information and operation information of the chip to be configured, the multiple subsystems are divided into one or more subsystem sets with a configuration order according to the associated information and operation information, each subsystem set includes subsystems whose corresponding configuration operations have a degree of association less than a threshold value of the degree of association, and the subsystems in each subsystem set are configured according to the configuration order. The method of configuring the subsystems one by one in the startup order is replaced by the method of configuring multiple subsystems in each subsystem set at the same time, thereby improving the configuration efficiency of the subsystems in the chip. The above technical solution solves the problem of low simulation configuration efficiency of the chip in the related art and achieves the technical effect of improving the simulation configuration efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 1 is a schematic diagram of a hardware environment for a chip simulation configuration method according to an embodiment of the present application;

[0024] Figure 2 is a flowchart of a chip simulation configuration method according to an embodiment of the present application;

[0025] Figure 3 Schematic diagram of a backdoor simulation configuration method with priority time sharing according to an embodiment of the present application;

[0026] Figure 4 This is a flowchart of a backdoor simulation configuration method with priority time sharing according to an embodiment of the present application;

[0027] Figure 5 This is a structural block diagram of a chip simulation configuration device according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] The method embodiments provided in the embodiments of the present application can be executed in a computer terminal, a device terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 FIG. 1 is a schematic diagram of a hardware environment of a chip simulation configuration method according to an embodiment of the present application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown) a processor 102 (the processor 102 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 104 for storing data. In an exemplary embodiment, the computer terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include Figure 1 More or fewer components than shown, or with Figure 1 Equivalent functions or comparisons shown Figure 1 Shown are different configurations with more functionality.

[0031] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the chip simulation configuration method in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories can be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0032] The transmission device 106 is used to receive or transmit data via a network. A specific example of the aforementioned network may include a wireless network provided by a computer terminal's communications provider. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0033] In this embodiment, a chip simulation configuration method is provided, which is applied to the above-mentioned computer terminal. Figure 2 1 is a flow chart of a chip simulation configuration method according to an embodiment of the present application, the process comprising the following steps:

[0034] Step S202: detecting multiple subsystems included in the chip to be configured and association information and operation information of the chip to be configured, wherein the chip to be configured is a chip to be simulated and tested, the association information is used to indicate the degree of association between configuration operations of each subsystem, the operation information is used to indicate the operation sequence of configuration operations with a degree of association greater than or equal to a threshold value of the degree of association, and the configuration operation is used to control the corresponding subsystem to enter a system state corresponding to the simulation test;

[0035] Step S204: dividing the multiple subsystems into one or more subsystem sets having a configuration order according to the association information and the operation information, wherein each subsystem set includes subsystems whose corresponding configuration operations have a degree of association less than a threshold value of the degree of association;

[0036] Step S206: configure the subsystems in each subsystem set according to the configuration order.

[0037] Through the above steps, by detecting the multiple subsystems included in the chip to be configured and the association information and operation information of the chip to be configured, the multiple subsystems are divided into one or more subsystem sets with a configuration order according to the association information and operation information, each subsystem set includes subsystems whose corresponding configuration operations have a degree of association less than a threshold value of the degree of association, and the subsystems in each subsystem set are configured according to the configuration order. The method of configuring the subsystems one by one in the startup order is replaced by the method of configuring the multiple subsystems in each subsystem set at the same time, thereby improving the configuration efficiency of the subsystems in the chip. The above technical solution solves the problem of low simulation configuration efficiency of the chip in the related art and achieves the technical effect of improving the simulation configuration efficiency of the chip.

[0038] Optionally, in this embodiment, the chip simulation configuration method provided in this application can be applied to, but is not limited to, a simulation configuration tool.

[0039] In the technical solution provided in the above step S202, the chip to be configured may be, but is not limited to, a chip to be subjected to simulation testing. When performing actual simulation testing, it is necessary to configure the various parts of the chip so that the chip to be configured enters a state capable of performing simulation testing. Specifically, the chip to be configured may be, but is not limited to, an integrated circuit (IC) in the design process, which has not yet completed all configuration and verification steps and is in a stage where it needs to pass various tests and configurations to ensure its functional correctness and performance indicators. The configuration of the chip to be configured generally involves setting register values within the subsystem, initializing the state, setting the operating mode, etc., to ensure that the subsystem can work as expected under different test scenarios.

[0040] Optionally, in this embodiment, a subsystem may be, but is not limited to, a combination of components on a chip that implement a specific function. A subsystem may be, but is not limited to, smaller functional units that constitute the chip to be configured. Each subsystem is responsible for a specific function of the chip, but collaborates with each other through data exchange, control signals, etc. to jointly complete the overall function of the chip. The division of subsystems is based on different functions. For example, a complex chip may include a processor subsystem, a memory subsystem, an input / output subsystem, a communication interface subsystem, etc.

[0041] Optionally, in this embodiment, the association information may be used, but is not limited to, to indicate the degree of association between the configuration operations of the subsystems. The determination of whether the configuration operations of the subsystems are associated or not may be based on, but is not limited to, the magnitude relationship between the degree of association indicated by the association information and a threshold value of the degree of association. The determination of whether the configuration operations of the subsystems are associated may be, but is not limited to, when the degree of association indicated by the association information is greater than or equal to the threshold value of the degree of association; and when the degree of association indicated by the association information is less than the threshold value of the degree of association, the determination of whether the configuration operations of the subsystems are not associated.

[0042] Optionally, in this embodiment, the operation information may be, but is not limited to, an operation sequence for indicating configuration operations with a correlation degree greater than or equal to a correlation degree threshold.

[0043] Optionally, in an embodiment, the corresponding subsystem can be made to enter the system state corresponding to the simulation test by executing the configuration operation corresponding to each subsystem, but is not limited to. After each subsystem enters the corresponding system state, the chip to be configured enters a state capable of performing simulation testing.

[0044] Optionally, in this embodiment, the configuration operation may include, but is not limited to, writing the configuration files corresponding to each subsystem into the corresponding registers of each subsystem through backdoor configuration.

[0045] Optionally, in this embodiment, the signal interactions and dependencies between subsystems can be identified by analyzing the chip's hardware description language (such as Verilog, VHDL, etc.) code or design documents, thereby inferring the associated information and operation sequence of the chip to be configured.

[0046] Optionally, in this embodiment, a preliminary version of the chip design can be run in a simulation environment, but is not limited to running it, and the order and impact of subsystem configurations can be observed through test cases or specific test modes to obtain correlation information and operation information.

[0047] In the technical solution provided in the above step S204, the division of the multiple subsystems into one or more subsystem sets having a configuration order according to the association information and the operation information can be achieved, but is not limited to, in the following manner: dividing the multiple subsystems into a first subsystem set and a second subsystem set according to the association information, wherein each first subsystem in the first subsystem set has no related subsystem, each second subsystem in the second subsystem set has a related subsystem, and the degree of association between the configuration operation of the related subsystem and the configuration operation of the corresponding second subsystem is greater than or equal to a correlation degree threshold; creating a reference number of reference system sets, wherein the reference number is the number of subsystems included in the second subsystem set; dividing each second subsystem in the second subsystem set into each reference system set one by one, and dividing the first subsystem set into multiple reference subsystem sets, wherein each reference system set includes a second subsystem; determining the configuration order of each reference subsystem set according to the operation order of the configuration operation of the second subsystem and the configuration operation of the related subsystem of the second subsystem, to obtain one or more subsystem sets having a configuration order.

[0048] In the technical solution provided in the above step S206, configuring the subsystems in each subsystem set in accordance with the configuration order may include, but is not limited to, using a finite state machine to control the configuration order of the subsystem set, and the state machine advances to the next state by receiving a configuration start signal and a configuration completion signal: designing the state of the finite state machine, each state represents a configuration stage of a subsystem set; defining state transition logic, and advancing the state based on the configuration completion signal to ensure that the configuration operation follows a predetermined order; in each state, the finite state machine schedules the corresponding subsystem environment for configuration; adding a timeout detection and error handling mechanism to the state machine, so that when the configuration fails to be completed on time, it can identify and take remedial measures.

[0049] In an exemplary embodiment, it is possible, but not limited to, that when the chip to be configured includes both subsystems that can implement backdoor configuration and subsystems that cannot be backdoor configured, one or more subsystems that cannot be backdoor configured are first extracted, and the configuration files corresponding to each subsystem are transferred to the corresponding subsystem in a frontdoor configuration manner; then, for the subsystem that can implement backdoor configuration, the aforementioned chip simulation configuration method is used to implement the configuration of the subsystem.

[0050] As an optional implementation, multiple subsystems are divided into one or more subsystem sets with a configuration order according to association information and operation information, including: establishing a target number of initial sets according to the association information, wherein the target number is the maximum number of subsystems with an association relationship, and subsystems whose association degree indicated by the association information is greater than or equal to an association degree threshold have an association relationship; allocating multiple subsystems to each initial set according to the operation information and determining the configuration order of the target number of initial sets to obtain the target number of subsystem sets with a configuration order, wherein the subsystems in each subsystem set do not have an association relationship and are located in the same arrangement position in each configuration chain, and the configuration chain includes subsystems with an association relationship arranged in an operation order.

[0051] Optionally, in this embodiment, the number of initial sets can be but is not limited to the maximum number of subsystems with associated relationships in the chip to be configured. For example, in a chip to be configured, subsystem 1, subsystem 2 and subsystem 3 have an associated relationship, and subsystem 4 and subsystem 5 have an associated relationship. Then, for the chip to be configured, three initial sets need to be established.

[0052] Optionally, in this embodiment, the configuration chain can be established based on, but is not limited to, the operation sequence between the configuration operations of multiple subsystems with an associated relationship. For example, for a chip to be configured, which includes subsystem 6, subsystem 7 and subsystem 8 with an associated relationship, the operation information of the chip to be configured indicates that the configuration operation of subsystem 7 must be performed after the configuration operation of subsystem 6, and the configuration operation of subsystem 8 must be performed after the configuration operation of subsystem 9, then a configuration chain can be obtained: subsystem 6->subsystem 7->subsystem 8.

[0053] As an optional implementation, an initial set of target quantities is established based on association information, including: dividing multiple subsystems into one or more reference sets based on the association information, wherein the subsystems in each reference set have an association relationship; extracting a target set with the largest number of included subsystems from one or more reference sets; determining the number of subsystems included in the target set as the target quantity; and establishing an empty set of the target quantity to obtain the initial set of the target quantity.

[0054] Optionally, in this embodiment, multiple subsystems may be divided into one or more reference sets first, but are not limited to it. The subsystems in each reference set are associated with each other, and the number of subsystems in each reference set may be multiple or one.

[0055] As an optional implementation, multiple subsystems are allocated to each initial set according to operation information and the configuration order of the target number of initial sets is determined to obtain the target number of subsystem sets with the configuration order, including: converting one or more reference sets into one or more configuration chains according to the operation information; dividing the subsystems located at the same arrangement position in each configuration chain into the same initial set, and establishing a configuration order to obtain the target number of subsystem sets with the configuration order, wherein the arrangement position of each initial set in the configuration order is the arrangement order of the target subsystems included in each initial set in the target configuration chain, and the target configuration chain is the configuration chain converted by the target set.

[0056] Optionally, in this embodiment, each configuration chain may, but is not limited to, follow the same arrangement rule. For example, each subsystem may, but is not limited to, be arranged in a front-to-back arrangement order according to the operation sequence of the configuration operations corresponding to each subsystem, or each subsystem may, but is not limited to, be arranged in a back-to-front arrangement order according to the operation sequence of the configuration operations corresponding to each subsystem.

[0057] Optionally, in this embodiment, it is possible but not limited to obtaining a target number of subsystem sets by dividing the subsystems located at the same arrangement position in each configuration chain into the same initial set, then detecting the arrangement rules in the target configuration chain and the arrangement order of the target subsystems included in each subsystem set in the target configuration chain, and establishing a configuration order of the target number of subsystem sets based on the detected arrangement rules and the arrangement order of the target subsystems included in each subsystem set in the target configuration chain, to obtain a target number of subsystem sets with a configuration order.

[0058] Through the above content, the subsystems that can be configured together are divided into the same subsystem set, which makes it possible to configure each subsystem in the subsystem set at the same time according to the configuration order of the subsystem set.

[0059] As an optional implementation, a control environment and multiple subsystem environments are established in the simulation configuration tool, and the multiple subsystem environments correspond one-to-one to the multiple subsystems. Each subsystem environment is used to configure the corresponding subsystem, and the subsystems in each subsystem set are configured according to the configuration order, including: the control environment extracts subsystem sets one by one from one or more subsystem sets as target subsystem sets according to the configuration order; the control environment searches for subsystem environments corresponding to the subsystems included in the target subsystem set from multiple subsystem environments to obtain one or more target subsystem environments; the control environment simultaneously controls one or more target subsystem environments to configure the corresponding subsystems until one or more target subsystem environments complete the configuration of the corresponding subsystems.

[0060] Optionally, in this embodiment, a control environment and multiple subsystem environments corresponding to multiple subsystems may be established in the simulation configuration tool, but is not limited to the above. Each subsystem environment is used to configure the corresponding subsystem.

[0061] Optionally, in this embodiment, the control environment, also often referred to as the top-level environment or master control environment (top env), is the coordinator and manager of the entire simulation configuration process. The main responsibilities of the control environment may include, but are not limited to: Configuration sequence management: Based on the configuration priorities and dependencies between subsystems, the control environment is responsible for planning and executing the order of configuration to ensure that high-priority subsystems complete the configuration before the low-priority subsystems that depend on them. Signal scheduling: During the configuration process, the control environment is responsible for sending a configuration start signal to the subsystem environment and receiving a configuration completion signal. It coordinates the configuration time and sequence of each subsystem during the simulation process by scheduling these signals. Resource allocation: The control environment may also need to manage resource allocation in the simulation, such as the resources of the simulator, the supply of test data, etc., to ensure that the subsystem environment can obtain the necessary resource support during configuration.

[0062] Optionally, in this embodiment, the subsystem environment may be, but is not limited to, a simulation environment directly associated with each subsystem in the design to be tested. Each subsystem environment is designed for a specific subsystem to enable configuration and verification of the subsystem. The main functions of the subsystem environment may include, but are not limited to: Interface adaptation: The subsystem environment provides a software interface that matches the subsystem hardware interface to facilitate the execution of configuration operations and the injection of test data. Configuration execution: When the configuration start signal sent by the control environment is received, the subsystem environment performs specific configuration operations to adjust the subsystem to the desired system state. Response feedback: After the configuration is completed, the subsystem environment will send a configuration completion signal to the control environment, indicating that it is ready or entering the next configuration stage. Status monitoring: The subsystem environment may also need to monitor the status of the subsystem during the configuration process to ensure the correctness and effectiveness of the configuration operation.

[0063] Optionally, in this embodiment, the control environment can, but is not limited to, determine the current target subsystem set to be configured according to the configuration order. After determining the current target subsystem set to be configured, the target subsystem environment corresponding to each target subsystem in the target subsystem set is searched, and the target subsystem corresponding to the configuration of the found target subsystem environment is controlled.

[0064] As an optional implementation, the control environment simultaneously controls one or more target subsystem environments to configure corresponding subsystems until one or more target subsystem environments complete the configuration of the corresponding subsystems, including: the control environment simultaneously sends a configuration start signal to one or more target subsystem environments, wherein each target subsystem environment is used to configure the corresponding subsystem in response to the configuration start signal; and the control environment detects the configuration status of each target subsystem environment until the detected configuration status indicates that the corresponding target subsystem environment has completed the configuration of the corresponding subsystem.

[0065] Optionally, in this embodiment, the control environment may, but is not limited to, simultaneously send a configuration start signal to one or more target subsystem environments to trigger the one or more target subsystem environments to simultaneously start configuring corresponding subsystems.

[0066] As an optional implementation, the control environment detects the configuration status of each target subsystem environment until it is detected that the configuration status indicates that the corresponding target subsystem environment has completed the configuration of the corresponding subsystem, including: the control environment receives the configuration end signal returned by each target subsystem environment within the target time period after sending the configuration start signal, wherein each target subsystem environment is used to send a configuration end signal to the control environment when the corresponding subsystem is successfully configured; when the control environment receives the configuration end signal returned by all target subsystem environments within the target time period, it is determined that it is detected that the configuration status indicates that the corresponding target subsystem environment has completed the configuration of the corresponding subsystem; when the control environment does not receive the configuration end signal returned by all target subsystem environments within the target time period, it stops executing the step of extracting subsystem sets one by one from one or more subsystem sets as target subsystem sets in the configuration order.

[0067] Optionally, in this embodiment, it is possible but not limited to the case that the control environment does not receive the configuration end signal returned by all target subsystem environments within the target time period, and it is determined that the configuration of the target subsystem for which the control environment does not receive the configuration end signal within the target time period has failed, and the fault needs to be eliminated to avoid the impact of the fault on subsequent configurations. Therefore, it is necessary to stop executing the step of extracting subsystem sets one by one from one or more subsystem sets as target subsystem sets in the configuration order.

[0068] In order to better understand the above process, the above process is described below in conjunction with optional embodiments, but it is not used to limit the technical solutions of the embodiments of the present application.

[0069] In this embodiment, a universal backdoor simulation configuration method with priority time sharing is provided, which can be applied to all configurable system-level integration verifications and meet the configuration priority requirements of each subsystem. Figure 3 Schematic diagram of a backdoor simulation configuration method with priority time sharing according to an embodiment of the present application, such as Figure 3 As shown, for a chip to be configured including subsystem A (i.e., DUT (Design Under Test) A), subsystem B (i.e., DUT B), subsystem C (i.e., DUT C), subsystem D (i.e., DUT D), subsystem E (i.e., DUT E) and subsystem F (i.e., DUT F), it is possible but not limited to time-dividing the configuration priority of each subsystem in the chip to be configured, and sending a configuration start signal to multiple subsystems of the same level with high priority (subsystems of the same level are subsystems with no configuration association (i.e., no association relationship)) in the top-level env (Environment) (i.e., control environment). When the top-level env receives the response signal that the configuration of the subsystem is completed, the top-level env continues to send a configuration start signal to the subsystems of the same level at the next level, and so on, to complete the entire system-level integrated simulation configuration. Specifically, it is possible but not limited to first time-dividing the priority of the subsystems in the entire system level (i.e., dividing them into one or more subsystem sets with a configuration order), rather than directly performing backdoor configuration on each subsystem in turn. Treat subsystems of the same priority as a process block, such as Figure 3 As shown, L1 represents high priority, L2 represents low priority, the solid arrow represents a configuration start signal, and the dotted arrow represents a configuration end signal. The top-level env declares and instantiates the subsystem env of the entire chip to be configured. In the main_phase, it first sends a configuration start signal to the same-level subsystem env with high priority (that is, the configuration order is earlier), such as subsystems A, B, and C. After the subsystem env receives the configuration start signal, it performs backdoor configuration on subsystems A, subsystem B, and subsystem C at the same time. When the configuration completion signal (that is, the configuration end signal) of subsystems A, B, and C is returned to the top-level env, it triggers the top-level env to send a configuration start signal to the same-level subsystems D, E, and F with low priority (that is, the configuration order is later). Subsystems D, E, and F perform backdoor configuration at the same time. When the configuration of subsystems D, E, and F is completed, the subsystem env corresponding to subsystems D, E, and F will send a configuration completion signal to the top-level env. After receiving the configuration completion signal, the top-level env will send a configuration start indication signal to multiple subsystems at the lower level, and so on, until the configuration completion signal of each subsystem with the lowest priority is returned to the top-level env, and the entire system-level configuration is completed.

[0070] Figure 4 This is a flow chart of a backdoor simulation configuration method with priority time sharing according to an embodiment of the present application. Figure 4 As shown in the figure, the backdoor simulation configuration method with priority time sharing includes the following steps:

[0071] Step S0: The top-level env sends a configuration start signal to the envs of each high-priority subsystem;

[0072] Step S1: After receiving the configuration start signal, each high-priority subsystem env configures the design under test. After the configuration is completed, it returns a configuration end signal to the top-level env;

[0073] Step S2: The top-level env waits for the configuration completion signal of each high-priority subsystem;

[0074] Step S3: If all configuration end signals are not received within a configurable time (i.e., within the target time period after the control environment sends the configuration start signal), the top-level env will print the simulation exception information and exit the simulation platform;

[0075] Step S4: If the top-level env receives all the configuration end signals within a certain period of time, the top-level env will send a configuration start signal to each subsystem env with the next highest priority to configure the design under test. After the configuration is completed, the top-level env will return a configuration end signal to the top-level env.

[0076] Step S5: The top-level env waits for the configuration completion signal of each subsystem with the second highest priority;

[0077] Step S6: If the configuration end signal is not received within a period of time, the top-level env will print the simulation exception information and exit the simulation platform;

[0078] Step S7: If the top-level env receives the configuration completion signal within a configurable time, it configures the subsystems of each priority level in turn and returns the configuration completion signal to the top-level env, indicating that the configuration of the entire system level is completed.

[0079] Through the above method, the simulation efficiency of system-level integration verification can be improved, which is especially obvious for chips with larger specifications. The above method is universal for the integration verification of any chip, and the verification personnel can divide the configuration priority of each subsystem according to the chip verification requirements. In the configuration stage, one or more subsystems with high priority are configured at the same time, and then one or more subsystems of the lower level are triggered to be configured in parallel, and so on. The method given in this application meets the requirements of each subsystem for configuration priority in the configuration stage of system-level integration verification, and at the same time solves the problem of low efficiency of system-level integration verification simulation caused by long configuration time.

[0080] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software and the necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0081] Figure 5 is a structural block diagram of a chip simulation configuration device according to an embodiment of the present application; Figure 5 As shown, the chip simulation configuration device is applied to the simulation configuration tool, and the chip simulation configuration device includes:

[0082] Detection module 502 is configured to detect multiple subsystems included in the chip to be configured, as well as association information and operation information of the chip to be configured. The chip to be configured is a chip to be simulated and tested. The association information is used to indicate the degree of association between configuration operations of each subsystem. The operation information is used to indicate the operation sequence of configuration operations with a degree of association greater than or equal to a threshold value of the degree of association. The configuration operation is used to control the corresponding subsystem to enter the system state corresponding to the simulation test.

[0083] a partitioning module 504 configured to partition the plurality of subsystems into one or more subsystem sets having a configuration order based on the association information and the operation information, wherein each subsystem set includes subsystems whose corresponding configuration operations have a degree of association less than a threshold value of the degree of association;

[0084] The configuration module 506 is used to configure the subsystems in each subsystem set according to the configuration order.

[0085] Through the above embodiment, by detecting the multiple subsystems included in the chip to be configured and the association information and operation information of the chip to be configured, the multiple subsystems are divided into one or more subsystem sets with a configuration order according to the association information and operation information, each subsystem set includes subsystems whose corresponding configuration operations have a degree of association less than a threshold value of the degree of association, and the subsystems in each subsystem set are configured according to the configuration order. The method of configuring the subsystems one by one in the startup order is replaced by the method of configuring the multiple subsystems in each subsystem set at the same time, thereby improving the configuration efficiency of the subsystems in the chip. The above technical solution solves the problem of low simulation configuration efficiency of the chip in the related art and achieves the technical effect of improving the simulation configuration efficiency of the chip.

[0086] In an exemplary embodiment, the partitioning module includes: an establishment unit for establishing an initial set of a target number based on association information, wherein the target number is the maximum number of subsystems with an association relationship, and subsystems whose association degree indicated by the association information is greater than or equal to an association degree threshold have an association relationship; an allocation unit for allocating multiple subsystems to each initial set based on operation information and determining a configuration order of the initial set of the target number to obtain a target number of subsystem sets with a configuration order, wherein the subsystems in each subsystem set do not have an association relationship and are located in the same arrangement position in each configuration chain, and the configuration chain includes subsystems with an association relationship arranged in an operation order.

[0087] Optionally, the establishment unit is also used to: divide multiple subsystems into one or more reference sets based on association information, wherein the subsystems in each reference set have an association relationship; extract a target set with the largest number of subsystems included from one or more reference sets; determine the number of subsystems included in the target set as the target number; establish an empty set of the target number to obtain an initial set of the target number.

[0088] Optionally, the allocation unit is further used to: convert one or more reference sets into one or more configuration chains according to the operation information; divide the subsystems located at the same arrangement position in each configuration chain into the same initial set, and establish a configuration sequence to obtain a target number of subsystem sets with a configuration sequence, wherein the arrangement position of each initial set in the configuration sequence is the arrangement order of the target subsystems included in each initial set in the target configuration chain, and the target configuration chain is the configuration chain into which the target set is converted.

[0089] Optionally, a control environment and multiple subsystem environments are established in the simulation configuration tool, and the multiple subsystem environments correspond one-to-one to the multiple subsystems. Each subsystem environment is used to configure the corresponding subsystem. The configuration module includes: an extraction unit, which is used for the control environment to extract subsystem sets one by one from one or more subsystem sets as target subsystem sets in the configuration order; a search unit, which is used for the control environment to search for subsystem environments corresponding to subsystems included in the target subsystem set from multiple subsystem environments to obtain one or more target subsystem environments; and a control unit, which is used for the control environment to simultaneously control one or more target subsystem environments to configure the corresponding subsystems until one or more target subsystem environments complete the configuration of the corresponding subsystems.

[0090] Optionally, the control unit is further used to: send a configuration start signal from the control environment to one or more target subsystem environments at the same time, wherein each target subsystem environment is used to configure the corresponding subsystem in response to the configuration start signal; and detect the configuration status of each target subsystem environment by the control environment until the configuration status is detected to indicate that the corresponding target subsystem environment has completed the configuration of the corresponding subsystem.

[0091] Optionally, the control unit is further used to: receive, by the control environment, a configuration end signal returned by each target subsystem environment within a target time period after sending the configuration start signal, wherein each target subsystem environment is used to send a configuration end signal to the control environment when the corresponding subsystem is successfully configured; when the control environment receives the configuration end signal returned by all target subsystem environments within the target time period, determine that the detected configuration status is used to indicate that the corresponding target subsystem environment has completed the configuration of the corresponding subsystem; when the control environment does not receive the configuration end signal returned by all target subsystem environments within the target time period, stop executing the step of extracting subsystem sets one by one from one or more subsystem sets as target subsystem sets in the configuration order.

[0092] An embodiment of the present application further provides a storage medium, which includes a stored program, wherein the program executes any of the above-mentioned chip simulation configuration methods when running.

[0093] Optionally, in this embodiment, the storage medium may be configured to store program codes for executing the following steps:

[0094] S1, detecting multiple subsystems included in a chip to be configured and association information and operation information of the chip to be configured, wherein the chip to be configured is a chip to be simulated and tested, the association information is used to indicate the degree of association between configuration operations of various subsystems, the operation information is used to indicate the operation sequence of configuration operations with a degree of association greater than or equal to a threshold value of the degree of association, and the configuration operation is used to control the corresponding subsystem to enter a system state corresponding to the simulation test;

[0095] S2, dividing the multiple subsystems into one or more subsystem sets having a configuration order according to the association information and the operation information, wherein each subsystem set includes subsystems whose corresponding configuration operations have a degree of association less than a threshold value of the degree of association;

[0096] S3, configure the subsystems in each subsystem set according to the configuration order.

[0097] An embodiment of the present application further provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above chip simulation configuration method embodiments.

[0098] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0099] Optionally, in this embodiment, the processor may be configured to execute the following steps through a computer program:

[0100] S1, detecting multiple subsystems included in a chip to be configured and association information and operation information of the chip to be configured, wherein the chip to be configured is a chip to be simulated and tested, the association information is used to indicate the degree of association between configuration operations of various subsystems, the operation information is used to indicate the operation sequence of configuration operations with a degree of association greater than or equal to a threshold value of the degree of association, and the configuration operation is used to control the corresponding subsystem to enter a system state corresponding to the simulation test;

[0101] S2, dividing the multiple subsystems into one or more subsystem sets having a configuration order according to the association information and the operation information, wherein each subsystem set includes subsystems whose corresponding configuration operations have a degree of association less than a threshold value of the degree of association;

[0102] S3, configure the subsystems in each subsystem set according to the configuration order.

[0103] Optionally, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store program codes.

[0104] Optionally, specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be described in detail here.

[0105] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices. Alternatively, they can be implemented using program code executable by the computing device, so that they can be stored in a storage device and executed by the computing device. In some cases, the steps shown or described can be performed in a different order than herein, or they can be made into separate integrated circuit modules, or multiple modules or steps can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0106] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A chip simulation configuration method, characterized in that: Applied to a simulation configuration tool, the method includes: detecting multiple subsystems included in a chip to be configured and association information and operation information of the chip to be configured, wherein the chip to be configured is a chip to be simulated and tested, the association information is used to indicate the degree of association between configuration operations of various subsystems, the operation information is used to indicate the operation sequence of configuration operations whose association degree is greater than or equal to an association threshold, and the configuration operation is used to control the corresponding subsystem to enter a system state corresponding to the simulation test; Dividing the plurality of subsystems into one or more subsystem sets having a configuration order according to the association information and the operation information, wherein each subsystem set includes subsystems for which the association degree between corresponding configuration operations is less than the association degree threshold; The subsystems in each of the subsystem sets are configured in the configuration order.

2. The method according to claim 1, characterized in that The dividing the plurality of subsystems into one or more subsystem sets having a configuration order according to the association information and the operation information includes: Establishing an initial set of target numbers according to the association information, wherein the target number is a maximum number of the subsystems having an association relationship, and the subsystems having an association degree greater than or equal to an association degree threshold indicated by the association information have the association relationship; According to the operation information, the multiple subsystems are allocated to each of the initial sets and the configuration order of the target number of the initial sets is determined to obtain the target number of subsystem sets with the configuration order, wherein the subsystems in each of the subsystem sets do not have the association relationship and are located in the same arrangement position in each configuration chain, and the configuration chain includes subsystems with the association relationship arranged in the operation order.

3. The method according to claim 2, characterized in that The step of establishing an initial set of target quantities according to the association information includes: Dividing the plurality of subsystems into one or more reference sets according to the association information, wherein the subsystems in each of the reference sets have the association relationship; Extracting a target set including a largest number of subsystems from the one or more reference sets; determining the number of subsystems included in the target set as the target number; An empty set of the target number is established to obtain the initial set of the target number.

4. The method according to claim 3, characterized in that The allocating the plurality of subsystems to the respective initial sets according to the operation information and determining the configuration order of the target number of the initial sets to obtain the target number of subsystem sets having the configuration order includes: converting the one or more reference sets into one or more configuration chains according to the operation information; The subsystems located at the same arrangement position in each of the configuration chains are divided into the same initial set, and the configuration sequence is established to obtain the target number of subsystem sets with the configuration sequence, wherein the arrangement position of each of the initial sets in the configuration sequence is the arrangement sequence of the target subsystems included in each of the initial sets in the target configuration chain, and the target configuration chain is the configuration chain into which the target set is converted.

5. The method according to claim 1, wherein The simulation configuration tool establishes a control environment and multiple subsystem environments, wherein the multiple subsystem environments correspond one-to-one to the multiple subsystems, and each subsystem environment is used to configure the corresponding subsystem. The configuring of each subsystem in the subsystem set according to the configuration order includes: Extracting, by the control environment, subsystem sets from the one or more subsystem sets one by one as target subsystem sets according to the configuration order; The control environment searches for subsystem environments corresponding to subsystems included in the target subsystem set from the multiple subsystem environments to obtain one or more target subsystem environments; The control environment simultaneously controls the one or more target subsystem environments to configure corresponding subsystems until the one or more target subsystem environments complete the configuration of corresponding subsystems.

6. The method according to claim 5, characterized in that The controlling environment simultaneously controls the one or more target subsystem environments to configure corresponding subsystems until the one or more target subsystem environments complete configuration of corresponding subsystems, including: The control environment simultaneously sends a configuration start signal to the one or more target subsystem environments, wherein each target subsystem environment is configured to configure a corresponding subsystem in response to the configuration start signal; The control environment detects the configuration status of each target subsystem environment until the configuration status is detected to indicate that the corresponding target subsystem environment has completed the configuration of the corresponding subsystem.

7. The method according to claim 6, characterized in that The control environment detects the configuration status of each target subsystem environment until the configuration status is detected to indicate that the corresponding target subsystem environment has completed the configuration of the corresponding subsystem, including: The control environment receives, within a target time period after sending the configuration start signal, a configuration end signal returned by each of the target subsystem environments, wherein each of the target subsystem environments is configured to send the configuration end signal to the control environment if the corresponding subsystem is successfully configured; When the control environment receives the configuration completion signals returned by all the target subsystem environments within the target time period, it is determined that the configuration status detected is used to indicate that the corresponding target subsystem environments have completed the configuration of the corresponding subsystems; If the control environment does not receive the configuration end signal returned by all the target subsystem environments within the target time period, the step of extracting subsystem sets one by one as target subsystem sets from the one or more subsystem sets in the configuration order is stopped.

8. A chip simulation configuration device, characterized in that: Applied to a simulation configuration tool, the device includes: a detection module, configured to detect multiple subsystems included in a chip to be configured, as well as association information and operation information of the chip to be configured, wherein the chip to be configured is a chip to be simulated and tested, the association information is used to indicate the degree of association between configuration operations of various subsystems, the operation information is used to indicate the operation sequence of configuration operations whose degree of association is greater than or equal to a correlation threshold, and the configuration operations are used to control the corresponding subsystem to enter a system state corresponding to the simulation test; a partitioning module, configured to partition the plurality of subsystems into one or more subsystem sets having a configuration order according to the association information and the operation information, wherein each subsystem set includes subsystems for which the degree of association between corresponding configuration operations is less than the association degree threshold; A configuration module is used to configure each subsystem in the subsystem set according to the configuration order.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein the program executes the method according to any one of claims 1 to 7 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to execute the method according to any one of claims 1 to 7 through the computer program.

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