Voltage generator and display device

Abstract

The invention discloses a voltage generator and a display device. The voltage generator includes: an input circuit outputting a first request signal and a second request signal in response to a first voltage data signal and a second voltage data signal and a first feedback voltage and a second feedback voltage; a FIFO and priority logic that outputs one of the first selection signal and the second selection signal at an active level in synchronization with the clock signal when at least one of the first request signal and the second request signal is at the active level; a switching logic that outputs a plurality of switching signals in response to one of the first selection signal and the second selection signal at an active level; and a voltage converter that converts an input voltage into a first output voltage and a second output voltage, respectively, in response to the plurality of switching signals, and outputs a first feedback voltage and a second feedback voltage corresponding to the first output voltage and the second output voltage, respectively. When the first request signal and the second request signal are simultaneously at the active level, the FIFO and the priority logic output one of the first selection signal and the second selection signal at the active level according to the priority.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0016406, filed on February 2, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a voltage generator and a display device including the voltage generator. Background Art

[0004] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles typically include display devices capable of displaying images. Such display devices require various driving voltages to display images, and the driving voltages need to maintain a stable voltage level to ensure that the display devices provide high-quality images. Summary of the Invention

[0005] Embodiments of the present disclosure provide a voltage generator that generates a voltage having a stable voltage level and a display device including the voltage generator.

[0006] According to an embodiment of the present disclosure, a voltage generator includes: an input circuit that outputs first and second request signals in response to first and second voltage data signals and first and second feedback voltages; a first first-order input field (FIFO) and priority logic that outputs one of a first selection signal and a second selection signal at an active level in synchronization with a clock signal when at least one of the first and second request signals is at an active level; switching logic that outputs a plurality of switching signals in response to one of the first and second selection signals being at an active level; and a voltage converter that converts the input voltage into a first and second output voltage, respectively, in response to the plurality of switching signals, and outputs a first and second feedback voltage corresponding to the first and second output voltages, respectively. When the first and second request signals are both at an active level, the FIFO and priority logic output one of the first and second selection signals at an active level according to the priority level.

[0007] According to an embodiment, the input circuit may include: a first digital-to-analog converter, which converts the first voltage data signal into a first reference voltage; a first amplifier, which compares the first feedback voltage with the first reference voltage and outputs a first request signal; a second digital-to-analog converter, which converts the second voltage data signal into a second reference voltage; and a second amplifier, which compares the second feedback voltage with the second reference voltage and outputs a second request signal.

[0008] According to an embodiment, when a voltage level of the first feedback voltage is lower than or equal to a voltage level of the first reference voltage, the first amplifier may output the first request signal at an active level.

[0009] According to an embodiment, when the first request signal and the second request signal are simultaneously at an active level, the FIFO and the priority logic may output the first selection signal at an active level.

[0010] According to an embodiment, when the period of the clock signal is "P" and the first request signal and the second request signal are simultaneously in the active level, the FIFO and priority logic may output the first selection signal and the second selection signal so that the period of the first selection signal is 2P or less.

[0011] According to an embodiment, the input circuit may further output a third request signal in response to a third data signal and a third feedback voltage. When at least one of the first request signal, the second request signal, and the third request signal is at a valid level, the FIFO and the priority logic may output any one of the first selection signal, the second selection signal, and the third selection signal at a valid level in synchronization with the clock signal. The switching logic may output a plurality of switching signals in response to one of the first selection signal, the second selection signal, and the third selection signal being at a valid level. The voltage converter may convert the input voltage into a third output voltage in response to the plurality of switching signals, and may further output a third feedback voltage corresponding to the third output voltage.

[0012] According to an embodiment, the first request signal may have a higher priority than the second request signal, and the second request signal may have a higher priority than the third request signal.

[0013] According to an embodiment, when the period of the clock signal is "P" and the first request signal, the second request signal and the third request signal are simultaneously at the valid level, the FIFO and the priority logic may output the first selection signal, the second selection signal and the third selection signal so that the period of the first selection signal is 2P or less and the period of each of the second selection signal and the third selection signal is 4P or less.

[0014] According to an embodiment, the first voltage data signal and the second voltage data signal may be signals corresponding to target voltage levels of the first output voltage and the second output voltage, respectively.

[0015] According to an embodiment, the voltage converter may include a single inductor multiple output (SIMO) structure.

[0016] According to an embodiment of the present disclosure, a display device includes: a display panel; a scan driving circuit that provides a scan signal to the display panel; a data driving circuit that provides a data signal to the display panel; a driving controller that outputs first and second voltage data signals and a clock signal; and a voltage generator that provides first and second driving voltages to the display panel. The voltage generator includes: an input circuit that outputs first and second request signals in response to the first and second voltage data signals and first and second feedback voltages; a first first-order field-of-view (FIFO) and priority logic that outputs one of a first selection signal and a second selection signal at an active level in synchronization with a clock signal when at least one of the first and second request signals is at an active level; switching logic that outputs a plurality of switching signals in response to one of the first and second selection signals being at an active level; and a voltage converter that converts the input voltage into a first and second driving voltages, respectively, in response to the plurality of switching signals, and outputs a first and second feedback voltage corresponding to the first and second driving voltages, respectively. When the first request signal and the second request signal are at active levels at the same time, the FIFO and the priority logic output one of the first selection signal and the second selection signal at an active level according to the priority.

[0017] According to an embodiment, the input circuit may include: a first digital-to-analog converter, which converts the first voltage data signal into a first reference voltage; a first amplifier, which compares the first feedback voltage with the first reference voltage and outputs a first request signal; a second digital-to-analog converter, which converts the second voltage data signal into a second reference voltage; and a second amplifier, which compares the second feedback voltage with the second reference voltage and outputs a second request signal.

[0018] According to an embodiment, when a voltage level of the first feedback voltage is lower than or equal to a voltage level of the first reference voltage, the first amplifier may output the first request signal at an active level.

[0019] According to an embodiment, when the first request signal and the second request signal are simultaneously at an active level, the FIFO and the priority logic may output the first selection signal at an active level.

[0020] According to an embodiment, when the period of the clock signal is "P" and the first request signal and the second request signal are simultaneously in the active level, the FIFO and priority logic may output the first selection signal and the second selection signal so that the period of the first selection signal is 2P or less.

[0021] According to an embodiment, the input circuit may further output a third request signal in response to a third data signal and a third feedback voltage. When at least one of the first request signal, the second request signal, and the third request signal is at a valid level, the FIFO and the priority logic may output any one of the first selection signal, the second selection signal, and the third selection signal at a valid level in synchronization with the clock signal. The switching logic may output a plurality of switching signals in response to one of the first selection signal, the second selection signal, and the third selection signal being at a valid level. The voltage converter may convert the input voltage into a third drive voltage in response to the plurality of switching signals, and may further output a third feedback voltage corresponding to the third drive voltage.

[0022] According to an embodiment, the first request signal may have a higher priority than the second request signal, and the second request signal may have a higher priority than the third request signal.

[0023] According to an embodiment, when the period of the clock signal is "P" and the first request signal, the second request signal and the third request signal are simultaneously at the valid level, the FIFO and the priority logic may output the first selection signal, the second selection signal and the third selection signal so that the period of the first selection signal is 2P or less and the period of each of the second selection signal and the third selection signal is 4P or less.

[0024] According to an embodiment, the voltage converter may include a single inductor multiple output (SIMO) structure.

[0025] According to an embodiment, the first voltage data signal and the second voltage data signal may be signals corresponding to target voltage levels of the first output voltage and the second output voltage, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2is a circuit diagram illustrating a voltage generator according to an embodiment of the present disclosure.

[0029] Figure 3A 、 Figure 3B and Figure 3C is a timing diagram illustrating first to sixth switching signals output from the switching logic.

[0030] Figure 4 and Figure 5 is a timing diagram for the operation of a voltage generator according to an embodiment of the present disclosure.

[0031] Figure 6 is a timing diagram illustrating first and third request signals and first and second selection signals according to voltage levels of the first and third feedback voltages.

[0032] Figure 7A and Figure 7B 1 and 2 are timing diagrams illustrating operations of the FIFO and the priority logic and the voltage converter according to the voltage levels of the first driving voltage, the second driving voltage, and the third driving voltage, respectively.

[0033] Figure 8A and Figure 8B is a timing diagram illustrating operations of the FIFO and the priority logic and the voltage converter when the priority of the second driving voltage is higher than the priority of the third driving voltage. DETAILED DESCRIPTION

[0034] In the specification, a component (or region, layer, part, etc.) referred to as being "on," "connected to" or "coupled to" another component means that the former can be directly on, directly connected to or directly coupled to the latter, or can be on, connected to or coupled to the latter via one or more intervening components.

[0035] The term "and / or" includes one or more combinations of the associated listed items. Unless otherwise specified, singular forms include plural forms.

[0036] The terms "first," "second," and the like are used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component, and vice versa, without departing from the spirit or scope of the present disclosure.

[0037] The terms "under," "beneath," "on," and "above" are used herein to describe relationships between components. The terms are relative and may be specifically described with reference to directions indicated in the drawings.

[0038] The terms “include,” “comprise,” “have,” etc. specify the presence of features, numbers, steps, operations, elements or components or a combination thereof described in the specification, but do not exclude the presence or additional possibility of one or more other features, numbers, steps, operations, elements or components or a combination thereof.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as that commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0040] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Like reference numerals in the description and various drawings refer to like components. In addition, in the drawings, the thickness, proportion, and size of components may be exaggerated for the purpose of effectively describing the technical content.

[0041] Figure 1 is a block diagram illustrating a display device DD according to an embodiment of the present disclosure.

[0042] refer to Figure 1 , the display device DD includes a display panel DP, a driving controller 100 , a data driving circuit 200 and a voltage generator 300 .

[0043] The driving controller 100 receives the image signal RGB and the control signal CTRL. The driving controller 100 converts the image signal RGB into the image data signal DS. The driving controller 100 outputs the emission control signal ECS, the scan control signal SCS, the data control signal DCS, the image data signal DS and the voltage control signal VCS.

[0044] The data driving circuit 200 receives a data control signal DCS and an image data signal DS from the driving controller 100. The data driving circuit 200 converts the image data signal DS into a data signal and then outputs the data signal to a plurality of data lines DL1 to DLm to be described later.

[0045] The voltage generator 300 generates voltages required for the operation of the display device DD in response to the voltage control signal VCS from the driving controller 100. Figure 1In an embodiment, the voltage generator 300 generates a first driving voltage ELVDD, a second driving voltage ELVSS, and a third driving voltage AVDD. The first driving voltage ELVDD and the second driving voltage ELVSS may be voltages required for the operation of the pixels PX in the display panel DP, and the third driving voltage AVDD may be a voltage required for the operation of the data driving circuit 200.

[0046] In this specification, the voltage generator 300 is illustrated and described as an example of generating the first driving voltage ELVDD, the second driving voltage ELVSS, and the third driving voltage AVDD, but the present disclosure is not limited thereto. The type and number of driving voltages generated by the voltage generator 300 may vary.

[0047] The display panel DP includes scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX, where n and m are integers greater than 1. The display panel DP may further include a scan driving circuit SDC and a light emission driving circuit EDC.

[0048] exist Figure 1 In an embodiment, a scan driving circuit SDC is located on a first side of the display panel DP. Scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1 extend from the scan driving circuit SDC in a first direction DR1. The scan driving circuit SDC may receive a scan control signal SCS from the driving controller 100. In response to the scan control signal SCS, the scan driving circuit SDC may output scan signals to the scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1.

[0049] The light emission driving circuit EDC may be arranged at the second side of the display panel DP. Emission control lines EML1 to EMLn extend from the light emission driving circuit EDC in a direction opposite to the first direction DR1. The light emission driving circuit EDC may receive an emission control signal ECS from the driving controller 100. The light emission driving circuit EDC may output an emission signal to the emission control lines EML1 to EMLn in response to the emission control signal ECS.

[0050] In an embodiment, the scan driving circuit SDC and the light emission driving circuit EDC may include transistors formed by the same process of forming the pixels PX.

[0051] The scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, and the emission control lines EML1 to EMLn are spaced apart from each other in the second direction DR2. The data lines DL1 to DLm extend from the data driving circuit 200 in a direction opposite to the second direction DR2 and are spaced apart from each other in the first direction DR1.

[0052] exist Figure 1 In the example illustrated in FIG, the scan driving circuit SDC and the light emission driving circuit EDC face each other with the pixel PX interposed therebetween, but the present disclosure is not limited thereto. For example, the scan driving circuit SDC and the light emission driving circuit EDC may be adjacent to each other in the non-display area NDA of the display panel DP. In an embodiment, the scan driving circuit SDC and the light emission driving circuit EDC may be implemented as a single circuit.

[0053] The pixels PX are electrically connected to the scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, the emission control lines EML1 to EMLn and the data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines and one emission control line. For example, Figure 4 , the pixels PX in the first row may be connected to the scan lines GIL1, GCL1, GWL1, and GWL2 and the emission control line EML1. Typically, the pixels PX in the i-th row may be connected to the scan lines GILi, GCLi, GWLi, and GWLi+1 and the emission control line EMLi.

[0054] Each of the plurality of pixels PX receives a first driving voltage ELVDD and a second driving voltage ELVSS from the voltage generator 300 .

[0055] Figure 2 A circuit diagram of a voltage generator 300 according to an embodiment of the present disclosure is illustrated.

[0056] refer to Figure 2 , the voltage generator 300 includes an input circuit 310 , a first-in-first-out (FIFO) and priority logic 320 , a switching logic 330 , and a voltage converter 340 .

[0057] The input circuit 310 includes a first digital-to-analog converter DAC1, a second digital-to-analog converter DAC2, and a third digital-to-analog converter DAC3, a first amplifier 311, a second amplifier 312, and a third amplifier 313, and a level shifter 314. The input circuit 310 outputs a first request signal CP1, a second request signal CP2, and a third request signal CP3 in response to the first voltage data signal VD1, the second voltage data signal VD2, and the third voltage data signal VD3 and the first feedback voltage FB1, the second feedback voltage FB2, and the third feedback voltage FB3. In an embodiment, the first request signal CP1 is output from the first request signal CP2. The second request signal CP3 is output from the second request signal CP3. Figure 1 The voltage control signal VCS of the driving controller 100 illustrated in FIG may include first, second, and third voltage data signals VD1, VD2, and VD3. In an embodiment, the voltage converter 340 may provide first, second, and third feedback voltages FB1, FB2, and FB3. Figure 2 An embodiment is shown in which the level shifter 314 generates the second feedback voltage FB2 by shifting the second output voltage VO2 from the voltage converter 340 .

[0058] The first, second, and third voltage data signals VD1, VD2, and VD3 may be digital signals corresponding to target voltage levels of the first, second, and third output voltages VO1, VO2, and VO3, respectively, output from the voltage converter 340. The first and third digital-to-analog converters DAC1 and DAC3 convert the first and third voltage data signals VD1 and VD3, respectively, into first and third reference voltages VREF1 and VREF3, which are analog signals.

[0059] The second digital-to-analog converter DAC2 converts the second voltage data signal VD2 into an analog signal VA2 . The level shifter 314 outputs a second feedback voltage FB2 in response to the analog signal VA2 and a second output voltage VO2 from the voltage converter 340 .

[0060] The first amplifier 311 receives the first reference voltage VREF1 and the first feedback voltage FB1 and outputs the first request signal CP1. For example, when the voltage level of the first reference voltage VREF1 is greater than the voltage level of the first feedback voltage FB1, the first amplifier 311 may output the first request signal CP1 having a high level.

[0061] The second amplifier 312 receives the second reference voltage VREF2 and the second feedback voltage FB2 and outputs the second request signal CP2. For example, when the voltage level of the second feedback voltage FB2 is greater than the voltage level of the second reference voltage VREF2, the second amplifier 312 may output the second request signal CP2 having a high level.

[0062] The third amplifier 313 receives the third reference voltage VREF3 and the third feedback voltage FB3 and outputs a third request signal CP3. For example, when the voltage level of the third reference voltage VREF3 is greater than the voltage level of the third feedback voltage FB3, the third amplifier 313 may output the third request signal CP3 having a high level.

[0063] In an embodiment, each of the first amplifier 311 , the second amplifier 312 , and the third amplifier 313 may be an operational amplifier.

[0064] The FIFO and priority logic 320 receives the first request signal CP1, the second request signal CP2, and the third request signal CP3. When a request signal having an active level exists among the first request signal CP1, the second request signal CP2, and the third request signal CP3, the FIFO and priority logic 320 outputs a selection signal corresponding to the request signal having the active level in synchronization with the clock signal VC.

[0065] The FIFO and priority logic 320 determines priorities of the first, second, and third request signals CP1, CP2, and CP3, and outputs one of the first, second, and third selection signals CT1, CT2, and CT3 at an active level in synchronization with the clock signal VC.

[0066] In an embodiment, from Figure 1 The voltage control signal VCS of the driving controller 100 illustrated in FIG. 1 may include a clock signal VC.

[0067] The switching logic 330 outputs first, second, third, S3, fourth, SA, fifth, SP, and sixth switching signals SN based on which one or more of the first, second, and third selection signals CT1, CT2, and CT3 are at active levels.

[0068] The voltage converter 340 receives an input voltage VIN. The voltage converter 340 converts the input voltage VIN into a first output voltage VO1, a second output voltage VO2, and a third output voltage VO3 in response to a first switching signal S1, a second switching signal S2, a third switching signal S3, a fourth switching signal SA, a fifth switching signal SP, and a sixth switching signal SN. In an embodiment, the first output voltage VO1, the second output voltage VO2, and the third output voltage VO3 may be respectively Figure 1 The first driving voltage ELVDD, the second driving voltage ELVSS and the third driving voltage AVDD shown in FIG.

[0069] The voltage converter 340 may include a single inductor multiple output (SIMO) structure including one inductor L1 and outputting a first output voltage VO1 , a second output voltage VO2 , and a third output voltage VO3 .

[0070] Figure 2 The voltage converter 340 in the embodiment shown in FIG includes an inductor L1, a first switching transistor ST1, a second switching transistor ST2, a third switching transistor ST3, a fourth switching transistor STA, a fifth switching transistor STP, and a sixth switching transistor STN, a capacitor CIN, a first capacitor CO1, a second capacitor CO2, and a third capacitor CO3, and resistors R1, R2, R3, and R4. The voltage converter 340, which includes a single-inductor multi-output structure, can minimize power consumption by using a single inductor L1 and capacitors CIN, CO1, CO2, and CO3. Figure 2 The circuit configuration of the voltage converter 340 illustrated in FIG. 1 is merely an example, and the present disclosure is not limited thereto.

[0071] exist Figure 2 In the embodiment of FIG. 5 , the inductor L1 is connected between the node Lx1 and the node Lx2 .

[0072] The first switching transistor ST1 is connected between the input node IN and the node Lx1 and includes a gate electrode receiving the first switching signal S1. The input node IN receives the input voltage VIN.

[0073] The second switching transistor ST2 is connected between the node Lx1 and a ground terminal, and includes a gate electrode receiving a second switching signal S2 .

[0074] The third switching transistor ST3 is connected between the node Lx2 and the ground terminal, and includes a gate electrode receiving a third switching signal S3 .

[0075] The fourth switching transistor STA is connected between the node Lx2 and the third output node OUT3 and includes a gate electrode receiving a fourth switching signal SA The third output node OUT3 outputs a third output voltage VO3.

[0076] The fifth switching transistor STP is connected between the node Lx2 and the first output node OUT1 and includes a gate electrode receiving a fifth switching signal SP. The first output node OUT1 outputs a first output voltage VO1.

[0077] The sixth switching transistor STN is connected between the node Lx1 and the second output node OUT2 and includes a gate electrode receiving a sixth switching signal SN. The second output node OUT2 outputs a second output voltage VO2.

[0078] Resistors R1 and R2 are sequentially connected in series between a third output node OUT3 and a ground terminal. A third feedback node N3, which is a connection node between resistors R1 and R2, outputs a third feedback voltage FB3. The third feedback voltage FB3 has a voltage level lower than that of the third output voltage VO3. When the third output voltage VO3 changes, the third feedback voltage FB3 also changes.

[0079] Resistors R3 and R4 are sequentially connected in series between a first output node OUT1 and a ground terminal. A first feedback node N1, which is a connection node between resistors R3 and R4, outputs a first feedback voltage FB1. The first feedback voltage FB1 has a voltage level lower than that of the first output voltage VO1. When the first output voltage VO1 changes, the first feedback voltage FB1 also changes.

[0080] Figure 3A 、 Figure 3B and Figure 3C 3 is a timing diagram illustrating the first switching signal S1 to the sixth switching signal SN output from the switching logic 300. Specifically, Figures 3A to 3C It is shown in the figure Figure 2 1 , 2 , 3 , 4 , 5 , and 6 , switching signals S1 , S2 , S3 , SA , SP , and SN , output from the switching logic 330 during example operation of the voltage generator 300 .

[0081] Figure 3A 1 is a timing diagram illustrating the first switching signal S1, the second switching signal S2, the third switching signal S3, the fourth switching signal SA, the fifth switching signal SP, and the sixth switching signal SN when the first selection signal CT1 is at an active level. The FIFO and priority logic 320 can determine that the first selection signal CT1 has an active level for generating a desired voltage level of the first output voltage VO1.

[0082] refer to Figure 2 and Figure 3A During the first switching period SP1, the first switching signal S1 and the third switching signal S3 are at a high level, thus turning on the first switching transistor ST1 and the third switching transistor ST3. During the first switching period SP1, the second switching transistor ST2, the fourth switching transistor STA, the fifth switching transistor STP, and the sixth switching transistor STN are turned off. As a result, the current generated by the input voltage VIN through the first switching transistor ST1, the inductor L1, and the third switching transistor ST3 rises to a desired level.

[0083] During the second switching period SP2, the first switching signal S1 and the fifth switching signal SP are at a high level, thus turning on the first switching transistor ST1 and the fifth switching transistor STP. During the second switching period SP2, the second switching transistor ST2, the third switching transistor ST3, the fourth switching transistor STA, and the sixth switching transistor STN are turned off. Consequently, the current flowing through the inductor L1 is redirected to the first output node OUT1 via the fifth switching transistor STP, and the first capacitor CO1 is charged.

[0084] During the third switching period SP3, the second switching signal S2 and the fifth switching signal SP are at a high level, so the second switching transistor ST2 and the fifth switching transistor STP are turned on. During the third switching period SP3, the first switching transistor ST1, the third switching transistor ST3, the fourth switching transistor STA, and the sixth switching transistor STN are turned off. Therefore, the first output voltage VO1 can be output to the first output node OUT1.

[0085] Figure 3B 1 is a timing diagram illustrating the first switching signal S1, the second switching signal S2, the third switching signal S3, the fourth switching signal SA, the fifth switching signal SP, and the sixth switching signal SN when the second selection signal CT2 is at an active level. The FIFO and priority logic 320 can determine that the second selection signal CT2 has an active level for generating a desired voltage level of the second output voltage VO2.

[0086] refer to Figure 2 and Figure 3B During the fourth switching period SP4, the first switching signal S1 and the third switching signal S3 are at a high level, thus turning on the first switching transistor ST1 and the third switching transistor ST3. During the fourth switching period SP4, the second switching transistor ST2, the fourth switching transistor STA, the fifth switching transistor STP, and the sixth switching transistor STN are turned off. Similarly, the current generated by the input voltage VIN through the first switching transistor ST1, the inductor L1, and the third switching transistor ST3 rises to a desired level.

[0087] During the fifth switching period SP5, the third switching signal S3 and the sixth switching signal SN are at a high level, thus turning on the third switching transistor ST3 and the sixth switching transistor STN. During the fifth switching period SP5, the first switching transistor ST1, the second switching transistor ST2, the fourth switching transistor STA, and the fifth switching transistor STP are turned off. The sixth switching transistor STN connects the inductor L1 to the second output node OUT2, and the current maintained by the inductor L1 discharges the second capacitor CO2 to a desired voltage level. As a result, the second output voltage VO2 can be output to the second output node OUT2.

[0088] Figure 3C 1 is a timing diagram illustrating the first switching signal S1, the second switching signal S2, the third switching signal S3, the fourth switching signal SA, the fifth switching signal SP, and the sixth switching signal SN when the third selection signal CT3 is at an active level. The FIFO and priority logic 320 can determine that the third selection signal CT3 has an active level to generate the desired voltage level of the third output voltage VO3.

[0089] refer to Figure 2 and Figure 3C During the sixth switching period SP6, the first switching signal S1 and the third switching signal S3 are at a high level, thus turning on the first switching transistor ST1 and the third switching transistor ST3. During the sixth switching period SP6, the second switching transistor ST2, the fourth switching transistor STA, the fifth switching transistor STP, and the sixth switching transistor STN are turned off. Similarly, the current generated by the input voltage VIN through the first switching transistor ST1, the inductor L1, and the third switching transistor ST3 rises to a desired level depending on the load of the current path.

[0090] During the seventh switching period SP7, the first switching signal S1 and the fourth switching signal SA are at a high level, thus turning on the first switching transistor ST1 and the fourth switching transistor STA. During the seventh switching period SP7, the second switching transistor ST2, the third switching transistor ST3, the fifth switching transistor STP, and the sixth switching transistor STN are turned off. Consequently, the current passing through the inductor L1 is redirected to the third output node OUT3 via the fourth switching transistor STA and charges the third capacitor CO3.

[0091] During the eighth switching period SP8, the second switching signal S2 and the fourth switching signal SA are at a high level, so the second switching transistor ST2 and the fourth switching transistor STA are turned on. During the eighth switching period SP8, the first switching transistor ST1, the third switching transistor ST3, the fifth switching transistor STP, and the sixth switching transistor STN are turned off. Therefore, the third output voltage VO3 can be output to the third output node OUT3.

[0092] Figure 4 and Figure 5 is a timing diagram for the operation of the voltage generator 300 according to an embodiment of the present disclosure.

[0093] refer to Figure 2 and Figure 4 , the clock signal VC is a pulse signal that periodically changes to a high level.

[0094] When one or more of the first request signal CP1, the second request signal CP2, and the third request signal CP3 are at an active level (e.g., a high level), the FIFO and priority logic 320 determines the priority of the first request signal CP1, the second request signal CP2, and the third request signal CP3. In an embodiment, when more than one of the first selection signal CT1, the second selection signal CT2, and the third selection signal CT3 are at an active level, the FIFO and priority logic 320 may determine the priority in the order of the first selection signal CT1, the second selection signal CT2, and the third selection signal CT3.

[0095] The FIFO and priority logic 320 outputs any one of the first selection signal CT1 , the second selection signal CT2 , and the third selection signal CT3 at an active level (eg, a high level) in response to the clock signal VC.

[0096] exist Figure 4 In the example illustrated in FIG, the first selection signal CT1, the second selection signal CT2, and the third selection signal CT3 sequentially transition to a high level in response to successive pulses of the clock signal VC. When the period of the clock signal VC is "P," the period of each of the first selection signal CT1, the second selection signal CT2, and the third selection signal CT3 may be 3P.

[0097] If the generation period of the first driving voltage ELVDD is too long, the first driving voltage ELVDD (reference Figure 1 ) may have a ripple. Since the first driving voltage ELVDD greatly affects the display quality of the display device DD, when the first driving voltage ELVDD includes a ripple, the display quality of the display device DD may be deteriorated. Figure 4 In the example of FIG. 5 , the generation period of the first output voltage VO1 (the first driving voltage ELVDD) is 3P.

[0098] refer to Figure 2 and Figure 5 , when the first request signal CP1, the second request signal CP2, and the third request signal CP3 are all at the valid level, the FIFO and priority logic 320 may determine the priority of the first selection signal CT1, the second selection signal CT2, and the third selection signal CT3 so that the period of the first selection signal CT1 is 2P or less, and the period of each of the second selection signal CT2 and the third selection signal CT3 is 4P or less. For example, the FIFO and priority logic 320 may sequentially output the first selection signal CT1, the second selection signal CT2, the first selection signal CT1, the third selection signal CT3, and the first selection signal CT1 at a high level. Figure 5In the example, the generation period of the first output voltage VO1 (first driving voltage ELVDD) is 2P, which is shorter than that in Figure 4 The examples provided in the build cycle are short build cycles.

[0099] Figure 6 is a timing diagram illustrating first and third request signals CP1 and CP3 and first and third selection signals CT1 and CT3 according to voltage levels of the first and third feedback voltages FB1 and FB3 .

[0100] refer to Figure 2 and Figure 6 , when the voltage level of the first reference voltage VREF1 is greater than the voltage level of the first feedback voltage FB1, the first amplifier 311 may output the first request signal CP1 having a high level. Figure 6 In the embodiment of the present invention, when the voltage level of the first feedback voltage FB1 is less than or equal to the voltage level of the first reference voltage VREF1 at the first time t1, the first amplifier 311 outputs the first request signal CP1 having a high level. The FIFO and priority logic 320 outputs the first selection signal CT1 corresponding to the first request signal CP1 at a high level in synchronization with the clock signal VC.

[0101] When the voltage level of the third reference voltage VREF3 is greater than the voltage level of the third feedback voltage FB3, the third amplifier 313 may output the third request signal CP3 having a high level. Figure 6 In the embodiment of the present invention, when the voltage level of the third feedback voltage FB3 is less than or equal to the voltage level of the third reference voltage VREF3 at the second time t2, the third amplifier 313 outputs the third request signal CP3 having a high level. The FIFO and priority logic 320 outputs the third selection signal CT3 corresponding to the third request signal CP3 at a high level in synchronization with the clock signal VC.

[0102] exist Figure 6 In the embodiment, the first request signal CP1 transitions to a high level at a first time t1, and then the second request signal CP2 transitions to a high level at a second time t2, so the FIFO and priority logic 320 can output the first selection signal CT1 and the third selection signal CT3 at a high level in response to the first request signal CP1 and the third request signal CP3, respectively. In detail, the FIFO and priority logic 320 performs a FIFO operation of first outputting the first selection signal CT1 at a high level in response to the first request signal CP1 transitioning to a high level, and then outputting the third selection signal CT3 at a high level in response to the third request signal CP3.

[0103] like Figure 5, when at least two of the first request signal CP1, the second request signal CP2, and the third request signal CP3 are simultaneously at a high level, the FIFO and priority logic 320 may output any one of the first selection signal CT1, the second selection signal CT2, and the third selection signal CT3 at a valid level based on the priority.

[0104] Figure 7A and Figure 7B 2 is a timing diagram illustrating operations of the FIFO and priority logic 320 and the voltage converter 340 according to the voltage levels of the first driving voltage ELVDD, the second driving voltage ELVSS, and the third driving voltage AVDD, respectively. Figure 7A and Figure 7B Particularly applicable to examples in which the first feedback voltage FB1, the second feedback voltage FB2, and the third feedback voltage FB3 are equal to the first output voltage VO1 (first drive voltage ELVDD), the second output voltage VO2 (second drive voltage ELVSS), and the third output voltage VO3 (third drive voltage AVDD), respectively (for example, in examples in which the resistor R1 and the resistor R3 are omitted or have zero resistance). Figure 2 voltage generator 300.

[0105] refer to Figure 2 and Figure 7A , when the first amplifier 311 outputs the first request signal CP1 having a high level indicating that the voltage level of the first feedback voltage FB1 is less than or equal to the voltage level of the first reference voltage VREF1, the FIFO and priority logic 320 determines that the voltage converter 340 needs a switching operation to generate the first output voltage VO1, that is, the first driving voltage ELVDD. Figure 7A For example, the first amplifier 311 may output the first request signal CP1 having a high level at each of time t13, time t16, and time t19.

[0106] When the voltage level of the second feedback voltage FB2 is greater than the voltage level of the second reference voltage VREF2, the second amplifier 312 determines that the voltage converter 340 needs a switching operation to generate the second output voltage VO2, that is, the second driving voltage ELVSS, and outputs a second request signal CP2 having a high level. Figure 7A For example, the second amplifier 312 may output the second request signal CP2 having a high level at each of time t12, time t14, and time t17.

[0107] When the voltage level of the third feedback voltage FB3 is less than or equal to the voltage level of the third reference voltage VREF3, the third amplifier 313 determines that the voltage converter 340 needs a switching operation to generate the third output voltage VO3, that is, the third driving voltage AVDD, and outputs the third request signal CP3 having a high level. Figure 7A For example, the third amplifier 313 may output the third request signal CP3 having a high level at each of time t11, time t15, and time t18.

[0108] like Figure 7A , when the FIFO and priority logic 320 outputs the first selection signal CT1, the second selection signal CT2, and the third selection signal CT3 in the order of appearance of the first request signal CP1, the second request signal CP2, and the third request signal CP3, the time during which the first driving voltage ELVDD is at a voltage level lower than the first reference voltage VREF1 may be long. In this case, the variation of the first driving voltage ELVDD may cause the display device DD (reference Figure 1 ) The image displayed on the display flickers.

[0109] refer to Figure 2 and Figure 7B , the first amplifier 311 may output the first request signal CP1 having a high level at each of time t23, time t26, and time t29. The second amplifier 312 may output the second request signal CP2 having a high level at each of time t22, time t24, and time t27. The third amplifier 313 may output the third request signal CP3 having a high level at each of time t21, time t25, and time t28.

[0110] Even if at least two of the first request signal CP1, the second request signal CP2, and the third request signal CP3 are simultaneously at a high level, the FIFO and priority logic 320 can output the first selection signal CT1, the second selection signal CT2, and the third selection signal CT3 according to priority. For example, when the voltage converter 340 performs a switching operation to output the third drive voltage AVDD, even if the second drive voltage ELVSS becomes greater than the second reference voltage VREF2 and then the first drive voltage ELVDD becomes less than the first reference voltage VREF1, the priority of the first drive voltage ELVDD is relatively high. Therefore, the FIFO and priority logic 320 first activates the first request signal CP1 to a high level. Therefore, when the switching operation to output the third drive voltage AVDD is completed, the voltage converter 340 performs a switching operation to output the first drive voltage ELVDD. Therefore, the time during which the first drive voltage ELVDD is at a voltage level lower than the first reference voltage VREF1 can be minimized.

[0111] Figure 8A and Figure 8B is a timing diagram illustrating operations of the FIFO and priority logic 320 and the voltage converter 340 when the priority of the second driving voltage ELVSS is higher than the priority of the third driving voltage AVDD.

[0112] refer to Figure 2 and Figure 8A When switching operations are required to generate all of the first driving voltage ELVDD, the second driving voltage ELVSS, and the third driving voltage AVDD, the FIFO and priority logic 320 can determine the priority in the order of the first driving voltage ELVDD, the second driving voltage ELVSS, and the third driving voltage AVDD. The priority of the second driving voltage ELVSS is higher than the priority of the third driving voltage AVDD, so when the generation period of the third driving voltage AVDD increases to 6P, the variation range of the third driving voltage AVDD can be increased.

[0113] refer to Figure 2 and Figure 8B , the FIFO and priority logic 320 may set the priority of the second driving voltage ELVSS to be higher than the priority of the third driving voltage AVDD, and may set the generation period of the third driving voltage AVDD to be a maximum of 4P. In an embodiment, when the device receiving the third driving voltage AVDD (e.g., the data driving circuit 200 (refer to Figure 1 )) when the load is small, the generation period of the third driving voltage AVDD can be changed to a value greater than 4P.

[0114] As described herein, a voltage generator with the above configuration can employ a single-inductor, multiple-output (SIMO) structure to generate multiple drive voltages. By prioritizing the drive voltage that has the greatest impact on display quality or drives the heaviest load, the voltage generator can also operate in SIMO mode. Consequently, the drive voltage levels can be stably maintained while minimizing power consumption. Consequently, the display quality of the display device can be maintained.

[0115] Although the exemplary embodiments of the present disclosure have been disclosed for illustrative purposes, it will be apparent to those skilled in the art that various modifications and substitutions are possible without departing from the scope and spirit of the present disclosure as disclosed in the appended claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description, but should be defined by the claims.

Claims

1. A voltage generator comprising: an input circuit configured to output a first request signal and a second request signal in response to the first and second voltage data signals and the first and second feedback voltages; a FIFO and priority logic configured to output one of a first selection signal and a second selection signal at an active level in synchronization with a clock signal when at least one of the first request signal and the second request signal is at the active level; a switching logic configured to output a plurality of switching signals in response to one of the first selection signal and the second selection signal being at the active level; as well as a voltage converter configured to convert an input voltage into a first output voltage and a second output voltage, respectively, in response to the plurality of switching signals, and output a first feedback voltage and a second feedback voltage corresponding to the first output voltage and the second output voltage, respectively; and When the first request signal and the second request signal are at the valid level at the same time, the FIFO and priority logic output one of the first selection signal and the second selection signal at the valid level according to the priority.

2. The voltage generator according to claim 1, wherein: The input circuit comprises: a first digital-to-analog converter configured to convert the first voltage data signal into a first reference voltage; a first amplifier configured to compare the first feedback voltage with the first reference voltage and output the first request signal; a second digital-to-analog converter configured to convert the second voltage data signal into a second reference voltage; and a second amplifier configured to compare the second feedback voltage with the second reference voltage and output the second request signal.

3. The voltage generator according to claim 2, wherein: When a voltage level of the first feedback voltage is lower than or equal to a voltage level of the first reference voltage, the first amplifier outputs the first request signal at the active level.

4. The voltage generator according to claim 1, wherein: When the first request signal and the second request signal are simultaneously at the active level, the FIFO and priority logic outputs the first selection signal at the active level.

5. The voltage generator according to claim 1, wherein: When the period of the clock signal is P and the first request signal and the second request signal are simultaneously at the active level, the FIFO and priority logic output the first selection signal and the second selection signal so that the period of the first selection signal is 2P or less.

6. The voltage generator according to claim 1, wherein: The input circuit further outputs a third request signal in response to the third data signal and the third feedback voltage. wherein, when at least one of the first request signal, the second request signal, and the third request signal is at the active level, the FIFO and priority logic output any one of the first selection signal, the second selection signal, and the third selection signal at the active level in synchronization with the clock signal; wherein the switching logic outputs the plurality of switching signals in response to one of the first selection signal, the second selection signal, and the third selection signal being at the active level, and The voltage converter converts the input voltage into a third output voltage in response to the plurality of switching signals, and further outputs the third feedback voltage corresponding to the third output voltage.

7. The voltage generator according to claim 6, wherein: The first request signal has a higher priority than the second request signal, and the second request signal has a higher priority than the third request signal.

8. The voltage generator according to claim 7, wherein: When the period of the clock signal is P and the first request signal, the second request signal and the third request signal are simultaneously at the valid level, the FIFO and priority logic outputs the first selection signal, the second selection signal and the third selection signal so that the period of the first selection signal is 2P or less, and the period of each of the second selection signal and the third selection signal is 4P or less.

9. The voltage generator according to claim 1, wherein: The first voltage data signal and the second voltage data signal are signals corresponding to a target voltage level of the first output voltage and a target voltage level of the second output voltage, respectively.

10. The voltage generator according to claim 1, wherein The voltage converter includes a single inductor multiple output (SIMO) structure.

11. A display device comprising: Display panel; a scan driving circuit configured to provide a scan signal to the display panel; a data driving circuit configured to provide a data signal to the display panel; a driving controller configured to output a first voltage data signal, a second voltage data signal, and a clock signal; as well as a voltage generator configured to provide a first driving voltage and a second driving voltage to the display panel, Wherein, the voltage generator comprises: an input circuit configured to output a first request signal and a second request signal in response to the first and second voltage data signals and a first and second feedback voltages; a FIFO and priority logic configured to output one of a first selection signal and a second selection signal at an active level in synchronization with the clock signal when at least one of the first request signal and the second request signal is at the active level; a switching logic configured to output a plurality of switching signals in response to one of the first selection signal and the second selection signal being at the active level; and a voltage converter configured to convert an input voltage into a first drive voltage and a second drive voltage, respectively, in response to the plurality of switching signals, and output the first feedback voltage and the second feedback voltage corresponding to the first drive voltage and the second drive voltage, respectively; and When the first request signal and the second request signal are at the valid level at the same time, the FIFO and priority logic output one of the first selection signal and the second selection signal at the valid level according to the priority.

12. The display device according to claim 11, wherein The input circuit comprises: a first digital-to-analog converter configured to convert the first voltage data signal into a first reference voltage; a first amplifier configured to compare the first feedback voltage with the first reference voltage and output the first request signal; a second digital-to-analog converter configured to convert the second voltage data signal into a second reference voltage; and a second amplifier configured to compare the second feedback voltage with the second reference voltage and output the second request signal.

13. The display device according to claim 12, wherein: When a voltage level of the first feedback voltage is lower than or equal to a voltage level of the first reference voltage, the first amplifier outputs the first request signal at the active level.

14. The display device according to claim 11, wherein When the first request signal and the second request signal are simultaneously at the active level, the FIFO and priority logic outputs the first selection signal at the active level.

15. The display device according to claim 11, wherein When the period of the clock signal is P and the first request signal and the second request signal are simultaneously at the active level, the FIFO and priority logic output the first selection signal and the second selection signal so that the period of the first selection signal is 2P or less.

16. The display device according to claim 11, wherein The input circuit further outputs a third request signal in response to the third data signal and the third feedback voltage. wherein, when at least one of the first request signal, the second request signal, and the third request signal is at the active level, the FIFO and the priority logic output any one of the first selection signal, the second selection signal, and the third selection signal at the active level in synchronization with the clock signal; wherein the switching logic outputs the plurality of switching signals in response to one of the first selection signal, the second selection signal, and the third selection signal being at the active level, and The voltage converter converts the input voltage into a third driving voltage in response to the plurality of switching signals, and further outputs the third feedback voltage corresponding to the third driving voltage.

17. The display device according to claim 16, wherein: The first request signal has a higher priority than the second request signal, and the second request signal has a higher priority than the third request signal.

18. The display device according to claim 17, wherein: When the period of the clock signal is P and the first request signal, the second request signal and the third request signal are simultaneously at the valid level, the FIFO and priority logic outputs the first selection signal, the second selection signal and the third selection signal so that the period of the first selection signal is 2P or less, and the period of each of the second selection signal and the third selection signal is 4P or less.

19. The display device according to claim 11, wherein The voltage converter includes a single inductor multiple output (SIMO) structure.

20. The display device according to claim 11, wherein The first voltage data signal and the second voltage data signal are signals corresponding to target voltage levels of the first driving voltage and the second driving voltage, respectively.

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