Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a plurality of pixel units, and each pixel unit comprises a light-emitting device and a pixel driving circuit. The pixel driving circuit comprises a pulse width modulation sub-circuit and a pulse amplitude modulation sub-circuit which are electrically connected; the pulse amplitude modulation sub-circuit comprises a voltage compensation module and a first driving transistor, a first electrode of the first driving transistor and a positive end of a first power line are connected to a first node, a second electrode is connected to an anode of the luminescent device, and a control electrode and the voltage compensation module are connected to a second node; in a light-emitting period in a display frame, the voltage compensation module is used for adjusting a first target voltage written into the second node in a data writing period in the display frame to a second target voltage according to the first light-emitting control signal, and the first driving transistor generates light-emitting current for driving the light-emitting device according to the second target voltage. Therefore, the light-emitting current is not influenced by the fluctuation of the power supply voltage.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In electroluminescent display panels, particularly micro-light-emitting diode (Micro-LED) display panels, the pixel driver circuit plays a key role in display quality. Conventional Micro-LED display panels employ pulse amplitude modulation (PAM) driving methods, which switch between different grayscales by varying the current amplitude. However, this driving method can cause pockmarks in the actual display at low currents and low grayscales, resulting in poor display uniformity. To address the shortcomings of pure PAM driving, the industry has introduced a hybrid driving circuit combining PAM and pulse width modulation (PWM), known as pulse hybrid modulation (PHM) driving circuits. In a PHM driving circuit, high grayscales are switched using the PAM circuit to adjust the current, while low grayscales are switched using the PWM circuit to adjust the light emission time. This hybrid driving method improves display quality to a certain extent. However, the light emission current in conventional PHM driving circuits is significantly affected by power supply voltage fluctuations, resulting in poor display uniformity. Summary of the Invention

[0003] Embodiments of the present application provide a display panel and a display device, aiming to solve the above-mentioned problems.

[0004] An embodiment of the present application provides a display panel, comprising a plurality of pixel units; the pixel units comprise a light-emitting device and a pixel driving circuit; the pixel driving circuit comprises an electrically connected pulse width modulation sub-circuit and a pulse amplitude modulation sub-circuit; the pulse amplitude modulation sub-circuit comprises: a voltage compensation module and a first driving transistor, wherein the first electrode of the first driving transistor is connected to the positive end of the first power line at a first node, the second electrode is connected to the anode of the light-emitting device, and the control electrode is connected to the voltage compensation module at a second node; wherein, during a light-emitting period within a display frame of the display panel, the voltage compensation module is used to adjust the first target voltage written to the second node during a data writing period before the light-emitting period within the display frame to a second target voltage according to a first light-emitting control signal, so that the first driving transistor generates a light-emitting current for driving the light-emitting device according to the second target voltage during the light-emitting period.

[0005] An embodiment of the present application also provides a display device, comprising the display panel as described above, and a signal control circuit, wherein the signal control circuit is used to generate a control signal for controlling the display panel; the control signal includes at least one of a scan signal, a reset signal, and a light-emitting control signal.

[0006] The display panel and display device provided by the present application, by setting a voltage compensation module in the pixel driving circuit, adjust the first target voltage written into the control electrode of the first driving transistor during the light-emitting period of a display frame to a second target voltage, so that the first driving transistor generates a light-emitting current for driving the light-emitting device according to the second target voltage during the light-emitting period. In this way, the light-emitting current of the first driving transistor is compensated so that the magnitude of the light-emitting current is not affected by the fluctuation of the power supply voltage connected to the pixel driving circuit, thereby improving display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present application is further described below with reference to the accompanying drawings. It should be noted that the drawings described below are only used to illustrate some embodiments of the present application, and those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0008] Figure 1 This is a structural block diagram of the display device provided in an embodiment of the present application.

[0009] Figure 2 A circuit for a pixel unit of a display panel provided in an embodiment of the present application Figure 1 .

[0010] Figure 3 The embodiment of this application provides Figure 2 The driving timing of the pixel unit is shown.

[0011] Figure 4 A circuit for a pixel unit of a display panel provided in an embodiment of the present application Figure 2 .

[0012] Figure 5 The embodiment of this application provides Figure 4 The driving timing of the pixel unit is shown. DETAILED DESCRIPTION

[0013] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0014] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0015] The embodiments of the present application may be combined with each other.

[0016] like Figure 1 As shown, the display device provided in the embodiments of the present application may be, for example, an organic light emitting diode (OLED) display device. Of course, the display device may also be a sub-millimeter light emitting diode (Mini-LED) display device or a Micro-LED display device. The display device may include a display panel, a source driver circuit, a gate driver circuit, a timing controller, a light controller, a power management chip, a data line for transmitting a data signal DATA, a scan line for transmitting a scan signal SCAN, a power line for transmitting a voltage VDD at a positive end of the power line or a voltage VSS at a negative end of the power line, a light control signal line for transmitting a light control signal EM, and the like.

[0017] The substrate may be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), etc. The display panel includes a pixel array composed of a plurality of pixel units PX arranged in rows and columns, forming a plurality of pixel rows arranged along the row direction and a plurality of pixel columns arranged along the column direction, each pixel row and each pixel column including a plurality of pixel units. For ease of description, the pixel rows and pixel columns may also be referred to as "rows" and "columns" hereinafter. Taking an OLED display panel as an example, the pixel unit may include an organic light-emitting device and a pixel driving circuit. The pixel driving circuit may include a driving transistor, which is used to control the brightness of the corresponding organic light-emitting device in the display panel. In an actual pixel unit, the driving transistor may include, but is not limited to, a thin film transistor (TFT) made of low-temperature polycrystalline silicon (LTPS) and a metal oxide semiconductor. The TFT may adopt a dual-gate structure, with the organic light-emitting device electrically connected to the first electrode or the second electrode of the TFT. The organic light-emitting device may include a light-emitting layer, an electron transport layer, a hole transport layer, a cathode, and an anode. Different organic materials can emit light of different wavelengths to achieve full-color display. The encapsulation layer includes a multi-layer structure of alternating organic / inorganic layers. The gate driver circuit (GOA, Gatedriver On Array) is mainly used for scanning and driving pixel rows. For example, the GOA circuit may include cascaded gate driver units, wherein each level of gate driver units corresponds to controlling one or more pixel rows to realize the gating of pixel units. In some embodiments, GOA may adopt unilateral drive or bilateral drive for multiple pixel rows, wherein the unilateral drive may be to arrange the gate driver unit only on one side (such as the left or right side), and drive multiple pixel rows by scanning row by row in a cascade manner. Bilateral drive may be to arrange the driver units on both the left and right sides of the multiple pixel rows, and drive multiple pixel rows by scanning row by row through the cooperation of both sides. The source driver circuit is used to provide data signals to the pixel units. The timing controller is used to receive external input image data and synchronization signals, and generate signals required by the gate driver circuit and the source driver circuit. The power management chip is used to provide the required operating voltage for each part of the display panel. It should be noted that, Figure 1 This is an exemplary schematic diagram, and the connection relationship of the components shown is only used to explain the functional logical relationship of the display panel, rather than to limit the actual physical structure.

[0018] This application proposes a new hybrid driving circuit that combines pulse amplitude modulation and pulse width modulation. A voltage compensation method is added to the pulse amplitude modulation so that the luminous current used to drive the light-emitting device to emit light in the pixel unit during the luminous period is not affected by power supply voltage fluctuations, thereby improving display uniformity.

[0019] Example 1

[0020] like Figure 2 As shown, an embodiment of the present application exemplarily provides a display panel 1, which may include a plurality of pixel units 100. The pixel units 100 may include a red pixel unit, a green pixel unit, and a blue pixel unit. Each of the pixel units 100 may include a light-emitting device 10 and a pixel driving circuit 20, wherein the light-emitting device 10 may be, but not limited to, an OLED, an MLED, a Min-LED, etc. The pixel driving circuit 20 may include an electrically connected pulse width modulation subcircuit 201 and a pulse amplitude modulation subcircuit 202; the pulse amplitude modulation subcircuit 202 may include: a voltage compensation module 2021, a first reset module 2022, a first driving transistor PT8, and a first light-emitting control module 2023.

[0021] In which, the first electrode of the first driving transistor PT8 is connected to the positive end of the first power line at the first node N1, the second electrode is connected to the anode of the light-emitting device 10, and the control electrode is connected to the voltage compensation module 2021 at the second node N2; in which, during the light-emitting period within a display frame of the display panel 1, the voltage compensation module 2021 is used to adjust the first target voltage written to the second node N2 during the data writing period before the light-emitting period in the display frame to a second target voltage according to the first light-emitting control signal EMPAM, so that the first driving transistor PT8 generates a light-emitting current for driving the light-emitting device 10 according to the second target voltage during the light-emitting period.

[0022] The voltage compensation module 2021 may include a first data write transistor PT7, a voltage compensation transistor PT6, a first capacitor C2, and a first transmission transistor PT9. The first data write transistor PT7 has a first electrode connected to the first data voltage VData_PAM and a second electrode connected to the third node N3. The voltage compensation transistor PT6 has a first electrode connected to the third node N3 and a second electrode connected to the compensation voltage Vi_Gc. The first capacitor C2 is connected between the third node N3 and the second node N2. The first transmission transistor PT9 has a first electrode connected to the second node N2, a second electrode connected to the second electrode of the first drive transistor PT8, and a control electrode connected to the first scan signal PAM[n].

[0023] The first reset module 2022 may be configured to transmit the first power supply voltage VDD_PAM connected to the positive end of the first power line to the third node N3 in the voltage compensation module 2021 and the first reset voltage Vi_Ga to the second node N2 in accordance with a first reset control signal PAM[n-1] during a reset period preceding the data write period within the display frame, and to transmit the second reset voltage Vi_A to the anode of the light-emitting device 10 in accordance with a second reset control signal Discharge, thereby respectively resetting the third node N3, the second node N2, and the anode. The first reset module 2022 may include a first reset transistor PT14, a second reset transistor PT11, and a third reset transistor PT13. The first reset transistor PT14 has a first electrode connected to the first node N1 and a second electrode connected to the third node N3. The control electrode of the first reset transistor PT14 is connected to the first power supply voltage VDD_PAM and is configured to be turned on during the reset period in accordance with the first reset control signal PAM[n-1] to transmit the first power supply voltage VDD_PAM to the third node N3 to reset the third node N3. The second reset transistor PT11 has a first electrode connected to the second node N2, a second electrode connected to the first reset voltage Vi_Ga, and a control electrode connected to the first reset control signal PAM[n-1]. The second reset transistor PT11 is configured to conduct during the reset period according to the first reset control signal PAM[n-1] to transmit the first reset voltage Vi_Ga to the second node N2, thereby resetting the second node N2. The third reset transistor PT13 has a first electrode connected to the anode of the light-emitting device 10, a second electrode connected to the second reset voltage Vi_A, and a control electrode connected to the second reset control signal Discharge. The third reset transistor PT13 is configured to conduct during the reset period according to the second reset control signal Discharge to transmit the second reset voltage to the anode of the light-emitting device 10, thereby resetting the anode. In some embodiments, the reset period lasts approximately 1 to 5 microseconds (μs).

[0024] Among them, the first light-emitting control module 2023 may include a first light-emitting control transistor PT10; the first electrode of the first light-emitting control transistor PT10 and the second electrode of the first driving transistor PT8 are connected to the fourth node N4, the second electrode is connected to the anode of the light-emitting device, and the control electrode is used to access the first light-emitting control signal EMPAM.

[0025] In some embodiments, the pulse width modulation sub-circuit 201 may include a second drive transistor PT3, a second data write transistor PT2, a fourth reset transistor PT12, a second transfer transistor PT4, a second emission control transistor PT1, a third emission control transistor PT5, and a second capacitor C1. The first electrode of the second drive transistor PT3 is connected to the fifth node N5, the second electrode is connected to the sixth node N6, and the control electrode is connected to the seventh node N7. The first electrode of the second data write transistor PT2 is connected to the fifth node N5, the second electrode is used to receive the second data voltage VData_PWM, and the control electrode is used to receive the second scan signal PWM[n]. The first electrode of the fourth reset transistor PT12 is connected to the seventh node N7, the second electrode is used to receive the third reset voltage Vi_Gw, and the control electrode is used to receive the third reset control signal PWM[n-1]. The first electrode of the second transfer transistor PT4 is connected to the seventh node N7, the second electrode is connected to the sixth node N6, and the control electrode is used to receive the second scan signal PWM[n]. The second light-emission control transistor PT1 has a first electrode connected to the positive terminal of the second power line, a second electrode connected to the fifth node N5, and a control electrode connected to the second light-emission control signal EMPWM. The third light-emission control transistor PT5 has a first electrode connected to the sixth node N6, and a second electrode connected to the third node N3. The control electrode of the third light-emission control transistor PT5 is connected to the control electrode of the second light-emission control transistor PT1. The second capacitor C1 has a first electrode connected to the seventh node N7, and a second electrode connected to the ramp voltage Sweep. The cathode of the light-emitting device 10 is connected to the negative terminal of the power line for receiving the voltage VSS.

[0026] This application Figure 2 The working period of the pixel unit in a display frame may include: reset period, data writing period and light emitting period. It should be noted that in the embodiment of the present application, each transistor included in the pixel driving circuit 20 may be a P-type transistor. Based on this, in a display frame, for the driving timing of the pixel unit, as shown in FIG. Figure 3 shown.

[0027] 1. Reset period.

[0028] The first reset control signal PAM[n-1] is at a low level, the first reset transistor PT14 and the second reset transistor PT11 are turned on, respectively transmitting the first power supply voltage VDD_PAM to the third node N3 to reset the third node N3 to a high potential; and transmitting the first reset voltage Vi_Ga to the second node N2 to reset the second node N2.

[0029] The second reset control signal Discharge is at a low level, the second reset transistor PT13 is turned on, and the second reset voltage Vi_A is transmitted to the anode of the light emitting device 10 to reset the anode of the light emitting device 10 .

[0030] The third reset control signal PWM[n-1] is at a low level, and the fourth reset transistor PT12 is turned on to transmit the third reset voltage Vi_Gw to the seventh node N7 to reset the seventh node N7.

[0031] 2. Data writing period.

[0032] The first scan signal PAM[n] is at a low level, turning on the first data write transistor PT7 and the first transfer transistor PT9, and transmitting the first data voltage VData_PAM to the third node N3. Since the second node N2 is reset to the first reset voltage Vi_Ga and the first node N1 is reset to the first power supply voltage VDD_PAM during the reset period, the gate voltage Vg1 of the first drive transistor PT8 (which is the voltage Vi_GA at the second node N2) is less than the source voltage Vs1 (which is the voltage VDD_PAM at the first node N1), i.e., Vgs1 = Vg1 - Vs1 = Vi_GA - VDD_PAM < 0. This turns on the first drive transistor PT8, transmitting the first power supply voltage VDD_PAM to the second node N2. Since the first transfer transistor PT9 is also turned on, shorting the fourth node N4 to the second node N2 (by diode contact), the first power supply voltage VDD_PAM is also transmitted to the second node N2. Furthermore, when VData_PAM is written to the third node N3, the voltage at the second node N2 is pulled higher due to the coupling effect of the first capacitor C2, and is higher than the source voltage Vs1 of the first driver transistor PT8, turning off the first driver transistor PT8. At this point, Vgs1 will be equal to the threshold voltage Vth1 of the first driver transistor PT8. Based on this, since the voltage at the first node N1 is always VDD_PAM, Vg1 = Vgs1 + VDD_PAM = Vth1 + VDD_PAM. Based on the above description, after the data writing period ends, the voltage at the second node N2 is Vg1 = Vgs1 + VDD_PAM = Vth1 + VDD_PAM, which is the first target voltage.

[0033] During the data writing period, the second scanning signal PWM[n] is also at a low level, the second data writing transistor PT3 and the second transmission transistor PT4 are turned on, and the second data voltage VData_PWM is transmitted to the fifth node N5, that is, the source voltage Vs2 of the second driving transistor PT3 = VData_PWM. Since the seventh node N7 is reset to the third reset voltage Vi_Gw during the aforementioned reset period, that is, the gate voltage Vg2 of the second driving transistor PT3 = Vi_Gw, then the gate voltage of the second driving transistor PT3 is less than the source voltage, and the second driving transistor PT3 is turned on, so that the second data voltage VData_PWM is transmitted to the sixth node N6. Since the second transmission transistor PT4 is also turned on, the sixth node N6 and the seventh node N7 are short-circuited (in a diode contact manner), therefore, the second data voltage VData_PWM is also transmitted to the seventh node N7, so that the second driving transistor PT3 is turned off because the gate voltage is greater than the source voltage, so that the voltage of the seventh node is the sum of the second data voltage VData_PWM and the threshold voltage Vth2 of the second driving transistor PT3, that is, Vg2 = VData_PWM + Vth2.

[0034] 3. Luminous period.

[0035] The first light-emission control signal EMPAM is at a low level, turning on the first light-emission control transistor PT10 and the voltage compensation transistor PT6. Since the voltage compensation transistor PT6 is turned on, the compensation voltage Vi_Gc is transmitted to the third node N3, and the voltage at the third node N3 becomes the compensation voltage Vi_Gc. Due to the presence of the first capacitor C2, the voltage difference between the second node N2 and the third node N3 must be maintained constant. Therefore, the voltage at the second node N2 is adjusted to Vg1 = Vth1 + VDD_PAM + Vi_Gc - VData_PAM, which is the second target voltage. During this light-emission period, the voltage at the third node N3 is reset from VData_PAM to Vi_Ga, and the voltage at the second node N2 is pulled down by the first capacitor C2, turning on the first drive transistor PT8 and causing the light-emitting device 10 to begin emitting light. The light-emitting current of the light-emitting device 10 can be generated based on the second target voltage. The formula for this light-emitting current can be derived as follows.

[0036]

[0037] It can be seen from the above formula (3) that during the light-emitting period, due to the conduction of the voltage compensation transistor PT6, after the first target voltage written during the data writing period is adjusted to the second target voltage, the calculation formula of the light-emitting current does not involve VDD_PAM and Vth1. Therefore, it is not affected by VDD_PAM and Vth1. In other words, the first power supply voltage and the threshold voltage of the first driving transistor are compensated.

[0038] At the same time, in this light-emitting period, the second light-emitting control signal EMPWM is also at a low level, and the second light-emitting transistor PT1 and the third light-emitting transistor PT5 are turned on. At the beginning of the light-emitting period, since the second driving transistor PT3 is turned off after the data writing period ends, at the beginning of the light-emitting period, the second driving transistor PT3 is turned off. Since the ramp voltage Sweep changes gradually, as shown in FIG. Figure 3 As shown, the voltage changes in a negative direction. Simultaneously, due to the presence of the second capacitor C1, a stable voltage difference must be maintained between the two electrodes. Therefore, as the ramp voltage Sweep changes in a negative direction, the voltage at the seventh node N7 is gradually pulled down, causing the gate voltage Vg2 of the second driver transistor PT3 to be less than the source voltage Vs2. The second driver transistor PT3 is therefore turned on, which in turn increases the voltage at the second node N2. This also increases the gate voltage of the first driver transistor PT8, turning off the first driver transistor PT8 and stopping the light-emitting device 10 from emitting light. In this way, the on-time and off-time of the second and first driver transistors are controlled according to the ramp voltage and the second power supply voltage to control the light-emitting duration of the light-emitting device.

[0039] In this embodiment, the compensation voltage Vi_Gc and the first reset voltage Vi_Ga are different voltages, and the first reset voltage Vi_Ga can be set to be smaller than the compensation voltage Vi_Gc to better reset the second node N2 during the reset period. The first reset voltage Vi_Ga and the third reset voltage Vi_Gw can be the same voltage, for example, Vi_G.

[0040] In this embodiment, for Figure 2The display panel shown in FIG. 1 turns on the voltage compensation transistor PT6 during the light-emitting period, lowering the voltage at the third node N3 and adjusting the voltage at the second node N2 to a second target voltage. This allows the light-emitting current driving the light-emitting device 10 during the light-emitting period to be solely dependent on the compensation voltage Vi_Gc at the third node N3 and the first data voltage VData_PAM, without being affected by the first power supply voltage VDD_PAM and Vth1. This effectively alleviates the display unevenness problem of the display panel caused by power supply voltage fluctuations. Furthermore, threshold voltage compensation can be performed on the first and second drive transistors PT8 and PT3 using diode contacts, eliminating the display unevenness problem of the display panel caused by threshold voltage fluctuations due to process factors and other factors.

[0041] Example 2

[0042] like Figure 4 and Figure 5 As shown, another display panel 2 and driving timing are provided as examples in the present application. The display panel 2 in the second embodiment differs from the display panel 1 in the first embodiment in that, in the second embodiment, the compensation voltage, the first reset voltage, and the third reset voltage are the same voltage Vi_G, thereby reducing design costs. For an understanding of the structure and driving timing of the display panel 2, please refer to the description in the first embodiment and will not be repeated here.

[0043] In some embodiments, the present application also provides a display device including the display panel as described above, and a signal control circuit, wherein the signal control circuit is used to generate a control signal for controlling the display panel; the control signal includes at least one of a scan signal, a reset signal, and a light control signal. Figure 1 One of the source driving circuit, gate driving circuit, timing controller, and light emitting controller shown.

[0044] The above is a detailed introduction to the display panel and display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: Comprising a plurality of pixel units; the pixel units comprising a light emitting device and a pixel driving circuit; The pixel driving circuit includes a pulse width modulation subcircuit and a pulse amplitude modulation subcircuit electrically connected; The pulse amplitude modulation subcircuit includes: a voltage compensation module and a first driving transistor, wherein a first electrode of the first driving transistor is connected to a positive end of a first power line at a first node; a second electrode of the first driving transistor is connected to an anode of the light-emitting device; and a control electrode of the first driving transistor is connected to a second node of the voltage compensation module. Among them, during the light-emitting period within a display frame of the display panel, the voltage compensation module is used to adjust the first target voltage written into the control electrode of the first driving transistor during the data writing period before the light-emitting period in the display frame to a second target voltage according to a first light-emitting control signal, so that the first driving transistor generates a light-emitting current for driving the light-emitting device according to the second target voltage during the light-emitting period.

2. The display panel according to claim 1, wherein: The voltage compensation module includes a first data writing transistor, a voltage compensation transistor, and a first capacitor; the first electrode of the first data writing transistor is used to receive a first data voltage, the second electrode is connected to a third node, and the control electrode is used to receive a first scanning signal; the first electrode of the voltage compensation transistor is connected to the third node, the second electrode is used to receive a compensation voltage, and the control electrode is used to receive the first light-emitting control signal; the first capacitor is connected between the third node and the second node; In which, during the data writing period, the first data writing transistor is turned on according to the first scanning signal connected to transmit the first data voltage to the third node, so that the first driving transistor is turned on to transmit the first target voltage to the second node; the first target voltage is the sum of the first power supply voltage connected to the positive end of the first power line and the threshold voltage of the first driving transistor; during the light-emitting period, the voltage compensation transistor is turned on according to the first light-emitting control signal connected to transmit the compensation voltage to the third node, so that the voltage of the second node is adjusted to the second target voltage, so that there is a stable voltage difference between the second node and the third node during the data writing period and the light-emitting period; the second target voltage is the sum of the first power supply voltage, the threshold voltage of the first driving transistor and the voltage change of the third node during the data writing period and the light-emitting period; the voltage change is the voltage difference between the compensation voltage and the first data voltage.

3. The display panel according to claim 2, wherein: The voltage compensation module further includes: a first transmission transistor; a first electrode of the first transmission transistor is connected to the second node, a second electrode is connected to the second electrode of the first driving transistor, and a control electrode is used to receive the first scanning signal; In the data writing period, the first transmission transistor is turned on according to the first scanning signal, so that the second node is short-circuited with the second electrode of the first driving transistor, so as to compensate the threshold voltage of the first driving transistor.

4. The display panel according to claim 1, wherein: The pulse amplitude modulation sub-circuit also includes: a first reset module, which is used to transmit the first power supply voltage connected to the positive end of the first power line to the third node in the voltage compensation module and transmit the first reset voltage to the second node according to a first reset control signal during the reset period before the data writing period in the display frame, and transmit the second reset voltage to the anode of the light-emitting device according to a second reset control signal, so as to reset the third node, the second node and the anode respectively.

5. The display panel according to claim 4, wherein: The first reset module includes a first reset transistor, a second reset transistor and a third reset transistor, wherein: The first reset transistor has a first electrode connected to the first node, a second electrode connected to the third node, and a control electrode for receiving the first power supply voltage; the first reset transistor is configured to be turned on during the reset period according to the first reset control signal to transmit the first power supply voltage to the third node to reset the third node; The first electrode of the second reset transistor is connected to the second node, the second electrode is connected to the first reset voltage, and the control electrode is connected to the first reset control signal; the second reset transistor is configured to be turned on during the reset period according to the first reset control signal to transmit the first reset voltage to the second node to reset the second node; The first electrode of the third reset transistor is connected to the anode of the light-emitting device, the second electrode is connected to the second reset voltage, and the control electrode is used to connect to the second reset control signal; the third reset transistor is used to be turned on according to the second reset control signal during the reset period to transmit the second reset voltage to the anode of the light-emitting device to reset the anode.

6. The display panel according to claim 5, wherein: The first reset voltage is the same as the compensation voltage connected to the second electrode of the voltage compensation transistor included in the voltage compensation module.

7. The display panel according to claim 5, wherein: The first reset voltage and the compensation voltage connected to the second electrode of the voltage compensation transistor included in the voltage compensation module are different voltages, wherein the first reset voltage is smaller than the compensation voltage.

8. The display panel according to claim 5, wherein: The pulse amplitude modulation subcircuit further includes a first light-emitting control module; the first light-emitting control module includes a first light-emitting control transistor; the first electrode of the first light-emitting control transistor and the second electrode of the first driving transistor are connected to a fourth node, the second electrode is connected to the anode of the light-emitting device, and the control electrode is used to receive the first light-emitting control signal; In the light-emitting period, the first light-emitting control transistor is turned on according to the first light-emitting control signal, so that the first driving transistor generates a light-emitting current according to the second target voltage to drive the light-emitting device to emit light.

9. The display panel according to claim 1, wherein: The pulse width modulation sub-circuit includes: a second driving transistor, a second data writing transistor and a fourth reset transistor, wherein, The first electrode of the second driving transistor is connected to the fifth node, the second electrode is connected to the sixth node, and the control electrode is connected to the seventh node; The first electrode of the second data writing transistor is connected to the fifth node, the second electrode is used to receive the second data voltage, and the control electrode is used to receive the second scan signal; The first electrode of the fourth reset transistor is connected to the seventh node, the second electrode is used to receive the third reset voltage, and the control electrode is used to receive the third reset control signal; wherein, in a reset period before the data writing period in the display frame, the fourth reset transistor is turned on according to the third reset control signal to transmit the third reset voltage to the seventh node; During the data writing period, the second data writing transistor is turned on according to the second scanning signal, so that the second driving transistor is turned on to transmit the second data voltage to the seventh node.

10. The display panel according to claim 9, wherein: The pulse width modulation sub-circuit further includes: a second transmission transistor; a first electrode of the second transmission transistor is connected to the seventh node, a second electrode is connected to the sixth node, and a control electrode is used to receive the second scanning signal; During the data writing period, the second transmission transistor is turned on according to the second scanning signal, so that the seventh node and the sixth node are short-circuited, so as to perform threshold voltage compensation on the second driving transistor.

11. The display panel according to claim 10, wherein: The pulse width modulation sub-circuit further includes: a second light emitting control transistor, a third light emitting control transistor and a second capacitor, wherein: The first electrode of the second light emitting control transistor is connected to the positive end of the second power line, the second electrode is connected to the fifth node, and the control electrode is used to receive the second light emitting control signal; The first electrode of the third light emitting control transistor is connected to the sixth node, and the second electrode is connected to the second node; the control electrode of the third light emitting control transistor is connected to the control electrode of the second light emitting control transistor; The first electrode of the second capacitor is connected to the seventh node, and the second electrode is connected to the ramp voltage; In which, during the light-emitting period, the voltage of the seventh node gradually changes with the change of the ramp voltage; the second light-emitting control transistor and the third light-emitting control transistor are turned on according to the second light-emitting control signal connected, and the second power supply voltage connected to the positive end of the second power line is transmitted to the fifth node, so as to control the on-time and off-time of the second driving transistor and the first driving transistor according to the ramp voltage and the second power supply voltage, so as to control the light-emitting time of the light-emitting device.

12. A display device, characterized in that: It comprises a display panel as described in any one of claims 1 to 11, and a signal control circuit, wherein the signal control circuit is used to generate a control signal for controlling the display panel; the control signal includes at least one of a scan signal, a reset signal, and a light-emitting control signal.

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