Compensation circuit, display panel and display device

Abstract

The invention provides a compensation circuit, a display panel and display equipment, and relates to the technical field of display, the compensation circuit comprises at least one driving module and a control module, each driving module corresponds to a plurality of output channels, and each output channel is used for providing data voltage for different pixel units in the same column. And the control module is used for acquiring delay information of each output channel corresponding to any one of the plurality of driving modules. And the control module is also used for compensating the time when each output channel outputs the data voltage at the second frame according to the data voltage of the first frame and the second frame of the pixel units in the same row and the delay information of each output channel. The first frame and the second frame are adjacent frames. According to the technical scheme provided by the invention, the output delay time between different output channels can be optimized, so that the influence of wrong charging on the display panel is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a compensation circuit, a display panel, and a display device. Background Art

[0002] With the rapid development of display technology, the demand for long-term charging time for large-size, high-refresh-rate LCDs has also increased significantly. These display devices have increasingly stringent requirements for circuit driving performance and charging efficiency, especially in high-resolution and high-refresh-rate applications. Due to the larger drive area and higher refresh rate, the available charging time for each row of pixels is greatly compressed.

[0003] In current display panels, due to the chip-on-film (COF) manufacturing process, the data lines connecting thin-film transistors (TFTs) vary in distance and length. This causes a delay when the output channels connected to the COF output data through the data lines to charge pixels. Furthermore, the data output by the output channels of different COFs may also rise at different rates. As charging times become shorter and shorter, this makes it more likely that when the output channels output data to charge a row of pixels, pixels in other rows will be mistakenly charged. Summary of the Invention

[0004] In view of this, the present application provides a compensation circuit, a display device, and a display panel for compensating the time when an output channel outputs a data voltage to solve the problem of mischarging.

[0005] In order to achieve the above-mentioned objectives, in a first aspect, an embodiment of the present application provides a compensation circuit, which is applied to a display panel, and the display panel includes N rows × M columns of pixel units. The circuit includes: at least one driving module and a control module, each driving module corresponds to a plurality of output channels, and each output channel is used to provide data voltages for different pixel units in the same column. The control module is used to obtain the delay information of each output channel corresponding to any driving module among the multiple driving modules. The control module is also used to compensate for the time when each output channel outputs the data voltage in the second frame based on the data voltages of the first frame and the second frame of the pixel units in the same row, and the delay information of each output channel. The first frame and the second frame are adjacent frames.

[0006] In the present application, the compensation circuit includes at least one driving module and a control module. Each driving module corresponds to a plurality of output channels, and each output channel is used to provide data voltages for different pixel units in the same column. Since the position of each output channel is different, different delays will be generated when outputting the data voltage, which can easily cause mischarging. Therefore, the control module in the compensation circuit obtains the delay information of each output channel corresponding to any driving module among the multiple driving modules, and then compensates for the time when each output channel outputs the data voltage in the second frame based on the data voltage of the first frame and the second frame of the pixel unit in the same row, as well as the delay information of each output channel. In this way, the delay time between the outputs of different output channels can be optimized, thereby reducing the impact of mischarging on the display panel.

[0007] In one possible implementation of the first aspect, the circuit further includes a detection module and an analog-to-digital conversion module, wherein the analog-to-digital conversion module is connected between the detection module and the control module. The detection module is configured to detect a data voltage output by each output channel corresponding to any driver module. The detection module is further configured to determine a voltage difference between each output channel and a first output channel based on the data voltage output by each output channel. The detection module is further configured to determine delay information for each output channel based on the voltage difference between each output channel and the first output channel. The analog-to-digital conversion module is configured to convert the delay information into a digital signal.

[0008] As an optional implementation of the embodiment of the present application, the data voltage of each output channel can be collected by the detection module, and the delay information of each output channel can be calculated.

[0009] In one possible implementation of the first aspect, the detection module is specifically configured to detect a data voltage of each output channel corresponding to any driving module during a period from a first moment to a second moment. The first moment is when the first output channel starts outputting the data voltage, and the second moment is when the first output channel stops outputting the data voltage.

[0010] As an optional implementation of the embodiment of the present application, the first moment and the second moment are determined by the time of the first output channel, so that the delay information of each output channel can be determined based on the time when the first output channel outputs the data voltage.

[0011] In one possible implementation of the first aspect, the control module is further configured to determine a compensation time for each output channel based on a difference between data voltages of pixel units in the same row in the first frame and the second frame, and delay information of each output channel. The control module is further configured to compensate for a time when each output channel outputs the data voltage in the second frame based on the compensation time.

[0012] As an optional implementation of the embodiment of the present application, the control module can determine the compensation time of each output channel based on the difference in data voltages between adjacent frames to eliminate the mischarging phenomenon caused by the excessive difference in data voltages between adjacent frames.

[0013] In a possible implementation of the first aspect, the multiple driving modules include a first driving module and a second driving module. The detection module is further configured to detect a linear integral of a data voltage output by a second output channel of the first driving module and a linear integral of a data voltage output by a second output channel of the second driving module during a first time period when the data voltage changes from 0 to a common voltage, and to determine a linear integral difference. The control module is further configured to compensate the data voltage output by the second output channel of the first driving module or the second driving module based on the linear integral difference.

[0014] As an optional implementation of the embodiment of the present application, for output channels at the same position of different driving modules, the control module can also reduce the impact of the rise time difference of different output channels on the charging time by compensating the data voltage.

[0015] In a possible implementation of the first aspect, the first time period starts at a time when the data voltage rises to a first voltage threshold, and ends at a time when the data voltage rises to a second voltage threshold. The first voltage threshold is lower than the second voltage threshold, and both the first voltage threshold and the second voltage threshold are determined by a common voltage.

[0016] As an optional implementation of the embodiment of the present application, this can control the length of the first time period.

[0017] In a possible implementation of the first aspect, when the linear integral difference is greater than 0, the control module is configured to compensate for the data voltage output by the second output channel of the second driving module. When the linear integral difference is less than 0, the control module is configured to compensate for the data voltage output by the second output channel of the first driving module.

[0018] As an optional implementation of the embodiment of the present application, the data voltages of the output channels in different driving modules can be flexibly compensated.

[0019] In a possible implementation of the first aspect, the control module is further configured to determine a compensation voltage based on the linear integral difference and to compensate a data voltage output by the second output channel of the first driving module or the second driving module based on the compensation voltage.

[0020] As an optional implementation of the embodiment of the present application, the linear integral difference can indicate the difference in the rising rates of the output data voltages of different output channels, so that the data voltage output by the output channel can be compensated according to the difference in rising rates.

[0021] In a second aspect, an embodiment of the present application provides a display panel, which includes the circuit as described in the first aspect.

[0022] In a third aspect, an embodiment of the present application provides a display device, which includes the display panel described in the second aspect.

[0023] It can be understood that the beneficial effects of the second to third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic structural diagram of a display panel provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a data voltage curve of SOUT at different positions in the same COF provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of a data voltage curve of SOUT at the same position in different COFs provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of the structure of a compensation circuit provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of a curve of the output data voltages of SOUT0 and SOUTn of the same driving module provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of a curve of the SOUT0 output data voltage of a different driving module provided in an embodiment of the present application;

[0030] Figure 7 A schematic diagram of a circuit layout of a display panel provided in an embodiment of the present application;

[0031] Figure 8 A circuit diagram of a display panel provided in an embodiment of the present application.

[0032] Description of reference numerals:

[0033] 401, driving module; 401a, first driving module; 401b, second driving module;

[0034] 402, control module; 403, detection module; 404, analog-to-digital conversion module. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. The terms used in the implementation methods of the embodiments of the present application are only used to explain the specific embodiments of the present application and are not intended to limit the present application. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0036] Before explaining the embodiments of the present application in detail, the application scenarios of the embodiments of the present application are first explained.

[0037] With the iterative upgrade of display technology, high refresh rate, high resolution, and large-size display panels have gradually become the mainstream of the market. However, these display panels have some impact on the sensitivity of charging time and charging efficiency. For example, a high refresh rate requires a shorter frame period, which greatly compresses the available charging time for each row of pixels in the display panel. For another example, a large-size display panel will extend the signal transmission path, which will further exacerbate the problem of reduced charging efficiency.

[0038] Chip on film (COF) in display panels is a key technology for data transmission and mainly outputs data voltage through the output channel (SOUT). Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present application, wherein the display panel includes multiple COFs, wherein each COF is used to provide a data voltage to multiple columns of pixel units through multiple SOUTs, wherein each SOUT corresponds to a column of pixel units. Figure 1 The middle transmission channel SOUT0 and the farthest transmission channel SOUTn are taken as examples. The gate driver provides a driving voltage to each row of pixel units to turn on the switch connected to the pixel unit. For example, each pixel unit can be connected to a thin film transistor (TFT) as the switch of the pixel unit. For example, when the gate driver provides a driving voltage to the first row of pixel units, the gate of the thin film transistor (TFT) connected to each pixel unit in the first row receives the driving voltage, turning on the TFT. At this time, each pixel unit in the first row receives the data voltage from SOUT through the TFT to drive the pixel unit.

[0039] In a possible scenario of the present application, for a COF, due to the process of the COF, there will be a delay in the output voltage between SOUT at different positions, such as Figure 2 As shown, Figure 2 The solid line 1 in the figure shows the data voltage curve output by SOUT (denoted as SOUT0) in the middle of the COF, and the dashed line 1 shows the data voltage curve output by SOUT (denoted as SOUTn) at the farthest end of the COF. Since SOUTn has the longest trace, there is a delay in outputting the data voltage compared to SOUT0. Ideally, the gate of the TFT stops receiving the data voltage at the moment it is turned off. However, in reality, after the gate of the TFT is turned off, the gate voltage decreases slowly, which is a non-ideal process, as shown in the following figure. Figure 2 As shown in the gate voltage curve (solid line 2) in FIG. 1 , when the gate of the next row of TFTs is turned on, SOUTn is still outputting the data voltage, resulting in mischarging.

[0040] In a possible scenario of the present application, for different COFs, the data voltage output by SOUT at the same position may have different rising rates, such as Figure 3 As shown, Figure 3 The solid line 1 in the figure shows the data voltage curve output by COF1's SOUT1, and the dashed line 1 shows the data voltage curve output by COFn's SOUT1. Because the data voltage output by COFn's SOUT1 rises slower than that output by COF1's SOUT1, COFn's SOUT1 outputs a data voltage for charging, resulting in reduced charging efficiency. Furthermore, the fall time of the data voltage output by COFn's SOUT1 is also prolonged. Consequently, when the gate of the next row of TFTs is turned on, SOUTn also outputs a data voltage, resulting in mischarging.

[0041] To this end, embodiments of the present application provide a compensation circuit, a display panel, and a display device. The compensation circuit can detect and calculate the output of SOUT to compensate for the output time of SOUT, thereby optimizing the impact of output delays between different SOUTs on charging time. Alternatively, by detecting and calculating the output of SOUT with different COFs, the output data voltage is compensated to reduce the impact on charging time.

[0042] The following is a detailed explanation of a compensation circuit, a display panel, and a display device provided in the embodiments of the present application.

[0043] like Figure 4 As shown, Figure 4 This is a schematic diagram of a compensation circuit provided in an embodiment of the present application. The circuit is applied to a display panel, which includes N rows×M columns of pixel units. The circuit includes: at least one driving module 401 (for example, Figure 4 The driving module 401a, the driving module 401b) and the control module 402.

[0044] Each driving module 401 corresponds to a plurality of output channels, and each output channel is used to provide data voltages to different pixel units in the same column.

[0045] For example, driver module 401a corresponds to SOUT0-SOUTn, which are used to provide data voltages for pixel cells in columns A0-An, respectively. Driver module 401b corresponds to SOUT0-SOUTn, which are used to provide data voltages for pixel cells in columns B0-Bn, respectively. In other words, different driver module pairs are used to provide data voltages for different pixel cells.

[0046] In a possible embodiment, the positions of the multiple output channels corresponding to different driving modules 401 may correspond one to one.

[0047] For example, SOUT0 of driver module 401a and SOUT0 of driver module 401b are located at the same position in their respective driver modules, for example, both are middle output channels in the driver modules. SOUTn of driver module 401a and SOUTn of driver module 401b are located at the same position in their respective driver modules, for example, both are farthest output channels in the driver modules.

[0048] In a possible embodiment, the driving module 401 may be a driving chip. The driving chip uses COF technology to connect the output pins to multiple output channels. The driving chip can output data voltages through the multiple output channels to charge the pixel units.

[0049] As an example, the number of output channels is the same as the number of columns of pixel units, and each output channel is used to provide a data voltage for a corresponding column of pixel units.

[0050] In the embodiment of the present application, for the convenience of description, the driving module 401 can be represented by COF, that is, COF can be understood as a module. For example, the driving module 401a can be COF1, and the driving module 401b can be COFn.

[0051] The control module 402 is configured to obtain delay information of each output channel corresponding to any driving module among the plurality of driving modules.

[0052] In a possible embodiment, the delay information of each output channel is used to indicate the time difference when each output channel outputs a data voltage.

[0053] As an example, taking the time when the first output channel of the driving module 401a outputs the data voltage as a reference, the time difference between the time when each of the remaining output channels outputs the data voltage and the time when the first output channel outputs the data voltage is the delay information of each of the remaining output channels.

[0054] For example, driver module 401a corresponds to n+1 output channels, namely SOUT0 to SOUTn, with SOUT0 being the first output channel. Assuming SOUT0 outputs a data voltage at time t0, SOUT1 outputs a data voltage at time t0+Δt1, where Δt1 is the time difference between the output times of SOUT0 and SOUT1, i.e., the delay information when SOUT1 outputs the data voltage. SOUTn outputs a data voltage at time t0+Δtn, where Δtn is the time difference between the output times of SOUT0 and SOUTn, i.e., the delay information when SOUTn outputs the data voltage.

[0055] The control module 402 is further configured to compensate the time for each output channel to output the data voltage in the second frame based on the data voltages of the first and second frames of the pixel units in the same row and the delay information of each output channel, wherein the first and second frames are adjacent frames.

[0056] In a possible embodiment, the data voltages of adjacent frames include the data voltage dataN of the Nth frame and the data voltage dataN+1 of the N+1th frame.

[0057] In one possible implementation, the control module 402 may first determine a preliminary compensation time for the output data voltage of each output channel based on the delay information of each output channel. Because the difference in data voltages between adjacent frames affects charging time, the control module 402 then determines an additional compensation time based on the difference in data voltages between adjacent frames. The preliminary compensation time and the additional compensation time can be used to determine the final compensation time.

[0058] As an example, when the difference between the data voltages of adjacent frames is large, the required additional compensation time is increased; when the difference between the data voltages of adjacent frames is small, the required additional compensation time is reduced, or no additional compensation time is required.

[0059] In a possible embodiment, the final compensation time may satisfy the formula: Δttotal=Δt+k*ΔD, where Δt is the delay information of each output channel, ΔD is the difference in data voltages between adjacent frames, and k is the compensation coefficient.

[0060] As an example, the output channels of the driving module 401a include SOUT0 to SOUTn. The control module 402 can obtain the delay information of SOUT0 to SOUTn, thereby determining the preliminary compensation time of each transmission channel as Δt0 to Δtn. When the difference in data voltages between adjacent frames is 0, the final compensation time of the time when SOUT0 to SOUTn output the data voltage is Δt0 to Δtn, respectively. When the difference in data voltages between adjacent frames is ΔD, the final compensation time of the time when SOUT0 to SOUTn output the data voltage is Δt0 + k*ΔD to Δtn + k*ΔD, respectively.

[0061] For example, if the delay time for the data voltage output by SOUTn of the driver module 401a is Δtn = 0.6 μs, the difference in data voltages between adjacent frames ΔD = 4 V, and k is 0.1, the final compensation time for the time when SOUTn outputs the data voltage is 0.6 + 0.1 * 4 = 1 μs, that is, the time when SOUTn outputs the data voltage is advanced by 1 μs.

[0062] In the present application, the compensation circuit includes at least one driving module and a control module. Each driving module corresponds to a plurality of output channels, and each output channel is used to provide data voltages for different pixel units in the same column. Since the position of each output channel is different, different delays will be generated when outputting the data voltage, which can easily cause mischarging. Therefore, the control module in the compensation circuit obtains the delay information of each output channel corresponding to any driving module among the multiple driving modules, and then compensates for the time when each output channel outputs the data voltage in the second frame based on the data voltage of the first frame and the second frame of the pixel unit in the same row, as well as the delay information of each output channel. In this way, the delay time between the outputs of different output channels can be optimized, thereby reducing the impact of mischarging on the display panel.

[0063] In a possible embodiment of the present application, the circuit further includes a detection module 403 and an analog-to-digital conversion module 404. The analog-to-digital conversion module 404 is connected between the detection module 403 and the control module 402.

[0064] The detection module 403 is configured to detect the data voltage output by each output channel corresponding to any driver module. It is also configured to determine the voltage difference between each output channel and the first output channel based on the data voltage output by each output channel. It is also configured to determine delay information for each output channel based on the voltage difference between each output channel and the first output channel.

[0065] In one possible embodiment, the first output channel is the middle output channel of any driver module. Since the middle output channel is located in the middle of the driver module, the output delay of the first output channel when outputting the data voltage is minimal. In the embodiment of the present application, the middle output channel is considered to have no delay.

[0066] In one possible embodiment of the present application, the detection module 403 is specifically configured to detect the data voltage of each output channel corresponding to any driver module during a period from a first moment to a second moment, wherein the first moment is when the first output channel starts outputting the data voltage, and the second moment is when the first output channel stops outputting the data voltage.

[0067] For example, take any driving module as driving module 401a, SOUT0 is the first output channel of driving module 401a. Figure 5 As shown, Figure 5 t1 is the time when SOUT0 starts to output the data voltage, and t2 is the time before the gate is turned off.

[0068] In a possible embodiment, since each output channel outputs a data voltage at a different time, the voltage change from the first moment to the second moment is also different.

[0069] For example, Figure 5 As shown in FIG. 1 , the voltage of SOUT0 changes from 0 to V0 at time t1 to t2, and the voltage of SOUTn changes from 0 to Vn at time t1 to t2. Therefore, the voltage difference ΔV between SOUTn and SOUT0 is V0-Vn.

[0070] In a possible implementation, the delay information of each output channel is determined by a voltage difference between each output channel and the first output channel, and a voltage change rate of an output of each output channel.

[0071] As an example, the delay information of each output channel is the time difference Δtn between the time when the output channel outputs the data voltage and the time when the first output channel outputs the data voltage. Δtn can be determined by the voltage change rate (dVn / dt) output by the output channel and the difference between the voltage difference between the output channel and the first output channel.

[0072] For example, Figure 5As shown, the voltage of SOUT0 changes from 0 to V0 between t1 and t2; the voltage of SOUTn changes from 0 to Vn between t1 and t2. Therefore, the difference between the voltage difference of SOUT0 and SOUTn is ΔVn = V0 - Vn. Based on the voltage change rate of SOUTn (dVn / dt) and the voltage difference ΔVn, the delay information of SOUTn is determined as Δtn = ΔVn / (dVn / dt). For example, if the voltage change rate of SOUTn is 0.5V / μs and the difference between the voltage differences of SOUT0 and SOUTn is 0.25V, the delay information of SOUTn is 0.25 / 0.5 = 0.5μs.

[0073] The analog-to-digital conversion module 404 is configured to convert the delay information into a digital signal.

[0074] In a possible embodiment, an input end of the analog-to-digital conversion module 404 is connected to an output end of the detection module 403 , and an output end of the analog-to-digital conversion module 404 is connected to an input end of the control module 402 .

[0075] For example, the analog-to-digital conversion module 404 may be an analog-to-digital converter (ADC). The ADC may convert a continuous analog signal (e.g., voltage, current) into a discrete digital signal for processing and storage by the control module 402. The number of ADCs may be one or more, and is not limited in the embodiments of the present application.

[0076] In one possible embodiment, the control module 402 is a timing controller (TCON). The input end of the TCON is connected to the analog-to-digital conversion module 404, and the output end of the TCON is connected to the driver module 401. The TCON first obtains the data voltage to be output, receives the digital signal corresponding to the delay information of each output channel, and then controls the timing of the data voltage based on the delay information, and sends the data voltage to the driver module 401.

[0077] In one possible embodiment of the present application, the control module 402 is further configured to determine a compensation time for each output channel based on the difference between the data voltages of the pixel units in the first frame and the second frame in the same row and the delay information of each output channel. The control module 402 is further configured to compensate the time when each output channel outputs the data voltage in the second frame based on the compensation time.

[0078] In one possible embodiment, the control module 402 determines a preliminary compensation time for the output data voltage of each output channel based on the digital signal corresponding to the delay information of each output channel. The control module 402 then determines an additional compensation time based on the difference in data voltages between adjacent frames. The compensation time is determined by the preliminary compensation time and the additional compensation time. For example, the compensation time is the sum of the preliminary compensation time and the additional compensation time.

[0079] For example, if the initial compensation time for SOUTn of driver module 401a to output the data voltage in frame N is Δtn = 0.6 μs, the data voltage difference between adjacent frames is ΔD = 4V, and k is 0.1, then the additional compensation time is 0.1*4 = 0.4 μs. Control module 402 determines a first compensation parameter for the time SOUTn outputs the data voltage as 0.6 + 0.4 = 1 μs. Control module 402 controls SOUTn of driver module 401a to advance the time it outputs the data voltage in frame N+1 by 1 μs.

[0080] In a possible embodiment of the present application, the plurality of driving modules include a first driving module and a second driving module.

[0081] For example, the first driving module is the driving module 401 a , and the second driving module is the driving module 401 b .

[0082] Among them, the detection module 403 is also used to detect the linear integral of the data voltage output by the second output channel of the first driving module and the linear integral of the data voltage output by the second output channel of the second driving module in the first time period when the data voltage changes from 0 to the common voltage, and determine the linear integral difference.

[0083] In one possible embodiment, the start time of the first time period is the time when the data voltage rises to a first voltage threshold, and the end time of the first time period is the time when the data voltage rises to a second voltage threshold. The first voltage threshold is lower than the second voltage threshold, and both the first voltage threshold and the second voltage threshold are determined by a common voltage.

[0084] As an example, the first voltage threshold is a voltage value when the data voltage output by the output channel is A% of the common voltage, and the second voltage threshold is a voltage value when the data voltage output by the output channel is B% of the common voltage, where A is less than B.

[0085] For example, the first voltage threshold is a voltage value when the data voltage output by the output channel is 10% of Vcom, and the second voltage threshold is a voltage value when the data voltage output by the output channel is 90% of Vcom.

[0086] For example, the second output channel is SOUT0, the first driving module is driving module 401a, and the second driving module is driving module 401b. Figure 6 As shown, the time required for the data voltage outputted by SOUT0 of the driving module 401a to change from V1 to V2 is tr0 (t0-t1), and the time required for the data voltage outputted by SOUT0 of the driving module 401b to change from V1 to V2 is trn (t2-t3). Wherein, V1 is 10% of Vcom and V2 is 90% of Vcom.

[0087] The linear integration is the integration of the voltage waveform within a certain time period. For example, the start time of the first time period is t0 and the end time of the first time period is t1. The linear integration is the integration calculation of the waveform from the first voltage threshold to the second voltage threshold between t0 and t1.

[0088] For example, the first driving module is driving module 401a, the second driving module is driving module 401b, and the linear integral of SOUT0 of driving module 401a in tr0 (t0~t1) is The linear integral of SOUT0 of the driving module 401b in trn (t2-t3) is The difference between the linear integrals of SOUT0 of the driving module 401 a and SOUT0 of the driving module 401 b is Integral 0−Integral n.

[0089] The control module 402 is further configured to compensate the data voltage output by the second output channel of the first driving module or the second driving module according to the linear integral difference.

[0090] In one possible embodiment of the present application, when the linear integral difference is greater than 0, the control module 402 is configured to compensate the data voltage output by the second output channel of the second driving module. When the linear integral difference is less than 0, the control module 402 is configured to compensate the data voltage output by the second output channel of the first driving module.

[0091] As an example, when the thrust of the data voltage output by the second output channel of the first driver module is greater than the thrust of the data voltage output by the second output channel of the second driver module, the data voltage output by the second output channel of the second driver module needs to be compensated. When the thrust of the data voltage output by the second output channel of the first driver module is less than the thrust of the data voltage output by the second output channel of the second driver module, the data voltage output by the second output channel of the first driver module needs to be compensated.

[0092] For example, when the linear integral difference Integral 0-Integral n between SOUT0 of the driving module 401a and SOUT0 of the driving module 401b is greater than 0, it means that the thrust of the data voltage output by SOUT0 of the driving module 401a is greater than the thrust of the data voltage output by SOUT0 of the driving module 401b. Therefore, the data voltage output by SOUT0 of the driving module 401b is compensated according to the linear integral difference.

[0093] Similarly, when the linear integral difference Integral0-Integral n between SOUT0 of the driving module 401a and SOUT0 of the driving module 401b is less than 0, it means that the thrust of the data voltage output by SOUT0 of the driving module 401b is greater than the thrust of the data voltage output by SOUT0 of the driving module 401a. Therefore, the data voltage output by SOUT0 of the driving module 401a is compensated according to the linear integral difference.

[0094] In a possible embodiment of the present application, the control module 402 is further configured to determine a compensation voltage based on the linear integral difference and to compensate the data voltage output by the second output channel of the first driving module or the second driving module based on the compensation voltage.

[0095] In a possible embodiment, the compensation voltage is determined by the compensation coefficient and the state information. For example, the compensation voltage is the product of the compensation coefficient and the state information.

[0096] The compensation coefficient is determined by the common voltage and the linear integral difference. For example, when the actual common voltage is greater than the preset common voltage, the compensation coefficient is reduced; when the actual common voltage is less than the preset common voltage, the compensation coefficient is increased.

[0097] As an example, compensation coefficient A = Db / α, where α is the ratio of the actual common voltage Vcom to the preset common voltage Vcom'. When Vcom is greater than Vcom', α is greater than 1, and compensation coefficient A decreases. When Vcom is less than Vcom', α is less than 1, and compensation coefficient A increases.

[0098] For example, the first driving module is driving module 401a, the second driving module is driving module 401b, and the control module 404 determines the linear integral difference Db of the time information of SOUT0 on driving module 401a and SOUT0 on driving module 401b, and the compensation voltage is A*Db.

[0099] In a possible embodiment, the control module 404 compensates for the data voltage output by the second output channel of the second driving module in the Nth frame.

[0100] For example, the control module 402 receives data (n) of SOUT0 from the driving module 401b in the Nth frame. Then, according to the compensation voltage A*Db, the data voltage of SOUTn in the Nth frame is compensated to data(n)+A*Db.

[0101] like Figure 7 The figure shows a schematic diagram of the circuit layout of a display panel. The driving module 401 is a COF, including COF1 and COFn. Each COF1 corresponds to multiple SOUTs (only SOUT0 of COF1 and SOUT0 and SOUTn of COFn are drawn in the figure). The control module 402 is TCON, and the analog-to-digital converter 404 is ADC (due to the positional relationship of the COF in the figure, ADC1 and ADC2 are set, and each ADC has the same function).

[0102] The following combination Figure 7 The specific implementation method of the embodiment of the present application is described, including two cases, one is for SOUT on the same COF, and the other is for SOUT on different COFs.

[0103] Case 1: For SOUT on the same COF, take COFn as an example.

[0104] Step 1: The detection module 403 detects the voltage difference of each SOUT on COFn from the first moment to the second moment.

[0105] The first time t0 is the time when SOUT0 starts to output the data voltage, and the second time t1 is the time when SOUT0 stops outputting the data voltage.

[0106] For example, the detection module 403 detects the voltage of SOUTn during the time period t0 to t1. The voltage of SOUTn is 0 at t0 and is Vn at t1. Therefore, the voltage of SOUTn during the time period t0 to t1 is Vn-0=Vn.

[0107] Step 2: The detection module 403 determines the delay information of each SOUT according to the data voltage output by each SOUT and the data voltage output by SOUT0.

[0108] As an example, the detection module 403 determines the voltage difference between each SOUT and SOUT0 based on the data voltage of each SOUT output and the data voltage of SOUT0, and then determines the delay information based on the voltage difference between each SOUT and SOUT0 and the voltage change rate of each SOUT output.

[0109] For example, the voltage difference of SOUT0 during the period t0 to t1 is V0-0=V0. Given that the voltage difference of SOUTn during the period t0 to t1 is Vn, the voltage difference between SOUT0 and SOUTn is ΔVn=V0-Vn. Based on the voltage change rate of SOUTn (dVn / dt) and the voltage difference ΔVn, the delay information of SOUTn is determined as Δtn=ΔVn / (dVn / dt).

[0110] Step 3: The detection module 403 sends the delay information of each SOUT to the ADC. Correspondingly, the ADC receives the delay information of each SOUT from the detection module 403.

[0111] For example, the detection module 403 sends the delay information of each SOUT to ADC2.

[0112] Step 4: The ADC converts the analog signal corresponding to the delay information into a digital signal and sends the digital signal to the TCON. Correspondingly, the TCON receives the digital signal from the ADC.

[0113] For example, the detection module 403 receives the digital signal from ADC2.

[0114] Step 5: TCON compensates the time for each SOUT to output the data voltage in the second frame according to the data voltages of the first and second frames of the pixel units in the same row and the delay information of each SOUT.

[0115] The first and second frames are adjacent frames. For example, the first frame is the Nth frame, and the second frame is the N+1th frame. The data difference between adjacent frames is the difference between the data of the Nth frame and the data of the N+1th frame. The following description uses the example of a data difference of 0 between adjacent frames.

[0116] In a possible implementation, TCON determines the compensation time of each SOUT according to the digital signal corresponding to the delay information of each SOUT.

[0117] As an example, the time for SOUT to output the data voltage is compensated by enabling SOUT to output the data voltage in advance or by enabling SOUT to output the data voltage in a delayed manner.

[0118] For example, SOUT0 outputs the data voltage at time t0 and controls SOUTn to output the data voltage at time t0-Da. Alternatively, SOUTn outputs the data voltage at time t0 and controls SOUT0 to output the data voltage at time t0+Da.

[0119] In a possible implementation, the maximum time compensation is performed on SOUTn, and the time for SOUT0 to SOUTn to output the data voltage gradually increases.

[0120] As an example, the time when SOUTn outputs the data voltage in the N+1 frame is compensated to t0-Da, the time when SOUTn-1 outputs the data voltage in the N+1 frame is t0-Da(n-1) / n, and so on.

[0121] For example, SOUT0 is the middle SOUT of COF, SOUT5 is the SOUT at the farthest end of COF, and the compensation time for SOUT5 to output the data voltage in the N+1 frame is t0-5ns, the compensation time for SOUT4 to output the data voltage in the N+1 frame is t0-5(5-1) / 5=t0-4ns, the compensation time for SOUT3 to output the data voltage in the N+1 frame is t0-5(5-2) / 5=t0-3ns, the compensation time for SOUT2 to output the data voltage in the N+1 frame is t0-5(5-3) / 5=t0-2ns, and the compensation time for SOUT1 to output the data voltage in the N+1 frame is t0-5(5-4) / 5=t0-1ns.

[0122] Case 2: For SOUT on different COFs, take COF1 and COFn as examples.

[0123] Step 1: The detection module 403 detects the linear integral of the data voltage output from SOUT0 of COF1 and the linear integral of the data voltage output from SOUT0 of COFn during the first time period when the data voltage changes from 0 to the common voltage, and determines the linear integral difference.

[0124] In a possible embodiment, the detection module 403 determines a linear integral according to the first time end obtained by timing.

[0125] The first time period starts when the data voltage rises to a first voltage threshold, and ends when the data voltage rises to a second voltage threshold. The first voltage threshold is less than the second voltage threshold, and both the first voltage threshold and the second voltage threshold are determined by a common voltage.

[0126] For example, when the output voltage of SOUT0 on COF1 rises from 0 to the common voltage Vcom, timing begins when the voltage reaches 10% of Vcom. This time is t0, and the corresponding voltage is the first voltage threshold. Timing ends when the voltage reaches 90% of Vcom. This time is t1, and the corresponding voltage is the second voltage threshold. The first time period from t0 to t1 is denoted as tr0.

[0127] Similarly, as the output voltage of SOUT0 on COFn rises from 0 to the common voltage Vcom, timing begins when the voltage reaches 10% of Vcom. This time is t2, and the corresponding voltage is the first voltage threshold. Timing ends when the voltage reaches 90% of Vcom. This time is t3, and the corresponding voltage is the second voltage threshold. The time period from t2 to t3 is trn.

[0128] The linear integral is determined by the voltage waveform from the first voltage threshold to the second voltage threshold and the first time period.

[0129] For example, the time required for the data voltage output by SOUT0 of COFn to change from the first voltage threshold to the second voltage threshold is the time period from t2 to t3, and the waveform from the first voltage to the second voltage satisfies V n (t), t is the time variable. Then the linear integral of the time information of SOUT0 on COFn is

[0130] Similarly, the time required for the voltage of SOUT0 on COF1 to change from the first voltage to the second voltage is the time period from t0 to t1, and the waveform from the first voltage to the second voltage satisfies V1(t), where t is the time variable. The linear integral of the time information of SOUT0 on COF1 is Therefore, the linear integral difference of SOUT0 on COFn is Db=Integral 0-Integral n.

[0131] Step 2: The detection module 403 sends the linear integral difference between the SOUTs of different COFs to the ADC. Correspondingly, the ADC receives the linear integral difference between the SOUTs of different COFs from the detection module 403.

[0132] For example, the detection module 403 sends the linear integral difference Db between SOUT0 of COF1 and SOUT0 of COFn to the ADC.

[0133] Step 3: The ADC converts the linear integral difference into a digital signal and sends the digital signal to the TCON. Correspondingly, the TCON receives the digital signal from the ADC.

[0134] For example, the ADC sends a digital signal of the linear integral difference Db to the TCON.

[0135] Step 4: TCON determines the compensation voltage based on the linear integral difference between SOUT of different COFs.

[0136] In a possible embodiment, the compensation voltage is determined by the compensation coefficient and the linear integral difference. For example, the compensation voltage is A*Db, where A is the compensation coefficient and Db is the state information.

[0137] For example, the control module 404 uses the linear integration difference Db between the time information of SOUT0 on COF1 and SOUT0 on COFn as a reference value of the compensation voltage, and the compensation voltage is A*Db.

[0138] Step 5: TCON compensates the data voltage output by SOUT of COF in the Nth frame according to the compensation voltage.

[0139] For example, the data of SOUT0 of COFn received by TCON in the Nth frame is data(n), then according to the compensation voltage A*Db, the data voltage of SOUT0 of COFn in the Nth frame is compensated to data(n)+A*Db.

[0140] Case 1 and Case 2 above describe compensation for SOUT on the same COF and compensation for SOUT on different COFs, respectively. Combining Cases 1 and 2, the TCON can first compensate for SOUT on multiple COFs and then compensate for SOUT on each of the multiple COFs. Alternatively, the TCON can first compensate for SOUT on each COF and then compensate for SOUT on different COFs.

[0141] The following example illustrates how TCON first compensates for SOUT on multiple COFs and then compensates for SOUT on each of the multiple COFs. Figure 8 As shown, the driving module 401 includes COF1, COF2, COF3 and COF4, and each COF corresponds to a plurality of SOUTs (SOUT0 and SOUTn of each COF are shown in the figure).

[0142] The first step is to compensate for SOUT of different COFs.

[0143] TCON instructs the detection module 402 to detect SOUT at the same position in different COFs. TCON determines the compensation voltage based on the linear integral difference between SOUT of different COFs and compensates the data voltage output by SOUT of COF in the Nth frame.

[0144] For example, TCON instructs detection module 402 to detect SOUT0 in COF1, COF2, COF3, and COF4. If TCON receives data (2) for SOUT0 of COF2 in frame N, then based on the compensation voltage, the data voltage of SOUT0 of COF2 in frame N is compensated to data (2) + A*Db. The specific implementation method is described in the above embodiment, and will not be repeated here. The same applies to COF3 and COF4.

[0145] In the implementation of the present application, the first step is to solve the inconsistent charging efficiency and potential cross-row mischarging problems caused by the difference in rise / fall rates of the same position SOUT between different COFs, thereby improving the brightness uniformity of the display areas corresponding to different COFs.

[0146] The second step is to compensate for SOUT in each COF.

[0147] TCON instructs the detection module 402 to detect all SOUTs in each COF and compensates each SOUT of each COF according to the calculated final compensation time.

[0148] For example, TCON instructs the detection module 403 to detect all SOUTs of COF1. Then, based on the calculated final compensation time, it performs timing advance or delay compensation on each SOUT in COF1 at the time of outputting the data voltage of the N+1th frame. The specific implementation method is described in the above embodiment, and will not be repeated here. COF2, COF3, and COF4 are also compensated in the same way.

[0149] In the implementation of this application, the second step aims to solve the problem of inconsistent signal transmission delay within the same COF due to differences in output channel wiring lengths, optimize the charging time window, and effectively reduce the inter-row mischarging phenomenon caused by delay differences.

[0150] The collaborative strategy of first performing compensation across the COF and then performing compensation within the COF can more comprehensively address the problems of insufficient charging efficiency, uneven brightness, and mischarging caused by differences in output channels in high refresh rate, large-size display panels, significantly improving display quality.

[0151] Based on the same inventive concept, an embodiment of the present application also provides a display device. Since the display device in this embodiment includes the voltage adjustment circuit in the above embodiment, that is, the display device in this embodiment has all the technical features and technical effects of the embodiment of the above voltage adjustment circuit, please refer to the above embodiment for details and will not be repeated here.

[0152] Based on the same inventive concept, an embodiment of the present application also provides a display panel. Since the display panel in this embodiment includes the display device in the above embodiment, that is, the display panel in this embodiment has all the technical features and technical effects of the embodiment of the above display device, please refer to the above embodiment for details and will not be repeated here.

[0153] It should be understood that in the description of this application specification and the appended claims, the terms "include", "comprises", "has" and any variations thereof are intended to cover non-exclusive inclusions and mean "including but not limited to", unless otherwise specifically emphasized.

[0154] In the description of this application, unless otherwise specified, " / " indicates that the objects associated before and after are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is used to describe the association relationship of associated objects, indicating that three relationships can exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0155] Furthermore, in the description of this application, unless otherwise specified, "a plurality of" refers to two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items.

[0156] In addition, in the description of the present application, it should be understood that the terms "longitudinal", "horizontal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "vertical", "top", "bottom", "inside", "outside", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0157] In this application, unless otherwise clearly specified and limited, the terms "connection", "connected", etc. should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection between two elements or the interaction relationship between two elements. Unless otherwise clearly specified and limited, ordinary technicians in this field can understand the specific meanings of the above terms in this application according to specific circumstances.

[0158] In addition, in the description of this application specification and the appended claims, the terms "first," "second," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or precedence, nor should they be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein; and features specified as "first" or "second" may explicitly or implicitly include at least one of such features.

[0159] In the embodiments of this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a concrete manner.

[0160] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A compensation circuit, characterized in that: The circuit is applied to a display panel including N rows and M columns of pixel units. The circuit includes at least one driving module and a control module. Each driving module corresponds to a plurality of output channels, and each output channel is used to provide data voltages to different pixel units in the same column. The control module is configured to obtain delay information of each output channel corresponding to any one of the plurality of driving modules; The control module is further configured to compensate the time for each output channel to output the data voltage in the second frame according to the data voltages of the pixel units in the same row in the first frame and the second frame and the delay information of each output channel; The first frame and the second frame are adjacent frames.

2. The circuit according to claim 1, characterized in that The circuit further includes: a detection module and an analog-to-digital conversion module, wherein the analog-to-digital conversion module is connected between the detection module and the control module; The detection module is configured to detect the data voltage output by each output channel corresponding to any one of the driving modules; further configured to determine a voltage difference between each output channel and a first output channel based on the data voltage output by each output channel; and further configured to determine delay information of each output channel based on the voltage difference between each output channel and the first output channel. The analog-to-digital conversion module is used to convert the delay information into a digital signal.

3. The circuit according to claim 1, wherein: The detection module is specifically configured to detect the data voltage of each output channel corresponding to any one of the driving modules during a period from a first moment to a second moment; The first moment is the moment when the first output channel starts to output the data voltage, and the second moment is the moment when the first output channel stops outputting the data voltage.

4. The circuit according to any one of claims 1 to 3, characterized in that: The control module is further configured to determine a compensation time for each of the output channels according to a difference between a data voltage of a first frame and a data voltage of a second frame of the pixel units in the same row and delay information of each of the output channels; The control module is further configured to compensate, according to the compensation time, the time during which each output channel outputs the data voltage in the second frame.

5. The circuit according to claim 1, wherein: The plurality of driving modules include a first driving module and a second driving module; The detection module is further configured to detect that, during a first time period when the data voltage changes from 0 to a common voltage, the second output channel of the first driving module outputs a linear integral of the data voltage and the second output channel of the second driving module outputs a linear integral of the data voltage, and determine a linear integral difference; The control module is further configured to compensate the data voltage output by the second output channel of the first driving module or the second driving module according to the linear integral difference.

6. The circuit according to claim 5, characterized in that The start time of the first time period is the time when the data voltage rises to the first voltage threshold, and the end time of the first time period is the time when the data voltage rises to the second voltage threshold; The first voltage threshold is lower than the second voltage threshold, and both the first voltage threshold and the second voltage threshold are determined by the common voltage.

7. The circuit according to claim 5, characterized in that When the linear integral difference is greater than 0, the control module is configured to compensate the data voltage output by the second output channel of the second driving module; When the linear integral difference is less than 0, the control module is configured to compensate the data voltage output by the second output channel of the first driving module.

8. The circuit according to any one of claims 5 to 7, characterized in that: The control module is further configured to determine a compensation voltage according to the linear integral difference; The control module is further configured to compensate the data voltage output by the second output channel of the first driving module or the second driving module according to the compensation voltage.

9. A display panel, characterized in that: The display panel includes a display area and a non-display area, the display area includes a light-emitting layer, and the non-display area is connected to the compensation circuit according to any one of claims 1 to 8.

10. A display device, characterized in that: The display device includes a power module and the display panel according to claim 9, wherein the power module is configured to provide power to the display panel.

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