Display panel and display device

Abstract

The invention relates to the field of display, and particularly discloses a display panel and a display device.The display panel comprises a substrate, the interior of a display area is divided into a first subarea and a second subarea, and the first subarea is arranged on the periphery of the second subarea; a driving area is further arranged in the first subarea, the display panel further comprises gate driving circuits, the gate driving circuits comprise the first gate driving circuit and the second gate driving circuit, the first gate driving circuit is arranged in the non-display area, and the second gate driving circuit is arranged in the driving area; the first gate drive circuit is at least electrically connected with the display module in the first partition, and the second gate drive circuit is at least electrically connected with the display module in the second partition; the preset refresh rates of the first gate drive circuit and the second gate drive circuit are different. By means of the mode, under the condition that display of the display panel at different refresh rates is achieved, the black edge of the screen is reduced.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a display panel and a display device. Background Art

[0002] In the display panel of a wearable device, the pixels on the entire screen usually use the same refresh rate; however, in actual usage environments, different display partitions of the same display panel do not necessarily need to refresh data in the same display frame. If different display partitions of the same display panel use the same refresh rate for data refresh, the power consumption of the display panel will increase, which will greatly reduce the battery life of the device. Therefore, a partition refresh design is currently used to reduce power consumption.

[0003] Different refresh areas require different gate drive circuits to provide gate signals of different frequencies. And because the drive circuits of the two partitions are usually designed in the non-display area of the frame, it will cause the problem of larger black edges on the screen, resulting in a poor viewing experience.

[0004] Therefore, how to reduce the width of the black border of the screen when displaying at different refresh rates of the display panel. Summary of the Invention

[0005] The present application discloses a display panel and a display device, the purpose of which is to reduce the width of the black border of the screen when the display panel displays at different refresh rates.

[0006] An embodiment of the present application discloses a display panel, which includes a substrate, which is divided into a display area and non-display areas at least on both sides of the display area. The display area is divided into a first partition and a second partition, and the first partition is arranged outside the second partition; a driving area is also provided in the first partition, and the display panel also includes a gate driving circuit, which includes a first gate driving circuit and a second gate driving circuit, the first gate driving circuit is arranged in the non-display area, and the second gate driving circuit is arranged in the driving area; the first gate driving circuit is electrically connected to at least the display module in the first partition, and the second gate driving circuit is electrically connected to at least the display module in the second partition; the first gate driving circuit and the second gate driving circuit have different preset refresh rates.

[0007] Optionally, a plurality of array-arranged display modules are provided in the first partition and the second partition; each of the display modules includes a pixel circuit and a pixel anode, the pixel circuit is located below the pixel anode and is electrically connected to the pixel anode for providing an anode signal to the pixel anode; the second gate drive circuit is located below the pixel anode.

[0008] Optionally, in the display module corresponding to the driving area position, at least part of the pixel circuit and the pixel anode are offset, and at least part of the second gate driving circuit is arranged directly below the pixel anode and in the same layer as the pixel circuit.

[0009] Optionally, the driving region is located on two opposite sides of the second partition, and an edge of the driving region is adjacent to an edge of the second partition.

[0010] Optionally, the orthographic projection area of at least part of the pixel circuits in the first partition on the substrate is smaller than the orthographic projection area of at least part of the pixel circuits in the second partition on the substrate; and / or the number of transistors in at least part of the pixel circuits in the first partition is less than the number of transistors in at least part of the pixel circuits in the second partition.

[0011] Optionally, the scan lines of the first partition and the scan lines of the second partition are disconnected from each other, the scan lines of the first partition are electrically connected to the multiple display modules in the same row of the first partition, and the scan lines of the second partition are electrically connected to the multiple display modules in the same row of the second partition; the refresh rate of the first gate drive circuit is lower than the refresh rate of the second gate drive circuit.

[0012] Optionally, two ends of the scan lines of the second partition are connected to the scan lines of the same row in the first partition via switching tubes.

[0013] Optionally, in the full-screen low refresh mode: the switch tube is in the on state, the first gate drive circuit drives the first partition and the second partition to display at low refresh rate, and the second gate drive circuit is in the off state; in the partition refresh mode: the switch tube is in the off state, the first gate drive circuit drives the first partition to display at low frequency, and the second gate drive circuit drives the second partition to display at high refresh rate; in the first local display mode: the switch tube is in the on state, the second gate drive circuit drives the second partition and the left and right areas of the first partition to display at high refresh rate, the upper and lower areas of the first partition to display at off rate, and the first gate drive circuit is in the off state; in the second local display mode: the switch tube is in the off state; the first gate drive circuit drives the first partition to display at low refresh rate, and the second gate drive circuit is turned off to turn off the display of the second partition; or, the first gate drive circuit is turned off to turn off the display of the first partition, and the second gate drive circuit drives the second partition to display at high refresh rate.

[0014] Optionally, the pixel anode corresponding to the driving area position includes an anode body and an anode wiring, one side of the anode wiring is connected to the anode body, and the other side extends toward the first gate driving circuit and is connected to the staggered pixel circuit.

[0015] An embodiment of the present application further discloses a display device, including a housing. The display device also includes the above-mentioned display panel, and the display panel is disposed in the housing.

[0016] The present application sets two different gate drive circuits in the display panel to control the display modules in the first partition and the second partition of the display area respectively, so that the display modules in the first partition and the second partition display different refresh rates according to the drive signals of different gate drive circuits, thereby realizing different refresh rate displays in different display partitions of the display panel, effectively reducing display power consumption and improving the battery life of the display panel; and the present application only sets the first gate drive circuit in the non-display area of the display panel, and by additionally setting a drive area in the first partition within the display area and setting the second gate drive circuit in the drive area, on the one hand, the influence of the second gate drive circuit on the display of the first partition and the second partition can be reduced, and on the other hand, the first gate drive circuit and the second gate drive circuit will not be concentrated in the non-display area, so that the area of the non-display area can be effectively reduced, thereby reducing the black screen of the display panel, which is beneficial to improving the screen-to-body ratio and display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive work. In the drawings:

[0018] Figure 1 A schematic diagram of partitions in the first embodiment of the display panel of the present application;

[0019] Figure 2 for Figure 1 A partial enlarged view of

[0020] Figure 3 This is a schematic diagram showing the connection between a pixel anode and a pixel circuit in a driving area in a first embodiment of a display panel of the present application;

[0021] Figure 4 This is a structural diagram showing the connection between the pixel anode and the pixel circuit in the driving area in the first embodiment of the display panel of the present application;

[0022] Figure 5 A schematic diagram of partitions in the second embodiment of the display panel of the present application;

[0023] Figure 6 A schematic diagram of partitions in a third embodiment of the display panel of the present application;

[0024] Figure 7 FIG. 1 is a schematic diagram of an embodiment of a display device of the present application.

[0025] Among them, 10, display device; 100, display panel; 200, shell; 110, substrate; 120, display area; 121, first partition; 122, second partition; 123, driving area; 130, non-display area; 140, gate drive circuit; 141, first gate drive circuit; 142, second gate drive circuit; 150, display module; 151, pixel circuit; 151a, first pixel circuit; 151b, second pixel circuit; 152, thin film transistor; 153, base layer; 154, drain; 155, passivation layer; 156, flat layer; 157, via; 160, pixel anode; 161, anode body; 162, anode wiring; 170, scan line; 171, first scan line; 172, second scan line; 180, switch tube; 190, pixel light-emitting unit; 191, light-emitting layer; 192, cathode. DETAILED DESCRIPTION

[0026] The present application is described in detail below with reference to the accompanying drawings and optional embodiments. It should be noted that, under the premise of no conflict, the embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0027] Figure 1 This is a schematic diagram of display partitions in the first embodiment of the display panel of the present application. Figure 2 for Figure 1 A partial enlarged view of Figure 3 This is a schematic diagram showing the connection between a pixel anode and a pixel circuit in a driving area in a first embodiment of a display panel of the present application; Figure 4 This is a structural diagram of the connection between the pixel anode and the pixel circuit in the driving area in the first embodiment of the display panel of the present application; Figures 1 to 4As shown, an embodiment of the present application discloses a display panel 100, which includes a substrate 110. The substrate 110 is divided into a display area 120 and a non-display area 130 arranged at least on both sides of the display area. The display area 120 is divided into a first partition 121 and a second partition 122, and the first partition 121 is arranged outside the second partition 122; a driving area 123 is also arranged in the first partition 121, and the display panel 100 also includes a gate driving circuit 140. The gate driving circuit 140 includes a first gate driving circuit 141 and a second gate driving circuit 142. The first gate driving circuit 141 is arranged in the non-display area 130, and the second gate driving circuit 142 is arranged in the driving area 123; the first gate driving circuit 141 is electrically connected to at least the display module 150 in the first partition 121, and the second gate driving circuit 142 is electrically connected to at least the display module 150 in the second partition 122; the preset refresh rates of the first gate driving circuit 141 and the second gate driving circuit 142 are different.

[0028] In the embodiment of the present application, two different gate drive circuits 140 are provided in the display panel 100 to control the display modules 150 in the first partition 121 and the second partition 122 of the display area 120 respectively, so that the display modules 150 in the first partition 121 and the second partition 122 display different refresh rates according to the drive signals of different gate drive circuits 140, thereby achieving different refresh rate displays in different display partitions of the display panel 100, effectively reducing display power consumption and improving the battery life of the display panel 100; and in the present application, only the first gate drive circuit 141 is provided in the non-display area of the display panel 100. The display area 130 is formed by additionally setting a driving area 123 in the first partition 121 in the display area 120 and setting the second gate driving circuit 142 in the driving area 123. On the one hand, the influence of the second gate driving circuit 142 on the display of the first partition 121 and the second partition 122 can be reduced. On the other hand, the first gate driving circuit 141 and the second gate driving circuit 142 will not be concentrated in the non-display area 130. In this way, the area of the non-display area 130 can be effectively reduced, thereby reducing the black border of the display panel 100, which is beneficial to improving the screen-to-body ratio and display effect of the display panel 100.

[0029] It should be noted that the display panel 100 in the embodiments of the present application is primarily for use with a limited screen size and relatively high internal space requirements, such as the display panel 100 in a wearable device, including a display panel 100 in a smartwatch. In other embodiments, the display panel 100 may also be used in other display devices, such as monitors and televisions.

[0030] When the display panel 100 of the embodiment of the present application is the display panel 100 in a smart watch, the first partition 121 can be a display area 120 that displays a time scale on the periphery of the display panel 100, and the second partition 122 can be a display area 120 that displays relevant information such as a pointer in the middle of the display panel 100. Since the first partition 121 displays a fixed time scale image and the second partition 122 displays a real-time changing image, when the first gate drive circuit 141 and the second gate drive circuit 142 respectively control the first partition 121 and the second partition 122 to display different refresh rates, the refresh rate of the first partition 121 can be lower than the refresh rate of the second partition 122, which can effectively reduce the power consumption of the smart watch and extend the service life of the display panel 100.

[0031] refer to Figure 2 In the embodiment of the present application, the first gate driving circuit 141 and the second gate driving circuit 142 are respectively distributed in the non-display area 130 and the display area 120. The first gate driving circuit 141 can provide a gate signal for row-by-row scanning for the pixel circuit 151 (first pixel circuit 151a) in the first partition 121, and the second gate driving circuit 142 can provide a gate signal for row-by-row scanning for the pixel circuit 151 (second pixel circuit 151b) in the second partition 122. The non-display area 130 is also provided with a driving chip, and the driving chip inputs the data signal of each frame of the picture through the data write line.

[0032] For details, please refer to Figure 2 A plurality of array-arranged display modules 150 are provided in the first partition 121 and the second partition 122; each display module 150 includes a pixel circuit 151 and a pixel light emitting unit 190 (refer to FIG. Figure 4 ), the pixel light emitting unit 190 includes a pixel anode 160, a light emitting layer 191 and a cathode 192 (reference Figure 4 The pixel circuit 151 is located below the pixel anode 160 and is electrically connected to the pixel anode 160 for providing an anode signal to the pixel anode 160 to control the pixel light emitting unit 190 to emit light for display. The second gate driving circuit 142 is located below the pixel anode 160 .

[0033] In the display area 120 of the embodiment of the present application, a plurality of display modules 150 are arrayed, and each display module 150 independently controls the pixel anode 160 through the pixel circuit 151 to ensure normal display of the first partition 121 and the second partition 122. In the present application, the second gate drive circuit 142 is arranged below the pixel anode 160, that is, the side of the pixel anode 160 facing away from the light-emitting side, so that the second gate drive circuit 142 can avoid blocking the pixel light-emitting unit, thereby ensuring that the light emitted by the pixel light-emitting unit can be displayed normally.

[0034] Since the second gate driving circuit 142 needs to be disposed in the driving region 123 of the display panel 100, if it is disposed directly below the display module 150 in the driving region 123, the overall thickness of the display panel 100 will increase. Therefore, in order to ensure that the second gate driving circuit 142 can be properly disposed below the pixel anode 160, the present application has made improvements to the display module 150 located in the driving region 123:

[0035] In the display module 150 corresponding to the driving area 123, at least part of the pixel circuit 151 is staggered with the pixel anode 160 to avoid the second gate driving circuit 142. At least part of the second gate driving circuit 142 is set directly below the pixel anode 160 and is set on the same layer as the pixel circuit 151.

[0036] In other words, reference Figure 4 In the display module 150 of the driving area 123 in the display panel 100, the pixel circuit 151 is located obliquely below the pixel anode 160, and the pixel circuit 151 and the pixel anode 160 are staggered. In other areas, the pixel circuits 151 close to the driving area 123 are also staggered accordingly. This can make the overall occupied space of the display module 150 smaller, so that more display modules 150 can be arranged in the same display panel 100, thereby effectively improving the display effect of the display panel 100; by staggering the pixel circuit 151 and the pixel anode 160 of the display module 150 in the driving area 123, the pixel circuit 151 is staggered relative to the pixel anode 160. Corresponding space is avoided at the same layer position, so that the second gate drive circuit 142 can be arranged directly below the pixel anode 160 and arranged on the same layer as the pixel circuit 151, effectively utilizing the wiring space within the display panel 100, and without additionally increasing the thickness of the display panel 100, the second gate drive circuit 142 is arranged in the display area 120, so that the non-display area 130 of the display panel 100 only needs to be arranged with the first gate drive circuit 141, and there is no need to arrange two gate drive circuits 140 in the non-display area 130 at the same time, thereby effectively reducing the area of the non-display area 130, which is beneficial to reducing the width of the black border of the display panel 100.

[0037] Furthermore, in order to reduce the impact of the second gate driving circuit 142 on the pixel circuit 151 after it is disposed below the pixel anode 160 and to ensure the stability of the connection between the pixel circuit 151 and the pixel anode 160, so that the pixel anode 160 located in the driving area 123 can emit light normally under the control of the pixel circuit 151, the present application further improves the structure of the pixel anode 160 located in the driving area 123, as follows:

[0038] refer to Figure 3 The pixel anode 160 corresponding to the driving area 123 includes an anode body 161 and an anode wiring 162 . One side of the anode wiring 162 is connected to the anode body 161 , and the other side is connected to the pixel circuit 151 arranged in an offset manner through a via 157 .

[0039] In the embodiment of the present application, the pixel anode 160 in the driving area 123 includes an anode body 161 and an anode wiring 162. The anode wiring 162 is connected to the anode body 161, making it an extension of the anode body 161. The anode wiring 162 is extended toward the first gate driving circuit 141 so as to be connected to the staggered pixel circuit 151. In this way, the relatively staggered pixel circuit 151 can be connected to the anode body 161 at a certain distance through the anode wiring 162. Even in the case of a staggered setting, electrical conduction can be ensured between the pixel circuit 151 and the anode body 161, and the anode body 161 can be controlled by the pixel circuit 151 to perform light-emitting display. In addition, since the anode wiring 162 extends toward the first gate driving circuit 141, that is, toward the non-display area, the influence of the anode wiring 162 on the second partition 122 that mainly performs display can be minimized, thereby ensuring the overall display effect of the display panel 100.

[0040] Of course, in order to cooperate with the misalignment of the pixel circuit 151 in the driving area 123, the pixel anode 160 in the area between the first gate driving circuit 141 and the second gate driving circuit 142 can also adopt the above design, so that the corresponding pixel circuit 151 is also misaligned accordingly when cooperating with the misalignment of the pixel circuit 151 in the driving area 123, and is connected to the pixel anode 160 at the original position. In this way, the normal display of the area can be guaranteed without reducing the display module 150, thereby ensuring the display effect of the display panel 100.

[0041] For further reference, Figure 4 Pixel circuit 151 includes a thin film transistor 152, which is disposed on a base layer 153. Thin film transistor 152 includes a drain electrode 154, a passivation layer 155, and a planarization layer 156, which are sequentially stacked on base layer 153. A via 157 is formed through passivation layer 155 and planarization layer 156, and anode trace 162 is connected to drain electrode 154 through via 157. Second gate driver circuit 142 also includes a thin film transistor 152, and the multi-layer structure of thin film transistor 152 of second gate driver circuit 142 can be disposed on the same layer as the multi-layer structure of thin film transistor 152 of pixel circuit 151.

[0042] In the embodiment of the present application, the anode trace 162 extending from the anode body 161 is directly connected to the drain 154 of the thin film transistor 152 in the pixel circuit 151 through the via 157, which can reduce resistance and thus improve the response speed and stability of the circuit.

[0043] Continue to refer Figure 2 , the orthographic projection area of at least part of the pixel circuit 151 of the first partition 121 on the substrate 110 is smaller than the orthographic projection area of at least part of the pixel circuit 151 of the second partition 122 on the substrate 110; and / or, the number of transistors in at least part of the pixel circuit 151 of the first partition 121 is less than the number of transistors in at least part of the pixel circuit 151 of the second partition 121.

[0044] In this embodiment, the orthographic projection area of the pixel circuit 151 of the first partition 121 on the substrate 110 is smaller than the orthographic projection area of the pixel circuit 151 of the second partition 122 on the substrate 110, so that the space occupied by the pixel circuit 151 in the first partition 121 can be further reduced, thereby allowing the second gate driver circuit 142 on the same layer as the pixel circuit 151 to obtain a larger layout space. Therefore, without affecting the normal layout of the pixel circuits 151 in the first partition 121 and the second partition 122, the second gate driver circuit 142 is arranged in the display area 120, thereby effectively utilizing the wiring space in the display panel 100. Moreover, the second gate driver circuit 142 can be arranged in the display panel 100 without additionally increasing the thickness of the display panel 100, so that the non-display area 130 of the display panel 100 only needs to be arranged with the first gate driver circuit 141, and there is no need to arrange both gate driver circuits 140 in the non-display area 130 at the same time, thereby effectively reducing the width of the black border of the display panel 100.

[0045] In addition, taking the display panel 100 as the display panel of a smart watch as an example, since the first partition 121 is mainly used to display relatively static content (such as a time scale), and the second partition 122 is mainly used to display dynamic content (such as a pointer or real-time updated information), the power consumption of the first partition 121 is actually less than that of the second partition 122. When the number of transistors in the pixel circuit 151 of the first partition 121 is less than the number of transistors in the pixel circuit 151 of the second partition 122, the power consumption of the first partition 121 is further reduced.

[0046] In addition, compared with the dynamic display of the second partition 122, the static display of the first partition 121 has lower requirements for display quality. Therefore, the first partition 121 can simplify the pixel circuit function and use fewer transistors and a smaller orthographic projection area to meet the basic display requirements; while the pixel circuit of the second partition 122 uses more transistors and a larger orthographic projection area to bring higher display quality. For example, compared with the first pixel circuit 151a, the second pixel circuit 151b can add transistors with functions such as reset and compensation, and its transistors can use a larger feature size.

[0047] Of course, it is also possible to set the number of transistors in the pixel circuit 155 of the first partition 121 to be less than the number of transistors in the pixel circuit 155 of the second partition 122 while making the orthographic projection area of the pixel circuit 151 of the first partition 121 on the substrate 110 smaller than the orthographic projection area of the pixel circuit 155 of the second partition 122 on the substrate 110; in this way, it is possible to reduce the power consumption of the display panel 100 while reducing the black border width of the display panel 100, thereby ensuring both low power consumption and better display effect.

[0048] In some embodiments, as Figure 5 As shown, Figure 5 1 is a schematic diagram of partitions in the second embodiment of the display panel of the present application. The driving region 123 is located on two opposite sides of the second partition 122 , and the edge of the driving region 123 is adjacent to the edge of the second partition 122 .

[0049] In this embodiment, the driving area 123 is arranged on opposite sides of the second partition 122, and its edges are adjacent to the edges of the second partition 122, which can effectively utilize the limited space in the display area 120; and avoids the second gate driving circuit 142 in the driving area 123 occupying the space of the non-display area 130, thereby helping to reduce the overall area of the non-display area 130, thereby reducing the black border of the display panel 100.

[0050] In addition, the driving area 123 being adjacent to the second partition 122 can also shorten the distance between the second gate driving circuit 142 and the corresponding display module 150 , thereby reducing loss and delay in signal transmission and improving driving efficiency.

[0051] The following will describe several display modes in detail in combination with the relationship between the two gate driving circuits 140 and the two partitions.

[0052] refer to Figure 2The scan lines 170 of the first partition 121 are disconnected from the scan lines 170 of the second partition 122. The scan lines 170 of the first partition 121 are electrically connected to the multiple display modules 150 in the same row of the first partition 121, while the scan lines 170 of the second partition 122 are electrically connected to the multiple display modules 150 in the same row of the second partition 122. The refresh rate of the first gate driver circuit 141 is lower than the refresh rate of the second gate driver circuit 142. In other words, the first scan lines 171 and the second scan lines 172 are isolated from each other, driving the first partition 121 and the second partition 122 for display, respectively, without crossing the driven partitions. In some embodiments, the first scan lines 171 may extend only in the first partition 121; in other embodiments, the first scan lines 171 may extend from the first partition 121 to the second partition 122, i.e., the first scan lines 171 span the entire display area 120 but are not electrically connected to the display modules 150 in the second partition 122.

[0053] In this embodiment, the display panel 100 is taken as the display panel on a smart watch as an example. Since the display content of the first partition 121 is usually static (such as a time scale), its refresh rate can be set to a lower level, thereby significantly reducing the power consumption of this area; while the second partition 122 is responsible for dynamic display content (such as pointers or real-time information), and requires a higher refresh rate to ensure a smooth display effect.

[0054] Therefore, in this embodiment, by disconnecting the scan lines of the first partition 121 and the second partition 122 from each other, the scan line of the first partition 121 controls the display module 150 in the first partition 121, and the scan line 170 of the second partition 122 controls the display module 150 in the second partition 122, so that each partition can independently transmit the gate drive signal; in this way, the refresh rate of the first partition 121 and the second partition 122 can be set separately according to their respective needs, avoiding signal crosstalk between the two partitions, thereby improving the stability and clarity of the display.

[0055] refer to Figure 6 , Figure 6 This is a schematic diagram of the partitions in the third embodiment of the display panel of the present application. Figure 6 In the illustrated embodiment, both ends of the scan line 170 of the second partition 122 are connected to the same row of scan lines 170 of the first partition 121 via a switch tube 180 .

[0056] This embodiment differs from the previous embodiment in that, in this embodiment, the scan lines 170 of the second subarea 122 are connected to the scan lines 170 of the first subarea 121 in the same row via a switch 180. In other words, a switch 180 can be provided between the first scan line 171 and the second scan line 172 in the same row. The switch 180 can control whether the first scan line 171 is electrically connected to or disconnected from the second scan line 172. The switch 180 can be a thin-film transistor (TFT), and the gates of all TFT switches can be connected together and controlled by the same signal, thereby simplifying the control of the switches 180. For example, if all switches 180 are NTFTs, a high voltage input to their gates turns them on, while a low voltage input to their gates turns them off. Of course, the switches 180 can also be PTFTs. By controlling the states of the switches 180, different display states can be achieved for the two subareas.

[0057] When it is determined that both subareas can display at a low refresh rate, the control switch 180 is turned on. At this time, the pixel circuits 151 in the first subarea 121 and the second subarea 122 are driven by the first gate driver circuit 141 in the non-display area 130, and the second gate driver circuit 142 in the display area 120 does not need to operate. In other words, in this mode, only the first gate driver circuit 141 drives all scan lines 170, and the second gate driver circuit 142 does not need to provide drive signals to the scan lines 170, thereby achieving the purpose of reducing power consumption.

[0058] When the first partition 121 is refreshed at low speed and the second partition 122 is refreshed at high speed, the switch 180 can be controlled to be disconnected. At this time, the pixel circuits 151 in the two partitions are driven by their respective corresponding gate drive circuits. In this mode, both gate drive circuits 140 need to work.

[0059] If the drive area 123 is located on the left and right sides of the second subarea 122, when partial display is required, for example, the upper and lower sides of the first subarea 121 are not displayed, and the left and right sides of the second subarea 122 and the first subarea 121 are displayed, the switch tube 180 is turned on, and the second gate drive circuit 142 of the display area 120 is driven. The first gate drive circuit 141 of the non-display area 130 is directly turned off, which can also achieve the purpose of reducing power consumption. In this mode, the second gate drive circuit 142 needs to operate, and the first gate drive circuit 141 does not need to operate.

[0060] Specifically, in the full-screen low refresh mode: the switch tube 180 is in the on state, the first gate drive circuit 141 drives the first partition 121 and the second partition 122 to display low refresh, and the second gate drive circuit 142 is in the off state;

[0061] In the partition refresh mode: the switch tube 180 is in the off state, the first gate drive circuit 141 drives the first partition 121 to display at a low frequency, and the second gate drive circuit 142 drives the second partition 122 to display at a high refresh rate;

[0062] In the first partial display mode, the switch tube 180 is in the on state, the second gate drive circuit 142 drives the second partition 122 and the left and right areas of the first partition 121 to display in high refresh rate, the upper and lower areas of the first partition 121 are turned off, and the first gate drive circuit 141 is in the off state.

[0063] In the second partial display mode: the switch tube 180 is in the off state; the first gate drive circuit 141 drives the first partition 121 to display at a low refresh rate, and the second gate drive circuit 142 is turned off to turn off the display of the second partition 122; or, the first gate drive circuit 141 is turned off to turn off the display of the first partition 121, and the second gate drive circuit 142 drives the second partition 122 to display at a high refresh rate.

[0064] In this embodiment, in the full-screen low refresh mode, the switch tube 180 is turned on, and the first gate drive circuit 141 drives the first partition 121 and the second partition 122 at the same time, so that both are displayed at a low refresh rate; at this time, the second gate drive circuit 142 is turned off, avoiding unnecessary power consumption, thereby reducing the overall power consumption of the display panel.

[0065] In partition refresh mode, switch 180 is off, and first gate driver circuit 141 drives only first partition 121 at a low refresh rate, while second gate driver circuit 142 drives second partition 122 at a high refresh rate. This allows for flexible adjustment of the refresh rate based on actual usage, further optimizing power consumption and ensuring smooth display of dynamic content areas while maintaining low power consumption in static content areas.

[0066] In the first partial display mode, the switch 180 is turned on, and the second gate drive circuit 142 drives the second partition 122 and the left and right areas of the first partition 121 to display at a high refresh rate, while the upper and lower areas of the first partition 121 are turned off. This enables the center and left and right sides of the screen to display at a high refresh rate, enabling the display of local dynamic content at a high refresh rate, while turning off unnecessary areas to save power.

[0067] In the second partial display mode, there are two working states:

[0068] The first partition 121 displays at a low refresh rate, while the second partition 122 is completely off; alternatively, the first partition 121 is completely off, while the second partition 122 displays at a high refresh rate. This allows for flexible selection of display areas based on user needs. By dynamically switching between the first gate drive circuit 141 and the second gate drive circuit 142 by switching the switch 180 on or off, different display effects can be achieved.

[0069] This embodiment can flexibly adapt to various application scenarios through a variety of display modes, including low-power standby, dynamic content display, local high refresh display, etc., to meet the diverse needs of users.

[0070] It should be noted that the above-mentioned display modes can be detected and identified by the sensor inside the display panel 100 to determine the user's usage status, and the display panel 100 can be controlled to be in different display modes according to the system program built into the display panel 100, thereby controlling the state of the switch tube 180 in the corresponding display mode. The method of controlling the display panel 100 to be in different display modes through the system program and switching the state of the switch tube 180 using the driver chip in different modes are conventional means in this field and will not be repeated in this application.

[0071] Figure 7 This is a schematic diagram of an embodiment of the display device of the present application, as shown in FIG. Figure 7 As shown, the embodiment of the present application further discloses a display device 10, comprising a housing 200. The display device 10 also comprises the aforementioned display panel 100, which is disposed within the housing 200. The housing 200 is used to protect the display panel 100 from damage caused by external forces during movement, and can prevent external moisture from entering the display panel 100 to a certain extent, thereby effectively improving the service life of the display device 10.

[0072] It should be noted that the display device 10 in the present application is mainly for display devices that have limitations in screen size and have high requirements for internal space structure, such as smart watches among wearable devices.

[0073] However, in a display device, display panels with different refresh partitions require different gate drive circuits to provide gate signals of different frequencies, and since the drive circuits of different partitions are usually designed in the non-display area of the display panel frame, it will cause the problem of large black edges on the screen, resulting in a poor viewing experience.

[0074] Based on the above problems, the present application sets two different gate drive circuits 140 in the display panel 100 to control the display modules 150 in the first partition 121 and the second partition 122 of the display area 120 respectively, so that the display modules 150 in the first partition 121 and the second partition 122 display different refresh rates according to the drive signals of different gate drive circuits 140, thereby achieving different refresh rate displays in different display partitions of the display panel 100, effectively reducing display power consumption and improving the battery life of the display panel 100; and the present application only sets the first gate drive circuit 141 in the non-display area 121 of the display panel 100. 30, and by additionally setting a driving area 123 in the first partition 121 in the display area 120 and setting the second gate driving circuit 142 in the driving area 123, on the one hand, the influence of the second gate driving circuit 142 on the display of the first partition 121 and the second partition 122 can be reduced, and on the other hand, the first gate driving circuit 141 and the second gate driving circuit 142 will not be concentrated in the non-display area 130, so that the area of the non-display area 130 can be effectively reduced, thereby reducing the black screen of the display panel 100, which is beneficial to improving the screen-to-body ratio and display effect of the display panel 100, and further improving the quality of the display device 10.

[0075] It should be noted that the inventive concept of this application can form a large number of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the various embodiments or technical features described above can be arbitrarily combined to form new embodiments. After the various embodiments or technical features are combined, the original technical effects will be enhanced.

[0076] The above content is a further detailed description of the present application in conjunction with specific optional implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, they can make several simple deductions or substitutions without departing from the concept of the present application, which should be considered to fall within the scope of protection of the present application.

Claims

1. A display panel comprising a substrate, wherein the substrate is divided into a display area and non-display areas at least provided on both sides of the display area, wherein: The display area is divided into a first partition and a second partition, and the first partition is arranged outside the second partition; A driving area is further provided in the first subarea, and the display panel further includes a gate driving circuit, the gate driving circuit including a first gate driving circuit and a second gate driving circuit, the first gate driving circuit being provided in the non-display area, and the second gate driving circuit being provided in the driving area; the first gate driving circuit being electrically connected to at least the display module in the first subarea, and the second gate driving circuit being electrically connected to at least the display module in the second subarea; The first gate driving circuit and the second gate driving circuit have different preset refresh rates.

2. The display panel according to claim 1, wherein A plurality of array-arranged display modules are provided in the first partition and the second partition; each of the display modules includes a pixel circuit and a pixel anode, the pixel circuit is electrically connected to the pixel anode and is used to provide an anode signal to the pixel anode; the second gate drive circuit is located below the pixel anode.

3. The display panel according to claim 2, wherein: In the display module corresponding to the driving area, at least part of the pixel circuit is offset from the pixel anode, and at least part of the second gate driving circuit is arranged directly below the pixel anode and in the same layer as the pixel circuit.

4. The display panel according to claim 3, wherein: The driving regions are located at two opposite sides of the second partition, and edges of the driving regions are adjacent to edges of the second partition.

5. The display panel according to claim 3, wherein: An orthographic projection area of at least a portion of the pixel circuits in the first subarea on the substrate is smaller than an orthographic projection area of at least a portion of the pixel circuits in the second subarea on the substrate; And / or, the number of transistors in at least part of the pixel circuits in the first partition is less than the number of transistors in at least part of the pixel circuits in the second partition.

6. The display panel according to claim 3, wherein: The scan lines of the first partition and the scan lines of the second partition are disconnected from each other, the scan lines of the first partition are electrically connected to the multiple display modules in the same row of the first partition, and the scan lines of the second partition are electrically connected to the multiple display modules in the same row of the second partition; A refresh rate of the first gate driving circuit is lower than a refresh rate of the second gate driving circuit.

7. The display panel according to claim 3, wherein: Both ends of the scan lines of the second partition are connected to the scan lines of the same row in the first partition via switch tubes.

8. The display panel according to claim 7, wherein: In the full-screen low refresh mode: the switch tube is in the on state, the first gate drive circuit drives the first partition and the second partition to display in the low refresh mode, and the second gate drive circuit is in the off state; In the partition refresh mode: the switch tube is in the off state, the first gate drive circuit drives the first partition to display at a low frequency, and the second gate drive circuit drives the second partition to display at a high refresh rate; In the first partial display mode, the switch tube is in the on state, the second gate drive circuit drives the second partition and the left and right areas of the first partition to display at a high refresh rate, the upper and lower areas of the first partition are turned off, and the first gate drive circuit is in the off state; In the second partial display mode: the switch tube is in the cut-off state; the first gate drive circuit drives the first partition to display at a low refresh rate, and the second gate drive circuit is turned off to turn off the display of the second partition; or, the first gate drive circuit is turned off to turn off the display of the first partition, and the second gate drive circuit drives the second partition to display at a high refresh rate.

9. The display panel according to claim 3, wherein: The pixel anode corresponding to the driving area position includes an anode body and an anode wiring. One side of the anode wiring is connected to the anode body, and the other side is connected to the pixel circuit arranged in a staggered manner through a via hole.

10. A display device comprising a housing, characterized in that: The display device further includes a display panel according to any one of claims 1 to 9, and the display panel is disposed in the housing.

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