Display panel and display device

Abstract

The application relates to the display field and specifically discloses a display panel and a display device. The display panel comprises a substrate, a first subarea and a second subarea are divided in a display area, the first subarea is arranged at the periphery of the second subarea, a driving area is further arranged in the first subarea, the display panel further comprises a gate driving circuit, the gate driving circuit comprises a first gate driving circuit and a second gate driving circuit, the first gate driving circuit is arranged in the non-display area, and the second gate driving circuit is arranged in the driving area; the first gate driving circuit is electrically connected with at least a display module in the first subarea, the second gate driving circuit is electrically connected with at least a display module in the second subarea; and the preset refresh rates of the first gate driving circuit and the second gate driving circuit are different. In the case of realizing different refresh rate display of the display panel, the application reduces the screen black border through the above mode.

Description

Technical Field

[0001] This application relates to the field of displays, and more particularly to a display panel and a display device. Background Technology

[0002] In the display panels of wearable devices, the entire screen pixels usually use the same refresh rate; however, in actual use, different display partitions of the same display panel may not necessarily need to refresh data under the same display frame. If different display partitions of the same display panel use the same refresh rate to refresh data, it will increase the power consumption of the display panel, which will greatly reduce the battery life of the device. Therefore, partitioned refresh design is currently used to reduce power consumption.

[0003] Different refresh areas require different gate drive circuits to provide gate signals of different frequencies. Since the drive circuits for both types of zones are usually designed in the non-display area of ​​the bezel, it causes a large black border on the screen, resulting in a poor viewing experience.

[0004] Therefore, how can we reduce the width of the black border on the screen while enabling different refresh rates on the display panel? Summary of the Invention

[0005] This application discloses a display panel and a display device, the purpose of which is to reduce the width of the black border on the screen while achieving different refresh rates of the display panel.

[0006] This application discloses a display panel, which includes a substrate. The substrate is divided into a display area and non-display areas at least on both sides of the display area. The display area is characterized by being divided into a first partition and a second partition, with the first partition located around the second partition. The first partition also includes a driving area. The display panel further includes a gate driving circuit, comprising a first gate driving circuit and a second gate driving circuit. The first gate driving circuit is located within the non-display area, and the second gate driving circuit is located within the driving area. The first gate driving circuit is electrically connected to at least a display module within the first partition, and the second gate driving circuit is electrically connected to at least a display module within the second partition. The first gate driving circuit and the second gate driving circuit have different preset refresh rates.

[0007] Optionally, both the first and second partitions are provided with multiple display modules arranged in an array; each display module includes a pixel circuit and a pixel anode, the pixel circuit is located below the pixel anode and electrically connected to the pixel anode, and is used to provide an anode signal to the pixel anode; the second gate driving circuit is located below the pixel anode.

[0008] Optionally, in the display module corresponding to the position of the driving area, at least a portion of the pixel circuit is misaligned with the pixel anode, and at least a portion of the second gate driving circuit is disposed directly below the pixel anode and disposed on the same layer as the pixel circuit.

[0009] Optionally, the driving regions are located on opposite sides of the second partition, and the edges of the driving regions are adjacent to the edges of the second partition.

[0010] Optionally, the projected area of ​​at least a portion of the pixel circuits in the first partition on the substrate is smaller than the projected area of ​​at least a portion of the pixel circuits in the second partition on the substrate; and / or, the number of transistors in at least a portion of the pixel circuits in the first partition is less than the number of transistors in at least a portion of the pixel circuits in the second partition.

[0011] Optionally, the scan lines of the first partition and the scan lines of the second partition are disconnected from each other. The scan lines of the first partition are electrically connected to a plurality of display modules in the same row of the first partition, and the scan lines of the second partition are electrically connected to a plurality of display modules in the same row of the second partition. The refresh rate of the first gate driving circuit is lower than the refresh rate of the second gate driving circuit.

[0012] Optionally, the two ends of the scan line of the second partition are connected to the same row of the scan line of the first partition via a switching transistor.

[0013] Optionally, in full-screen low refresh rate mode: the switching transistor is in the on state, the first gate driving circuit drives both the first partition and the second partition to display at a low refresh rate, and the second gate driving circuit is in the off state; in partition refresh rate mode: the switching transistor is in the off state, the first gate driving circuit drives the first partition to display at a low frequency, and the second gate driving circuit drives the second partition to display at a high refresh rate; in the first partial display mode: the switching transistor is in the on state, the second gate driving circuit drives the second partition and the left and right sides of the first partition to display at a high refresh rate, the top and bottom sides of the first partition are turned off, and the first gate driving circuit is in the off state; in the second partial display mode: the switching transistor is in the off state; the first gate driving circuit drives the first partition to display at a low refresh rate, and the second gate driving circuit is turned off to turn off the display of the second partition; or, the first gate driving circuit is turned off to turn off the display of the first partition, and the second gate driving circuit drives the second partition to display at a high refresh rate.

[0014] Optionally, the pixel anode corresponding to the position of the driving region includes an anode body and an anode trace. One side of the anode trace is connected to the anode body, and the other side extends toward the first gate driving circuit and is connected to the pixel circuit that is misaligned.

[0015] This application also discloses a display device, including a housing, and the display device further includes the aforementioned display panel, which is disposed within the housing.

[0016] This application sets up two different gate driving circuits within the display panel to control the display modules in the first and second partitions of the display area, respectively. This allows the display modules in the first and second partitions to display different refresh rates according to the driving signals of the different gate driving circuits, thereby achieving different refresh rate displays in different display partitions of the display panel. This effectively reduces display power consumption and improves the battery life of the display panel. Furthermore, this application only places the first gate driving circuit in the non-display area of ​​the display panel, while additionally setting up a driving area within the first partition of the display area and placing the second gate driving circuit within the driving area. On the one hand, this reduces the impact of the second gate driving circuit on the display of the first and second partitions; on the other hand, it prevents the first and second gate driving circuits from being concentrated in the non-display area, thus effectively reducing the area of ​​the non-display area and reducing black screen on the display panel, which is beneficial to improving the screen ratio and display effect of the display panel. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the embodiments of this application and form part of the specification. They serve to demonstrate implementation methods of this application and, together with the textual description, explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort. In the drawings:

[0018] Figure 1 This is a schematic diagram of the partitions in the first embodiment of the display panel of this application;

[0019] Figure 2 for Figure 1 A magnified view of a portion of the image;

[0020] Figure 3 This is a schematic diagram showing the connection between the pixel anode and the pixel circuit in the driving area of ​​the first embodiment of the display panel of this application;

[0021] Figure 4 This is a structural diagram showing the connection between the pixel anode and the pixel circuit in the driving area of ​​the display panel in the first embodiment of this application;

[0022] Figure 5 This is a schematic diagram of the partitions in the second embodiment of the display panel of this application;

[0023] Figure 6 This is a schematic diagram of the partitions in the third embodiment of the display panel of this application;

[0024] Figure 7 This is a schematic diagram of an embodiment of the display device of this application.

[0025] Wherein, 10 is a display device; 100 is a display panel; 200 is a housing; 110 is a substrate; 120 is a display area; 121 is a first partition; 122 is a second partition; 123 is a driving area; 130 is a non-display area; 140 is a gate driving circuit; 141 is a first gate driving circuit; 142 is a second gate driving circuit; 150 is a display module; 151 is a pixel circuit; 151a is a first pixel circuit; 151b is a second pixel circuit; 152 is a thin-film transistor; 153 is a substrate layer; 154 is a drain; 155 is a passivation layer; 156 is a planarization layer; 157 is a via; 160 is a pixel anode; 161 is an anode body; 162 is an anode trace; 170 is a scan line; 171 is a first scan line; 172 is a second scan line; 180 is a switching transistor; 190 is a pixel light-emitting unit; 191 is a light-emitting layer; 192 is a cathode. Detailed Implementation

[0026] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0027] Figure 1 This is a schematic diagram of the display partition in the first embodiment of the display panel of this application. Figure 2 for Figure 1 A magnified view of a portion of the image. Figure 3 This is a schematic diagram showing the connection between the pixel anode and the pixel circuit in the driving area of ​​the first embodiment of the display panel of this application; Figure 4 This is a structural diagram showing the connection between the pixel anode and the pixel circuit in the driving area of ​​the display panel in the first embodiment of this application; as shown. Figures 1 to 4As shown in the figure, this application discloses a display panel 100, which includes a substrate 110. The substrate 110 is divided into a display area 120 and non-display areas 130 at least on both sides of the display area. The display area 120 is divided into a first partition 121 and a second partition 122. The first partition 121 is located outside the second partition 122. A driving area 123 is also provided in the first partition 121. The display panel 100 also includes a gate driving circuit 140, which includes a first gate driving circuit 141 and a second gate driving circuit 142. The first gate driving circuit 141 is located in the non-display area 130, and the second gate driving circuit 142 is located in the driving area 123. The first gate driving circuit 141 is electrically connected to at least a display module 150 in the first partition 121, and the second gate driving circuit 142 is electrically connected to at least a display module 150 in the second partition 122. The first gate driving circuit 141 and the second gate driving circuit 142 have different preset refresh rates.

[0028] This application embodiment uses two different gate driving circuits 140 within the display panel 100 to control the display modules 150 in the first partition 121 and the second partition 122 of the display area 120, respectively. This allows the display modules 150 in the first partition 121 and the second partition 122 to display different refresh rates according to the driving signals of the different gate driving circuits 140, thereby achieving different refresh rate displays in different display partitions of the display panel 100. This effectively reduces display power consumption and improves the battery life of the display panel 100. Furthermore, this application only places the first gate driving circuit 141 in the non-... The display area is 130. By additionally setting a driving area 123 within the first partition 121 of the display area 120 and setting the second gate driving circuit 142 within the driving area 123, the influence of the second gate driving circuit 142 on the display of the first partition 121 and the second partition 122 can be reduced. On the other hand, the first gate driving circuit 141 and the second gate driving circuit 142 will not be concentrated in the non-display area 130. This can effectively reduce the area of ​​the non-display area 130, thereby reducing the black border of the display panel 100 and improving the screen ratio and display effect of the display panel 100.

[0029] It should be noted that the display panel 100 in this embodiment is mainly a display panel 100 with limited screen size and high requirements for its internal space structure, such as the display panel 100 in wearable devices, including the display panel 100 in smartwatches. In other embodiments, it can also be applied to other display devices, such as monitors, televisions, etc.

[0030] When the display panel 100 in this embodiment is a display panel 100 in a smartwatch, the first partition 121 can be a display area 120 on the periphery of the display panel 100 that displays time scales, and the second partition 122 can be a display area 120 in the middle of the display panel 100 that displays pointers and other related information. Since the first partition 121 displays a fixed time scale image, while the second partition 122 displays a real-time changing image, when the first gate driving circuit 141 and the second gate driving circuit 142 control the first partition 121 and the second partition 122 to display different refresh rates, the refresh rate of the first partition 121 can be lower than the refresh rate of the second partition 122. This can effectively reduce the power consumption of the smartwatch and extend the service life of the display panel 100.

[0031] refer to Figure 2 In this embodiment, the first gate driving circuit 141 and the second gate driving circuit 142 are respectively distributed in the non-display area 130 and the display area 120. The first gate driving circuit 141 can provide the pixel circuit 151 (first pixel circuit 151a) in the first partition 121 with a progressive scan gate signal, and the second gate driving circuit 142 can provide the pixel circuit 151 (second pixel circuit 151b) in the second partition 122 with a progressive scan gate signal. The non-display area 130 is also provided with a driving chip, which inputs the data signal of each frame of the image through the data writing line.

[0032] For details, please refer to [link / reference]. Figure 2 Each of the first partition 121 and the second partition 122 contains multiple display modules 150 arranged in an array; each display module 150 includes a pixel circuit 151 and a pixel light-emitting unit 190 (see reference). Figure 4 The pixel light-emitting unit 190 includes a pixel anode 160, a light-emitting layer 191, and a cathode 192 (see reference). Figure 4 The pixel circuit 151 is located below the pixel anode 160 and is electrically connected to the pixel anode 160. It is used to provide an anode signal to the pixel anode 160 and control the pixel light-emitting unit 190 to emit light for display. The second gate driving circuit 142 is located below the pixel anode 160.

[0033] In this embodiment, multiple display modules 150 are arrayed within the display area 120. Each display module 150 independently controls the pixel anode 160 through the pixel circuit 151 to ensure the normal display of the first partition 121 and the second partition 122. In this application, the second gate driving circuit 142 is located below the pixel anode 160, that is, on the side of the pixel anode 160 that is away from the light-emitting side. This allows the second gate driving circuit 142 to avoid blocking the pixel light-emitting unit, thereby ensuring that the light emitted by the pixel light-emitting unit can be displayed normally.

[0034] Since the driving region 123 within the display panel 100 needs to house the second gate driving circuit 142, directly placing it below the display module 150 in the driving region 123 would increase the overall thickness of the display panel 100. Therefore, to ensure that the second gate driving circuit 142 can be properly positioned below the pixel anode 160, this application has made improvements to the display module 150 located within the driving region 123.

[0035] In the display module 150 corresponding to the position of the driving region 123, at least a portion of the pixel circuit 151 is offset from the pixel anode 160 to avoid the second gate driving circuit 142. At least a portion of the second gate driving circuit 142 is located directly below the pixel anode 160 and is arranged on the same layer as the pixel circuit 151.

[0036] In other words, reference Figure 4 In the display module 150 of the driving area 123 within the display panel 100, the pixel circuit 151 is located diagonally below the pixel anode 160, and the pixel circuit 151 and the pixel anode 160 are offset. In other areas, the pixel circuits 151 near the driving area 123 are also offset accordingly. This makes the overall space occupied by the display module 150 smaller, allowing more display modules 150 to be arranged within the same display panel 100, thereby effectively improving the display effect of the display panel 100. By offsetting the pixel circuits 151 and the pixel anode 160 of the display module 150 within the driving area 123, the pixel circuit 151 relative to the pixel anode 160... By leaving space in the same layer, the second gate driving circuit 142 can be placed directly below the pixel anode 160 and on the same layer as the pixel circuit 151. This effectively utilizes the wiring space within the display panel 100. Furthermore, without increasing the thickness of the display panel 100, the second gate driving circuit 142 can be placed within the display area 120. This means that only the first gate driving circuit 141 needs to be placed in the non-display area 130 of the display panel 100, eliminating the need to place both gate driving circuits 140 in the non-display area 130 simultaneously. This effectively reduces the area of ​​the non-display area 130 and helps to reduce the width of the black border of the display panel 100.

[0037] Furthermore, in order to reduce the impact of the second gate driving circuit 142 on the pixel circuit 151 after it is positioned below the pixel anode 160, and to ensure the stability of the connection between the pixel circuit 151 and the pixel anode 160, so that the pixel anode 160 located in the driving region 123 can emit light normally under the control of the pixel circuit 151, this application also improves the structure of the pixel anode 160 located in the driving region 123, as follows:

[0038] refer to Figure 3 The pixel anode 160 corresponding to the position of the driving region 123 includes an anode body 161 and an anode trace 162. One side of the anode trace 162 is connected to the anode body 161, and the other side is connected to the misaligned pixel circuit 151 through a via 157.

[0039] In this embodiment, the pixel anode 160 within the driving region 123 includes an anode body 161 and an anode trace 162. The anode trace 162 is connected to the anode body 161, making it an extension of the anode body 161. The anode trace 162 extends towards the first gate driving circuit 141, connecting with the misaligned pixel circuit 151. This allows the relatively misaligned pixel circuit 151 to connect with the anode body 161, which is at a certain distance, through the anode trace 162. Even in the case of misalignment, electrical conduction can be ensured between the pixel circuit 151 and the anode body 161, allowing the pixel circuit 151 to control the anode body 161 to emit light for display. Furthermore, since the anode trace 162 extends towards the first gate driving circuit 141, i.e., towards the non-display area, the impact of the anode trace 162 on the second partition 122, which is mainly used for display, can be minimized, ensuring the overall display effect of the display panel 100.

[0040] Of course, in order to accommodate the misalignment of the pixel circuit 151 within the driving area 123, the pixel anode 160 in the area between the first gate driving circuit 141 and the second gate driving circuit 142 can also adopt the above design. This allows the corresponding pixel circuit 151 to also be misaligned when it aligns with the misalignment of the pixel circuit 151 within the driving area 123, and to connect with the pixel anode 160 in its original position. In this way, the normal display of this area can be guaranteed without reducing the display module 150, thereby ensuring the display effect of the display panel 100.

[0041] Further reference Figure 4 The pixel circuit 151 includes a thin-film transistor 152 disposed on a substrate layer 153. The thin-film transistor 152 includes a drain 154, a passivation layer 155, and a planarization layer 156 sequentially stacked on the substrate layer 153. A via 157 is formed through the passivation layer 155 and the planarization layer 156, and the anode trace 162 is connected to the drain 154 through the via 157. The second gate driving circuit 142 also includes a thin-film transistor 152, and the multilayer structure of the thin-film transistor 152 in the second gate driving circuit 142 can be disposed on the same layer as the multilayer structure of the thin-film transistor 152 in the pixel circuit 151.

[0042] In this embodiment, the anode trace 162 extending from the anode body 161 is directly connected to the drain 154 of the thin-film transistor 152 in the pixel circuit 151 through the via 157, which can reduce resistance and thus improve the response speed and stability of the circuit.

[0043] Continue to refer to Figure 2 The projected area of ​​at least a portion of the pixel circuit 151 in the first partition 121 on the substrate 110 is smaller than the projected area of ​​at least a portion of the pixel circuit 151 in the second partition 122 on the substrate 110; and / or, the number of transistors in at least a portion of the pixel circuit 151 in the first partition 121 is less than the number of transistors in at least a portion of the pixel circuit 151 in the second partition 121.

[0044] In this embodiment, the projected area of ​​the pixel circuit 151 in the first partition 121 on the substrate 110 is smaller than that of the pixel circuit 151 in the second partition 122 on the substrate 110. This allows the space occupied by the pixel circuit 151 in the first partition 121 to be further reduced, thereby enabling the second gate driving circuit 142, which is on the same layer as the pixel circuit 151, to have a larger layout space. Thus, without affecting the normal layout of the pixel circuit 151 in the first partition 121 and the second partition 122, the second gate driving circuit 142 can be placed in the display area 120, thereby effectively utilizing the wiring space in the display panel 100. Furthermore, the second gate driving circuit 142 can be placed in the display panel 100 without increasing the thickness of the display panel 100. This means that only the first gate driving circuit 141 needs to be placed in the non-display area 130 of the display panel 100, instead of placing both gate driving circuits 140 in the non-display area 130 simultaneously, thereby effectively reducing the black border width of the display panel 100.

[0045] Furthermore, taking the display panel 100 as an example of a smartwatch display panel, since the first partition 121 is mainly used to display relatively static content (such as time scale), while the second partition 122 is mainly used to display dynamic content (such as pointers or real-time updated information), the power consumption of the first partition 121 is actually less than that of the second partition 122. When the number of transistors in the pixel circuit 151 of the first partition 121 is less than the number of transistors in the pixel circuit 151 of the second partition 122, the power consumption of the first partition 121 is further reduced.

[0046] Furthermore, compared to the dynamic display of the second partition 122, the static display of the first partition 121 has lower requirements for display quality. Therefore, the first partition 121 can simplify the pixel circuit function and use fewer transistors and a smaller projected area to meet the basic display requirements. On the other hand, the pixel circuit of the second partition 122 can bring higher display quality by using more transistors and a larger projected area. For example, compared to the first pixel circuit 151a, the second pixel circuit 151b can add transistors with functions such as reset and compensation, and its transistors can use larger feature sizes.

[0047] Of course, it is also possible to make the projected area of ​​the pixel circuit 151 of the first partition 121 on the substrate 110 smaller than the projected area of ​​the pixel circuit 155 of the second partition 122 on the substrate 110, while setting the number of transistors in the pixel circuit 155 of the first partition 121 to be less than the number of transistors in the pixel circuit 155 of the second partition 122; in this way, the power consumption of the display panel 100 can be reduced while reducing the black border width of the display panel 100, thus ensuring both low power consumption and good display effect.

[0048] In some embodiments, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the partitioning in the second embodiment of the display panel of this application. The driving area 123 is located on both sides of the second partition 122, and the edge of the driving area 123 is adjacent to the edge of the second partition 122.

[0049] In this embodiment, the driving region 123 is set on opposite sides of the second partition 122, and its edge is adjacent to the edge of the second partition 122. This can effectively utilize the limited space in the display region 120. It avoids the second gate driving circuit 142 in the driving region 123 from occupying the space of the non-display region 130, thereby helping to reduce the overall area of ​​the non-display region 130 and thus reducing the black border of the display panel 100.

[0050] Furthermore, the driving region 123 being adjacent to the second partition 122 can shorten the distance between the second gate driving circuit 142 and the corresponding display module 150, thereby reducing signal loss and delay during signal transmission and improving driving efficiency.

[0051] The following section will explain several display modes in detail by combining the relationship between the two gate drive circuits 140 and the two partitions.

[0052] refer to Figure 2The scan lines 170 of the first partition 121 and the second partition 122 are disconnected from each other. The scan lines 170 of the first partition 121 are electrically connected to multiple display modules 150 in the same row of the first partition 121, and the scan lines 170 of the second partition 122 are electrically connected to multiple display modules 150 in the same row of the second partition 122. The refresh rate of the first gate driving circuit 141 is lower than the refresh rate of the second gate driving circuit 142. In other words, the first scan line 171 and the second scan line 172 are isolated from each other, and they drive the first partition 121 and the second partition 122 for display respectively, without crossing over the driven partitions. In some embodiments, the first scan line 171 may extend only in the first partition 121; in other embodiments, the first scan line 171 may also extend from the first partition 121 to the second partition 122, that is, the first scan line 171 spans the entire display area 120, but is not electrically connected to the display modules 150 of the second partition 122.

[0053] In this embodiment, the display panel 100 is taken as the display panel on a smartwatch. Since the display content of the first partition 121 is usually static (such as time scale), its refresh rate can be set to a low level, thereby significantly reducing the power consumption of this area. The second partition 122 is responsible for displaying dynamic content (such as pointers or real-time information), which requires a higher refresh rate to ensure a smooth display effect.

[0054] Therefore, in this embodiment, by disconnecting the scan lines of the first partition 121 and the second partition 122 from each other, the scan lines of the first partition 121 control the display module 150 within the first partition 121, and the scan lines 170 of the second partition 122 control the display module 150 within the second partition 122, so that each partition can independently transmit gate drive signals. In this way, the first partition 121 and the second partition 122 can set their refresh rates according to their respective needs, avoiding signal crosstalk between the two partitions, thereby improving the stability and clarity of the display.

[0055] refer to Figure 6 , Figure 6 This is a schematic diagram of the partitioning in the third embodiment of the display panel of this application. Figure 6 In the embodiment shown, the two ends of the scan line 170 of the second partition 122 are connected to the same row of scan lines 170 of the first partition 121 through the switching transistor 180.

[0056] The difference between this embodiment and the previous embodiment is that in this embodiment, the scan line 170 of the second partition 122 and the scan line 170 of the first partition 121 in the same row are connected by a switching transistor 180. In other words, a switching transistor 180 can be set between the first scan line 171 and the second scan line 172 in the same row. The switching transistor 180 can control the first scan line 171 and the second scan line 172 to be disconnected or electrically connected. The switching transistor 180 can be a thin-film transistor (TFT), and the gates of all TFTs can be connected together and controlled by the same signal, thereby simplifying the control method of the switching transistor 180. For example, if all switching transistors 180 are NTFTs, a high level input to their gate controls the switching transistor 180 to be turned on, and a low level input to their gate controls the switching transistor 180 to be turned off. Of course, the switching transistor 180 can also be a PTFT. By controlling the state of the switching transistor 180, the two partitions can be in different display states.

[0057] When it is detected that both partitions can be displayed at a low refresh rate, the control switch 180 is turned on. At this time, the pixel circuits 151 in the first partition 121 and the second partition 122 are driven by the first gate driving circuit 141 of the non-display area 130, and the second gate driving circuit 142 of the display area 120 can be inactive. That is, in this mode, only the first gate driving circuit 141 drives all scan lines 170, while the second gate driving circuit 142 does not need to provide driving signals to the scan lines 170, thereby reducing power consumption.

[0058] When the first partition 121 is at a low refresh rate and the second partition 122 is at a high refresh rate, the switching transistor 180 can be turned off. At this time, the pixel circuits 151 in the two partitions are driven by their respective gate driving circuits. In this mode, both gate driving circuits 140 need to be operational.

[0059] When the driving area 123 is located on the left and right sides of the second partition 122, and partial display is required (e.g., the top and bottom sides of the first partition 121 are not displayed, while the second partition 122 and the left and right sides of the first partition 121 are displayed), the switching transistor 180 is turned on, and the second gate driving circuit 142 of the display area 120 is used for driving. The first gate driving circuit 141 of the non-display area 130 is directly turned off, which can also reduce power consumption. In this mode, the second gate driving circuit 142 needs to work, while the first gate driving circuit 141 does not need to work.

[0060] Specifically, in full-screen low refresh mode: the switch 180 is in the on state, the first gate driving circuit 141 drives the first partition 121 and the second partition 122 to display at low refresh, and the second gate driving circuit 142 is in the off state.

[0061] In partition refresh mode: the switch transistor 180 is in the off state, the first gate drive circuit 141 drives the first partition 121 to display at a low frequency, and the second gate drive circuit 142 drives the second partition 122 to display at a high refresh rate.

[0062] In the first partial display mode: the switching transistor 180 is in the on state, the second gate driving circuit 142 drives the second partition 122 and the left and right sides of the first partition 121 to display at a high refresh rate, the upper and lower sides of the first partition 121 are turned off, and the first gate driving circuit 141 is in the off state.

[0063] In the second partial display mode: the switching transistor 180 is in the off state; the first gate driving circuit 141 drives the first partition 121 to display at a low refresh rate, and the second gate driving circuit 142 is turned off to turn off the display of the second partition 122; or, the first gate driving circuit 141 is turned off to turn off the display of the first partition 121, and the second gate driving circuit 142 drives the second partition 122 to display at a high refresh rate.

[0064] In this embodiment, in the full-screen low refresh mode, the switch 180 is turned on, and the first gate driving circuit 141 simultaneously drives the first partition 121 and the second partition 122, so that both are displayed at a low refresh rate; at this time, the second gate driving circuit 142 is turned off, avoiding unnecessary power consumption, thereby reducing the overall power consumption of the display panel.

[0065] In partitioned refresh mode, the switch 180 is turned off. The first gate drive circuit 141 drives only the first partition 121 to display at a low refresh rate, while the second gate drive circuit 142 drives the second partition 122 to display at a high refresh rate. This allows for flexible adjustment of the refresh rate based on actual usage, further optimizing power consumption and ensuring smooth display of dynamic content areas while maintaining low-power display of static content areas.

[0066] In the first partial display mode, the switching transistor 180 is turned on, and the second gate driving circuit 142 drives the second partition 122 and the left and right sides of the first partition 121 to display at a high refresh rate, while the top and bottom sides of the first partition 121 are turned off. This enables the center and left and right sides of the screen to display at a high refresh rate, allowing for the display of local dynamic content at a high refresh rate, while turning off unnecessary areas to save power.

[0067] In the second partial display mode, there are two working states:

[0068] The first partition 121 displays at a low refresh rate, while the second partition 122 is completely off; alternatively, the first partition 121 is completely off, while the second partition 122 displays at a high refresh rate. This allows for flexible selection of the display area according to user needs. By controlling the on or off state of the switching transistor 180, dynamic switching between the first gate drive circuit 141 and the second gate drive circuit 142 can be achieved, resulting in different display effects.

[0069] This embodiment can flexibly adapt to various application scenarios through a variety of different display modes, including low-power standby, dynamic content display, and local high refresh rate display, to meet the diverse needs of users.

[0070] It should be noted that the above-mentioned display modes can be detected and identified by the sensors inside the display panel 100, and the display panel 100 can be controlled to be in different display modes according to the built-in system program of the display panel 100. In turn, the state of the switch transistor 180 is controlled in the corresponding display mode. The method of controlling the display panel 100 to be in different display modes through the system program, and switching the state of the switch transistor 180 through the driver chip in different modes, is a conventional method in the art, and will not be described in detail in this application.

[0071] Figure 7 This is a schematic diagram of an embodiment of the display device of this application, as shown below. Figure 7 As shown in the figure, this application also discloses a display device 10, including a housing 200. The display device 10 also includes the aforementioned display panel 100, which is disposed within the housing 200. The housing 200 is used to protect the display panel 100 from damage caused by external forces during movement, and can also prevent external moisture from entering the display panel 100 to a certain extent, thereby effectively improving the service life of the display device 10.

[0072] It should be noted that the display device 10 in this application is mainly for display devices with limited screen size and high requirements for internal space structure, such as smartwatches in wearable devices.

[0073] In display devices, display panels that implement different refresh zones require different gate drive circuits to provide gate signals of different frequencies. Since the drive circuits for different zones are usually designed in the non-display area of ​​the display panel bezel, it causes a large black border on the screen, resulting in a poor viewing experience.

[0074] To address the aforementioned issues, this application addresses this problem by providing two different gate drive circuits 140 within the display panel 100. These circuits control the display modules 150 within the first partition 121 and the second partition 122 of the display area 120, respectively. This allows the display modules 150 in the first and second partitions 121 and 122 to display different refresh rates based on the drive signals from the different gate drive circuits 140. This achieves different refresh rates in different display partitions of the display panel 100, effectively reducing power consumption and extending the battery life of the display panel 100. Furthermore, this application only places the first gate drive circuit 141 within the non-display area 1 of the display panel 100. 30. By additionally setting a driving region 123 within the first partition 121 of the display area 120 and setting the second gate driving circuit 142 within the driving region 123, the influence of the second gate driving circuit 142 on the display of the first partition 121 and the second partition 122 can be reduced. On the other hand, the first gate driving circuit 141 and the second gate driving circuit 142 will not be concentrated in the non-display area 130. This can effectively reduce the area of ​​the non-display area 130, thereby reducing the black screen of the display panel 100, which is conducive to improving the screen ratio and display effect of the display panel 100, and thus improving the quality of the display device 10.

[0075] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0076] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A display panel, the display panel comprising a substrate, the substrate being divided into a display area and non-display areas disposed on at least two sides of the display area, characterized in that, The display area is divided into a first partition and a second partition, with the first partition located outside the second partition; The first partition also includes a driving area, and the display panel further includes a gate driving circuit, which includes a first gate driving circuit and a second gate driving circuit. The first gate driving circuit is disposed in the non-display area, and the second gate driving circuit is disposed in the driving area. The first gate driving circuit is electrically connected to at least the display module in the first partition, and the second gate driving circuit is electrically connected to at least the display module in the second partition. The first gate driving circuit and the second gate driving circuit have different preset refresh rates; Both the first and second partitions are equipped with multiple display modules arranged in an array; each display module includes a pixel circuit and a pixel anode, the pixel circuit being electrically connected to the pixel anode and used to provide an anode signal to the pixel anode; the second gate driving circuit is located below the pixel anode; In the display module corresponding to the position of the driving area, at least a portion of the pixel circuits are misaligned with the pixel anode, and at least a portion of the second gate driving circuits are disposed directly below the pixel anode and are disposed on the same layer as the pixel circuits; The driving regions are located on opposite sides of the second partition, and the edges of the driving regions are adjacent to the edges of the second partition. The pixel anode corresponding to the position of the driving region includes an anode body and an anode trace. One side of the anode trace is connected to the anode body, and the other side extends toward the first gate driving circuit and is electrically connected to the pixel circuit that is misaligned. In the region between the first gate driving circuit and the second gate driving circuit, the corresponding pixel circuit is misaligned in coordination with the pixel circuit in the driving region, and is electrically connected to the anode body of the corresponding pixel anode through the anode trace of the corresponding pixel anode.

2. The display panel as described in claim 1, characterized in that, The projected area of ​​at least a portion of the pixel circuits in the first partition on the substrate is smaller than the projected area of ​​at least a portion of the pixel circuits in the second partition on the substrate. And / or, the number of transistors in at least a portion of the pixel circuitry of the first partition is less than the number of transistors in at least a portion of the pixel circuitry of the second partition.

3. The display panel as described in claim 2, characterized in that, The scan lines of the first partition and the scan lines of the second partition are disconnected from each other. The scan lines of the first partition are electrically connected to a plurality of display modules in the same row of the first partition, and the scan lines of the second partition are electrically connected to a plurality of display modules in the same row of the second partition. The refresh rate of the first gate driving circuit is lower than that of the second gate driving circuit.

4. The display panel according to claim 1, characterized in that, The two ends of the scan line of the second partition are connected to the same row of the scan line of the first partition through a switching transistor.

5. The display panel according to claim 4, characterized in that, In full-screen low refresh mode: the switching transistor is in the on state, the first gate driving circuit drives the first partition and the second partition to be displayed in low refresh mode, and the second gate driving circuit is in the off state; In partition refresh mode: the switching transistor is in the off state, the first gate driving circuit drives the first partition to display at a low frequency, and the second gate driving circuit drives the second partition to display at a high refresh rate. In the first partial display mode: the switching transistor is in the on state, the second gate driving circuit drives the second partition and the left and right sides of the first partition to display at a high refresh rate, the upper and lower sides of the first partition are turned off, and the first gate driving circuit is in the off state. In the second partial display mode: the switching transistor is in the off state; the first gate driving circuit drives the first partition to display at a low refresh rate, and the second gate driving circuit is turned off to turn off the display of the second partition; or, the first gate driving circuit is turned off to turn off the display of the first partition, and the second gate driving circuit drives the second partition to display at a high refresh rate.

6. A display device, comprising a housing, characterized in that, The display device further includes a display panel as described in any one of claims 1 to 5, the display panel being disposed within the housing.

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