Static memory cells and memory architectures

Abstract

The application provides a static memory cell and a memory architecture which can reduce write power consumption when storing data with high storage sparsity, and can balance storage stability and storage density. The static memory cell comprises: an inverter circuit with an output end electrically connected to a first storage node, an input end electrically connected to a second storage node, and a power supply end electrically connected to a first power supply; an asymmetric pull-up transistor with a gate electrically connected to the first storage node, a drain electrically connected to the second storage node, and a source electrically connected to a second power supply; a read operation transistor with a gate electrically connected to the first storage node, a drain electrically connected to a read bit line, and a source electrically connected to a read word line; and a write transfer transistor with a drain electrically connected to the second storage node, a gate electrically connected to a write word line, and a source electrically connected to a write bit line.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, and in particular to a high-density two-port static memory cell for a system-on-chip and a memory architecture comprising the same. BACKGROUND

[0002] Thanks to the progress of computer technology, cloud services, meta-computing, Internet of Things, 5G interconnection and other technologies are booming, bringing unprecedented convenience and novelty to people's production and life. At present, with the all-round development of computer technology-driven productivity, emerging technologies represented by virtual reality (VR) and augmented reality (AR) are expected to promote a new round of computer technology innovation.

[0003] Among the many hardware devices of VR / AR, the cost of the graphics processing unit (GPU) responsible for image processing, rendering and computing, and the central processing unit (CPU) is about 16%. At the same time, in the microprocessor (Microprocessor), the area overhead of static random access memory (SRAM) accounts for more than 50% of the total chip cost, and consumes most of the static power consumption of the processor. In short, the SRAM used as a first-level cache and a built-in second-level cache inside the CPU, whose overhead is a non-negligible part of the VR / AR terminal hardware.

[0004] In addition, with the evolution of Moore's Law, process nodes are constantly shrinking, and the cost of memory devices is increasing. As a relatively mature design technology, static random access memory has become a storage medium that is fully compatible with advanced CMOS technology and can be mass-produced. At the same time, compared with various new types of memory, SRAM has faster operating speed and durability. However, at present, SRAM still faces problems such as low storage density and relatively high design complexity.

[0005] In the past, as a commonly used SRAM cell structure, the following two specific schemes are proposed.

[0006] Figure 8 is a schematic diagram showing the overall structure of a single-port 6T-SRAM cell circuit of the prior art. As shown in the figure, the 6T-SRAM cell circuit comprises a memory cell and a read / write circuit. Figure 8As shown in FIG, a single-port 6T-SRAM cell includes six MOS transistors. Among them, the first pull-up transistor P1 and the second pull-up transistor P2 composed of PMOS transistors and the first pull-down transistor N1 and the second pull-down transistor N2 composed of NMOS transistors form a pair of end-to-end inverters inside the 6T-SRAM cell. The first transfer transistor N5 and the second transfer transistor N6 composed of NMOS transistors serve as transfer transistors to support read and write operations.

[0007] Figure 9 Schematic diagram showing the overall structure of a two-port 8T-SRAM unit circuit in the prior art. Figure 9 As shown, the two-port 8T-SRAM cell includes eight MOS transistors, which, in addition to the six MOS transistors in the aforementioned 6T-SRAM cell, also include two additional NMOS transistors dedicated to read operations, namely, a read select transistor N7 and a read pull-down transistor N8.

[0008] Prior art literature

[0009] Non-patent literature

[0010] "VR / AR is the middle game, Metaverse is the end game", Industry in-depth analysis - Securities Research Report, Essence Securities, September 2021 Summary of the Invention

[0011] Technical problem to be solved by the invention

[0012] In such Figure 8 In the 6T-SRAM cell shown, during a read operation, the first and second transfer transistors N5 and N6 are enabled by setting the word line WL to a high level. The data stored in the first and second storage nodes Q and QB are then read through the precharged bit line BL and inverted bit line BLB. However, because the read and write operation paths of this 6T-SRAM cell overlap, and during a read operation, the bit line BL and the first storage node Q are directly connected via the source and drain of the first transfer transistor N5, if, for example, the first storage node Q stores a zero, the precharge voltage on the bit line BL may interfere with the storage state of the first storage node Q for some reason during the initial read, leading to errors during subsequent reads of the same storage cell. This means that the 6T-SRAM structure faces the problem of read interference-induced read damage, which can affect the stability of the 6T-SRAM.

[0013] In contrast, in Figure 9In the 8T-SRAM cell shown, the double-side operation mode is still adopted during the write operation, but during the read operation, the read selection transistor N7 and the read pull-down transistor N8 are used as the circuit of the read part, so that the 8T-SRAM cell has the characteristic of read-write separation. Thus, the read interference problem faced by the 6T-SRAM is solved, and the stability of the SRAM structure is improved. However, since two NMOS transistors need to be added, the storage density of the memory will deteriorate, and the problem of increased area overhead will occur.

[0014] In addition, whether it is the 6T-SRAM cell shown in Figure 8 or the 8T-SRAM cell shown in Figure 9 , the inverters composed of the first pull-up transistor P1 and the first pull-down transistor N1 and the inverters composed of the second pull-up transistor P2 and the second pull-down transistor N2 in the cell are both physically symmetric structures, so when the SRAM cell is powered on, the first storage node Q (the second storage node QB) will not have any tendency to flip. When using such existing SRAM cells to form an SRAM array, if it is desired to store data with a high sparsity (i.e., a high proportion of 0s) in the SRAM array, a certain amount of time and power consumption will be consumed to write the data with high sparsity after power-on, thus increasing the write time and write power consumption. Especially when storing various neural network models, since common neural network models all have the characteristic of high weight sparsity, as the storage size increases, the problem of increased write power consumption becomes particularly prominent.

[0015] The present application is completed to solve the above problems, and aims to provide a static memory cell and a memory architecture that can reduce the write power consumption when storing data with high sparsity, improve the storage stability and anti-read interference capability of the memory, and also take into account the improvement of storage density and the reduction of area overhead.

[0016] Technical solutions for solving technical problems

[0017] To solve the above technical problems, the static memory cell of the first aspect of the present application comprises: an inverter circuit, an output end of the inverter circuit being electrically connected to a first storage node, an input end of the inverter circuit being electrically connected to a second storage node, and a power supply end of the inverter circuit being electrically connected to a first power supply; an asymmetric pull-up transistor, a gate of the asymmetric pull-up transistor being electrically connected to the first storage node, a drain of the asymmetric pull-up transistor being electrically connected to the second storage node, and a source of the asymmetric pull-up transistor being electrically connected to a second power supply; a read operation transistor, a gate of the read operation transistor being electrically connected to the first storage node, a drain of the read operation transistor being electrically connected to a read bit line, and a source of the read operation transistor being electrically connected to a read word line; and a write transfer transistor, a drain of the write transfer transistor being electrically connected to the second storage node, a gate of the write transfer transistor being electrically connected to a write word line, and a source of the write transfer transistor being electrically connected to a write bit line.

[0018] Optionally, when the static memory cell is powered on, the second storage node is pulled up to a high level by turning on the second power supply, so that 0 is written to the first storage node.

[0019] Optionally, when the static memory cell is powered on, the first power supply is turned on after the second power supply is turned on and a specified time interval elapses.

[0020] Optionally, the inverter circuit comprises a first pull-up transistor and a first pull-down transistor, a drain of the first pull-up transistor and a drain of the first pull-down transistor being electrically connected to the first storage node, a gate of the first pull-up transistor and a gate of the first pull-down transistor being electrically connected to the second storage node, a source of the first pull-up transistor being electrically connected to the first power supply as the power supply end of the inverter circuit, and a source of the first pull-down transistor being grounded.

[0021] Optionally, a substrate of the asymmetric pull-up transistor and a substrate of the first pull-up transistor are both electrically connected to the first power supply, and a voltage of the first power supply is higher than a voltage of the second power supply.

[0022] Optionally, in a read operation, the read bit line is pre-charged to a first voltage, the read word line is clamped to a second voltage lower than the first voltage, and the data stored in the first storage node is read by detecting a voltage difference of the read bit line.

[0023] Optionally, in a read operation, the write word line and the write bit line are kept at a low level.

[0024] Optionally, in a write operation, the write word line is set to a high level, and data is written to the second storage node by inputting a third voltage or a fourth voltage lower than the third voltage to the write bit line, so that data is written to the first storage node.

[0025] Optionally, the read word line and the read bit line are kept at low level during the write operation.

[0026] Optionally, the write word line, the write bit line, the read word line and the read bit line are all kept at low level during the holding state.

[0027] In addition, in order to solve the above technical problems, the memory architecture according to a second aspect of the present application comprises: a memory array composed of a plurality of static memory cells according to the first aspect of the present application, the source of the read operation transistor of the static memory cells in the same row is electrically connected to the same read word line, the gate of the write transfer transistor of the static memory cells in the same row is electrically connected to the same write word line, the drain of the read operation transistor of the static memory cells in the same column is electrically connected to the same read bit line, and the source of the write transfer transistor of the static memory cells in the same column is electrically connected to the same write bit line; a row driving circuit electrically connected to the read word line and the write word line of each row of the memory array, for selecting the row to be read according to the row address code signal through the read word line, or selecting the row to be written according to the row address code signal through the write word line; a column pre-charge driving circuit electrically connected to the read bit line and the write bit line of each column of the memory array, for pre-charging the read bit line of the column to be read according to the column address code signal, or pre-charging the write bit line of all columns, and writing data to the static memory cells of the column to be written through the write bit line according to the column address code signal; a read circuit electrically connected to the read bit line of each column of the memory array, for gating the column to be read, and generating and outputting the read data based on the voltage of the read bit line of the column to be read; and a self-power-on control circuit for providing the first power supply and the second power supply to each static memory cell respectively.

[0028] Optionally, the self-power-on control circuit controls the turn-on sequence of the first power supply and the second power supply based on the obtained clock signal, so that the first power supply is turned on after the second power supply is turned on and a specified time interval elapses.

[0029] Optionally, the row driving circuit comprises a row decoder for converting the obtained row address code signal into a row selection signal.

[0030] Optionally, the row driving circuit further comprises a read word line driver, during a read operation, the read word line driver clamps the read word line of the row to be read to a second voltage according to the row selection signal, the second voltage is lower than the first voltage pre-charged on the read bit line of the column to be read.

[0031] Optionally, the row driving circuit further comprises a write word line driver, during a write operation, the write word line driver sets the write word line of the row to be written to high according to the row selection signal.

[0032] Optionally, the column pre-charging driving circuit comprises a column decoder, the column decoder converts the column address code signal obtained to a column selection signal.

[0033] Optionally, the column pre-charging driving circuit further comprises a read bit line pre-charger, during a read operation, the read bit line pre-charger pre-charges the read bit line of the column to be read to a first voltage according to the column selection signal, the first voltage is higher than the second voltage clamped on the read word line of the row to be read.

[0034] Optionally, the read bit line pre-charger pre-charges the read bit line of the column to be read to the first voltage in a bit width unit.

[0035] Optionally, the column pre-charging driving circuit further comprises a write bit line pre-charging driver, before a write operation, the write bit line pre-charging driver pre-charges the write bit line of all columns to high, during a write operation, the write bit line pre-charging driver inputs a third voltage or a fourth voltage lower than the third voltage to the write bit line of the column to be written according to the column selection signal based on a data signal from outside, thereby writing data to the static memory cell to be written.

[0036] Optionally, the write bit line pre-charging driver writes data to the static memory cell to be written in a bit width unit.

[0037] Optionally, the read circuit comprises a sense amplifier, during a read operation, the sense amplifier amplifies the voltage variable of the read bit line of the column to be read as read data.

[0038] Optionally, the read circuit further comprises a multiplexer, the multiplexer selects the column to be read.

[0039] Optionally, the multiplexer selects in a bit width unit.

[0040] Inventive effects

[0041] According to the static memory cell and the memory architecture related to the present application, the write power consumption can be reduced when storing data with high sparsity, the storage stability and the anti-reading interference capability of the memory can be improved, and the storage density can be increased and the area overhead can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a schematic diagram showing the structure of the static memory cell related to the embodiment 1 of the present application.

[0043] Figure 2 is a circuit diagram showing a specific embodiment of the static memory cell.

[0044] Figure 3 is a timing diagram showing an action example of the static memory cell.

[0045] Figure 4 is a column chart showing the comparison results of the cell area of the static memory cell related to the present application and the single-port 6T-SRAM cell and the two-port 8T-SRAM cell of the prior art.

[0046] Figure 5(A) is a 1K-point Monte Carlo simulation diagram of the Q-point power-on automatic setting of 0 of the static memory cell related to the embodiment 1 of the present application.

[0047] Figure 5(B) is a 1K-point Monte Carlo simulation diagram of the QB-point power-on automatic setting of 1 of the static memory cell related to the embodiment 1 of the present application.

[0048] Figure 5(C) is a 1K-point Monte Carlo simulation diagram of the Q-point voltage of the static memory cell related to the embodiment 1 of the present application after 1Gs holding time after storing 1 in the Q-point.

[0049] Figure 5(D) is a 1K-point Monte Carlo simulation diagram of the QB-point voltage of the static memory cell related to the embodiment 1 of the present application after Gs holding time after storing 0 in the QB-point.

[0050] Figure 6 is a block diagram showing the structure of the memory architecture related to the embodiment 2 of the present application.

[0051] Figure 7 is a schematic diagram showing a specific embodiment of the memory architecture.

[0052] Figure 8 is a schematic diagram showing the overall structure of the single-port 6T-SRAM cell circuit of the prior art.

[0053] Figure 9 is a schematic diagram showing the overall structure of the two-port 8T-SRAM cell circuit of the prior art. DETAILED DESCRIPTION

[0054] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It should be understood that the specific implementation manners described herein are only used to illustrate and explain the embodiments of the present application and should not be used to limit the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0055] It should be noted that the technical solutions among the various embodiments of the present application can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can implement it. When the combination of technical solutions appears to be contradictory or unimplementable, it should be considered that the combination of technical solutions does not exist and is not within the scope of protection claimed by the present application.

[0056] Embodiment 1

[0057] The static memory cell involved in the present embodiment will be described below with reference to Figure 1 FIG. 5.

[0058] Figure 1 is a schematic diagram showing the structure of the static memory cell involved in the embodiment of the present application. The SRAM (static memory) cell of the present application is a two-port memory cell, which can be used for high-density two-port cache of a system-on-chip, and is especially suitable for storage of data with high sparsity characteristics of weights, such as various neural networks. The static memory cell includes an inverter circuit NOT, an asymmetric pull-up transistor P2, a read operation transistor N3 and a write transmission transistor N4.

[0059] As shown in Figure 1 , the output end of the inverter circuit NOT is electrically connected to the first storage node Q, the input end is electrically connected to the second storage node QB, and the power supply end is electrically connected to the first power supply VDDL. The asymmetric pull-up transistor P2 is a PMOS transistor. The gate of the asymmetric pull-up transistor P2 is electrically connected to the first storage node Q, the drain is electrically connected to the second storage node QB, and the source is electrically connected to the second power supply VDDR. Thus, the inverter circuit NOT and the asymmetric pull-up transistor P2 constitute the latch part of the SRAM cell, and the first storage node Q and the second storage node QB store a pair of inverted data.

[0060] The read operation transistor N3 is an NMOS transistor, the gate of which is electrically connected to the first storage node Q, the drain of which is electrically connected to the read bit line RBL, and the source of which is electrically connected to the read word line RWL. In the present application, the read operation is accomplished by controlling the gate of the read operation transistor N3 by the first storage node Q, in a manner of differential current, and this will be described in detail later.

[0061] The write transfer transistor N4 is an NMOS transistor, the drain of which is electrically connected to the second storage node QB, the gate of which is electrically connected to the write word line WWL, and the source of which is electrically connected to the write bit line WBL. In the present application, the write operation is accomplished by writing data to the second storage node QB by the write transfer transistor N4, in a manner of single-side operation, and this will be described in detail later.

[0062] Figure 2 is a circuit diagram of one specific embodiment of the static memory cell of Figure 1 In Figure 2 , an embodiment of an inverter circuit NOT as shown in Figure 1 is shown to be constructed by a pair of PMOS transistor and NMOS transistor. However, the structure of the inverter circuit is not limited to this. As long as the structure is capable of realizing the function of the inverter, it can be used to construct the inverter circuit of the present application. In addition, in Figure 2 , the same reference numerals are used to denote the same parts as Figure 1 .

[0063] As shown in Figure 2 , the static memory cell includes three NMOS transistors and two PMOS transistors, and is constructed as a two-port 4T 1T-SRAM cell circuit.

[0064] In which, the first pull-up transistor P1 is a PMOS transistor, and the first pull-down transistor N1 is an NMOS transistor. The drain of the first pull-up transistor P1 and the drain of the first pull-down transistor N1 are electrically connected to the first storage node Q, the gate of the first pull-up transistor P1 and the gate of the first pull-down transistor N1 are electrically connected to the second storage node QB, the source of the first pull-up transistor P1 is electrically connected to the first power supply VDDL, and the source of the first pull-down transistor N1 is electrically connected to the ground VSS. Thus, the first pull-up transistor P1 and the first pull-down transistor N1 constitute an inverter NOT as shown in Figure 1 , and the source of the first pull-up transistor P1 becomes the power supply terminal of the inverter NOT.

[0065] According to the above structure, by controlling the power-up of the first power supply VDDL and the second power supply VDDR, power-up self-write of the first storage node Q and the second storage node QB can be realized. Also, by controlling the level (hereinafter, also referred to as voltage, and "high level" is written as "high voltage", and "low level" is written as "low voltage") on the read word line RWL, the read bit line RBL, the write word line WWL, and the write bit line WBL, read and write operations of the data stored in the first storage node Q and the second storage node QB can be realized. Regarding the above two points, the following will be described with reference to the drawings.

[0066] Figure 3 is a timing chart showing an example of the operation of the static memory cell.

[0067] As shown in Figure 3 , when the static memory cell is powered up, first, by turning on the second power supply VDDR, the potential of the second storage node QB is pulled up to the high voltage, thereby self-writing 0 to the first storage node Q. Next, after a predetermined time interval, the first power supply VDDL is turned on, thereby completing the self-power-up of the first storage node Q of the static memory cell to 0.

[0068] Specifically, as shown in Figure 2 , Figure 3 , in the present embodiment, when the second power supply VDDR is turned on, the source potential of the asymmetric pull-up transistor P2 is pulled up to the second power supply VDDR. At this time, since the static memory cell has a physically asymmetric structure, no pull-down transistor is disposed below the asymmetric pull-up transistor P2, and therefore the drain potential of the second storage node QB is more likely to be inverted to the potential of the second power supply VDDR. Accordingly, the potential of the first storage node Q is more likely to be inverted to the ground potential (VSS). Thus, the first storage node Q of the static memory cell can be once reset to 0 in a short time with low power consumption.

[0069] In addition, since the first power supply VDDL is turned on after the second power supply VDDR is turned on and a predetermined time interval elapses, regardless of the size relationship of the conduction threshold values of the first pull-up transistor P1 and the asymmetric pull-up transistor P2, it can be ensured that the first storage node Q is self-written to 0 after power-up, and the first storage node Q is not set to 1. However, the present application is not limited thereto, for example, the first power supply VDDL and the second power supply VDDR can be turned on at the same time. The reason for this is that although the sources of the first pull-up transistor P1 and the asymmetric pull-up transistor P2 are pulled up to the high voltage at the same time, the physically asymmetric structure of the present application can still ensure that the first storage node Q has a considerable probability (more than about 90%) of being self-written to 0.

[0070] Furthermore, in the static memory cell of this embodiment, the substrates of the asymmetric pull-up transistor P2 and the first pull-up transistor P1 are both electrically connected to the first power supply VDDL, and the voltage of the first power supply VDDL is set higher than the voltage of the second power supply VDDR, i.e., VDDR < VDDL. Due to the body bias effect of the MOS transistor (i.e., the turn-on threshold of the MOS transistor is affected by controlling the voltage difference between the source and substrate of the MOS transistor), since the voltage difference between the source and substrate of the first pull-up transistor P1 is zero, while the voltage difference between the source and substrate of the asymmetric pull-up transistor P2 is VDDL-VDDR, the turn-on threshold of the asymmetric pull-up transistor P2 is significantly higher than that of the first pull-up transistor P1. Therefore, although the asymmetric pull-up transistor P2 lacks a pull-down transistor on one side, the subthreshold leakage current of the asymmetric pull-up transistor P2 is suppressed, thereby improving the stability of the second storage node QB when storing a low voltage. This structure helps improve the stability of the 4T1T-SRAM cell, thereby avoiding the need for dynamic data refresh.

[0071] like Figure 2 、 Figure 3 As shown, during the read operation, first, the read bit line RBL is precharged to a first voltage V HIGH and clamp the read word line RWL to a second voltage V LOW , wherein the second voltage V LOW Lower than the first voltage V HIGH Next, the voltage difference of the read bit line RBL is detected to read the data stored in the first storage node Q. That is, the static memory cell of this embodiment uses the so-called "voltage difference current" method to complete the read operation.

[0072] Specifically, if Figure 2 、 Figure 3 As shown in FIG, when the data stored in the first storage node Q is 0, a low voltage is applied to the gate of the read operation transistor N3. At this time, the channel between the drain and source of the read operation transistor N3 is closed, so that no voltage difference current flows from the read bit line RBL to the read word line RWL. The read bit line RBL maintains the precharged first voltage V HIGH As a result, a sense amplifier (SA) (not shown) connected to the read bit line RBL reads out that the value stored in the first storage node Q is 1 (correspondingly, the value stored in the second storage node QB is 0).

[0073] On the other hand, when the data stored in the first storage node Q is 1, the gate of the read operation transistor N3 is applied with a high voltage, at this time, the channel between the drain and the source of the read operation transistor N3 is opened, so that the read bit line RBL discharges to the read word line RWL through the read operation transistor N3 until the voltage of the read bit line RBL drops from the first voltage V HIGH to the second voltage V LOW on the read word line RWL. In this discharge process, a certain voltage difference (V HIGH -V LOW ) is generated on the read bit line RBL. Thus, the not-shown sense amplifier connected to the read bit line RBL reads that the data stored in the first storage node Q is 0 (correspondingly, the data stored in the second storage node QB is 1).

[0074] In the present application, the specific voltage values of the first voltage V HIGH and the second voltage V LOW are not particularly limited, and can be set arbitrarily between the voltage of the power supply VDD and the ground VSS.

[0075] In the write operation, first, the write word line WWL is set to a high voltage, so that the enable of the write transfer transistor N4 is completed. Then, by inputting the third voltage WrQB1 or the fourth voltage WrQB0 to the write bit line WBL, the data is written to the second storage node QB, and further, the data is written to the first storage node Q. The third voltage WrQB1 and the fourth voltage WrQB0 are pre-set voltages, which are pull-up voltage and pull-down voltage respectively, for completing writing 1 or 0 to the second storage node QB, and the fourth voltage WrQB0 is lower than the third voltage WrQB1. That is, the static memory cell of the present embodiment adopts the so-called "single-side operation" to complete the write operation.

[0076] Specifically, when the data 0 is to be written to the first storage node Q, the gate of the write transfer transistor N4 is applied with a high voltage, and the write bit line WBL is set to the third voltage WrQB1. At this time, the channel between the drain and the source of the write transfer transistor N4 is opened, and the voltage on the drain is pulled up to be equal to the third voltage WrQB1 on the source, so that the data 1 is written to the second storage node QB, and further, the data 0 is written to the first storage node Q through the cross-coupled latch circuit.

[0077] On the other hand, when data 1 is to be written to the first storage node Q, the gate of the write transfer transistor N4 is applied with a high voltage, and the write bit line WBL is set to the fourth voltage WrQB0. At this time, the channel between the drain and the source of the write transfer transistor N4 is opened, and the voltage on the drain is pulled down to be equal to the fourth voltage WrQB0 on the source, so that data 0 is written to the second storage node QB, and data 1 is further written to the first storage node Q through the cross-coupled latch circuit.

[0078] In the present application, the specific voltage values of the third voltage WrQB1 and the fourth voltage WrQB0 are not particularly limited. However, in order to further improve the driving capability during the write operation, it is preferred that the write bit line WBL is driven with full swing, i.e., the third voltage WrQB1 is set to the power supply voltage VDD, and the fourth voltage WrQB0 is set to the ground voltage VSS (equivalent to the voltage VSS). In addition, it is further preferred that the write word line WWL is also driven with full swing, i.e., the voltage of the write word line WWL is set to the power supply voltage VDD when the write operation is performed, and the voltage of the write word line WWL is set to the ground voltage VSS (equivalent to the voltage VSS) when the write operation is not performed.

[0079] In addition, in the hold state, the write word line WWL, the write bit line WBL, the read word line RWL and the read bit line RBL are all set to a low voltage. Thus, there is no voltage difference between the source and the drain of the read operation transistor N3, so that no differential current will be generated on the read bit line RBL regardless of whether 1 or 0 is stored in the first storage node Q. In addition, the gate and the source of the write transfer transistor N4 are kept at a low voltage, so that the second storage node QB will not be written.

[0080] In addition, during the read operation, the write word line WWL and the write bit line WBL can be kept at a low voltage. During the write operation, the read word line RWL and the read bit line RBL can be kept at a low voltage. Thus, during any one of the read and write operations, the state of the other operation is kept unchanged, so that the mutual interference between the read and write operations can be avoided.

[0081] The technical effects of the static memory cell of the present application will be described below by comparing with the single-port 6T-SRAM cell and the two-port 8T-SRAM cell of the prior art.

[0082] Figure 4 is a bar chart showing the comparison results of the cell area of the static memory cell of the present application and the single-port 6T-SRAM cell and the two-port 8T-SRAM cell of the prior art. The data in the chart is derived from the 28 nm process node, and the height of each column represents the area of the SRAM cell, in um 2 In Figure 4 , theFigure 2 The two-port 4T1T-SRAM cell shown is shown as a representative of the static memory cell of the present application.

[0083] As shown in Figure 4 Compared with the two-port 8T-SRAM cell of one of the prior arts, the two-port 4T1T-SRAM cell of the present application has a SRAM cell area reduced to about 56% of the two-port 8T-SRAM cell, which is equivalent to the area reduction ratio of 51% of the single-port 6T-SRAM cell. At the same time, the two-port 4T1T-SRAM cell of the present application also has a high stability and a high anti-read disturbance capability comparable to the two-port 8T-SRAM cell.

[0084] The accuracy of the power-on self-write of the storage node of the static memory cell of the present application and the stability of the data retention after the write are described below by using Monte Carlo simulation graphs.

[0085] Fig. 5(A) is a 1K-point Monte Carlo simulation graph of the Q-point power-on automatic setting to 0 of the static memory cell of the present embodiment, and Fig. 5(B) is a 1K-point Monte Carlo simulation graph of the QB-point power-on automatic setting to 1 of the static memory cell of the present embodiment. In the graphs, the horizontal axis represents the voltage of the first storage node Q / second storage node QB after the power-on, and the vertical axis represents the number of sampling points. Also, the voltage of the first power supply VDDL is set to 700 mV, and the voltage of the second power supply VDDR is set to 500 mV.

[0086] As shown in Fig. 5(A) and Fig. 5(B), in the static memory cell of the present embodiment, after the power-on, the 1000 simulation results of the voltage of the first storage node Q are all distributed near the low voltage, and the average thereof is about 100 μV or so, and after the power-on, the 1000 simulation results of the voltage of the second storage node QB are all distributed near the high voltage, and the average thereof is about 500 mV or so.

[0087] It can be seen that the 4T1T-SRAM cell of the present embodiment can provide the functions of stable Q-point self-power-on loading of 0 and QB-point self-power-on loading of 1.

[0088] Fig. 5(C) is a 1K-point Monte Carlo simulation graph of the Q-point voltage of the static memory cell of the present embodiment after the 1Gs retention time after the storage of 1 in the Q-point, and Fig. 5(D) is a 1K-point Monte Carlo simulation graph of the QB-point voltage of the static memory cell of the present embodiment after the 1Gs retention time after the storage of 0 in the QB-point. In the graphs, the horizontal axis represents the voltage of the first storage node Q / second storage node QB after the 1Gs (i.e. 10 9The horizontal axis represents the number of sampling points, and the vertical axis represents the voltage of the first storage node Q / second storage node QB after a retention time of 1 second. The voltage of the first power supply VDDL was set to 700 mV, and the voltage of the second power supply VDDR was set to 500 mV.

[0089] As shown in FIG. 5(C), in the static memory cell according to the embodiment, in the case of self-writing 1 to the first storage node Q, after the persistent tracking simulation 1 Gs, the 1000 simulation results of the voltage of the first storage node Q are still stably concentrated around a high voltage, and the average value thereof is about 700 mV. On the other hand, as shown in FIG. 5(D), in the case of self-writing 0 to the second storage node QB, after the persistent tracking simulation 1 Gs, the distribution of the voltage of the second storage node QB is dispersed, but is still basically maintained around a low voltage, and the average value thereof is about 118 mV. The reason for the difference in the distribution concentration degree between FIG. 5(C) and FIG. 5(D) is that the 4T1T-SRAM cell according to the embodiment lacks a pull-down transistor on the side of the asymmetric pull-up transistor P2, thereby causing a phenomenon that the 4T1T-SRAM cell has a weak store 0 and a strong store 1 at the second storage node QB. Although there is such a strong-weak tendency, as shown in FIG. 5(C) and FIG. 5(D), the data stored in the first storage node Q and the second storage node QB are still stable after 1 Gs. In particular, in the case of writing 0 to the second storage node QB, the static voltage of the second storage node QB can be maintained around 100 mV under the leakage effect at the threshold value of the asymmetric pull-up transistor P2 and the write transfer transistor N4 in the off state. Therefore, it is proved that the static memory cell according to the embodiment can stably provide the function of SRAM without relying on the dynamic refresh of data like DRAM.

[0090] As described above, according to the static memory cell according to the embodiment, compared with the inverter circuit NOT composed of the first pull-up transistor P1 and the first pull-down transistor N1, the pull-down transistor below the asymmetric pull-up transistor P2 on the right side is removed, and thus the asymmetric pull-up transistor P2 and the inverter circuit NOT on the left side constitute a physically asymmetric structure. With the above structure, the first storage node Q is more likely to flip to the ground potential at power-on of the static memory cell, and thus the static memory cell is given the feature that the first storage node Q is self-loaded with 0 after power-on. Therefore, in the case where it is necessary to store data with high sparsity by using a storage array composed of the static memory cell, the static memory cell according to the embodiment has the advantage of naturally low write power consumption.

[0091] In addition, according to the static memory cell involved in the embodiment, since the gate of the read operation transistor N3 for completing the read operation is separated from the source and the drain, there is no direct charging and discharging path between the read bit line RBL and the read word line RWL and the latch circuit part of the SRAM memory cell, thereby solving the read disturbance problem faced by the prior art 6T-SRAM.

[0092] In addition, according to the static memory cell involved in the embodiment, since the write operation adopts a single-side operation mode, compared with the prior art 8T-SRAM, the use of one NMOS write transfer tube (i.e., the first transfer transistor N5 in the 8T-SRAM cell) is reduced. At the same time, since the read operation directly adopts a differential pressure current mode, compared with the prior art 8T-SRAM, the use of one NMOS read transfer tube (i.e., the read selection transistor N7 in the 8T-SRAM cell) is also reduced. In addition, in order to ensure logic correctness, the read pull-down transistor N8 is moved to the Q point side to become the read operation transistor N3. Thus, the static memory cell of the embodiment can solve the problem of excessive cell area of the prior art 8T-SRAM by reducing the number of MOS transistors.

[0093] Embodiment 2

[0094] Next, the memory architecture involved in the embodiment is described with reference to Figure 6 and Figure 7 .

[0095] Figure 6 is a block diagram showing the structure of the memory architecture involved in the embodiment. The memory architecture of the embodiment can be used for a high-density two-port buffer of a system-on-chip. As shown in Figure 6 , the memory architecture includes a memory array 1, a row drive circuit 2, a column pre-charge drive circuit 3, a read circuit 4, and a power-on self-control circuit 5.

[0096] The memory array 1 is composed of a plurality of static memory cells as described in Embodiment 1. In FIG. 5, the structure of the memory array 1 is briefly shown by taking the first four columns of the second row as an example. Among them, one box represents one static memory cell, combined with Figure 1 , 2As shown in FIG. 5, the source of the read operation transistor of the static memory cell in the same row is electrically connected to the same read word line RWL, the gate of the write transfer transistor of the static memory cell in the same row is electrically connected to the same write word line WWL, the drain of the read operation transistor of the static memory cell in the same column is electrically connected to the same read bit line RBL, and the source of the write transfer transistor of the static memory cell in the same column is electrically connected to the same write bit line WBL. In addition, considering the voltage division and speed drop caused by the length, capacitance and resistance of the word bit line, in the present embodiment, the number of rows of the memory array 1 is preferably controlled to be within 64 rows. When a larger capacity is required, a hierarchical storage structure can be used to splice multiple storage blocks.

[0097] The row drive circuit 2 is electrically connected to the read word line RWL and the write word line WWL of each row of the memory array 1, and selects the row to be read according to the row address code signal from the control circuit not shown by the read word line RWL, or selects the row to be written according to the row address code signal from the control circuit not shown by the write word line WWL.

[0098] The column pre-charge drive circuit 3 is electrically connected to the read bit line RBL and the write bit line WBL of each column of the memory array 1, and pre-charges the read bit line RBL of the column to be read according to the column address code signal from the control circuit not shown, or pre-charges all the write bit lines WBL, and writes data to the static memory cell of the column to be written according to the column address code signal by the write bit line WBL.

[0099] The read circuit 4 is electrically connected to the read bit line RBL of each column of the memory array 1, and gates the column to be read, and generates and outputs the read data based on the voltage of the read bit line RBL of the column to be read.

[0100] The self-power-on control circuit 5 provides the first power supply VDDL and the second power supply VDDR to each static memory cell in the memory array 1, respectively.

[0101] Figure 7 is a schematic diagram of one specific embodiment of the memory architecture of Figure 6 . In Figure 7 , the same reference numerals are used to denote the same parts as Figure 6 .

[0102] In combination with Figure 6 , Figure 7 , the row drive circuit 2 can include a row decoder 21, a read word line driver 22 and a write word line driver 23. The column pre-charge drive circuit 3 can include a column decoder 31, a read bit line pre-charger 32 and a write bit line pre-charge driver 33. The read circuit 4 can include a sense amplifier 41 and a multiplexer 42.

[0103] The first power supply VDDL and the second power supply VDDR are supplied from the power-up control circuit 5 to the memory array 1. The source of the first pull-up transistor P1 and the source of the asymmetric pull-up transistor P2 of each static memory cell in the memory array 1 are in electrical contact with the first power supply VDDL and the second power supply VDDR, respectively. Thus, as described above, at the time of power-up, the power-up control circuit 5 can pull up the second storage node QB of all the static memory cells to the high voltage by turning on the second power supply VDDR, thereby simultaneously self-writing 0 to all the first storage nodes Q.

[0104] In addition, the power-up control circuit 5 can also control the turn-on sequence of the first power supply VDDL and the second power supply VDDR based on the acquired clock signal Clk, so that each static memory cell turns on the first power supply VDDL after the second power supply VDDR is turned on and a specified time interval elapses. Thus, the accuracy of self-writing 0 to the first storage nodes Q can be further improved.

[0105] The row decoder 21 converts the acquired row address code signals Al, A2,..., Ax into 2 x =M row selection signals. The row address code signals Al, A2,..., Ax are, for example, a series of binary codes containing the row address to be read or written. The row decoder 21 is, for example, a row address decoder that converts the binary row address code signals Al, A2,..., Ax into a decimal row address and outputs it as a row selection signal.

[0106] The column decoder 31 converts the acquired column address code signals Bl, B2,..., Bm into 2 m =M column selection signals. The column address code signals Bl, B2,..., Bm are, for example, a series of binary codes containing the column address to be read or written. The column decoder 31 is, for example, a column address decoder that converts a certain binary column address code signal Bl, B2,..., Bm into one of 2 m =M possible column addresses and outputs it as a column selection signal in the form of a M-bit one-hot code to select one of 2 m =M rows. Each row corresponds to N column storage units, so the array has a total of MxN column size.

[0107] In the read operation, the read word line driver 22 clamps the read word line RWL of the row to be read to the second voltage V LOW , and the read bit line pre-charger 32 pre-charges the read bit line RBL of the column to be read to the first voltage VHIGH wherein the second voltage V LOW is lower than the first voltage V HIGH The multiplexer 42 selects the column to be read. In this embodiment, the multiplexer 42 selects N read bit lines RBL of N column memory cells to be read from M read bit lines RBL according to the column address of the read operation, and connects the N read bit lines RBL to the sense amplifier 41. The sense amplifier 41 amplifies the voltage variation of the N read bit lines RBL of the N column memory cells to be read, and outputs the amplified voltage variation as the read data.

[0108] In addition, in the read operation, the read word line driver 22 maintains the read word line RWL of the row not to be read at a high voltage, and the read bit line pre-charger 32 maintains the read bit line RBL of the column not to be read at a high voltage.

[0109] In the read operation read 0 (the Q point of the read memory cell stores 0, and the read operation transistor N3 is closed), for the selected column in the unselected row, since the unselected row and the selected column are both at a high voltage, the voltage of the selected column will not be affected, and no misreading will occur.

[0110] In the read operation read 1 (the Q point of the read memory cell stores 1, and the read operation transistor N3 is opened), the RBL of the selected column will discharge to the low voltage V LOW through the opened read operation transistor N3 to the RWL of the selected row. At this time, if the unselected row of the column has a memory cell storing 1, there will be further discharge between the high voltage V HIGH of the unselected row and the low voltage V LOW of the selected column after being pulled down. For this, the circuit will eventually stabilize at the static operating point of V HIGH -ΔV. When the number of control array rows is not more than 64 rows at the 28 nm node, ΔV>10mV. At this time, the pressure difference of 10mV is sufficient for the sense amplifier 41 to correctly read 1. In other design backgrounds and process nodes, the configuration of "not more than 64 rows" can be adaptively adjusted according to the above principle. Therefore, the present application does not only protect the literal meaning of "not more than 64 rows", but also any technology using the above principle design is within the protection scope of the present application.

[0111] In the read operation, for the unselected column in the selected row, since the multiplexer 42 will not further connect the read bit line RBL connected thereto to the sense amplifier 41, the read data will not be affected.

[0112] Before a write operation, the write bit line precharge driver 33 precharges the write bit lines WBL of all columns to a high voltage. During a write operation, the write word line driver 23 sets the write word line WWL of the row to be written to a high voltage based on the row select signal. The write bit line precharge driver 33 inputs the third voltage WrQB1 or a fourth voltage WrQB0, which is lower than the third voltage WrQB1, to the write bit line WBL of the column to be written based on the column select signal and an external data signal, thereby writing data to the static memory cell to be written.

[0113] Furthermore, during a write operation, the write word line driver 23 maintains the write word line WWL of the row not being written to at a low voltage, and the write bit line precharge driver 33 maintains the write bit line WBL of the column not being written to at a low voltage. This selects the row and column to be written to.

[0114] Furthermore, during a write operation, for static memory cells in unselected rows within a selected column, the gate of their write-pass transistor N4 is at a low voltage, closing the channel between its source and drain. Therefore, the voltage of the write bit line WBL is not written into the static memory cell. For static memory cells in unselected columns within a selected row, their write bit lines WBL are unselected and remain in a floating high-impedance state. They are not driven by the third voltage WrQB0 or ​​the fourth voltage WrQB1 used for write operations and are therefore maintained at the precharge voltage. Furthermore, the cross-latch circuit within these memory cells exhibits positive feedback characteristics, providing strong retention capabilities. Therefore, the voltage of the second storage node QB is not affected by the precharge voltage of the high-impedance write bit line WBL.

[0115] In practical applications, the number of rows in a stored data array is typically much greater than the number of columns. To avoid an imbalance in the number of rows and columns in memory array 1 and to ensure that the number of rows in memory array 1 is as close to or equal to the number of columns as possible, the concept of "bit width" is introduced. Specifically, the rows of the stored data array can be segmented according to a certain bit width (e.g., N bits), and the segmented data can be folded into a nearly square or square data array for read and write operations.

[0116] Therefore, if Figure 6 As shown, in this embodiment, taking into account the bit width of the stored data, the memory array 1 can be divided into M groups along the row direction, each group containing N columns of static memory cells. That is, the memory array 1 includes a total of M×N columns of static memory cells. M column select signals can be used to select which group to perform read or write operations on, and when a read or write operation is performed on the selected group, the static memory cells in all columns of the group are read or written simultaneously.

[0117] In the above case, at the time of the read operation, the read bit line pre-charger 32 pre-charges the read bit line RBL of the column to be subjected to the read operation to the first voltage V HIGH And the multiplexer 42 selects the read bit line RBL in units of the bit width Nbit, that is, selects N pieces of the read bit line RBL from the M pieces of the read bit line RBL to be electrically connected to the sense amplifier 41.

[0118] On the contrary, at the time of the write operation, the write bit line pre-charge driver 33 also writes data to the static memory cell to be subjected to the write operation in units of the bit width. And the data signal from the outside is Nbit data, and the write bit line pre-charge driver 33 writes the Nbit data to the selected N columns of the static memory cell at one time in units of the bit width.

[0119] The bit number N of the bit width can be set according to the actual storage needs. In some specific cases, the bit width can even be set to 1bit.

[0120] As described above, according to the memory architecture related to the present embodiment, since the static memory cell as described above is used to constitute the memory array, when data with high sparsity is stored, for example, the 0 setting can be completed at one time in a short time after power-on, and the power consumption of data storage can be reduced. And the area overhead can be reduced by controlling the number of transistors, the storage density can be improved, and independent functional paths can be provided for the read operation and the write operation, respectively, to improve the reliability.

[0121] The static memory cell and the memory architecture including the static memory cell related to the present application are described above. It is worth noting that the contents not described in detail in the embodiments of the present application belong to the prior art known to those skilled in the art.

[0122] In addition, the above description is only the preferred specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any changes or replacements easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims. The information disclosed in the background section of this document is only intended to deepen the understanding of the overall background of the present application, and should not be regarded as acknowledging or implying in any form that the information constitutes prior art known to those skilled in the art.

[0123] Industrial applicability

[0124] As described above, the static memory cell and the memory architecture including the same according to the present application are useful for high-density cache of system-on-chip, especially for static memory having high sparsity characteristics of weight values such as neural networks.

[0125] REFERENCE NUMERALS

[0126] 1 memory array

[0127] 2 row driver circuit

[0128] 3 column precharge driver circuit

[0129] 4 read circuit

[0130] 5 power-on self test control circuit

[0131] 21 row decoder

[0132] 22 read word line driver

[0133] 23 write word line driver

[0134] 31 column decoder

[0135] 32 read bit line precharger

[0136] 33 write bit line precharge driver

[0137] 41 sense amplifier

[0138] 42 multiplexer

[0139] P1 first pull-up transistor

[0140] P2 asymmetric pull-up transistor

[0141] N1 first pull-down transistor

[0142] N2 second pull-down transistor

[0143] N3 read operation transistor

[0144] N4 write transfer transistor

[0145] N5 first transfer transistor

[0146] N6 second transfer transistor

[0147] N7 read selection transistor

[0148] N8 read pull-down transistor

[0149] NOT inverter circuit

[0150] RWL read word line

[0151] RBL read bit line

[0152] BL bit line

[0153] BLB inverted bit line

[0154] WWL write word line

[0155] WBL write bit line

[0156] WL word line

[0157] WBLB inverted write bit line

[0158] Q first storage node

[0159] QB second storage node

[0160] VDDL first power supply

[0161] VDDR second power supply

[0162] VSS ground.

Claims

1. A static memory cell, characterized in that: include: an inverter circuit, wherein an output terminal of the inverter circuit is electrically connected to the first storage node, an input terminal of the inverter circuit is electrically connected to the second storage node, and a power supply terminal of the inverter circuit is electrically connected to the first power supply; an asymmetric pull-up transistor, wherein the gate of the asymmetric pull-up transistor is electrically connected to the first storage node, the drain is electrically connected to the second storage node, and the source is electrically connected to a second power supply; a read operation transistor, wherein the gate of the read operation transistor is electrically connected to the first storage node, the drain is electrically connected to a read bit line, and the source is electrically connected to a read word line; as well as A write pass transistor has a drain electrically connected to the second storage node, a gate electrically connected to a write word line, and a source electrically connected to a write bit line.

2. The static memory cell according to claim 1, wherein When the static memory unit is powered on, the second power supply is turned on to pull the second storage node to a high level, thereby writing 0 to the first storage node.

3. The static memory cell according to claim 2, wherein: When the static memory unit is powered on, the first power supply is turned on after a prescribed time interval has passed after the second power supply is turned on.

4. The static memory cell according to any one of claims 1 to 3, wherein: The inverter circuit includes a first pull-up transistor and a first pull-down transistor, the drain of the first pull-up transistor and the drain of the first pull-down transistor are electrically connected to the first storage node, the gate of the first pull-up transistor and the gate of the first pull-down transistor are electrically connected to the second storage node, the source of the first pull-up transistor is electrically connected to the first power supply as the power supply terminal of the inverter circuit, and the source of the first pull-down transistor is grounded.

5. The static memory cell according to claim 4, wherein A substrate of the asymmetric pull-up transistor and a substrate of the first pull-up transistor are both electrically connected to the first power supply, and a voltage of the first power supply is higher than a voltage of the second power supply.

6. The static memory cell according to claim 1, wherein During a read operation, the read bit line is precharged to a first voltage, the read word line is clamped to a second voltage lower than the first voltage, and the data stored in the first storage node is read by detecting the voltage difference of the read bit line.

7. The static memory cell according to claim 6, wherein: During a read operation, the write word line and the write bit line are kept at a low level.

8. The static memory cell according to claim 1, wherein During a write operation, the write word line is set to a high level, and data is written to the second storage node by inputting a third voltage or a fourth voltage lower than the third voltage to the write bit line, thereby writing data to the first storage node.

9. The static memory cell according to claim 8, wherein During a write operation, the read word line and the read bit line are kept at a low level.

10. The static memory cell according to any one of claims 6 to 9, characterized in that In the hold state, the write word line, the write bit line, the read word line, and the read bit line are all set to a low level.

11. A memory architecture, characterized in that: include: A memory array, the memory array comprising a plurality of static memory cells according to any one of claims 1 to 10, wherein the sources of the read transistors of the static memory cells in the same row are electrically connected to the same read word line, the gates of the write pass transistors of the static memory cells in the same row are electrically connected to the same write word line, the drains of the read transistors of the static memory cells in the same column are electrically connected to the same read bit line, and the sources of the write pass transistors of the static memory cells in the same column are electrically connected to the same write bit line; a row driver circuit, the row driver circuit being electrically connected to a read word line and a write word line of each row of the memory array, and selecting a row to be read through the read word line according to a row address code signal, or selecting a row to be written through the write word line according to a row address code signal; a column precharge drive circuit, the column precharge drive circuit being electrically connected to the read bit lines and write bit lines of each column of the memory array, and precharging the read bit lines of the column to be read according to the column address code signal, or precharging the write bit lines of all columns and writing data to the static memory cells of the column to be written through the write bit lines according to the column address code signal; a read circuit electrically connected to a read bit line of each column of the memory array, selecting a column to be read, and generating and outputting read data based on a voltage of the read bit line of the column to be read; as well as A self-power-on control circuit provides the first power supply and the second power supply to each of the static memory units respectively.

12. The memory architecture of claim 11, wherein: The self-power-on control circuit controls the order of turning on the first power supply and the second power supply based on the acquired clock signal, so that the first power supply is turned on after a predetermined time interval has passed after the second power supply is turned on.

13. The memory architecture according to claim 11 or 12, wherein: The row driving circuit includes a row decoder, which converts the acquired row address code signal into a row selection signal.

14. The memory architecture of claim 13, wherein: The row driving circuit also includes a read word line driver. During a read operation, the read word line driver clamps the read word line of the row to be read to a second voltage based on the row selection signal, and the second voltage is lower than the first voltage precharged on the read bit line of the column to be read.

15. The memory architecture of claim 13, wherein: The row driving circuit further includes a write word line driver. During a write operation, the write word line driver sets the write word line of the row to be written to a high level according to the row selection signal.

16. The memory architecture according to claim 11 or 12, wherein: The column precharge driving circuit includes a column decoder, which converts the acquired column address code signal into a column selection signal.

17. The memory architecture of claim 16, wherein: The column pre-charge drive circuit also includes a read bit line pre-charger. During a read operation, the read bit line pre-charger pre-charges the read bit line of the column to be read to a first voltage according to the column selection signal. The first voltage is higher than the second voltage clamped on the read word line of the row to be read.

18. The memory architecture of claim 17, wherein: The read bit line precharger precharges the read bit line of a column to be read to the first voltage in units of bit width.

19. The memory architecture of claim 16, wherein: The column pre-charge drive circuit also includes a write bit line pre-charge driver. Before a write operation, the write bit line pre-charge driver pre-charges the write bit lines of all columns to a high level. During a write operation, the write bit line pre-charge driver inputs a third voltage or a fourth voltage lower than the third voltage to the write bit line of the column to be written based on the column selection signal and the data signal from the outside, thereby writing data to the static memory cell to be written.

20. The memory architecture of claim 19, wherein: The write bit line precharge driver writes data to the static memory cell to be written using a bit width as a unit.

21. The memory architecture according to claim 11 or 12, wherein: The reading circuit includes a sense amplifier. During a reading operation, the sense amplifier amplifies the voltage variation of the read bit line of the column to be read as read data.

22. The memory architecture of claim 21, wherein: The reading circuit further includes a multiplexer that selects a column to be read.

23. The memory architecture of claim 22, wherein: The multiplexer performs the gating in units of bit width.

Images