A control circuit for a switching power supply

Abstract

The present application relates to a control circuit for a switching power supply, comprising: an error amplification module, which compares a feedback voltage obtained based on an output signal of a controllable switch with a first reference signal and generates a first error signal; a mirror unit, which copies or deforms the first error signal to obtain a second error signal; a first comparison module, which influences the duty cycle of the controllable switch during operation based on the comparison result of the first error signal or its deformation with the second reference signal; a second comparison module, which is configured to compare the second error signal with a third reference signal and generate a first control signal; a mode detection module, which generates a second control signal indicating whether the control circuit is in PWM mode or PFM mode based on the first error signal and a reference signal; and a mode control module, which receives a clock signal and a first control signal and a second control signal, and determines whether to output the clock signal based on the first control signal and the second control signal. The present application also relates to an electronic device.

Description

Technical Field

[0001] The present invention relates to electrical control, in particular to a control circuit of a switching power supply. Background Art

[0002] A controllable switch supplies power to the load by controlling the alternating operation of switching transistors, thereby maintaining a stable output voltage and current of the power conversion system. Depending on the application scenario, controllable switches can have various configurations, including Boost, Buck, and Buck-Boost.

[0003] Typically, under heavy loads, a controlled switch operates in continuous conduction mode (CCM), maintaining a constant switching frequency. Under light loads, to quickly respond to load changes and reduce power consumption, the control circuit automatically enters light load mode to optimize efficiency. At this point, the controlled switch no longer operates in CCM, but instead starts and stops operating according to different control strategies.

[0004] Under light load, there are two main design schemes for the control mode of existing controllable switches. In the first scheme, the controllable switch operates continuously for several cycles and then stops for several cycles, eliminating switching losses during the off-cycle period. In this scheme, the result of comparing the feedback voltage with the reference voltage (the output of the error amplifier module) is used through an RC compensation structure to generate a control signal for controlling the operation of the controllable switch. In this scheme, the control signal generated by the RC compensation structure cannot quickly respond to changes in the power conversion system load, resulting in a slow response and large output ripple. In the second scheme, the controllable switch operates in PFM mode, still using the RC compensation structure to generate the control signal for controlling the operation of the controllable switch. Furthermore, current conversion and current control delay circuits are added to the power conversion system to convert the control signal into a current signal that controls the delay time of the PFM signal. This scheme has a complex circuit structure and large output ripple. The dynamic response speed of the power conversion system is affected not only by the RC compensation structure but also by the delay circuit. Summary of the Invention

[0005] In response to the technical problems existing in the prior art, the present application proposes a control circuit for a switching power supply, comprising: an error amplification module, configured to compare a feedback voltage obtained based on an output signal of a controllable switch with a first reference signal and generate a first error signal; it includes a mirror unit, configured to copy or deform the first error signal to obtain a second error signal; a first comparison module, whose first input end is electrically connected to the error amplification module, whose second input end receives a second reference signal, and is configured to influence the duty cycle of the controllable switch during operation based on a comparison result of the first error signal or its deformation with the second reference signal; a second comparison module, whose first input end is electrically connected to the error amplification module, and is configured to receiving the second error signal, comparing the second error signal with a third reference signal received at the second input terminal of the second comparison module, and generating a first control signal; a mode detection module, electrically connected to the error amplification module, configured to generate, based on the first error signal and the reference signal, a second control signal indicating that the control circuit is in PWM mode or PFM mode and / or a third control signal obtained by a logical inversion operation thereof; a mode control module, electrically connected to the mode detection module and the second comparison module, configured to receive a clock signal and a first control signal and a second control signal, and determine whether to output the clock signal based on the first control signal and the second control signal.

[0006] In particular, the control circuit outputs the clock signal when the first control signal and the second control signal are valid; and shields the clock signal when the first control signal and the second control signal are not valid at the same time.

[0007] In particular, the control circuit also includes a pull-down module configured to receive the first control signal, the first error signal and the third control signal, and obtain a pull-down signal by reducing the first error signal by a fixed value based on the first control signal and the third control signal.

[0008] In particular, the control circuit and the mode detection module also include a comparator, whose first input terminal is configured to receive the reference signal, and whose second input terminal is configured to receive the first error signal, and configured to output a second control signal; a first logic NOT unit, which is electrically connected to the output terminal of the comparator, and configured to output the third control signal; a pulse unit, which is electrically connected to the output terminal of the comparator, and configured to generate a pulse in response to the rising edge of the second control signal and serve as the fourth control signal; a second logic NOT unit, which is electrically connected to the pulse unit, and configured to receive the fourth control signal and perform a logical inversion operation to obtain a fifth control signal.

[0009] In particular, the control circuit, wherein the reference signal includes a first reference signal and a second reference signal; wherein the first reference signal is higher than the second reference signal; wherein the mode detection module also includes a first reference switching unit, whose output end is electrically connected to the second input end of the comparator, the first reference switching unit includes a first branch, which is configured to selectively output the first reference signal based on at least the received fourth control signal; the first reference switching unit also includes a second branch, which is configured to selectively output the second reference signal based on at least the fifth control signal.

[0010] Particularly, in the control circuit, the third reference signal is lower than the first reference signal and higher than the second reference signal.

[0011] In particular, the control circuit further includes a clamping module, whose first input terminal and output terminal are electrically connected to the first input terminal of the first comparison module, and is configured to determine whether to clamp the potential of the first input terminal of the first comparison module to the reference signal or stop working based on at least the size of the received first error signal.

[0012] In particular, the control circuit, wherein the reference signal includes a first reference signal and a second reference signal; the clamping module also includes a second reference switching unit, configured to select and output the first reference signal or the second reference signal based on at least the fourth control signal; and a clamping unit, whose first input end is electrically connected to the output end of the second reference switching unit, whose second input end is configured to receive the first error signal, and whose output end is electrically connected to the first input end of the first comparison module.

[0013] In particular, the control circuit, wherein the pull-down module includes a logic NOT unit, configured to perform a logic AND NOT operation on the received first control signal and the third control signal; a third logic NOT unit, configured to receive the output of the logic NAND unit and perform a logic NOT operation; a first resistor and a transistor, the first end of the first resistor is configured to receive the first error signal, and the second end of the first resistor is electrically connected to the first electrode of the transistor; the control electrode of the transistor is electrically connected to the output end of the first logic NOT unit; a current source, which is electrically connected between the second electrode of the transistor and the ground; a first capacitor, electrically connected between the first electrode of the transistor and the ground; and a second capacitor, electrically connected between the first end of the first resistor and the ground.

[0014] In particular, the control circuit, wherein the mode control module includes a fourth logic NOT unit, configured to receive the first control signal and perform a logical inversion operation on it; a first logic OR NOT unit, configured to receive the output of the fourth logic NOT unit, and perform a logical OR NOT operation on it and the second control signal to obtain a shielding signal; a fifth logic NOT unit, configured to receive the clock signal and perform a logical inversion operation on it; a second logic OR NOT unit, configured to receive the output of the fifth logic NOT unit and the shielding signal, and perform a logical OR NOT operation on the two.

[0015] The present application also relates to an electronic device comprising any of the control circuits described above.

[0016] The control circuit proposed in this application can ensure the output voltage accuracy of the power conversion system under light load conditions, effectively reduce the ripple of the output voltage / current of the power conversion system, improve the dynamic response speed of the control circuit, and make the power conversion system more reliable and stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0018] Figure 1 FIG2 is a partial structural diagram of a power conversion system according to an embodiment of the present application;

[0019] Figure 2 FIG2 is a schematic structural diagram of a PFM mode detection module according to an embodiment;

[0020] Figure 3 FIG2 is a schematic structural diagram of a PFM mode control module according to an embodiment of the present application;

[0021] Figure 4 Shown is a structural schematic diagram of a pull-down module according to one embodiment of the present application;

[0022] Figure 5 Shown Figure 1 The working timing diagram of the control circuit shown. DETAILED DESCRIPTION

[0023] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0025] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit the unconnected elements from being unable to communicate. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in the communication between the two elements or at least the number of outputs provided, and is not intended to limit the two elements to communicating only with the signals shown in the figure.

[0026] The control circuit proposed in this application utilizes a second comparison module to generate a control signal that causes the control circuit to enter PFM mode. This not only effectively reduces the ripple of the power conversion system's output voltage and current, but also enables the control circuit to have a higher dynamic response speed. This allows the power conversion system to provide a highly accurate output voltage under light load conditions to meet the requirements of high-precision applications. Furthermore, the control circuit can improve the reliability and stability of the power conversion system, reducing malfunctions and oscillations.

[0027] The following text uses a boost converter as an example to illustrate the control principle of the control circuit of the present application. However, it should not be considered that the control circuit disclosed in the present application is limited to this embodiment. The controllable switch may also be, for example, a buck converter, a boost-buck converter, etc., and adaptive adjustments or changes may be made according to different usage scenarios.

[0028] In the following detailed description, the effective level can be a high level or a low level according to different circuits. In the following detailed description, the high level is described as the effective level and the low level is described as the failure level.

[0029] Figure 1 Shown is a partial structural schematic diagram of a power conversion system according to an embodiment of the present application.

[0030] According to one embodiment, a power conversion system includes a controllable switch 10, an inductor L11 coupled between a first input terminal of the controllable switch 10 and a signal input terminal IN of the power conversion system, a capacitor C12 coupled between the signal input terminal IN of the power conversion system and ground, a capacitor C13 coupled between a signal output terminal OUT of the power conversion system and ground, a resistor R14 coupled between the signal output terminal OUT of the power conversion system and ground, and a control circuit 15 coupled to the controllable switch 10. The signal input terminal IN of the power conversion system receives an input, such as a voltage or current, and the signal output terminal OUT of the power conversion system outputs an output, such as a voltage or current, to a load.

[0031] In one embodiment of the present application, a controllable switch 10 includes a first transistor T101 and a second transistor T102 connected in series. A first electrode of the first transistor T101 is electrically connected to a first electrode of the second transistor T102, and the node at which they are electrically connected serves as a first input terminal of the controllable switch 10 and is coupled to an inductor L11. A second electrode of the first transistor T101 is electrically connected to a power conversion system signal output terminal OUT, and a second electrode of the second transistor T102 is grounded. Control electrodes of the first transistor T101 and the second transistor T102 are each electrically connected to a control circuit 15.

[0032] According to one embodiment, the control circuit 15 is configured to receive an output signal from the signal output terminal OUT of the power conversion system, adjust its own operating mode based on the output signal, and generate a signal to control the alternating conduction of the first transistor T101 and the second transistor T102 in the controllable switch 10, thereby achieving control of the output signal of the power conversion system.

[0033] According to one embodiment, the control circuit 15 may include a feedback network 151 , an error amplification module 152 , and a first comparison module 153 .

[0034] When the load of the power conversion system switches between heavy and light loads, the control circuit proposed in this application switches between PWM mode and PFM mode. The power conversion system directly compares the output of the error amplifier module or its modified version with the reference voltage to obtain a control signal, thereby determining the load condition of the power conversion system and controlling the operating state of the controllable switch.

[0035] When the load on the power conversion system increases, the feedback voltage is slightly lower, the output of the error amplification module or its deformation fluctuates around a higher value, and the control circuit operates in PWM mode, controlling the first and second transistors in the controllable switch to continuously alternately conduct. When the load on the power conversion system decreases, the feedback voltage gradually increases, the output of the error amplification module or its deformation fluctuates around a lower value, and the control circuit intermittently controls the first and second transistors in the controllable switch to alternately conduct. At this time, the control circuit operates in PFM mode. In this case, the control circuit controls the controllable switch to operate intermittently. This direct comparison, compared to the prior art method of using an RC compensation structure to obtain a control signal to control the power conversion system to enter light load mode, is more conducive to improving the system's dynamic response capability, ensuring that the power conversion system can quickly respond to changes in its load, avoiding the problem of power conversion system output signal errors caused by the delay of the RC compensation structure, and improving the accuracy of the power conversion system output signal.

[0036] According to one embodiment, as the load of a power conversion system gradually transitions from light / no load to heavy load, the time during which the controllable switch remains inoperative decreases. The control circuit can utilize a reference switching unit to implement reference signal switching, rapidly switching the control circuit's operating mode from PFM mode to PWM mode and the controllable switch from intermittent operation to continuous CCM mode. This prevents malfunctions in the power conversion system during control mode switching and improves the reliability of the control circuit. When the load of the power conversion system decreases from heavy load, the control circuit can also utilize a pull-down module to ensure that the power conversion system smoothly enters PFM mode.

[0037] In this application, the load condition affects the time it takes for a controllable switch in a power conversion system to stop working. The lighter the load, the longer the time it takes for the controllable switch to stop working, while the heavier the load, the shorter the time it takes for the controllable switch to stop working. During the transition from light / no load to heavy load in the power conversion system, the time it takes for the controllable switch to stop working gradually increases as the load decreases, or it decreases as the load increases.

[0038] According to one embodiment, the feedback network 151 is electrically connected to the output terminal OUT of the power conversion system, and is configured to receive the output of the power conversion system and generate a corresponding feedback voltage Vfb based on the output of the power conversion system.

[0039] According to one embodiment, the error amplification module 152 is electrically connected to the feedback network 151 and configured to receive the feedback voltage Vfb from the feedback network 151 and compare it with the first reference voltage Vref1 to generate and output the first error signal VEA1 .

[0040] In one embodiment of the present application, the error amplification module 152 may further include a mirror unit, which may be a functional module such as a current mirror, configured to replicate or deform the first error signal VEA1 to obtain a second error signal VEA2 related to the first error signal VEA1. The first error signal VEA1 and the second error signal VEA2 are positively correlated, and both increase or decrease simultaneously.

[0041] According to one embodiment, after the first error signal VEA1 is clamped or deformed, the second error signal VEA2 continues to increase as the feedback voltage Vfb decreases, or decreases as the feedback voltage Vfb increases.

[0042] According to one embodiment, the positive input terminal of the first comparison module 153 is electrically connected to the error amplification module 152, and the negative input terminal thereof receives the second reference voltage Vref2. The first comparison module 153 is configured to control the duty cycle of the controllable switch based on the first error signal VEA1 or the clamped first error signal VEA1. The second reference voltage Vref2 can be a triangular wave or a sawtooth wave.

[0043] According to one embodiment, the control circuit 15 may further include a second comparison module 154. The negative input terminal of the second comparison module 154 is electrically connected to the error amplification module 152, and the positive input terminal of the second comparison module 154 is configured to receive the third reference voltage Vref3. The second comparison module 154 is configured to receive the second error signal VEA2 from the error amplification module 152, compare the second error signal VEA2 with the third reference voltage Vref3, and generate a first control signal CV_ST to control the operation of the controllable switch.

[0044] In one embodiment, the second comparison module 154 may also be located inside the error amplification module 152 .

[0045] According to one embodiment, when the power conversion system is loaded, the control circuit uses a PWM mode to control the controllable switch to operate. When the feedback voltage Vfb of the power conversion system is near a low value, the values ​​of the first error signal VEA1 and the second error signal VEA2 are greater than the value of the third reference voltage Vref3, and the first control signal CV_ST is in a disabled state.

[0046] In other embodiments of the present application, when the load on the power conversion system is reduced, the control circuit uses PFM mode to control the operation of the controllable switch. The feedback voltage Vfb of the power conversion system fluctuates near a relatively high value, and the first control signal CV_ST switches between an active state and a disabled state based on the output signal of the power conversion system, thereby determining whether the controllable switch is operating. Because the load still exists, the output of the power conversion system gradually increases, and the values ​​of the first error signal VEA1 and the second error signal VEA2 gradually decrease. When the second error signal VEA2 is less than or equal to the value of the third reference voltage Vref3, the first control signal CV_ST is active, and the control circuit controls the controllable switch to stop operating. When the second error signal VEA2 is greater than the value of the third reference voltage Vref3, the first control signal CV_ST switches to disabled, and the control circuit controls the controllable switch to operate.

[0047] Second comparison module 154 can quickly capture changes in the power conversion system's output, thereby improving dynamic response speed. By reducing the use of energy storage devices such as capacitors in the control circuit, the ripple in the power conversion system's output voltage is reduced. Because both second error signal VEA2 and first error signal VEA1 are generated by error amplifier module 152, the output voltage accuracy is very high under light load conditions.

[0048] According to one embodiment, the control circuit 15 may further include a PFM mode detection module 155 electrically connected to the error amplification module 152 and configured to receive the first error signal. The PFM mode detection module 155 is configured to generate a second control signal BPFM_ST indicating whether the control circuit is in PFM mode or PWM mode, and / or a third control signal BPFM_STN obtained by performing a logical inversion thereof, based on the reference signal and the first error signal VEA1 from the error amplification module 152.

[0049] According to one embodiment, when the first error signal VEA1 is higher than the reference signal, the second control signal BPFM_ST is valid, indicating that the control circuit operates in the PWM mode.

[0050] According to one embodiment, when the first error signal VEA1 gradually decreases and is no longer higher than the reference signal, the second control signal BPFM_ST transitions to the disabled state, indicating that the control circuit switches to the PFM mode and the power conversion system enters a light-load state.

[0051] When a power conversion system switches from a light load to a heavy load, its output voltage fluctuates. This fluctuation is fed back to the control circuit through the feedback network, affecting the control circuit's operating mode and preventing a smooth transition from PFM to PWM mode. The control circuit uses a reference switching unit to ensure a smooth transition from PFM to PWM mode, preventing malfunction of the control circuit.

[0052] In this case, according to one embodiment of the present application, the PFM mode detection module 155 may further include a reference switching unit. The reference signal includes a first reference signal Vrefc1 and a second reference signal Vrefc2. The second reference signal Vrefc2 may be obtained by adjusting the first reference signal Vrefc1 downward by a fixed value. In this case, the PFM mode detection module 155 may also be configured to generate the fourth control signal BPFM_ST_P required for reference switching and / or a fifth control signal BPFM_ST_N obtained by performing a logical inversion operation thereof.

[0053] According to one embodiment of the present application, the reference switching unit is configured to receive the fourth control signal BPFM_ST_P and the first reference signal Vrefc1 and the second reference signal Vrefc2 , and select and output the first reference signal Vrefc1 or the second reference signal Vrefc2 based on the fourth control signal BPFM_ST_P.

[0054] According to one embodiment, when the power conversion system operates in PWM mode, the reference switching unit in the PFM mode detection module 155 outputs a first reference signal Vrefc1. When the power conversion system load switches from light to heavy, the second control signal BPFM_ST transitions from inactive to active, and the fourth control signal BPFM_ST_P transitions to an active pulse signal and is provided to the reference switching unit, causing the reference switching unit to output a second reference signal Vrefc2 that is lower than the first reference signal Vrefc1. By comparing the first error signal VEA1 with the second reference signal Vrefc2, the power conversion system is prevented from malfunctioning due to load changes, ensuring that the control circuit smoothly switches from PFM mode to PWM mode when the power conversion system load switches from heavy to light.

[0055] According to one embodiment of the present application, when the fourth control signal BPFM_ST_P is invalid, the reference switching unit outputs the first reference signal Vrefc1 ; when the fourth control signal BPFM_ST_P is valid, the reference switching unit outputs the second reference signal Vrefc2 .

[0056] Based on the above content, without creative effort, those skilled in the art can also select and output the first reference signal Vrefc1 and the second reference signal Vrefc2 based on the fourth control signal BPFM_ST_P and the fifth control signal BPFM_ST_N obtained by logical inversion operation thereof.

[0057] In the present application, the control circuit 15 may further include a PFM mode control module 156. The PFM mode detection module 155 and the PFM mode control module 156 work together to determine whether to perform masking processing on the original clock signal CLK to obtain the clock signal CLK_PFM required when the control circuit operates in the PFM mode. This simple processing maintains the quality of the original clock (such as jitter and phase noise) without the need for specialized circuits, thereby reducing the complexity of the hardware design.

[0058] According to one embodiment, the PFM mode control module 156 is electrically connected to the PFM mode detection module 155 and the second comparison module 154, and is configured to receive the clock signal CLK and the second control signal BPFM_ST from the PFM mode detection module 155 and the first control signal CV_ST from the second comparison module 154, and determine whether to output the clock signal CLK based on the first control signal CV_ST and the second control signal BPFM_ST.

[0059] According to one embodiment of the present application, when the second control signal BPFM_ST of the PFM mode detection module 155 is in the invalid state, the flag control circuit is in the PFM mode. During this period, when the first control signal CV_ST is valid, the PFM mode control module 156 outputs the clock signal CLK to control the controllable switch to be in the operating state. When the first control signal CV_ST is invalid, the PFM mode control module 156 outputs a low level to control the controllable switch to stop operating.

[0060] When the load on the power conversion system is reduced, the first error signal output by the error amplification module gradually decreases to a lower value, even approaching zero. When the first error signal or its variant fluctuates around a lower value, the voltage at the positive input of the first comparison module 153 decreases. However, excessively low voltages can reduce the control circuit's ability to effectively adjust the duty cycle of the controllable switch, impacting the efficiency and stability of the power conversion system. A threshold is set as the minimum value of the input signal received by the positive input of the first comparison module 153 to ensure normal operation. When the load on the power conversion system is reduced, the clamping module clamps the first error signal VEA1 so that after the first error signal VEA1 decreases to the threshold level, it remains at the threshold level. When the load on the power conversion system increases, the clamping module stops operating when the first error signal VEA1 output by the error amplification module rises and exceeds the threshold.

[0061] According to one embodiment, the control circuit 15 may further include a clamping module 157, whose first input and output are electrically connected to the positive input of the first comparison module 153, and whose second input is configured to receive a reference signal. The clamping module 157 is configured to determine whether to clamp the potential of the positive input of the first comparison module 153 to the reference signal based on a comparison result between the received first error signal VEA1 and the reference signal.

[0062] According to one embodiment, when the first error signal VEA1 is greater than the reference signal, the clamping module 157 ceases operation and does not affect the first error signal VEA1 received at the positive input of the first comparison module 153. When the first error signal VEA1 is less than the reference signal, the clamping module 157 outputs the reference signal to clamp the signal received at the positive input of the first comparison module 153, ensuring that the duty cycle of the controllable switch remains unchanged when the control circuit enters PFM mode, thereby ensuring that the power conversion system has a certain load capacity in PFM mode. The reference signal can also serve as a threshold for the control circuit to switch between PFM mode and PWM mode. Modifying the reference signal can adjust the threshold for switching between PFM and PWM modes.

[0063] According to one embodiment, the clamping module 157 includes a clamping unit 1571. A positive input terminal of the clamping unit 1571 is configured to receive a reference signal, a negative input terminal of the clamping unit 1571 is electrically connected to the error amplification module 152 and configured to receive the first error signal VEA1, and an output terminal of the clamping unit 1571 is electrically connected to a positive input terminal of the first comparison module 153. The clamping unit 1571 is configured to determine, based on the magnitude of the first error signal VEA1, whether to clamp the first error signal VEA1 received at the positive input terminal of the first comparison module 153 to the level of the reference signal or to stop the operation.

[0064] According to one embodiment, when the first error signal VEA1 is not higher than the reference signal, the clamping unit 1571 outputs the reference signal, so that the potential of the first error signal VEA1 received at the positive input terminal of the first comparison module 153 is clamped to the potential level of the reference signal. When the first error signal VAE1 is higher than the reference signal, the clamping module 157 stops operating and does not clamp the first error signal VEA1 received at the positive input terminal of the first comparison module 153.

[0065] According to one embodiment of the present application, the clamp module 157 may further include a reference switching unit 1573. In this case, the reference signal includes a first reference signal Vrefc1 and a second reference signal Vrefc2. The reference switching unit 1573 is configured to receive the fourth control signal BPFM_ST_P and the first reference signal Vrefc1 and the second reference signal Vrefc2, and select and output the first reference signal Vrefc1 or the second reference signal Vrefc2 based on the fourth control signal BPFM_ST_P.

[0066] According to one embodiment of the present application, when the fourth control signal BPFM_ST_P is invalid, the reference switching unit 1573 outputs the first reference signal Vrefc1 ; when the fourth control signal BPFM_ST_P is valid, the reference switching unit 1573 outputs the second reference signal Vrefc2 .

[0067] According to one embodiment, the control circuit 15 further includes a logic module 158 electrically connected to the first comparison module 153 and the PFM mode control module 156, configured to receive the output of the first comparison module 153 and the clock signal CLK_PFM output by the PFM mode control module 156, and generate a control signal for controlling the alternating conduction of the transistors in the controllable switch based on the output of the first comparison module 153 and the clock signal CLK_PFM output by the PFM mode control module 156.

[0068] According to one embodiment, the control circuit 15 may further include a pull-down module 159, which is configured to receive the first control signal CV_ST output by the second comparison module, the first error signal VEA1 output by the error amplification module 152, and the third control signal BPFM_STN output by the PFM mode detection module 155, and reduce the first error signal VEA1 by a fixed value based on the first control signal CV_ST and the third control signal BPFM_STN to obtain a pull-down signal VEAF, and the fixed value may be, for example, 1uA.

[0069] In one embodiment, in the control circuit, the PFM mode detection module 155 may also generate the second control signal BPFM_ST and the fourth control signal BPFM_ST_P based on the pull-down signal VEAF and the reference signal. In this case, the control circuit can smoothly transition from the PWM mode to the PFM mode, preventing the control circuit operating mode from switching back and forth between PWM and PFM.

[0070] In one embodiment, when both the first control signal CV_ST and the third control signal BPFM_STN are valid, the pull-down module 159 reduces the first error signal VEA1 by a fixed value to obtain the pull-down signal VEAF. In another embodiment, when the first control signal CV_ST and the third control signal BPFM_STN are not simultaneously valid, the pull-down module 159 does not reduce the first error signal VEA1, and the pull-down signal VEAF has a value similar to that of the first error signal VEA1.

[0071] In some embodiments of the present application, the value of the first reference signal Vrefc1 is higher than the value of the third reference voltage Vref3. For example, the first reference signal Vrefc1 may be 800 mV, and the third reference voltage Vref3 may be 600 mV. The value of the second reference signal Vrefc2 is lower than the third reference signal Vref3, for example, 500 mV.

[0072] According to one embodiment, the PFM mode detection module 155 and the clamping module 157 may share the same reference switching unit to obtain the reference signal.

[0073] According to one embodiment, the reference switching unit in the clamping module may have a similar structure to the reference switching unit in the PFM mode detection module.

[0074] Figure 2 FIG2 is a schematic diagram of the structure of a PFM mode detection module according to an embodiment. The PFM mode detection module may also have other structures, which are not limited in this application.

[0075] According to one embodiment, the PFM mode detection module 155 includes a reference switching unit 21 configured to receive the fourth control signal BPFM_ST_P and the fifth control signal BPFM_ST_N obtained by logically inverting the fourth control signal BPFM_ST_P, as well as the first reference signal Vrefc1 and the second reference signal Vrefc2.

[0076] According to one embodiment, the reference switching unit 21 may also have a different structure from the reference switching unit 1573 in the clamping module.

[0077] According to one embodiment, the reference switching unit 21 may include a transistor T1 and a transistor T2. The control electrode of the transistor T1 is configured to receive the fifth control signal BPFM_ST_N, the first electrode of the transistor T1 is configured to receive the first reference signal Vrefc1, and the second electrode of the transistor T1 is electrically connected to the second electrode of the transistor T2 and serves as the output terminal of the reference switching unit. The first electrode of the transistor T2 is configured to receive the second reference signal Vrefc2, and the control electrode of the transistor T2 is configured to receive the fourth control signal BPFM_ST_P.

[0078] According to one embodiment, the reference switching unit 21 includes a first branch configured to selectively output the first reference signal Vrefc1 based at least on receiving the fourth control signal BPFM_ST_P, and a second branch configured to selectively output the second reference signal Vrefc2 based at least on receiving the fifth control signal BPFM_ST_N.

[0079] According to one embodiment of the present application, when the fourth control signal BPFM_ST_P is valid and the fifth control signal BPFM_ST_N is invalid, the output of the reference switching unit may be the second reference signal Vrefc2. When the fourth control signal BPFM_ST_P is invalid, the output of the reference switching unit may be the first reference signal Vrefc1.

[0080] According to one embodiment, the PFM mode detection module 155 includes a comparator 22, a positive input terminal of which is configured to receive the first error signal VEA1, and a negative input terminal of which is electrically connected to the reference switching unit 21 and configured to receive the output of the reference switching unit 21. The comparator 22 is configured to compare the output of the reference switching unit 21 with the first error signal VEA1 to generate the second control signal BPFM_ST.

[0081] In one embodiment, to prevent the control circuit's operating mode from repeatedly switching between PWM and PFM due to the stability characteristics of the clamping unit 1571 when the power conversion system switches between heavy load and light load, the positive input of the comparator 22 can also be configured to receive the pull-down signal VEAF, which is the result of the first error signal VEA1 being reduced by a fixed value, to ensure that the control circuit smoothly switches from the PFM mode to the PWM mode.

[0082] According to one embodiment, the PFM mode detection module 155 further includes a logical NOT unit 23 electrically connected to the output terminal of the comparator 22 , configured to perform a logical inversion operation on the received second control signal BPFM_ST and generate a third control signal BPFM_STN.

[0083] According to one embodiment, the PFM mode detection module 155 further includes a pulse unit 24 electrically connected to the output terminal of the comparator 22 , configured to generate a pulse when a rising edge of the second control signal BPFM_ST arrives and output the pulse as the fourth control signal BPFM_ST_P.

[0084] According to one embodiment, the PFM mode detection module 155 further includes a logical NOT unit 25 electrically connected to the output terminal of the pulse unit 24 and configured to perform a logical inversion operation on the fourth control signal BPFM_ST_P and generate a fifth control signal BPFM_ST_N.

[0085] Figure 3FIG2 is a schematic diagram of the structure of a PFM mode control module according to an embodiment of the present application. The PFM mode control module may also have other structures, which are not limited in the present application.

[0086] According to one embodiment, the PFM mode control module 156 includes a logical NOT unit 31 and a logical NOR unit 32. The logical NOT unit 31 is configured to receive the first control signal CV_ST from the second comparison module and perform a logical NOT operation on it. A first input of the logical NOR unit 32 is electrically connected to the output of the logical NOT unit 31, and a second input of the logical NOR unit 32 is configured to receive the second control signal BPFM_ST from the PFM mode detection module. The logical NOR unit 32 receives the output of the logical NOT unit 31 and the control signal BFPM_ST, performs a logical NOR operation on the two, and generates a mask signal PFM_ST. The mask signal PFM_ST is used to determine whether to mask the clock signal CLK.

[0087] According to one embodiment, the PFM mode control module 156 further includes a logical NOT unit 33 and a logical NOR unit 34. The logical NOT unit 33 is configured to receive the clock signal CLK and perform a logical NOT operation. A first input of the logical NOR unit 34 is electrically connected to the output of the logical NOT unit 33, and a second input of the logical NOR unit 34 is configured to receive the mask signal PFM_ST. The logical NOR unit 34 is configured to receive the output of the logical NOT unit 33 and the output of the logical NOR unit 32, perform a logical NOR operation on the two, and generate the clock signal CLK_PFM required for the control circuit to operate in PFM mode.

[0088] According to one embodiment, when the shielding signal PFM_ST is high, the clock signal CLK is shielded and the clock signal CLK_PFM output by the PFM mode control module 156 is low. When the shielding signal PFM_ST is high, the PFM mode control module 156 outputs the clock signal CLK as the clock signal CLK_PFM.

[0089] Figure 4 FIG2 is a schematic diagram of the structure of a pull-down module according to an embodiment of the present application. The pull-down module may also have other structures, which are not limited in the present application.

[0090] According to one embodiment, pull-down module 159 includes a NAND unit 41 and a NOT unit 42 electrically connected in series. A first input terminal of NAND unit 41 is configured to receive a first control signal CV_ST, and a second input terminal of NAND unit 41 is configured to receive a third control signal BPFM_STN. NAND unit 41 is configured to perform a NAND operation on the two received signals. NOT unit 42 is configured to receive the output of NAND unit 41 and perform a NAND operation on the output.

[0091] According to one embodiment, the pull-down module 159 includes a resistor R43, a transistor T44, a current source 45, and capacitors C47 and C48. A first terminal of the resistor R43 is configured to receive the first error signal VEA1. The control electrode of the transistor T44 is electrically connected to the output terminal of the logical NOT unit 42. The current source 45 is electrically connected between the second terminal of the transistor T44 and ground, with its first terminal electrically connected to the second terminal of the resistor R43. Capacitor C47 is electrically connected between the first terminal of the transistor T44 and ground. A first plate of the capacitor C48 is electrically connected to the first terminal of the resistor R43 and configured to receive the first error signal VEA1. Its second terminal is electrically connected to ground. The pull-down module outputs the potential at the second terminal of the resistor R43 as the pull-down signal VEAF.

[0092] In one embodiment of the present application, when the first control signal CV_ST and the second control signal BPFM_ST are both valid, the transistor T44 is turned on, and the resistor R43 is used to reduce the first error signal VEA1 by a fixed value to obtain the pull-down signal VEAF.

[0093] Figure 5 Shown Figure 1 The working timing diagram of the control circuit shown. Figure 5 The embodiment shown includes two stages: light load and heavy load. When the power conversion system is in light load, the control circuit operates in PFM mode; when the power conversion system is in heavy load, the control circuit operates in PWM mode. Figure 1 The PFM mode detection module 155 can be Figure 2 As shown in the structure, the PFM mode control module 156 can be Figure 3 As shown in the structure, the pull-down module 159 can be Figure 4 The following describes the operation of the control circuit during the power conversion system load changes between light and heavy loads.

[0094] (1) Before time t1:

[0095] Before time t1, the power conversion system is heavily loaded. The feedback voltage Vfb of the power conversion system is lower than the first reference voltage Vref1. The first error signal VEA1 output by the error amplifier module is relatively high. Furthermore, the second error signal VEA2 is higher than the third reference voltage Vref3. Consequently, the first control signal CV_ST output by the second comparison module 154 is ineffective.

[0096] In this case, the values ​​of the first error signal VEA1 and the second error signal VEA2 are higher than the first reference signal Vrefc1 or the second reference signal Vrefc2 . The clamping module 157 stops working and does not clamp the first error signal VEA1 received by the positive input terminal of the first comparison module 153 .

[0097] The second control signal BPFM_ST output by the PFM mode detection module 155 is in the active state, indicating that the control circuit operates in the PWM mode. The third control signal BPFM_STN obtained by performing a logical inversion operation on the second control signal BPFM_ST is inactive, the fourth control signal BPFM_ST_P is inactive, and the fifth control signal BPFM_ST_N is active.

[0098] Based on the fifth control signal BPFM_ST_N in the active state, the reference switching unit 1573 outputs the first reference signal Vrefc1 .

[0099] Based on the first control signal CV_ST and the third control signal BPFM_STN in the failed state, the transistor T44 in the pull-down module 159 is turned off, and the value of the pull-down signal VEAF output by the pull-down module 159 is similar to the value of the first error signal VEA1.

[0100] Based on the disabled first control signal CV_ST and the enabled second control signal BPFM_ST, the masking signal PFM_ST is disabled, and the clock signal CLK_PFM output by the PFM mode control module 156 is the clock signal CLK. In this case, the controllable switches are controlled to alternately conduct and operate in CCM mode. The controllable switches output a continuous current IL, and the power conversion system provides a high current ILoad to the load.

[0101] Afterwards, the load of the power conversion system is switched from heavy load to light load.

[0102] (2) Time t1-t2:

[0103] As the load of the power conversion system decreases, the feedback voltage Vfb gradually increases and becomes higher than the first reference voltage Vref1 , and the first error signal VEA1 gradually decreases.

[0104] When the value of the first error signal VEA1 is not higher than the first reference signal Vrefc1 , the clamping module 157 outputs the first reference signal Vrefc1 to the positive input terminal of the first comparison module 153 to clamp the first error signal VEA1 received at the positive input terminal of the first comparison module 153 .

[0105] When the second error signal VEA2 decreases as the first error signal VEA1 decreases and is lower than the third reference voltage Vref3 , the first control signal CV_ST output by the second comparison module 154 jumps to active.

[0106] The pull-down module 159 receives a valid first control signal CV_ST and a disabled third control signal BPFM_STN, and outputs a pull-down signal VEAF which is the clamped first error signal VEA1 .

[0107] In the PFM mode detection module 155, the reference switching unit outputs a first reference signal Vrefc1 and compares it with the pull-down signal VEAF provided by the pull-down module 159, which is similar to the first error signal VEA1. The reference switching unit then outputs a second control signal BPFM_ST that transitions to an inactive state and / or a third control signal BPFM_STN that transitions to an active state, indicating that the control circuit has switched from PWM mode to PFM mode. The fourth control signal BPFM_ST_P output by the PFM mode detection module 155 remains inactive, and the fifth control signal BPFM_ST_N remains active. At this point, based on the active fifth control signal BPFM_ST_N, the reference switching unit 21 continues to output the first reference signal Vrefc1.

[0108] Afterwards, the first control signal CV_ST and the third control signal BPFM_STN received by the pull-down module are both in the valid state, and the transistor T44 is turned on, so that the clamped first error signal VEA1 is reduced by a fixed value to obtain the pull-down signal VEAF, and the pull-down signal VEAF is provided to the PFM mode detection module 155, so as to avoid the second control signal BPFM_ST generated by the PFM mode detection module 155 from erroneously jumping, causing the control circuit working mode to switch back and forth between PFM and PWM.

[0109] Based on the valid first control signal CV_ST and the invalid second control signal BPFM_ST, the masking signal PFM_ST generated by the PFM mode control module 156 becomes valid to mask the clock signal CLK, so that the output of the clock signal CLK_PFM is in the invalid state.

[0110] The logic module 158 controls the controllable switch to stop working and stop outputting the current IL based on the clock signal CLK_PFM in the failed state.

[0111] Subsequently, the feedback voltage Vfb surges to a high point and begins to gradually decrease, and the second error signal VEA2 gradually increases from a low point.

[0112] When the second error signal VEA2 is higher than the third reference voltage Vref3 , the first control signal CV_ST transitions to inactive.

[0113] In this case, the first error signal VEA1 is still lower than the first reference signal Vrefc1. The clamping module still clamps the first error signal VEA1 received by the positive input terminal of the first comparison module 153, and the signal output to the positive input terminal of the first comparison module 153 is still the first reference signal Vrefc1.

[0114] The pull-down module 159 stops reducing the first error signal VEA1 in response to the first control signal CV_ST transitioning to the disabled state.

[0115] The second control signal BPFM_ST output by the PFM mode detection module 155 is still in the inactive state, the third control signal BPFM_STN is still active, the fourth control signal BPFM_ST_P is still inactive, and the fifth control signal BPFM_ST_N is still active.

[0116] Based on the first control signal CV_ST and the second control signal BPFM_ST in the disabled state, the PFM mode control module 156 generates the PFM_ST signal and switches to disabled state and outputs the clock signal CLK. In this case, the control circuit controls the controllable switch to be in the working state, and the controllable switch outputs the current IL.

[0117] During this phase, the control circuit controls the controllable switch to operate intermittently. As the load decreases, the low point of the feedback voltage Vfb gradually rises, the time the controllable switch stops working becomes longer, and the current ILoad output by the power conversion system to the load gradually decreases to a lower value.

[0118] (3) Time t2-t3:

[0119] During this phase, the load on the power conversion system is still relatively light, and the control circuit controls the controllable switch to be in working state or to stop working according to the timing described in (2) above. The shielding signal PFM_ST generated by the control circuit lasts for a long time when in the effective state, so that the number of cycles of the clock signal CLK shielded by the control circuit is large. Accordingly, the controllable switch stops working for a long time. The controllable switch intermittently outputs the current IL, and the current ILoad output by the power conversion system to the load is maintained at a low value.

[0120] (4) Time t3-t4:

[0121] At this moment, the load on the power conversion system gradually increases from light to heavy. The highs of the feedback voltage Vfb1's fluctuations gradually decrease, while the lows of the second error signal VEA2's fluctuations gradually increase. The duration of the active state of the masking signal PFM_ST generated by the control circuit shortens, the number of cycles of the clock signal CLK masked by the control circuit decreases, and the time during which the controllable switch is inactive also becomes shorter and shorter. The current ILoad output by the power conversion system to the load gradually increases. The control circuit continues to operate in PFM mode.

[0122] Subsequently, when the feedback voltage Vfb1 is no longer higher than the first reference voltage Vref1 , the second error signal VEA2 is no longer lower than the third reference voltage Vref3 , and the first control signal CV_ST output by the second comparison module jumps to invalid.

[0123] In this case, when the first error signal VEA1 gradually increases to be higher than the first reference voltage Vrefc1 , the clamping module 157 stops working and stops clamping the first error signal VEA1 received by the positive input terminal of the first comparison module 153 .

[0124] The pull-down module 159 stops reducing the first error signal VEA1 in response to the first control signal CV_ST in the disabled state, and the pull-down signal VEAF has a value similar to the first error signal VEA1 .

[0125] As the first error signal VEA1 increases, the pull-down signal VEAF received by the PFM mode detection module 155 increases and becomes greater than the first reference signal Vrefc1. This causes the second control signal BPFM_ST output by the PFM mode detection module 155 to become active and the third control signal BPFM_STN to become inactive, indicating that the control circuit's operating mode has switched from PFM mode to PWM mode. In response to the rising edge of the second control signal BPFM_ST, the pulse unit 24 in the PFM mode detection module 155 outputs a pulse signal, which activates the fourth control signal BPFM_ST_P and deactivates the fifth control signal BPFM_ST_N, obtained by logically inverting the fourth control signal BPFM_ST_P.

[0126] When the fourth control signal BPFM_ST_P goes active, the reference switching unit selects and outputs a second reference signal Vrefc2, for example, which is lower than the first reference signal Vrefc1. The clamp module 157 compares the second reference signal Vrefc2 with the first error signal VEA1. Because the first error signal VEA1 is higher than the second reference signal Vrefc2, the clamp module 157 remains inactive.

[0127] In the PFM mode detection module 155, the reference switching unit selects the second reference signal Vrefc2 for output. The PFM mode detection module 155 compares the second reference signal Vrefc2 with the pull-down signal VEAF. Since the pull-down signal VEAF is higher than the second reference signal Vrefc2 at this point, the second control signal BPFM_ST remains active and the third control signal BPFM_STN remains inactive, causing the control circuit to remain in PWM mode. When the power conversion system load transitions from light to heavy load, the reference switching unit ensures that the control circuit switches to PWM mode quickly and smoothly, preventing the control circuit from repeatedly switching between PWM and PFM modes when the power conversion system output jitters.

[0128] Afterwards, the first control signal BPFM_ST remains active and the pulse unit 24 does not generate pulses. The fourth control signal BPFM_ST_P output by the pulse unit 24 is inactive and the fifth control signal BPFM_ST_N is active. The output of the reference switching circuit is switched to the first reference signal Vrefc1.

[0129] Based on the first control signal CV_ST in the disabled state and the second control signal BPFM_ST in the enabled state, the PFM_ST generated by the PFM mode control module 156 transitions to disabled, and the clock signal CLK is output as the clock signal CLK_PFM to the logic module 158. The control circuit operates in the PWM mode, controlling the controllable switches to alternately conduct and operate in the CCM mode. The controllable switches output a continuous current IL, and the current ILoad output by the power conversion system to the load gradually increases from a low value.

[0130] (5) After time t4:

[0131] The power conversion system is heavily loaded and operates in PWM mode. The feedback voltage Vfb of the power conversion system is lower than the first reference voltage Vref1. The first error signal VEA1 and the second error signal VEA2 output by the error amplifier module are relatively high. Furthermore, the value of the second error signal VEA2 is higher than the third reference voltage Vref3. The first control signal CV_ST output by the second comparison module 154 remains inactive. The clamp module 157 stops operating, the pull-down module 159 does not reduce the first error signal VEA1, the second control signal BPFM_ST output by the PFM mode detection module 155 remains active, and the PFM mode control module 156 outputs the original clock signal CLK to the logic module 158. The controllable switch outputs a continuous current IL, and the power conversion system supplies a high current ILoad to the load.

[0132] The present application also includes an electronic device comprising any of the control circuits described above.

[0133] The control circuit proposed in this application can quickly respond to load changes when the power conversion system changes between heavy load and light load, so that the power conversion system has higher output voltage accuracy under light load conditions, avoids frequent switching of the control circuit working mode during load changes, reduces the power consumption of the control circuit, and improves the reliability and stability of the power conversion system.

[0134] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A control circuit of a switching power supply, characterized in that: include: an error amplification module, configured to compare a feedback voltage obtained based on an output signal of the controllable switch with a first reference signal and generate a first error signal; It includes a mirror unit configured to copy or deform the first error signal to obtain a second error signal; a first comparison module, having a first input terminal electrically connected to the error amplification module and a second input terminal receiving a second reference signal, and configured to influence a duty cycle of the controllable switch during operation based on a comparison result of the first error signal or a variation thereof with the second reference signal; a second comparison module, a first input terminal of which is electrically connected to the error amplification module, configured to receive the second error signal, compare the second error signal with a third reference signal received at the second input terminal of the second comparison module, and generate a first control signal; a mode detection module, electrically connected to the error amplification module, and configured to generate, based on the first error signal and a reference signal, a second control signal indicating that the control circuit is in the PWM mode or the PFM mode and / or a third control signal obtained by performing a logical inversion operation thereof; A mode control module is electrically connected to the mode detection module and the second comparison module, and is configured to receive a clock signal and a first control signal and a second control signal, and determine whether to output the clock signal based on the first control signal and the second control signal; wherein, When the first control signal and the second control signal are valid, outputting the clock signal to control the controllable switch to be in an operating state; or, When the first control signal and the second control signal are not valid at the same time, the clock signal is shielded to control the controllable switch to stop working.

2. The control circuit according to claim 1, wherein: Also includes, The pull-down module is configured to receive the first control signal, the first error signal and the third control signal, and to obtain a pull-down signal by reducing the first error signal by a fixed value based on the first control signal and the third control signal.

3. The control circuit according to claim 2, wherein: The mode detection module also includes: a comparator, a first input terminal of which is configured to receive the reference signal, a second input terminal of which is configured to receive the first error signal, and configured to output a second control signal; a first logical NOT unit electrically connected to the output terminal of the comparator and configured to output the third control signal; a pulse unit, electrically connected to the output terminal of the comparator, configured to generate a pulse as a fourth control signal in response to a rising edge of the second control signal; The second logical NOT unit is electrically connected to the pulse unit and is configured to receive the fourth control signal and perform a logical inversion operation to obtain a fifth control signal.

4. The control circuit according to claim 3, wherein: in, The reference signal includes a first reference signal and a second reference signal; wherein the first reference signal is higher than the second reference signal; Wherein, the pattern detection module further includes: A first reference switching unit, whose output end is electrically connected to the second input end of the comparator, includes a first branch, which is configured to selectively output the first reference signal based on at least the received fourth control signal; the first reference switching unit also includes a second branch, which is configured to selectively output the second reference signal based on at least the fifth control signal.

5. The control circuit according to claim 4, wherein: in, The third reference signal is lower than the first reference signal and higher than the second reference signal.

6. The control circuit according to claim 5, wherein: Also includes, The clamping module has a first input terminal and an output terminal electrically connected to the first input terminal of the first comparison module, and is configured to determine whether to clamp the potential of the first input terminal of the first comparison module to the reference signal or stop working based on at least the size of the received first error signal.

7. The control circuit according to claim 6, wherein: in, The reference signal includes a first reference signal and a second reference signal; The clamping module further includes: a second reference switching unit, configured to select and output the first reference signal or the second reference signal based at least on the fourth control signal; as well as, The clamping unit has a first input terminal electrically connected to the output terminal of the second reference switching unit, a second input terminal configured to receive the first error signal, and an output terminal electrically connected to the first input terminal of the first comparison module.

8. The control circuit according to claim 3, wherein: The pull-down module includes: a logic NAND unit configured to perform a logic NAND operation on the received first control signal and the third control signal; a third logical NOT unit configured to receive the output of the logical NAND unit and perform a logical NOT operation; a first resistor and a transistor, wherein a first end of the first resistor is configured to receive the first error signal, and a second end of the first resistor is electrically connected to a first electrode of the transistor; The control electrode of the transistor is electrically connected to the output terminal of the first logical NOT unit; a current source electrically connected between the second electrode of the transistor and ground; a first capacitor electrically connected between the first electrode of the transistor and ground; The second capacitor is electrically connected between the first end of the first resistor and the ground.

9. The control circuit according to claim 4, wherein: in, The mode control module includes: a fourth logical NOT unit, configured to receive the first control signal and perform a logical inversion operation on the first control signal; a first logical NOT unit configured to receive the output of the fourth logical NOT unit and perform a logical NOT operation on the output and the second control signal to obtain a shielding signal; a fifth logical NOT unit, configured to receive the clock signal and perform a logical inversion operation on the clock signal; The second logical NOT unit is configured to receive the output of the fifth logical NOT unit and the shielding signal, and perform a logical NOT operation on the two.

10. An electronic device, characterized in that: The invention comprises the control circuit described in any one of claims 1 to 9.

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