Photovoltaic array line fault detection device based on injection signal

Abstract

The invention belongs to the technical field of detection devices, and particularly relates to a photovoltaic array line fault detection device based on injection signals. The invention provides a photovoltaic array line fault detection device based on injection signals. The device comprises a main control part, a power supply conversion part, a display part, a linear adjustable power supply part, a detection point signal acquisition part and an injection signal part, the device is characterized in that a signal transmission port of the main control part is respectively connected with a signal transmission port of the display part, a signal transmission port of the linear adjustable power supply part, a signal transmission port of the detection point signal acquisition part and a signal transmission port of the injection signal part; and an electric energy output port of the power supply conversion part is connected with a power supply port of the display part, a power supply port of the linear adjustable power supply part, a power supply port of the detection point signal acquisition part and a power supply port of the injection signal part respectively.

Description

Technical Field

[0001] The present invention belongs to the technical field of detection devices, and in particular relates to a photovoltaic array line fault detection device based on injection signals. Background Art

[0002] Existing photovoltaic array line fault detection devices are generally used to monitor issues such as arcing and grounding of photovoltaic panels in photovoltaic power plants. Arcing in photovoltaic power plants refers to the arcing phenomenon caused by high voltage or high current in the circuit when the current is disconnected or connected. This phenomenon can cause many hazards in electrical equipment. The following lists some specific hazards and precautions.

[0003] Hazards of arcing in photovoltaic power stations:

[0004] 1. Equipment damage

[0005] The high temperature generated by the arc can cause damage to the contact points or connection parts, such as burning of electrical components and aging or damage of insulation materials, thereby reducing the life of the equipment.

[0006] 2. Fire risk

[0007] Continuous or abnormal arcs may ignite surrounding combustibles, especially when the cable insulation or other materials are aged or damaged, which may cause a fire.

[0008] 3. Impact on system performance

[0009] Long-term or frequent arcing will cause the contact point resistance to increase, thereby affecting the overall electrical performance of the photovoltaic system and possibly resulting in a decrease in power generation efficiency.

[0010] 4. Interference with circuit operation

[0011] The instantaneous high temperature and high-frequency noise of the arc may affect the operation of other electrical equipment, causing system failure or even shutdown.

[0012] 5. Personal injury

[0013] The energy released by the arc may cause current shock or spark flying, causing electric shock or burns to workers.

[0014] 6. Environmental pollution

[0015] The high temperature generated by the arc may cause the insulation material to release harmful gases, especially in a closed environment, which may endanger the health of people.

[0016] The detection methods of the existing photovoltaic array line fault detection device include the following methods:

[0017] DC insulation testing technology: This technology measures the PV array's resistance to ground and leakage current to determine if a ground fault exists. The testing principle primarily involves insulation monitoring or leakage current sampling of the array circuit.

[0018] Data collection and analysis: Use the data collection box, current / voltage sensor, and communication module to upload the electrical parameters to the backend for analysis and judgment.

[0019] Passive detection and alarm system: When an abnormality is detected (such as sudden change in current, increased leakage), an alarm is issued through the alarm module.

[0020] The main problems existing in the prior art are:

[0021] Limited detection sensitivity: Traditional DC measurement methods have insufficient detection sensitivity for weak grounding and smaller arc faults, and are prone to missing small or instantaneous faults.

[0022] Slow response speed: It takes a certain amount of sampling time to compare and accumulate data before anomalies can be identified, and it is impossible to quickly detect and locate the fault point in real time.

[0023] Weak anti-interference ability: Affected by the complex electrical environment of photovoltaic power generation itself, it is easily interfered with, affecting the accuracy of the test results. Summary of the Invention

[0024] The present invention aims to solve the above problems and provides a hardware foundation for a photovoltaic array line fault detection device based on injection signals.

[0025] To achieve the above objectives, the present invention adopts the following technical solution, which includes a main control part, a power conversion part, a display part, a linear adjustable power supply part, a detection point signal acquisition part and an injection signal part, characterized in that the signal transmission port of the main control part is respectively connected to the signal transmission port of the display part, the signal transmission port of the linear adjustable power supply part, the signal transmission port of the detection point signal acquisition part, and the signal transmission port of the injection signal part, the power output port of the power conversion part is respectively connected to the power port of the display part, the power port of the linear adjustable power supply part, the power port of the detection point signal acquisition part, and the power port of the injection signal part, and the power adjustment port (i.e., VCC) of the injection signal part is connected to the regulated power output port (i.e., VCC) of the linear adjustable power supply part;

[0026] The main control part controls the injection signal part to inject a high-frequency signal into the photovoltaic array line. The detection point signal acquisition part monitors the changes of the injected high-frequency signal at the detection acquisition point and sends the detection value to the main control part. The main control part controls the amplitude of the injected high-frequency signal through the linear adjustable power supply part.

[0027] As a preferred solution, the main control part of the present invention includes an EP4CE15E22I7 chip U1, a W25Q128JVSIQTR chip U25 and an EPCS4SI8N chip U2, pin 12 of U1 is connected to FPGA-DCLK, pins 1, 2, 5 and 6 of U2 are respectively connected to FPGA-nCSO, FPGA-DATA0, FPGA-ASDO and FPGA-DCLK, pins 30 to 32 of U1 are respectively connected to M2, N2 and M3, pins 58 to 61, 64 to 69, 71 and 72 of U1 are respectively connected to G4, H11, H13, H12, G12, G11, G14, G13, E15, F14, F15 and G15, pin 13 of U1 is connected to FPGA-DATA0 through resistor R8, and pin 8 of U1 is respectively connected to M2, N2 and M3. The 77th, 80th, 83rd, and 87th pins of U1 are connected to N10, N11, N9, and P3 respectively. The 110th to 115th pins of U1 are connected to D12, C14, C13, B15, C15, and B14 respectively. The 98th to 101st, 103rd, and 104th pins of U1 are connected to E14, E13, E12, E11, F11, and D13 respectively. The 50th and 51st pins of U1 are connected to COM4_TXD and COM4_RXD respectively. The 132nd to 135th, 141st, and 142th pins of U1 are connected to PA4, PA6, PA5, PA7, B13, and A14 respectively. The 1st, 2nd, 5th, and 6th pins of U25 are connected to PA4, PA6, PA7, and PA5 respectively.

[0028] As another preferred embodiment, the power conversion part of the present invention includes an HLK-10M05C module POW3, an HLK-30M24C module POW1 and an HLK-30M12C module POW2. Pin 2 of POW3 is respectively connected to pin 2 of POW1, pin 2 of POW2 and one end of fuse F1. The other end of F1 is connected to pin 2 of connector P1. Pin 1 of P1 is respectively connected to pin 3 of POW1, pin 3 of POW2 and pin 3 of POW3. Pin 4 of POW3 is connected to +5V, pin 4 of POW1 is connected to +24V, and pin 4 of POW2 is connected to +12V.

[0029] As another preferred solution, the display part of the present invention adopts the DC32480S035 module CH1, and the 2nd and 3rd pins of CH1 are respectively connected to COM4_TXD and COM4_RXD.

[0030] As another preferred solution, the linear adjustable power supply part of the present invention includes an IRF250N tube Q1, the drain of Q1 is connected to +24V through an inductor L6, the gate of Q1 is connected to QG1, and the source of Q1 is connected to VCC;

[0031] Connect pin 2 of B1212S chip U18 to +12V, and pin 5 of U18 to +12V1;

[0032] Connect pin 2 of B1212S chip U22 to +12V, and pin 5 of U22 to +12V2;

[0033] Connect pin 2 of B1215S chip U24 to +12V, and pin 5 of U24 to +15V3;

[0034] Pins 3 and 4 of the GP8101S chip U21 are connected to B13 and +12V1 respectively. Pin 6 of U21 is connected to the cathode of diode D4 and pin 3 of the LM258 chip U19 through diode D2. Pin 2 of U19 is connected to DAC, pin 8 of U19 is connected to +15V3, and pin 1 of U19 is connected to QG1 through resistor R21.

[0035] Pins 3 and 4 of the GP8101S chip U23 are connected to A14 and +12V2 respectively, and pin 6 of U23 is connected to the anode of D4.

[0036] As another preferred solution, the detection point signal acquisition part of the present invention includes an ADS7042IDCUT chip U4, wherein pins 2, 3, and 4 of U4 are connected to G4, H11, and H13 respectively, and pins 2, 3, and 4 of the ADS7042IDCUT chip U6 are connected to H12, G12, and G11 respectively, and pins 2, 3, and 4 of the ADS7042IDCUT chip U7 are connected to G14, G13, and E15 respectively, and pins 2, 3, and 4 of the ADS7042IDCUT chip U8 are connected to F14, F15, and G15 respectively;

[0037] Pin 6 of U4 is connected to pin 6 of U6, pin 6 of U7, pin 6 of U8, and one end of resistor R11 respectively. Pin 5 of U4 is connected to pin 5 of U6, pin 5 of U7, and pin 5 of U8 respectively. The other end of R11 is connected to pin 1 of LM258 chip U5. Pin 3 of U5 is connected to the secondary side of transformer T1 through capacitor C79, resistor R22, capacitor C25, and inductor L2 in sequence; pin 3 of U5 is connected to GND and one end of resistor R23 through capacitor C80 respectively, and the other end of resistor R23 is connected to R22.

[0038] Secondly, the injection signal part of the present invention includes the LT1460-3.0 module U16, the 2nd pin of U16 is connected to RE-3V, the 1st pin of U16 is connected to +5V through the resistor R20 and the inductor L7 in sequence; +5V is connected to GND through the capacitor C53; RE-3V is connected to GND through the capacitor C54;

[0039] Pin 4 of the WH-L101-L module U3 is connected to P3, pins 19 to 21 of U3 are connected to M2, N2, and M3 respectively, and pins 2 and 3 of the connector J1 are connected to N2 and M3 respectively;

[0040] The Vin port of the AMS1117-3.3 module U12 is connected to +5V, and the Vout port of U12 is connected to +3.3V and one end of the inductor L5 respectively. The other end of L5 is connected to pin 2 of the AD9833 chip U11 through resistor R13. Pin 5 of U11 is connected to N12, and pins 6 to 8 of U11 are connected to N9, N11, and N10 respectively.

[0041] Pin 10 of U11 is connected to one end of capacitor C39, the other end of C39 is connected to pin 3 of LM258 chip U10, pin 2 of U10 is connected to DAC1, pin 1 of U10 is connected to one end of capacitor C37 and one end of resistor R14 respectively, the other end of R14 is connected to DAC1, the other end of C37 is connected to pin 3 of LM258 chip U14 and the primary side of transformer T2 respectively;

[0042] Pin 1 of U14 is connected to pin 6 of ADS7042IDCUT chip U13, pin 6 of ADS7042IDCUT chip U15, pin 6 of ADS7042IDCUT chip U17, and pin 6 of ADS7042IDCUT chip U20 through resistor R19. Pin 5 of U13 is connected to pin 5 of U15, pin 5 of U17, and pin 5 of U20 respectively. Pins 2, 3, and 4 of U13 are connected to E14, E13, and E12 respectively. Pins 2, 3, and 4 of U15 are connected to E11, F11, and D13 respectively. Pins 2, 3, and 4 of U17 are connected to D12, C14, and C13 respectively. Pins 2, 3, and 4 of U20 are connected to B15, C15, and B14 respectively.

[0043] In addition, the high-frequency signal injection point of the injection signal part of the present invention is set at the tail of the photovoltaic string array, and the detection and collection point of the detection point signal collection part is set at the head of the photovoltaic string array. The entire line is detected from the tail to the head of the photovoltaic string array to determine the signal change and the line condition.

[0044] The present invention has beneficial effects.

[0045] The main control part of the present invention controls the injection signal part to inject high-frequency signals into the photovoltaic array line, and the detection point signal acquisition part monitors the changes of the injected high-frequency signals at the detection acquisition points and sends the detection values to the main control part.

[0046] The power conversion part of the present invention provides the required voltage for each part of the device.

[0047] The display part of the present invention is used to display the input of relevant detection values and setting values.

[0048] The main control part of the present invention controls the amplitude of the injected high-frequency signal through the linear adjustable power supply part.

[0049] This invention uses active signal injection and detects the injected signal during injection (pins U13, U15, U17, and U20 are detection pins). At the acquisition point, the signal transmitted through the photovoltaic array circuit is collected and compared with the injected signal. Using active signal injection for detection can improve detection sensitivity.

[0050] The present invention injects signals in real time, detects signals in real time, performs online detection in real time, and outputs detection results in real time; the response speed is fast.

[0051] The detection device of the present invention transmits and collects signals by itself, and the parameters (amplitude, frequency, etc.) of the transmitted signals are controllable, and the device has a strong anti-interference capability.

[0052] From the above, it can be seen that the device of the present invention can reliably and efficiently detect photovoltaic array line faults. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The present invention is further described below with reference to the accompanying drawings and specific embodiments. The scope of protection of the present invention is not limited to the following description.

[0054] Figures 1 to 5 This is a schematic diagram of the main control circuit of the present invention.

[0055] Figure 6 This is a schematic diagram of the power conversion circuit of the present invention.

[0056] Figure 7 It is a schematic diagram of the circuit principle of the display part of the present invention.

[0057] Figure 8 This is a circuit schematic diagram of the linear adjustable power supply of the present invention.

[0058] Figure 9 This is a schematic diagram of the circuit principle of the detection point signal acquisition part of the present invention.

[0059] Figures 10 to 12 This is a schematic diagram of the signal injection circuit of the present invention. DETAILED DESCRIPTION

[0060] Judgment of amplitude attenuation:

[0061] When D<-5db (settable), it means the signal attenuation is too large. The smaller the arc value, the more serious the attenuation, and a record alarm will be issued.

[0062] Amplitude attenuation refers to the weakening of a signal's intensity during propagation. When amplitude attenuation is detected in a photovoltaic system, it indicates an abnormality in the circuit, such as an arc fault. The following is a correlation between amplitude attenuation and arc faults (this illustrates the working principle of the present invention: if an arc fault occurs, energy is lost after the arc is struck. A signal injected at T2, when detected at T1, will have attenuated signal amplitude, with the signal amplitude at the acquisition end being smaller than that at the injection end):

[0063] 1. Arc energy consumption

[0064] Energy conversion: Arc faults convert some electrical energy into heat and light, resulting in signal energy loss. At the moment of arcing, the current flowing through the arc zone becomes unstable, reducing the signal amplitude.

[0065] 2. Loss caused by reflection

[0066] Impedance mismatch: Arc faults often cause changes in the circuit's impedance. When a signal encounters an arc, it will experience reflections and losses due to impedance mismatch, causing signal amplitude attenuation.

[0067] Signal reflection: The local high impedance area formed by the arc will cause part of the injected signal to be reflected back instead of being fully transmitted to the detection point, thereby reducing the detected signal amplitude.

[0068] 3. Local heating and arc effect

[0069] Heat loss: The arc generates extremely high temperatures, which increases the resistance of the conductor and causes additional energy loss to the transmitted signal. In this case, the amplitude of the signal is weakened.

[0070] Arc instability: The generation of arcs causes instantaneous and violent current fluctuations, which make signal transmission unstable and eventually lead to amplitude attenuation.

[0071] The detection principle of the present invention can be compared to the detection of water pipe leakage. For a long water pipe used to transport water, the method of determining whether the water pipe is leaking is as follows:

[0072] 1. Inject water: Inject some water at a certain position of the water pipe (equivalent to the high-frequency signal injection point of the photovoltaic array circuit of the present invention) (equivalent to the high-frequency signal injection on the photovoltaic array circuit of the present invention). The high-frequency signal injection method is: the photovoltaic line passes through the ring-shaped current transformer T2, and the connection port of T2 (i.e. Figure 12 The high-frequency signal is injected into the photovoltaic cable through the mutual inductor T2.

[0073] 2. Observe the water flow: Observe the water flow at another location of the water pipe (equivalent to the detection and collection point of the present invention). If the water flow is normal and there is no leakage, the water will flow smoothly.

[0074] 3. Detecting water leaks: If there is a leak in the water pipe, water will flow out from the leak, causing the observed water flow change (equivalent to the signal of arcing or other faults in the photovoltaic array circuit). By observing the flow of water, it can be determined whether the water pipe has a leak (equivalent to the present invention judging whether there is a problem with the photovoltaic array circuit by monitoring the changes in the high-frequency signal injected at the detection and collection point). The signal collection method of the detection and collection point is as follows: the photovoltaic line passes through the ring-shaped current transformer T1, and the connection port of T1 (i.e. Figure 9 The upper end of T1 in the middle receives the collected signal.

[0075] A photovoltaic string array is a structure composed of dozens or even hundreds of photovoltaic arrays connected in series. The high-frequency signal injection point of the present invention can be set at the tail of the photovoltaic string array (the negative pole of the photovoltaic array), and the detection and collection point can be set at the head of the photovoltaic string array (the positive pole of the photovoltaic array). The entire line is detected from the tail to the head of the photovoltaic string array to determine signal changes and line conditions.

[0076] Normal situation: If the PV array is working properly, the signal will be stable, just like the smooth flow of water.

[0077] Abnormal conditions: If a fault such as arcing occurs in the photovoltaic array, just like a leaking water pipe, the signal will change, such as noise or unstable fluctuations, indicating that a problem has been detected.

[0078] The present invention utilizes an FPGA (U1) to configure an AD9833 (U11), with N10, N11, and N9 serving as control ports. N10 is an enable control, N11 is a clock signal, and N8 is a data signal. The FPGA configures U11 via the three ports N10, N11, and N9. The AD9833 (U11) generates a high-frequency sine wave (pin 10 of U11 outputs a high-frequency sine wave), which is amplified by U10 and then loaded onto the negative pole of a photovoltaic array via a mutual inductor T2. The distortion of the injected signal is detected at the positive pole of the photovoltaic array via a mutual inductor T1 to determine whether arcing or other problems exist in the entire circuit.

[0079] Both the injection port T2 and the receiving port T1 feature an array of four high-speed AD acquisition chips (ADS7042IDCUT). At the injection port (U13, U15, U17, and U20), these chips are used to detect the waveform of the injected signal. Using U13 as an example, the function of the signal transmission port is explained. E14, E13, and E12 are the signal transmission ports between U13 and U1. E14 is the clock signal sent from the FPGA (U1) to U13, E13 is the data signal sent from U13 to the FPGA (U1), and E12 is the chip select signal sent from the FPGA (U1) to U13. E13 detects the injected signal parameter values to ensure that the injected signal is injected according to the set parameters.

[0080] The acquisition end (U4, U6, U7, U8) is used to detect the waveform at that point (G4, H11, H13 are the ports for signal transmission between U4 and U1), and the waveforms of the injection and acquisition points are compared to determine whether arcing or other faults occur in the current array line.

[0081] U13, U15, U17, U20, U4, U6, U7, and U8 all use the ADS7042IDCUT chip and have the same working process, as described in the signal transmission port of U13 mentioned above.

[0082] Upon initial power-up (with no arcing faults present in the entire system), basic line characteristics are measured. After power-up, amplitude and phase calibration tests are performed. The injection end detects the injected signal value, and the acquisition end performs synchronous testing. The changes in the signal from the injected signal to the detection end under normal conditions, such as signal delay and amplitude, are determined throughout the entire line. The data is saved.

[0083] Phase delay determination

[0084] Phase delay calculation

[0085] After detecting the zero-crossing point of the injected signal, the internal timing circuit of the FPGA starts timing until a zero-crossing signal appears at the detection point, and the intermediate time is the delay time Δt.

[0086] formula:

[0087] Δt=T_d-T_i

[0088] T_d: The time when the detection signal reaches zero.

[0089] T_i: Time when the injected signal reaches zero.

[0090] φ=Δt×f×360°

[0091] f: signal frequency (Hz).

[0092] φ: Phase difference (degrees).

[0093] Under normal circumstances, the phase delay (φ) is within ±10° (can be set via touch screen CH1).

[0094] Alarm threshold: φ>10° or φ<-10° (can be set via touch screen CH1).

[0095] After the equipment is initially installed, and the system is ensured to be normal, the system records the current phase difference and amplitude attenuation, and sets an alarm when it exceeds ±% through the touch screen.

[0096] The value of φ can be used as an important indicator to determine whether an arc fault has occurred. It can be combined with amplitude attenuation to make a judgment and improve detection accuracy.

[0097] The study found that in the case of an arc fault, there are signal reflections and impedance mutations. The correlation between increased phase delay and arc faults is as follows:

[0098] 1. Impact of arc on signal propagation

[0099] Impedance discontinuity: Arc faults can cause sudden changes in local impedance within a circuit. When an arc occurs, a previously continuous circuit becomes unstable, causing changes in the speed and phase of signal propagation. The arcing also generates high-frequency noise, affecting the transmission time of normal signals.

[0100] Signal reflection: Arcing can cause signal reflection, forming a new signal path. This reflection causes a time delay between the signal received by the receiver and the signal transmitted, thereby increasing the phase difference.

[0101] 2. Changes in signal propagation paths

[0102] Signal path complexity: When an arc occurs, the signal no longer propagates along the original predetermined path. The arc causes uneven current distribution, and the signal propagation path becomes complex when passing through the arc, increasing the signal propagation time and thus the phase delay.

[0103] 3. Nonlinear characteristics of arc

[0104] Nonlinear impedance: Arcing is a nonlinear phenomenon, and its impedance is not constant. When current passes through an arc, it generates a transient high impedance. This nonlinear characteristic causes the signal's phase delay to vary, especially when the arc state is unstable, where the phase delay can fluctuate dramatically.

[0105] 4. Frequency characteristics of the signal

[0106] High-frequency signal sensitivity: Arcs generate high-frequency electromagnetic interference (EMI), which can affect the signal phase. When high-frequency signals pass through the arc area, the interference and reflections they encounter can cause increased phase delay.

[0107] As shown in the figure, the present invention includes a main control part, a power conversion part, a display part, a linear adjustable power supply part, a detection point signal acquisition part and an injection signal part. The signal transmission port of the main control part is respectively connected to the signal transmission port of the display part, the signal transmission port of the linear adjustable power supply part, the signal transmission port of the detection point signal acquisition part, and the signal transmission port of the injection signal part. The power output port of the power conversion part is respectively connected to the power port of the display part, the power port of the linear adjustable power supply part, the power port of the detection point signal acquisition part, and the power port of the injection signal part. The power adjustment port (i.e., VCC) of the injection signal part is connected to the adjustment power output port (i.e., VCC) of the linear adjustable power supply part.

[0108] The main control unit of the present invention controls the signal injection unit to inject a high-frequency signal into the photovoltaic array circuit. The detection point signal acquisition unit monitors changes in the injected high-frequency signal at the detection point and sends the detected value to the main control unit. Based on the detected value, the main control unit can determine whether the photovoltaic array circuit has arcing or other fault problems.

[0109] The power conversion part of the present invention provides the required voltage for each part of the device.

[0110] The display part of the present invention is used to display the input of relevant detection values and setting values.

[0111] The main control part of the present invention controls the amplitude of the injected high-frequency signal through the linear adjustable power supply part.

[0112] The main control part includes an EP4CE15E22I7 chip U1, a W25Q128JVSIQTR chip U25 and an EPCS4SI8N chip U2. Pin 12 of U1 is connected to FPGA-DCLK, and pins 1, 2, 5 and 6 of U2 are connected to FPGA-nCSO, FPGA-DATA0, FPGA-ASDO and FPGA-DCLK respectively. Pins 30 to 32 of U1 are connected to M2, N2 and M3 respectively. Pins 58 to 61, 64 to 69, 71 and 72 of U1 are connected to G4, H11, H13, H12, G12, G11, G14, G13, E15, F14, F15 and G15 respectively. Pin 13 of U1 is connected to FPGA-DATA0 through resistor R8, and pins 8 and 6 of U1 are connected to FPGA-nCSO and FPGA-ASDO are connected accordingly, U1's 77, 80, 83, and 87 pins are connected to N10, N11, N9, and P3 respectively, U1's 110-115 pins are connected to D12, C14, C13, B15, C15, and B14 respectively, U1's 98-101, 103, and 104 pins are connected to E14, E13, E12, E11, F11, and D13 respectively, U1's 50 and 51 pins are connected to COM4_TXD and COM4_RXD respectively, U1's 132-135, 141, and 142 pins are connected to PA4, PA6, PA5, PA7, B13, and A14 respectively; U25's 1, 2, 5, and 6 pins are connected to PA4, PA6, PA7, and PA5 respectively.

[0113] The U25 stores signal data from the PV array circuit under normal conditions, such as signal attenuation and signal limit delay time, to serve as a basis for judgment. This data is recorded when the system is first powered on after installation. Depending on the field conditions, the signal data under normal conditions will vary. For example, wire bends and wire length can affect phase delay and amplitude attenuation. Therefore, when installing the device, ensure that the system is in good condition. This good condition serves as the basis for judgment, and the difference between the two values serves as the alarm threshold.

[0114] The power conversion part includes an HLK-10M05C module POW3, an HLK-30M24C module POW1 and an HLK-30M12C module POW2. Pin 2 of POW3 is respectively connected to pin 2 of POW1, pin 2 of POW2 and one end of fuse F1. The other end of F1 is connected to pin 2 of connector P1. Pin 1 of P1 is respectively connected to pin 3 of POW1, pin 3 of POW2 and pin 3 of POW3. Pin 4 of POW3 is connected to +5V, pin 4 of POW1 is connected to +24V and pin 4 of POW2 is connected to +12V.

[0115] P1 is connected to the mains power supply.

[0116] By setting POW3, POW1, and POW2, the voltage required by each part of the device is converted.

[0117] The display uses the DC32480S035 module CH1, with pins 2 and 3 of CH1 connected to COM4_TXD and COM4_RXD respectively. CH1 can be used to display the current signal amplitude (including the injection signal amplitude and the detection signal amplitude of the detection point) and phase delay.

[0118] The linear adjustable power supply part includes an IRF250N tube Q1, the drain of Q1 is connected to +24V through an inductor L6, the gate of Q1 is connected to QG1, and the source of Q1 is connected to VCC;

[0119] Connect pin 2 of B1212S chip U18 to +12V, and pin 5 of U18 to +12V1;

[0120] Connect pin 2 of B1212S chip U22 to +12V, and pin 5 of U22 to +12V2;

[0121] Connect pin 2 of B1215S chip U24 to +12V, and pin 5 of U24 to +15V3;

[0122] Pins 3 and 4 of the GP8101S chip U21 are connected to B13 and +12V1 respectively. Pin 6 of U21 is connected to the cathode of diode D4 and pin 3 of the LM258 chip U19 through diode D2. Pin 2 of U19 is connected to DAC, pin 8 of U19 is connected to +15V3, and pin 1 of U19 is connected to QG1 through resistor R21.

[0123] Pins 3 and 4 of the GP8101S chip U23 are connected to A14 and +12V2 respectively, and pin 6 of U23 is connected to the anode of D4.

[0124] VCC is the amplitude of the high-frequency injection signal. The linear adjustable power supply is partially adjusted, resulting in the U10 power supply VCC being adjusted, resulting in the high-frequency injection signal amplitude being adjusted.

[0125] The linear adjustable power supply part uses two GP8101 chips (U21 and U23) with a range of 0V to 10V (0V to 10V refers to the output voltage range of the GP8101 chip). It is controlled by FPGA (U1) (B13 and A14 are digital control terminals) to output two sets of identical or different voltages. After superposition and amplification by U19, it controls Q1 and then controls the voltage value of VCC, completing digital control of analog output and adjusting the amplitude of the injected signal.

[0126] During initialization, if the PV array line attenuation is significant and the line is normal, the signal amplitude at the acquisition point will be relatively low (for example, the acquisition signal amplitude is 30% lower than the injection signal amplitude), falling below the device's sensitivity range. This allows the injection signal amplitude to be adjusted to make detection more pronounced at the acquisition point, improving acquisition accuracy. If the detection line is good, after the signal attenuation from the injection end to the acquisition end, it is best to maintain the acquisition end signal amplitude at 40% to 80% of the injection end.

[0127] FPGA (U1) controls U21 and U23 to output analog signals 0-10V. The output voltages of U21 and U23 are connected in series to obtain a 0-20V voltage. The 0-20V voltage is amplified by U19 to control the voltage of QG1, allowing Q1 to work in the variable resistance area, so that the VCC voltage can be adjusted by FPGA.

[0128] The FPGA (U1) controls the series connection of the outputs of U21 and U23, controlling the amplitude of the series connection and applying it to QG1 via U19. A higher value in the linear power supply QG1 increases the VCC value, enabling the FPGA (U1) to control the VCC voltage. The control signals B13 and A14 utilize SPI communication. U21 and U23 are DACs. Using SPI communication via the FPGA, U21 and U23 output a voltage of 0V to 10V.

[0129] The detection point signal acquisition part includes an ADS7042IDCUT chip U4, wherein pins 2, 3, and 4 of U4 are connected to G4, H11, and H13 respectively, pins 2, 3, and 4 of the ADS7042IDCUT chip U6 are connected to H12, G12, and G11 respectively, pins 2, 3, and 4 of the ADS7042IDCUT chip U7 are connected to G14, G13, and E15 respectively, and pins 2, 3, and 4 of the ADS7042IDCUT chip U8 are connected to F14, F15, and G15 respectively;

[0130] Pin 6 of U4 is connected to pin 6 of U6, pin 6 of U7, pin 6 of U8, and one end of resistor R11 respectively. Pin 5 of U4 is connected to pin 5 of U6, pin 5 of U7, and pin 5 of U8 respectively. The other end of R11 is connected to pin 1 of LM258 chip U5. Pin 3 of U5 is connected to the secondary side of transformer T1 through capacitor C79, resistor R22, capacitor C25, and inductor L2 in sequence; pin 3 of U5 is connected to GND and one end of resistor R23 through capacitor C80 respectively, and the other end of resistor R23 is connected to R22.

[0131] G4 is the clock signal sent from FPGA (U1) to U4, H11 is the data signal from U4 to FPGA (i.e., collected signal data), and H13 is the chip select signal from FPGA to U4.

[0132] The ADC acquisition speed of the chip ADS7042 is 1us; FPGA is used to control each ADS7042 chip (U4, U6, U7, U8) to perform time-sharing sequential acquisition:

[0133] Chip U4 sampling time point: 0 seconds;

[0134] Chip U6 sampling time point: 0.25us second;

[0135] Chip U7 sampling time point: 0.5us second;

[0136] Chip U8 sampling time point: 0.75us second.

[0137] Although the four low-speed AD chips (U4, U6, U7, and U8) have a relatively slow acquisition speed individually, they are controlled by FPGA, which allows the acquisition start time of each chip to be staggered. In this way, when originally only four sampling points could be obtained at the same time, by staggering the time, more sampling points can be obtained within the same total time. For example, a high-speed AD chip can collect 100 samples every 100 seconds and costs 100 yuan; while a low-speed chip can only collect 30 samples every 100 seconds and costs only 10 yuan. If we use four such low-speed chips and use FPGA to let them collect in sequence in an interleaved manner, we can achieve the effect of collecting 120 samples every 100 seconds, which far exceeds the cost of a single low-speed chip. At the same time, the total price (40 yuan) is significantly lower than the cost of using a high-speed chip (100 yuan). This not only improves the acquisition efficiency, but also greatly reduces the hardware investment, bringing higher cost-effectiveness to the project.

[0138] Using four ADS7042 chips, controlled by an FPGA, we achieve a 0.25µs acquisition speed. If all data is collected at the same time, the data will be the same. However, if the data is collected at different times, the acquisition frequency will increase.

[0139] The high input impedance of op amp U5, combined with the front-end resistors and capacitors (R22, C79, R23, and C80), forms a bandpass filter to filter the signal. The bandpass filter has a center frequency (f0) of 77.5kHz and a bandwidth (BW) of 280kHz. The injected signal frequency can be set to 77.5kHz, and the bandpass filter removes other high- and low-frequency signals.

[0140] The injection signal frequency can also be set to 77.5±30% kHz. A good balance is achieved between detection sensitivity, anti-interference ability, signal transmission and equipment cost. (1) It can resist interference and avoid power frequency and low-frequency noise. Low-frequency noise such as power grid power frequency (50Hz / 60Hz) and power supply ripple is widely present. High-frequency signals (such as 10kHz~10MHz) can be easily separated by filters to reduce the interference of environmental noise on the detection signal. (2) High-frequency bandpass filtering, narrowband demodulation and other technologies can be used to extract only the injected high-frequency signal, suppress low-frequency drift, DC offset and other noise, and improve the signal-to-noise ratio. (3) The surface state of the conductor is sensitive. When high-frequency signals propagate in the conductor, they will be concentrated on the surface of the conductor due to the skin effect (the skin depth decreases with increasing frequency). When the conductor has surface or local defects such as oxidation, corrosion, poor contact, and fracture, the transmission impedance of the high-frequency signal (especially the surface contact impedance) will change significantly, while the low-frequency signal is insensitive to surface defects due to its large skin depth (the signal penetrates into the conductor). For example, the skin depth of a 1kHz signal in a copper conductor is about 8.5mm, while at 1MHz it is only about 0.066mm. The high-frequency signal is completely dependent on the surface of the conductor for transmission. (4) Improve the sensitivity of defect detection. Local damage to the conductor (such as fine cracks, plating damage) has a more significant impact on the attenuation and reflection of the high-frequency signal, making it easier to identify faults through changes in signal amplitude and phase. (5) If the injection signal frequency is set too high, the back-end filter will have a large attenuation.

[0141] The injection signal part includes the LT1460-3.0 module U16, the 2nd pin of U16 is connected to RE-3V, the 1st pin of U16 is connected to +5V through the resistor R20 and the inductor L7 in sequence; +5V is connected to GND through the capacitor C53; RE-3V is connected to GND through the capacitor C54;

[0142] Pin 4 of the WH-L101-L module U3 is connected to P3, pins 19 to 21 of U3 are connected to M2, N2, and M3 respectively, and pins 2 and 3 of the connector J1 are connected to N2 and M3 respectively;

[0143] The Vin port of the AMS1117-3.3 module U12 is connected to +5V, and the Vout port of U12 is connected to +3.3V and one end of the inductor L5 respectively. The other end of L5 is connected to pin 2 of the AD9833 chip U11 through resistor R13. Pin 5 of U11 is connected to N12, and pins 6 to 8 of U11 are connected to N9, N11, and N10 respectively.

[0144] Pin 10 of U11 is connected to one end of capacitor C39, the other end of C39 is connected to pin 3 of LM258 chip U10, pin 2 of U10 is connected to DAC1, pin 1 of U10 is connected to one end of capacitor C37 and one end of resistor R14 respectively, the other end of R14 is connected to DAC1, the other end of C37 is connected to pin 3 of LM258 chip U14 and the primary side of transformer T2 respectively;

[0145] Pin 1 of U14 is connected to pin 6 of ADS7042IDCUT chip U13, pin 6 of ADS7042IDCUT chip U15, pin 6 of ADS7042IDCUT chip U17, and pin 6 of ADS7042IDCUT chip U20 through resistor R19. Pin 5 of U13 is connected to pin 5 of U15, pin 5 of U17, and pin 5 of U20 respectively. Pins 2, 3, and 4 of U13 are connected to E14, E13, and E12 respectively. Pins 2, 3, and 4 of U15 are connected to E11, F11, and D13 respectively. Pins 2, 3, and 4 of U17 are connected to D12, C14, and C13 respectively. Pins 2, 3, and 4 of U20 are connected to B15, C15, and B14 respectively.

[0146] M2 and N2 are the communication interfaces between FPAG (U1) and U3, M3 is the factory reset pin of U3, and P3 is the restart control pin of U3.

[0147] Connector J1 is used for device debugging.

[0148] U3 is a wireless communication module that can generate wireless alarms when arcing or other problems are detected. When arcing or broken wires are detected, the FPGA sends an alarm message to the remote host.

[0149] L7 and C53 form a sudden interference signal filtering circuit. When a sudden interference signal arrives, L7 becomes a high-impedance branch and C53 becomes a low-impedance pass-through branch. Most of the interference signal is shunted by C53, and the remaining small amount of interference signal is attenuated by L7.

[0150] C54 and R20 form an RC low-pass filter circuit to filter out high-frequency interference signals, with a cut-off frequency of 1694Hz.

[0151] It can be understood that the above specific description of the present invention is only used to illustrate the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that the present invention can still be modified or replaced by equivalents to achieve the same technical effects; as long as the use requirements are met, they are within the scope of protection of the present invention.

Claims

1. A photovoltaic array line fault detection device based on injection signal, comprising a main control part, a power conversion part, a display part, a linear adjustable power supply part, a detection point signal acquisition part and an injection signal part, characterized in that The signal transmission port of the main control part is respectively connected to the signal transmission port of the display part, the signal transmission port of the linear adjustable power supply part, the signal transmission port of the detection point signal acquisition part, and the signal transmission port of the injection signal part; the power output port of the power conversion part is respectively connected to the power port of the display part, the power port of the linear adjustable power supply part, the power port of the detection point signal acquisition part, and the power port of the injection signal part; the power regulation port of the injection signal part is connected to the regulated power output port of the linear adjustable power supply part; The main control part controls the injection signal part to inject a high-frequency signal into the photovoltaic array line. The detection point signal acquisition part monitors the changes of the injected high-frequency signal at the detection acquisition point and sends the detection value to the main control part. The main control part controls the amplitude of the injected high-frequency signal through the linear adjustable power supply part.

2. A photovoltaic array line fault detection device based on injection signal according to claim 1, characterized in that The main control part includes an EP4CE15E22I7 chip U1, a W25Q128JVSIQTR chip U25 and an EPCS4SI8N chip U2. Pin 12 of U1 is connected to FPGA-DCLK, and pins 1, 2, 5 and 6 of U2 are connected to FPGA-nCSO, FPGA-DATA0, FPGA-ASDO and FPGA-DCLK respectively. Pins 30 to 32 of U1 are connected to M2, N2 and M3 respectively. Pins 58 to 61, 64 to 69, 71 and 72 of U1 are connected to G4, H11, H13, H12, G12, G11, G14, G13, E15, F14, F15 and G15 respectively. Pin 13 of U1 is connected to FPGA-DATA0 through resistor R8, and pins 8 and 6 of U1 are connected to FPGA-nCSO and FPGA-ASDO are connected accordingly, U1's 77, 80, 83, and 87 pins are connected to N10, N11, N9, and P3 respectively, U1's 110-115 pins are connected to D12, C14, C13, B15, C15, and B14 respectively, U1's 98-101, 103, and 104 pins are connected to E14, E13, E12, E11, F11, and D13 respectively, U1's 50 and 51 pins are connected to COM4_TXD and COM4_RXD respectively, U1's 132-135, 141, and 142 pins are connected to PA4, PA6, PA5, PA7, B13, and A14 respectively; U25's 1, 2, 5, and 6 pins are connected to PA4, PA6, PA7, and PA5 respectively.

3. A photovoltaic array line fault detection device based on injection signal according to claim 1, characterized in that The power conversion part includes an HLK-10M05C module POW3, an HLK-30M24C module POW1 and an HLK-30M12C module POW2. Pin 2 of POW3 is respectively connected to pin 2 of POW1, pin 2 of POW2 and one end of fuse F1. The other end of F1 is connected to pin 2 of connector P1. Pin 1 of P1 is respectively connected to pin 3 of POW1, pin 3 of POW2 and pin 3 of POW3. Pin 4 of POW3 is connected to +5V, pin 4 of POW1 is connected to +24V and pin 4 of POW2 is connected to +12V.

4. A photovoltaic array line fault detection device based on injection signal according to claim 1, characterized in that The display part uses the DC32480S035 module CH1, and the 2nd and 3rd pins of CH1 are connected to COM4_TXD and COM4_RXD respectively.

5. A photovoltaic array line fault detection device based on injection signal according to claim 1, characterized in that The linear adjustable power supply part includes an IRF250N tube Q1, the drain of Q1 is connected to +24V through an inductor L6, the gate of Q1 is connected to QG1, and the source of Q1 is connected to VCC; Connect pin 2 of B1212S chip U18 to +12V, and pin 5 of U18 to +12V1; Connect pin 2 of B1212S chip U22 to +12V, and pin 5 of U22 to +12V2; Connect pin 2 of U24 of B1215S chip to +12V, and pin 5 of U24 to +15V3; Pins 3 and 4 of the GP8101S chip U21 are connected to B13 and +12V1 respectively. Pin 6 of U21 is connected to the cathode of diode D4 and pin 3 of the LM258 chip U19 through diode D2. Pin 2 of U19 is connected to DAC, pin 8 of U19 is connected to +15V3, and pin 1 of U19 is connected to QG1 through resistor R21. Pins 3 and 4 of the GP8101S chip U23 are connected to A14 and +12V2 respectively, and pin 6 of U23 is connected to the anode of D4.

6. A photovoltaic array line fault detection device based on injection signal according to claim 1, characterized in that The detection point signal acquisition part includes an ADS7042IDCUT chip U4, wherein pins 2, 3, and 4 of U4 are connected to G4, H11, and H13 respectively, pins 2, 3, and 4 of the ADS7042IDCUT chip U6 are connected to H12, G12, and G11 respectively, pins 2, 3, and 4 of the ADS7042IDCUT chip U7 are connected to G14, G13, and E15 respectively, and pins 2, 3, and 4 of the ADS7042IDCUT chip U8 are connected to F14, F15, and G15 respectively; Pin 6 of U4 is connected to pin 6 of U6, pin 6 of U7, pin 6 of U8, and one end of resistor R11 respectively. Pin 5 of U4 is connected to pin 5 of U6, pin 5 of U7, and pin 5 of U8 respectively. The other end of R11 is connected to pin 1 of LM258 chip U5. Pin 3 of U5 is connected to the secondary side of transformer T1 through capacitor C79, resistor R22, capacitor C25, and inductor L2 in sequence; pin 3 of U5 is connected to GND and one end of resistor R23 through capacitor C80 respectively, and the other end of resistor R23 is connected to R22.

7. A photovoltaic array line fault detection device based on injection signal according to claim 1, characterized in that The injection signal part includes the LT1460-3.0 module U16, the 2nd pin of U16 is connected to RE-3V, the 1st pin of U16 is connected to +5V through the resistor R20 and the inductor L7 in sequence; +5V is connected to GND through the capacitor C53; RE-3V is connected to GND through the capacitor C54; Pin 4 of the WH-L101-L module U3 is connected to P3, pins 19 to 21 of U3 are connected to M2, N2, and M3 respectively, and pins 2 and 3 of the connector J1 are connected to N2 and M3 respectively; The Vin port of the AMS1117-3.3 module U12 is connected to +5V, and the Vout port of U12 is connected to +3.3V and one end of the inductor L5 respectively. The other end of L5 is connected to pin 2 of the AD9833 chip U11 through resistor R13. Pin 5 of U11 is connected to N12, and pins 6 to 8 of U11 are connected to N9, N11, and N10 respectively. Pin 10 of U11 is connected to one end of capacitor C39, the other end of C39 is connected to pin 3 of LM258 chip U10, pin 2 of U10 is connected to DAC1, pin 1 of U10 is connected to one end of capacitor C37 and one end of resistor R14 respectively, the other end of R14 is connected to DAC1, the other end of C37 is connected to pin 3 of LM258 chip U14 and the primary side of transformer T2 respectively; Pin 1 of U14 is connected to pin 6 of ADS7042IDCUT chip U13, pin 6 of ADS7042IDCUT chip U15, pin 6 of ADS7042IDCUT chip U17, and pin 6 of ADS7042IDCUT chip U20 through resistor R19. Pin 5 of U13 is connected to pin 5 of U15, pin 5 of U17, and pin 5 of U20 respectively. Pins 2, 3, and 4 of U13 are connected to E14, E13, and E12 respectively. Pins 2, 3, and 4 of U15 are connected to E11, F11, and D13 respectively. Pins 2, 3, and 4 of U17 are connected to D12, C14, and C13 respectively. Pins 2, 3, and 4 of U20 are connected to B15, C15, and B14 respectively.

8. A photovoltaic array line fault detection device based on injection signal according to claim 1, characterized in that The high-frequency signal injection point of the injection signal part is set at the tail of the photovoltaic string array, and the detection and collection point of the detection point signal collection part is set at the head of the photovoltaic string array. The entire line is detected from the tail to the head of the photovoltaic string array to determine the signal change and the line condition.

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