Fast-locking low-jitter sub-sampling phase-locked loop

Abstract

The invention discloses a fast-locking low-jitter sub-sampling phase-locked loop structure. The sub-sampling phase-locked loop comprises a sub-sampling Bang-Bang phase discrimination circuit, a self-adaptive variable step size digital filter circuit, a delta sigma digital-to-analog conversion circuit and an oscillator circuit. The sub-sampling Bang-Bang phase discrimination circuit generates a phase discrimination output digital control signal according to an input reference signal and a feedback oscillator signal phase error, the adaptive variable step size digital filter circuit adaptively adjusts a filtering gain according to the phase discrimination output digital control signal, and the output of the filter circuit realizes digital-analog conversion after oversampling modulation. And the output analog signal controls the voltage-controlled oscillator to realize rapid low-jitter phase locking of the output and the reference signal.

Description

Technical Field

[0001] The present invention relates to a digital phase-locked loop circuit, belongs to the technical field of integrated circuits, and particularly relates to a fast-locking low-jitter sub-sampling phase-locked loop circuit. Technical Background

[0002] With the rapid development of communication technology, the demand for high-frequency, low-jitter clock signals is growing. Phase-locked loops (PLLs), as a crucial clock generation and recovery circuit, have a direct impact on the performance of the entire communication system. While traditional analog PLLs offer excellent noise performance, they suffer from drawbacks such as large size, high power consumption, and difficulty integrating. Digital phase-locked loops (DPLLs), however, have become a research hotspot due to their advantages such as ease of process migration and integration. However, traditional DPLs also have some limitations. For example, their jitter performance is limited by the trade-off between quantization noise and loop bandwidth. To reduce jitter, either quantization noise or loop bandwidth must be reduced, but this results in longer lock times or reduced stability. Furthermore, the loop bandwidth of traditional DPLs is typically fixed and cannot be dynamically adjusted based on input signal variations, limiting their application in complex environments. Summary of the Invention

[0003] The purpose of the present invention is to overcome the above-mentioned shortcomings and provide a fast locking, low-jitter sub-sampling phase-locked loop to solve the problems of traditional digital sub-sampling phase-locked loops with fixed loop bandwidth, long phase-locked time and large output jitter, thereby realizing a fast locking, low-jitter digital sub-sampling phase-locked loop.

[0004] The technical solution of the present invention is:

[0005] A fast-locking, low-jitter sub-sampling phase-locked loop circuit comprises a sub-sampling Bang-Bang phase-locked loop circuit, an automatic frequency control circuit, an adaptive variable-step-size digital filter circuit, a Δ∑ digital-to-analog conversion circuit, and a voltage-controlled oscillator circuit. The frequency-locked loop is used to maintain the frequency relationship between a feedback oscillator signal and an input reference signal through closed-loop control. The phase-locked loop detects the phase relationship between the input reference signal and the feedback oscillator signal through a phase error filtering control process and method, generates corresponding lead-lag signals and gain signals, and controls the step size selection of the adaptive variable-step-size digital filter circuit, which is converted into a control signal for the voltage-controlled oscillator through the Δ∑ digital-to-analog conversion circuit.

[0006] The sub-sampling Bang-Bang phase detection circuit includes a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a first delay unit τ1, a second delay unit τ2, a first NOR logic gate NOR, a first AND logic gate AND, and a first OR logic gate OR; the input reference signal is used to sub-sample the feedback oscillator signal through the first D flip-flop DFF1, and the output signal SIGN is connected to the inputs of the first NOR logic gate NOR and the first AND logic gate AND; the input reference signal is used to sub-sample the feedback oscillator signal through the second D flip-flop DFF2 through the first delay unit τ1, and the output signal is connected to the input of the first NOR logic gate NOR; the input reference signal is used to sub-sample the feedback oscillator signal after passing through the second delay unit τ2 through the third D flip-flop DFF3, and the output signal is connected to the input of the first AND logic gate AND; the outputs of the first NOR logic gate NOR and the first AND logic gate AND are simultaneously connected to the input of the first OR logic gate OR; the output of the first D flip-flop DFF1 and the output of the first OR logic gate OR are connected to the input of the adaptive variable step-size digital filter circuit.

[0007] Furthermore, the adaptive variable step-size digital filter circuit includes a first phase error integrator circuit, a first phase decision circuit PD, and a first digital filter circuit including a proportional path and an integral path; the output end of the sub-sampling Bang-Bang phase detection circuit is connected to the input end of the first phase error integrator circuit, the output end of the first phase error integrator circuit is connected to the input end of the proportional path and the integral path of the first digital filter circuit, the output end of the sub-sampling Bang-Bang phase detection circuit is connected to the input end of the first phase decision circuit PD, the output end of the first phase decision circuit PD is connected to the input end of the first phase error integrator circuit and the proportional path and the integral path of the first digital filter circuit, and the proportional path output end and the integral path output end of the first digital filter circuit are connected to the input end of the ΔΣ digital-to-analog conversion circuit.

[0008] Furthermore, the phase error filtering control process and method include a phase error integrator circuit that determines the current phase difference state according to the output of the sub-sampling Bang-Bang phase detection circuit, and adaptively adjusts K according to the phase difference threshold. B The value is set, and the filter gain is changed to gradually reduce the phase error in the next cycle, so as to realize the phase lock of the phase-locked loop. The phase error filter control process is as follows: when the system starts, the loop gain is initialized to make the gain state M=1, the statistical expectation of the phase error C=0, and the phase error is judged. Is it greater than the threshold Δt (where Δt is the sum of the DFF setup and hold time td and the delay τ), if the phase error If the value is greater than the set threshold Δt, the loop gain will increase and the output M = 1. Otherwise, the phase error will be If the threshold Δt is not exceeded, the output M=0 indicates that the gain at that time is the expected gain value. The phase decision module determines whether the system gain meets the locking requirement at this time. If so, the statistical expectation C=1 of the gain output phase error is minimized and the loop is determined to be locked. If the phase decision module determines that the system gain does not meet the locking requirement at this time, the loop gain is increased. At this time, M=1 and C=0 continue to optimize the loop gain.

[0009] Furthermore, the Δ∑ digital-to-analog conversion circuit includes a first digital interpolation filter circuit, a first noise shaping loop, a first analog-to-digital conversion circuit and a first analog filter circuit; the input end of the first digital interpolation filter circuit is connected to the output end of the adaptive variable step-size digital filter circuit and the input reference signal, and the output end of the first digital interpolation filter circuit is connected to the input end of the first noise shaping loop; the output end of the first digital interpolation filter circuit is connected to the input end of the first noise shaping loop; the input end of the first analog filter circuit is connected to the output end of the first analog-to-digital conversion circuit, and the output control voltage Vtune controls the oscillator tuning.

[0010] Furthermore, the voltage-controlled oscillator circuit includes a 5-bit switched capacitor array unit, a first NMOS capacitor tube C1, a second NMOS capacitor tube C2, a first variable capacitor tube C3, a second variable capacitor tube C4, a first inductor coil L and two pairs of cross-coupling pairs; it is used to receive the voltage control signal, the control code of the automatic frequency control circuit and the input DC bias, and output an oscillation frequency signal.

[0011] Furthermore, the 5-bit switched capacitor array unit includes a first NMOS transistor M0, a first resistor R0, a second resistor R1, a third resistor R2, a first NMOS capacitor CS1, a second NMOS capacitor CS2, and an inverter; the gate of the first NMOS transistor M0 receives the output five-bit control code S<4:0> of the automatic frequency control circuit, and the source of the first NMOS transistor M0 is connected to the drain of the first NMOS transistor M0 through the second resistor R1 and the third resistor R2 connected in series. At the same time, the source outputs an oscillation voltage OUTN through the first NMOS capacitor CS1, and the drain outputs an oscillation voltage OUTP through the second NMOS capacitor CS2. The output control code S<4:0> of the automatic frequency control circuit is also connected to the connection point of the second resistor R1 and the third resistor R2 through the inverter;

[0012] Furthermore, the cross-coupling pair includes a first POMS transistor M1, a second POMS transistor M2, a first NMOS transistor M3, and a second NMOS transistor M4; the gate of the first POMS transistor M1 is connected to the drain of the second POMS transistor M2 and is also connected to the output end of the oscillation voltage OUTP, the gate of the second POMS transistor M2 is connected to the drain of the first POMS transistor M1 and is also connected to the output end of the oscillation voltage OUTN, and the source terminals of the first POMS transistor M1 and the second POMS transistor M2 are simultaneously connected to the power supply VCC; one end of the inductor is connected to the output end of the oscillation voltage OUTN, and the other end is connected to the oscillation voltage OUTN. The output end of the oscillation voltage OUTP; the first NMOS capacitor C1, the first variable capacitor C3, the second variable capacitor C4, and the second NMOS capacitor C2 are connected in series, wherein the other end of the first NMOS capacitor C1 is connected to the output end of the oscillation voltage OUTN, wherein the other end of the second NMOS capacitor C2 is connected to the output end of the oscillation voltage OUTP, and the voltage control signal Vtune is connected between the first variable capacitor C3 and the second variable capacitor C4 to control the capacitance of the variable capacitor; the input DC bias is connected to the source end of the first NMOS transistor M3 and the second NMOS transistor M4.

[0013] Compared with the prior art, the present invention has the following advantages:

[0014] The present invention realizes a fast-locking, low-jitter digital sub-sampling phase-locked loop. Compared with conventional solutions, the present invention utilizes a phase error control technology composed of a sub-sampling Bang-Bang phase detector circuit and an adaptive variable-step-size digital filter circuit to greatly reduce loop locking time and jitter. Moreover, because the phase error control technology is insensitive to changes in PVT, this characteristic significantly reduces the quantization error caused by the phase detector, thereby realizing a fast-locking, low-jitter digital sub-sampling phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 This is a fast locking low jitter sub-sampling phase-locked loop circuit diagram of the present invention;

[0017] Figure 2 This is a VCO circuit diagram of a fast-locking low-jitter sub-sampling phase-locked loop of the present invention;

[0018] Figure 3The present invention provides a phase error filtering control process and method for a fast-locking low-jitter sub-sampling phase-locked loop circuit;

[0019] Figure 4 This is a schematic diagram of output jitter of a fast-locking, low-jitter sub-sampling phase-locked loop circuit of the present invention. DETAILED DESCRIPTION

[0020] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Examples of these embodiments are illustrated in the accompanying drawings. The embodiments of the present invention shown in and described with reference to the accompanying drawings are merely exemplary and are not intended to limit the scope of the present invention.

[0021] In addition, it should be noted that in order to avoid obscuring the present invention due to unnecessary details, the accompanying drawings only show structures and / or processing steps that are closely related to the solutions according to the present invention, while other details that are not closely related to the present invention are omitted.

[0022] Furthermore, in the description of the present invention, terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" indicate positions or relationships based on those shown in the accompanying drawings. These terms are used solely to facilitate and simplify the description of the present invention and are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0024] like Figure 1 As shown, a fast locking low-jitter sub-sampling phase-locked loop circuit mainly includes: the sub-sampling phase-locked loop includes a frequency-locked loop and a phase-locked loop, and the phase-locked loop includes a sub-sampling Bang-Bang phase detection circuit, an automatic frequency control circuit, an adaptive variable step-size digital filter circuit, a Δ∑ digital-to-analog conversion circuit and a voltage-controlled oscillator circuit.

[0025] The sub-sampling Bang-Bang phase detection circuit includes a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a first delay unit τ1, a second delay unit τ2, a first NOR logic gate NOR, a first AND logic gate AND, and a first OR logic gate OR; the input reference signal is used to sub-sample the feedback oscillator signal through the first D flip-flop DFF1, and the output signal SIGN is connected to the inputs of the first NOR logic gate NOR and the first AND logic gate AND; the input reference signal is used to sub-sample the feedback oscillator signal through the second D flip-flop DFF2 through the first delay unit τ1, and the output signal is connected to the input of the first NOR logic gate NOR; the input reference signal is used to sub-sample the feedback oscillator signal after passing through the second delay unit τ2 through the third D flip-flop DFF3, and the output signal is connected to the input of the first AND logic gate AND; the outputs of the first NOR logic gate NOR and the first AND logic gate AND are simultaneously connected to the input of the first OR logic gate OR; the output of the first D flip-flop DFF1 and the output of the first OR logic gate OR are connected to the input of the adaptive variable step-size digital filter circuit.

[0026] Specifically, the adaptive variable step-size digital filter circuit includes a first phase error integrator circuit, a first phase decision circuit PD, and a first digital filter circuit including a proportional path and an integral path; the output end of the sub-sampling Bang-Bang phase detection circuit is connected to the input end of the first phase error integrator circuit, the output end of the first phase error integrator circuit is connected to the input end of the proportional path and the integral path of the first digital filter circuit, the output end of the sub-sampling Bang-Bang phase detection circuit is connected to the input end of the first phase decision circuit PD, the output end of the first phase decision circuit PD is connected to the input end of the first phase error integrator circuit and the proportional path and the integral path of the first digital filter circuit, and the proportional path output end and the integral path output end of the first digital filter circuit are connected to the input end of the ΔΣ digital-to-analog conversion circuit.

[0027] Specifically, the phase error filtering control process and method include a phase error integrator that determines the current phase difference state according to the output of the sub-sampling Bang-Bang phase detection circuit, and adaptively adjusts K according to the phase difference threshold. B The phase error filter control process is as follows: when the system starts, the loop gain is initialized to make the gain state M=1, the statistical expectation of the phase error C=0, and the phase error is judged. Is it greater than the threshold Δt (where Δt is the sum of the DFF setup and hold time td and the delay τ), if the phase error If the value is greater than the set threshold Δt, the loop gain will increase and the output M = 1. Otherwise, the phase error will be If the threshold Δt is not exceeded, the output M=0 indicates that the gain at that time is the expected gain value. The phase decision module determines whether the system gain meets the locking requirement at this time. If so, the statistical expectation C=1 of the gain output phase error is minimized and the loop is determined to be locked. If the phase decision module determines that the system gain does not meet the locking requirement at this time, the loop gain is increased. At this time, M=1 and C=0 continue to optimize the loop gain.

[0028] Specifically, the Δ∑ digital-to-analog conversion circuit includes a first digital interpolation filter circuit, a first noise shaping loop, a first analog-to-digital conversion circuit and a first analog filter circuit; the input end of the first digital interpolation filter circuit is connected to the output end of the adaptive variable step-size digital filter circuit and the input reference signal, and the output end of the first digital interpolation filter circuit is connected to the input end of the first noise shaping loop; the output end of the first digital interpolation filter circuit is connected to the input end of the first noise shaping loop; the input end of the first analog filter circuit is connected to the output end of the first analog-to-digital conversion circuit, and the output control voltage Vtune controls the oscillator tuning.

[0029] Specifically, the voltage-controlled oscillator circuit includes a 5-bit switched capacitor array unit, a first NMOS capacitor tube C1, a second NMOS capacitor tube C2, a first variable capacitor tube C3, a first variable capacitor tube C4, a first inductor coil L and two pairs of cross-coupling pairs; it is used to receive the voltage control signal, the control code of the automatic frequency control circuit and the input DC bias, and output an oscillation frequency signal.

[0030] Specifically, the 5-bit switched capacitor array unit includes a first NMOS transistor M0, a first resistor R0, a second resistor R1, a third resistor R2, a first NMOS capacitor CS1, a second NMOS capacitor CS2, and an inverter; the gate of the first NMOS transistor M0 receives the output five-bit control code S<4:0> of the automatic frequency control circuit, and the source of the first NMOS transistor M0 is connected to the drain of the first NMOS transistor M0 through the second resistor R1 and the third resistor R2 connected in series. At the same time, the source outputs an oscillation voltage OUTN through the first NMOS capacitor CS1, and the drain outputs an oscillation voltage OUTP through the second NMOS capacitor CS2. The output control code S<4:0> of the automatic frequency control circuit is also connected to the connection point of the second resistor R1 and the third resistor R2 through the inverter;

[0031] Specifically, the cross-coupling pair includes a first POMS transistor M1, a second POMS transistor M2, a first NMOS transistor M3, and a second NMOS transistor M4; the gate of the first POMS transistor M1 is connected to the drain of the second POMS transistor M2 and is also connected to the output end of the oscillation voltage OUTP, the gate of the second POMS transistor M2 is connected to the drain of the first POMS transistor M1 and is also connected to the output end of the oscillation voltage OUTN, and the source of the first POMS transistor M1 and the second POMS transistor M2 is simultaneously connected to the power supply VCC; one end of the inductor L is connected to the output end of the oscillation voltage OUTN, and the other end is connected to the The output end of the oscillation voltage OUTP; the first NMOS capacitor tube C1, the first variable capacitor tube C3, the second variable capacitor tube C4 and the second NMOS capacitor tube C2 are connected in series, wherein the other end of the first NMOS capacitor tube C1 is connected to the output end of the oscillation voltage OUTN, wherein the other end of the second NMOS capacitor tube C2 is connected to the output end of the oscillation voltage OUTP, the voltage control signal Vtune is connected between the first variable capacitor tube C3 and the second variable capacitor tube C4 to control the capacitance of the variable capacitor tube; the input DC bias is connected to the source end of the first NMOS tube M3 and the second NMOS tube M4.

[0032] like Figure 2 As shown, the voltage-controlled oscillator circuit includes a 5-bit switched capacitor array unit, a first NMOS capacitor tube C1, a second NMOS capacitor tube C2, a first variable capacitor tube C3, a first variable capacitor tube C4, a first inductor coil L and two pairs of cross-coupling pairs; it is used to receive the voltage control signal, the control code of the automatic frequency control circuit and the input DC bias, and output an oscillation frequency signal.

[0033] Specifically, the 5-bit switched capacitor array unit includes a first NMOS transistor M0, a first resistor R0, a second resistor R1, a third resistor R2, a first NMOS capacitor CS1, a second NMOS capacitor CS2, and an inverter; the gate of the first NMOS transistor M0 receives the output five-bit control code S<4:0> of the automatic frequency control circuit, and the source of the first NMOS transistor M0 is connected to the drain of the first NMOS transistor M0 through the second resistor R1 and the third resistor R2 connected in series. At the same time, the source outputs an oscillation voltage OUTN through the first NMOS capacitor CS1, and the drain outputs an oscillation voltage OUTP through the second NMOS capacitor CS2. The output control code S<4:0> of the automatic frequency control circuit is also connected to the connection point of the second resistor R1 and the third resistor R2 through the inverter;

[0034] Specifically, the cross-coupling pair includes a first POMS transistor M1, a second POMS transistor M2, a first NMOS transistor M3, and a second NMOS transistor M4; the gate of the first POMS transistor M1 is connected to the drain of the second POMS transistor M2 and is also connected to the output end of the oscillation voltage OUTP, the gate of the second POMS transistor M2 is connected to the drain of the first POMS transistor M1 and is also connected to the output end of the oscillation voltage OUTN, and the source of the first POMS transistor M1 and the second POMS transistor M2 is simultaneously connected to the power supply VCC; one end of the inductor L is connected to the output end of the oscillation voltage OUTN, and the other end is connected to the The output end of the oscillation voltage OUTP; the first NMOS capacitor tube C1, the first variable capacitor tube C3, the second variable capacitor tube C4 and the second NMOS capacitor tube C2 are connected in series, wherein the other end of the first NMOS capacitor tube C1 is connected to the output end of the oscillation voltage OUTN, wherein the other end of the second NMOS capacitor tube C2 is connected to the output end of the oscillation voltage OUTP, the voltage control signal Vtune is connected between the first variable capacitor tube C3 and the second variable capacitor tube C4 to control the capacitance of the variable capacitor tube; the input DC bias is connected to the source end of the first NMOS tube M3 and the second NMOS tube M4.

[0035] Figure 3 This is a phase error filter control process and method for a fast-locked low-jitter sub-sampling phase-locked loop of the present invention. The phase error integrator determines the current phase difference state based on the output of the sub-sampling Bang-Bang phase detection circuit and adaptively adjusts K according to the phase difference threshold. B The phase error filter control process is as follows: when the system starts, the loop gain is initialized to make the gain state M=1, the statistical expectation of the phase error C=0, and the phase error is judged. Is it greater than the threshold Δt (where Δt is the sum of the DFF setup and hold time td and the delay τ), if the phase error If the value is greater than the set threshold Δt, the loop gain will increase and the output M = 1. Otherwise, the phase error will be If the threshold Δt is not exceeded, the output M=0 indicates that the gain at that time is the expected gain value. The phase decision module determines whether the system gain meets the locking requirement at this time. If so, the statistical expectation C=1 of the gain output phase error is minimized and the loop is determined to be locked. If the phase decision module determines that the system gain does not meet the locking requirement at this time, the loop gain is increased. At this time, M=1 and C=0 continue to optimize the loop gain.

[0036] Figure 4This is a schematic diagram of the output signal jitter of a fast-locking, low-jitter subsampling phase-locked loop circuit of the present invention. When the input reference clock frequency is 62.5MHz and the subsampling phase-locked loop output signal frequency is 96 times the frequency, the input reference clock is superimposed with an additional 20ps peak-to-peak jitter. Observe 10,000 DCO cycles and the DCO output peak-to-peak jitter (jitter) is 0. pp ) is 877.55fs, and the root mean square jitter (jitter RMS ) is 178.24fs.

[0037] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0038] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A fast locking low jitter subsampling phase-locked loop, characterized in that: The fast-locking low-jitter sub-sampling phase-locked loop circuit includes a frequency-locked loop and a phase-locked loop. The phase-locked loop includes a sub-sampling Bang-Bang phase-locked loop circuit, an automatic frequency control circuit, an adaptive variable-step-size digital filter circuit, a Δ∑ digital-to-analog conversion circuit, and a voltage-controlled oscillator circuit. The frequency-locked loop is used to maintain the frequency relationship between the feedback oscillator signal and the input reference signal through closed-loop control. The phase-locked loop detects the phase relationship between the input reference signal and the feedback oscillator signal through a phase error filtering control process and method, generates corresponding lead-lag signals and gain signals, and controls the step size selection of the adaptive variable-step-size digital filter circuit, which is converted into a control signal for the voltage-controlled oscillator through the Δ∑ digital-to-analog conversion circuit.

2. The fast locking low jitter sub-sampling phase-locked loop according to claim 1, characterized in that: The sub-sampling Bang-Bang phase detection circuit includes a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a first delay unit τ1, a second delay unit τ2, a first NOR logic gate NOR, a first AND logic gate AND, and a first OR logic gate OR; the input reference signal is used to sub-sample the feedback oscillator signal through the first D flip-flop DFF1, and the output signal SIGN is connected to the inputs of the first NOR logic gate NOR and the first AND logic gate AND; the input reference signal is used to sub-sample the feedback oscillator signal through the second D flip-flop DFF2 through the first delay unit τ1, and the output signal is connected to the input of the first NOR logic gate NOR; the input reference signal is used to sub-sample the feedback oscillator signal after passing through the second delay unit τ2 through the third D flip-flop DFF3, and the output signal is connected to the input of the first AND logic gate AND; the outputs of the first NOR logic gate NOR and the first AND logic gate AND are simultaneously connected to the input of the first OR logic gate OR; the output of the first D flip-flop DFF1 and the output of the first OR logic gate OR are connected to the input of the adaptive variable step-size digital filter circuit.

3. The fast locking low jitter sub-sampling phase-locked loop according to claim 1, characterized in that: The adaptive variable step-size digital filter circuit includes a first phase error integrator circuit, a first phase decision circuit PD, and a first digital filter circuit including a proportional path and an integral path; the output end of the sub-sampling Bang-Bang phase detection circuit is connected to the input end of the first phase error integrator circuit, the output end of the first phase error integrator circuit is connected to the input end of the proportional path and the integral path of the first digital filter circuit, the output end of the sub-sampling Bang-Bang phase detection circuit is connected to the input end of the first phase decision circuit PD, the output end of the first phase decision circuit PD is connected to the input end of the first phase error integrator circuit and the proportional path and the integral path of the first digital filter circuit, and the proportional path output end and the integral path output end of the first digital filter circuit are connected to the input end of the ΔΣ digital-to-analog conversion circuit; The phase error filtering control process and method include a phase error integrator circuit that determines the current phase difference state according to the output of the sub-sampling Bang-Bang phase detection circuit, and adaptively adjusts K according to the phase difference threshold. B The value is set, and the filter gain is changed to gradually reduce the phase error in the next cycle, so as to realize the phase lock of the phase-locked loop. The phase error filter control process is as follows: when the system starts, the loop gain is initialized to make the gain state M=1, the statistical expectation of the phase error C=0, and the phase error is judged. Is it greater than the threshold Δt? If the phase error If the value is greater than the set threshold Δt, the loop gain will increase and the output M = 1. Otherwise, the phase error will be If the threshold Δt is not exceeded, the output M=0 indicates that the gain at that time is the expected gain value. The phase decision module determines whether the system gain meets the locking requirement at this time. If so, the statistical expectation C=1 of the gain output phase error is minimized and the loop is determined to be locked. If the phase decision module determines that the system gain does not meet the locking requirement at this time, the loop gain is increased. At this time, M=1 and C=0 continue to optimize the loop gain.

4. The fast locking low jitter sub-sampling phase-locked loop according to claim 1, characterized in that: The Δ∑ digital-to-analog conversion circuit includes a first digital interpolation filter circuit, a first noise shaping loop, a first analog-to-digital conversion circuit, and a first analog filter circuit; the input end of the first digital interpolation filter circuit is connected to the output end of the adaptive variable step-size digital filter circuit and the input reference signal, the output end of the first digital interpolation filter circuit is connected to the input end of the first noise shaping loop; the output end of the first digital interpolation filter circuit is connected to the input end of the first noise shaping loop; the input end of the first analog filter circuit is connected to the output end of the first analog-to-digital conversion circuit, and the output control voltage Vtune controls the oscillator tuning.

5. The fast locking low jitter sub-sampling phase-locked loop according to claim 1, characterized in that: The voltage-controlled oscillator circuit includes a 5-bit switched capacitor array unit, a first NMOS capacitor tube C1, a second NMOS capacitor tube C2, a first variable capacitor tube C3, a first variable capacitor tube C4, a first inductor coil L and two pairs of cross-coupling pairs; it is used to receive the voltage control signal, the control code of the automatic frequency control circuit and the input DC bias, and output an oscillation frequency signal.

6. The fast locking low jitter sub-sampling phase-locked loop according to claim 5, characterized in that: The 5-bit switched capacitor array unit includes a first NMOS transistor M0, a first resistor R0, a second resistor R1, a third resistor R2, a first NMOS capacitor CS1, a second NMOS capacitor CS2, and an inverter circuit; the gate of the first NMOS transistor M0 receives the output five-bit control code S<4:0> of the automatic frequency control circuit, the source of the first NMOS transistor M0 is connected to the drain of the first NMOS transistor M0 through the second resistor R1 and the third resistor R2 connected in series, and the source outputs an oscillation voltage OUTN through the first NMOS capacitor CS1, and the drain outputs an oscillation voltage OUTP through the second NMOS capacitor CS2. The output control code S<4:0> of the automatic frequency control circuit is also connected to the connection point of the second resistor R1 and the third resistor R2 through an inverter; The cross-coupling pair includes a first POMS transistor M1, a second POMS transistor M2, a first NMOS transistor M3, and a second NMOS transistor M4; the gate of the first POMS transistor M1 is connected to the drain of the second POMS transistor M2 and is also connected to the output end of the oscillation voltage OUTP, the gate of the second POMS transistor M2 is connected to the drain of the first POMS transistor M1 and is also connected to the output end of the oscillation voltage OUTN, and the source of the first POMS transistor M1 and the second POMS transistor M2 is simultaneously connected to the power supply VCC; one end of the inductor L is connected to the output end of the oscillation voltage OUTN, and the other end is connected to the oscillation voltage VCC. The output end of the oscillation voltage OUTP is connected; the first NMOS capacitor tube C1, the first variable capacitor tube C3, the second variable capacitor tube C4, and the second NMOS capacitor tube C2 are connected in series, wherein the other end of the first NMOS capacitor tube C1 is connected to the output end of the oscillation voltage OUTN, wherein the other end of the second NMOS capacitor tube C2 is connected to the output end of the oscillation voltage OUTP, and the voltage control signal Vtune is connected between the first variable capacitor tube C3 and the second variable capacitor tube C4 to control the capacitance of the variable capacitor tube; the input DC bias is connected to the source end of the first NMOS tube M3 and the second NMOS tube M4.

Images