Broadband signal high-speed LDPC decoding method and device with low computing power requirement

Abstract

The invention provides a broadband signal high-speed LDPC decoding method and device with a low computing power requirement, relates to the field of radio monitoring, and solves the problems that a current LDPC code decoder is long in processing time consumption, large in resource occupation and difficult in engineering implementation. The method comprises the following steps: caching a data frame, reading and processing adjacent code words in a to-be-decoded data frame in a serial mode after configuration, determining long code words, designing a control logic time sequence, and realizing multi-channel concurrent processing of the long code words under a low computing power requirement in a parallelism parameter soft switching mode; designing a concurrent decoding processing path, and carrying out variable node iteration updating and check node iteration updating based on an improved NMSA decoding algorithm; and after an iteration stopping strategy is satisfied, obtaining a decoding bit sequence of the long code word, and forming a decoding result under a low computing power demand. The method has the advantages of being low in processing time delay, low in resource consumption and close to the actual use environment, and the satellite signal monitoring decoding processing rate and the decoding data throughput can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of radio monitoring technology and is applied to the decoding process of broadband satellite signals. In particular, it relates to a method and device for high-speed LDPC decoding of broadband signals with low computing power requirements. Background Art

[0002] Satellite communication systems have the characteristics of long communication distance, little influence from terrain, and wide communication beam coverage, and have been developing towards large capacity, high frequency and multi-service.

[0003] In recent years, the construction of various satellite constellations has boomed around the world, sparking intense competition for space frequency and orbital resources and presenting potential security risks for terrestrial communications and networks. Satellite network systems combine wide coverage, high transmission rates, and large communication capacity. However, their bandwidth exceeding hundreds of megabits and time constraints of tens of milliseconds present challenges in both performance and speed for radio signal monitoring and processing.

[0004] Since 2005, LDPC codes, due to their excellent error correction performance over wireless channels, have been continuously adopted in a range of satellite standards, including Digital Video Broadcasting (DVB) and Communications in Space Satellite Data Systems (CCSDS), forming the physical layer channel modulation and coding scheme. Most practical coding schemes use quasi-cyclic methods to construct QC-LDPC codes. Therefore, decoder hardware design can significantly improve decoder throughput by increasing parallelism. However, fully parallel LDPC codes used in typical satellite network systems have very demanding resource requirements. LDPC codes for satellite network systems have larger coding matrices and are irregular accumulation codes. Conventional parallel decoders cannot meet the practical requirements of large-bandwidth satellite signal monitoring and processing. Therefore, it is necessary to design a hardware architecture that balances decoder processing speed and resource utilization, improve system decoding throughput, simplify the decoding process complexity, and reduce system decoding latency. The integrated design of satellite signal LDPC decoders should preferably utilize domestically produced, miniaturized processing devices.

[0005] The research status of the prior art in this regard is as follows: The patented technical solution with application number CN202110932108.4, titled "A LDPC decoder logic design method for low-orbit satellite Internet systems," uses the log-likelihood ratio of the input information to calculate the current decoder's decision and make a check. This method can reduce the utilization rate of cache resources. However, it requires calculating and storing the column and row weights of the original check matrix, which increases the complexity of computational processing and parameter lookup, resulting in higher BRAM resource requirements.

[0006] The patented technical solution, application number CN201911166138.8 and titled "LDPC Code Decoding Method, Decoder and Receiver for Satellite Navigation," designs and implements decoding of 64-base LDPC codes. A hard decision vector is obtained by performing a hard decision on the received sequence vector, and a test vector is generated by selecting the target position. Error correction is performed using the test vector, and the error correction result is the decoding result. This method has a high algorithm complexity, consumes a large delay in the processing flow, and requires high computing power from the hardware platform.

[0007] In the patented technical solution with application number CN202410343907.1, titled "A high-speed LDPC decoder and interleaved decoding method suitable for near-Earth satellite communications," the conversion between the node's original code and its complement and the multiplication of the correction factor are designed into the variable node operation module. The serial processing structure adopted in this design has a large delay, and the computational complexity is high due to the multiplication operation, which also places high requirements on the computing power of the hardware platform. Summary of the Invention

[0008] Based on the current state of the art, the present invention aims to address the issues of long processing time, high resource usage, and difficult engineering implementation in LDPC code decoders used in wide-bandwidth satellite signal processing. Therefore, a method and device for high-speed LDPC decoding of broadband signals with low computing power requirements are proposed. This invention designs a processing architecture that combines single-channel serial processing with multi-channel concurrent processing, resulting in a fully domestically produced platform, low processing latency, low resource consumption, and practical applicability. The multi-channel concurrent processing in the decoding method effectively improves the satellite signal monitoring decoding processing rate and decoded data throughput, while the serial design helps reduce the device's hardware resource usage.

[0009] The present invention adopts the following technical solutions to achieve the purpose: A high-speed LDPC decoding method for broadband signals with low computing power requirements comprises the following steps: S1. Obtain a data frame to be decoded consisting of an LDPC code, preset configuration parameters including a length threshold, and then cache the data frame to be decoded and the configuration parameters; S2. Read and process multiple adjacent codewords in the data frame to be decoded in a serial manner, and determine codewords whose length exceeds a preset length threshold as long codewords; design a control logic timing based on an FPGA, which is used to extract long codewords from within the satellite signal, and achieve multi-channel concurrent processing of long codewords with low computing power requirements through soft switching of parallelism parameters; S3. During multi-channel concurrent processing, design the concurrent decoding processing path within the long codeword, that is, complete the decoding iteration of various node states: Firstly, the message values of each variable node are initialized and updated based on the improved NMSA decoding algorithm; Secondly, based on the improved OMSA algorithm, an offset is introduced to update the check node message value. Based on the long codeword multi-channel concurrent processing method that supports soft switching of parallelism parameters, an improved maximum value comparison control timing is used to accelerate the update calculation of this step. Finally, the design improves the partial sum of the intermediate calculation amount to participate in the calculation to obtain the iterative state value of the variable node, thereby executing the iterative update process; S4. The iterative update process stops after the iterative stop strategy is met, and a decoding bit sequence corresponding to the long codeword is obtained; after all codewords in the data frame to be decoded obtain corresponding decoding bit sequences and output them, decoding result data is obtained.

[0010] Specifically, in step S1, the data frame to be decoded is acquired by locking the satellite broadband signal parameters including carrier frequency, signal bandwidth, and modulation mode. The preset configuration parameters include length threshold, coding rate, and concurrent paths. The concurrent paths are supported by a control logic timing based on an FPGA design. The control logic timing is used to adjust the underlying processing structure and timing function for the data input of long and short codewords, complete the data cache and processing path parameter reset during the decoding process under user drive, and reconstruct the memory resource usage bit width and depth configuration parameters during the decoding process, so as to extract and load long codewords within the satellite signal. The cache of the data frame to be decoded adopts a message matrix mode.

[0011] Specifically, in step S2, based on the preset number of concurrent paths, the long codeword is internally divided into multiple paths of concurrent data; when processing the long codeword, each path of data is decoded in a concurrent manner.

[0012] Furthermore, in step S3, the iteration is started based on the improved NMSA decoding algorithm. First, the priori message corresponding to each channel of data of the long codeword currently being decoded in the data frame to be decoded is obtained from the message matrix, and the entry of the initial message value is completed to obtain the corresponding multi-channel data before the first iteration. variable nodes The message value of Represents the Iterations; then, based on the parity check matrix in the prior message, determine variable nodes and The connection relationship between the check nodes is then calculated based on the logarithmic field. During the iteration, the long code word corresponds to the variable node in the multi-channel data and check nodes The message value is cached.

[0013] Preferably, when processing the data frames to be decoded and caching the message values of the variable nodes and the check nodes during the iteration process, a dual-port RAM is used to perform ping-pong cache management.

[0014] Preferably, based on the improved OMSA algorithm, for the check node update operation of each data path during the iteration process, the update message value transmitted by the check node is expressed as follows:

[0015] Where, is the offset parameter, and its value range is 0 to 1; Represents the verification node Calculated and sent to the variable node The message value, Representative The bit reliability of the message value at iterations; Represents the relevant product terms when the check node calculates and updates the message value; during the check node calculation and update process, the improved optimization design is based on the multi-channel concurrent maximum value comparison control timing to complete the filtering and screening comparison of the minimum sum of the message value.

[0016] Preferably, based on the variable node update operation of each data in the iterative process of the improved NMSA decoding algorithm optimization, the initial message value of the current variable node is first determined, and then the data substitution subtraction processing method is designed based on the optimized algorithm principle to obtain the updated message value of the variable node, as shown in the following formula:

[0017] Where, Represents the slave variable node To the verification node The message value, Representative The bit reliability of the message value at iterations; Represents a variable node The initial message value of is the partial sum value, which includes all nodes except the check node Except for the variable nodes The sum of the message values transmitted by the connected check nodes; partial sum Cache as an intermediate variable during iteration.

[0018] Specifically, in step S4, after the iteration stop strategy is satisfied, the variable node update messages and the initial messages cached during the decoding process are read in sequence and summed up; after performing a logical judgment based on the sign bit on the summation result, the decoding bit sequence corresponding to the long codeword is obtained.

[0019] The present invention also provides a high-speed LDPC decoding device for broadband signals with low computing power requirements, which includes a user-driven system and an underlying decoding system in communication connection, wherein: The user-driven system is used to receive input of data frames to be decoded and configuration parameters, and transmit them to the underlying decoding system. At the same time, it receives the decoding result data uploaded by the underlying decoding system after decoding, and performs business function applications. It is also used to issue commands to perform soft switching of parallelism parameters of the decoding device to meet the requirements of multi-channel concurrent processing of long codewords of large-bandwidth satellite signals under low computing power requirements. The underlying decoding system includes the following functional modules: The state active conversion module is used to serially read multiple adjacent codewords in the data frame to be decoded and, based on the length threshold and number of concurrent paths in the configuration parameters, perform serial-to-parallel conversion on long codewords whose length exceeds the preset threshold. It is also used to support concurrent path reconfiguration, reconstruct the programmable logic path for decoding long codewords in the satellite's large-bandwidth signal, and construct multiple channels of data for concurrent processing. The message matrix cache module is used to cache the data frames to be decoded that are serially read into the state active conversion module; The node iterative calculation module is used to perform iterative calculations on variable nodes and check nodes in the long codeword in a multi-channel concurrent manner based on the data cached in the message matrix cache module, and update the message value of the corresponding node; A decision processing integration module is used to determine the decoding bit sequence based on the symbol decision according to the message values of the variable nodes and the check nodes after the current iteration update when the iteration stop strategy is met, and integrate it into the decoding result data corresponding to the data frame to be decoded; The result data uploading module uploads the decoding result data obtained by the decision processing integration module to the user drive system based on the data frame to be decoded and the configuration parameters obtained by the state active conversion module.

[0020] Preferably, the node iteration calculation module is also used to store the message values of the variable nodes and the check nodes updated after each iterative calculation into the calculation data storage call array; the decision processing integration module obtains the message values of the variable nodes and the check nodes when the iteration stops from the calculation data storage call array.

[0021] In summary, due to the adoption of this technical solution, the beneficial effects of the present invention are as follows: The implementation of this invention can bring about numerous technological advancements and user conveniences. It can utilize a fully domestically produced platform design for engineering applications, enhancing the system's autonomy and controllability while also providing users with a solution more tailored to their actual application environments. In terms of resource consumption, this solution significantly reduces hardware resource usage, enabling miniaturization and lightweighting of the device, thereby expanding its application scenarios.

[0022] By combining a single-channel serial processing architecture with a multi-channel concurrent processing architecture, this invention achieves a dual improvement in processing efficiency and performance. The multi-channel concurrent processing mechanism significantly increases the satellite signal monitoring and decoding processing rate and data throughput, ensuring efficient data transmission and processing capabilities. The serial design helps optimize the device's internal structure, reduces hardware resource requirements, and further improves resource utilization and overall system performance.

[0023] Furthermore, this invention effectively reduces processing latency, ensuring real-time performance and responsiveness, while maintaining system stability and reliability while meeting high-speed data processing requirements. This optimization not only enhances user experience but also provides solid technical support for a wider range of applications. Taken together, these improvements contribute to the development of LDPC code decoding technology for broadband satellite signals, making it more adaptable to future high-efficiency, low-energy applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram briefly describing the overall steps of the decoding method of the present invention; Figure 2 Schematic diagram of the structure and data transmission relationship of the decoding device of the present invention; Figure 3 A schematic diagram of the flow of the decoding process implemented by the decoding device of the present invention; Figure 4 Schematic diagram of the bit error rate performance simulation results during the simulation process of the present invention. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0027] Example 1 A high-speed LDPC decoding method for broadband signals with low computing power requirements. The overall process of this method can be briefly described in Figure 1 The main steps of this embodiment are summarized as follows: S1. Obtain a data frame to be decoded consisting of an LDPC code, preset configuration parameters including a length threshold, and then cache the data frame to be decoded and the configuration parameters; S2. Read and process multiple adjacent codewords in the data frame to be decoded in serial mode, determine codewords whose length exceeds a preset length threshold as long codewords, and design a control logic sequence based on FPGA that supports soft switching of parallelism parameters, multi-channel concurrency, and flexible processing of long and short codewords. This facilitates the extraction of long codewords within high-bandwidth, high-rate satellite signals, and performs high-speed, multi-channel concurrent processing that meets low computing power requirements. S3. During multi-path concurrent processing, design the concurrent decoding processing path within the long codeword. The key path is to iterate the decoding to complete various node states: First, the message values of each variable node are initialized and updated based on the improved NMSA algorithm; Secondly, based on the improved OMSA algorithm, an offset is introduced to update the check node message value. Based on the long codeword concurrent processing architecture design that supports soft switching, an improved maximum value comparison control timing is used to accelerate the update calculation in this step. Finally, the improved intermediate calculation amount "partial sum value" is designed to participate in the calculation to obtain the iterative state value of the variable node, thereby executing the iterative update process; S4. The iterative update process stops after the iterative stop strategy is met, and a decoding bit sequence corresponding to the long codeword is obtained; after all codewords in the data frame to be decoded obtain corresponding decoding bit sequences and output them, decoding result data is obtained.

[0028] This embodiment will introduce the details of each step in detail according to the above step sequence.

[0029] In step S1, the data frame to be decoded is acquired by locking the satellite broadband signal parameters, including carrier frequency, signal bandwidth, and modulation mode. Preset configuration parameters include length threshold, coding rate, and number of concurrent channels. The FPGA-based multi-channel concurrent processing method, which supports soft switching of concurrent parameters and the corresponding control logic timing, provides flexible adjustment of the underlying processing structure and control timing for long and short codeword data inputs. Under user-driven control, the data cache and processing channel parameters in the decoding device can be reset. This allows the user-driven system to effectively reconfigure the memory resource usage bit width, depth, and other configuration parameters of the decoding device. This facilitates the extraction and rapid loading of long codewords within high-bandwidth, high-speed satellite signals, reduces the scale of the data matrix required for underlying hardware resources, improves the decoding processing rate, and adapts to actual low-computing power requirements. The cache of the data frame to be decoded adopts a message matrix mode.

[0030] In step S2, the long codeword is internally divided into multiple concurrent data paths based on the preset number of concurrent paths. Each path of data is decoded concurrently when processing the long codeword. This processing method achieves a decoding pipeline that combines single-path serial processing with multi-path concurrent processing, effectively improving the decoding rate.

[0031] In step S3, the iteration is started based on the improved NMSA decoding algorithm. First, the priori message corresponding to each channel of data of the long codeword currently being decoded in the data frame to be decoded is obtained from the message matrix, and the entry of the initial message value is completed to obtain the corresponding multi-channel data before the first iteration. variable nodes The message value of Represents the Iterations; then, based on the parity check matrix in the prior message, determine variable nodes and The connection relationship between the check nodes is then calculated based on the logarithmic field. During the iteration, the long code word corresponds to the variable node in the multi-channel data and check nodes The message value is cached.

[0032] In step S4, after the iteration stop strategy is satisfied, the variable node update messages and initial messages cached in the decoding process are read in sequence and summed up; after performing a logical judgment based on the sign bit on the summation result, the decoding bit sequence corresponding to the long codeword is obtained. In this embodiment, the iteration stop strategy can adopt the maximum iteration number strategy, that is, when the number of iterations is After reaching the preset maximum number threshold, the iteration stop condition is triggered, and the decoding bit sequence of the corresponding long codeword is determined based on the current variable node message value.

[0033] During the above-described method, this embodiment performs serial-to-parallel conversion on the long codewords in the data frame to be decoded, and stores the various nodes contained therein in an array based on the number of concurrent paths. This achieves a solution architecture that allows for multi-path concurrent processing within the same codeword and serial reading between adjacent codewords. This combines single-path serial and multi-path concurrent decoding processes, effectively improving the decoding processing rate. This approach reduces the computational complexity of the intermediate node update process, optimizes the logical control steps of the hardware design, and achieves the goals of shortening processing latency and reducing hardware resource utilization. Ultimately, it significantly increases the throughput of the decoding device to over 400Mbps and supports high-speed decoding of satellite broadband signals operating at clock rates exceeding 200MHz.

[0034] Example 2 Based on Example 1, this example preferably introduces some details of the high-speed LDPC decoding method.

[0035] Regarding the main features of the method of this embodiment, namely, the scheme architecture of multiple concurrent processing within the same codeword and serial reading between adjacent codewords, when the preset number of concurrent paths is determined in the configuration parameters When the operation of all node data in the same codeword is completed under the driving of each beat processing clock Data operation is performed on the long codeword to realize Therefore, the processing delay of the iterative update processing of the two key nodes, variable nodes and check nodes, in the long codeword can be shortened to the time taken by the traditional serial processing of the long codeword. , and also enables the decoding device using this method to support processing signal bandwidth ranges to above 10 MHz.

[0036] In the actual situation of limited hardware resources, compared with the traditional method of directly dividing the entire data frame to be decoded into multiple segments containing multiple codewords and processing them in parallel, the application of this embodiment requires relatively small resource scale, and only performs internal concurrent processing division for the long codeword currently processed serially, and the processing volume of each concurrent path is relatively low. Compared with the traditional method of always using a serial design to process the entire data frame to be decoded in sequence, this embodiment has a lower time delay in the decoding process of long codewords, which is crucial for improving bandwidth and can support higher bandwidth signal decoding processing processes, and the decoding throughput can be improved. times.

[0037] Based on the above design considerations, this embodiment also preferably utilizes dual-port RAM for "ping-pong" cache management when processing data frames to be decoded and caching variable and check node message values during the iterative process. This method of caching data frames to be decoded enables continuous, alternating caching of data frames at a high-speed clock. Specifically, when applied to the data input process, the "ping-pong" cache mechanism utilizes two independent storage areas (also referred to as buffer A and buffer B). This allows the system to process the current data frame or message value in one buffer while preparing the next data frame or updated message value in the other buffer. This allows the system to quickly switch to the prepared new data after the current processing cycle completes, thereby improving data processing efficiency and the system's decoding throughput.

[0038] In this embodiment, for each parallel data path in a long codeword, the decoding process adopts the operation principle of transforming the data into the logarithmic domain. As a mathematical concept, the logarithmic domain can transform the multiplication operation into the addition operation through logarithmic transformation. In the traditional decoding process, when updating the variable nodes and check nodes, a large number of multiplication operations are involved. Therefore, after this transformation, the operation complexity can be effectively reduced, and the multiplication pipeline processing can be transformed into the addition pipeline processing. For a data path in a long codeword, when the number of its variable nodes is In this case, it will reduce The consumption of multiplier resources can save at least The processing delay of one clock.

[0039] In this embodiment, based on the improved OMSA algorithm, for the check node update operation of each data path during the iteration process, the preferred method is to express the update message value transmitted by the check node as follows:

[0040] Where, is the offset parameter, and its value range is 0 to 1; Represents the verification node Calculated and sent to the variable node The message value, Representative The bit reliability of the message value at iterations; Represents the relevant product term when the check node calculates the updated message value; this method can effectively prevent the decoding effect from being reduced due to the overestimation of the message value. The implemented bit right shift logic can replace the multiplication process, further reducing the occupation of multiplier resources.

[0041] In the calculation and update process of the check node, this embodiment improves and optimizes the design of a multi-path concurrent maximum value comparison control sequence to accelerate the filtering and screening comparison of the minimum sum of message values, effectively shortening the processing delay of comparing multiple values at the same time. During the iterative decoding process of the LDPC code, the check node needs to process the message value transmitted by the variable node to which it is connected. This process will involve complex mathematical operations, such as calculating products, finding minimum or maximum values, etc. In particular, when it is necessary to find the maximum or minimum value from multiple candidate values, directly comparing one by one may take a lot of time, especially in high-throughput application scenarios. After introducing a concurrent multi-level comparator structure in this embodiment, multiple comparison tasks can be processed in parallel; for example, the values to be compared can be divided into several groups first, and the comparisons can be performed simultaneously in each group; then the comparison results of each group can be grouped and compared again until the global maximum or minimum value is finally found. This detailed method takes advantage of parallel computing and significantly reduces the total time required to complete all comparisons.

[0042] This embodiment optimizes the variable node update operation of each data channel during the iterative process based on the improved NMSA decoding algorithm. First, the initial message value of the current variable node is determined. Then, based on the optimized algorithm principle, a data substitution subtraction processing method is designed to obtain the updated message value of the variable node, as shown in the following formula:

[0043] Where, Represents a slave variable node To the verification node The message value, Representative The bit reliability of the message value at iterations; Represents variable node The initial message value of is the "partial sum value", which includes all nodes except the check node Except for the variable nodes The sum of the message values passed by the connected check nodes; "partial sum value" This improved method makes full use of the intermediate values generated in each iteration, saving a large number of repeated summation operations at each node in each iteration, thereby effectively reducing the adder resource call and processing delay, optimizing the calculation path of the new message value, and meeting the high-speed decoding processing of large-bandwidth satellite signals under low computing power requirements. Based on this caching method, the final result can be obtained. Variable node at iteration Updated message value. This method reduces the resources of the subtractor and the two's complement conversion operation, simplifies the control logic of the node update process, and compresses the accumulation scale of all message values of long codewords in a multi-channel concurrent structure.

[0044] Finally, conditional judgment is performed based on the number of iterations. When the iteration stopping strategy is met, the variable node update messages and initial messages cached during the decoding process are read sequentially and summed up. After performing a logical judgment based on the sign bit on the summation result, the complete judgment message value is obtained, and the decoding bit sequence corresponding to the long codeword can be output.

[0045] Example 3 Based on the embodiment 1 or 2, this embodiment introduces the relevant content of a high-speed LDPC decoding device for broadband signals with low computing power requirements after the high-speed LDPC decoding method is applied to a hardware device. Figure 2 A major feature of this device is that it can be implemented using a national platform hardware, specifically including a user-driven system with communication connections and an underlying decoding system, where: The user-driven system receives inputs of data frames to be decoded and configuration parameters, and transmits them to the underlying decoding system. It also receives the decoded result data uploaded by the underlying decoding system after decoding, and performs business functions. This allows the user-driven system to issue commands to the decoding device to perform soft switching of parallelism parameters, meeting the requirements of high-speed, multi-channel concurrent processing of long codewords of large-bandwidth satellite signals with low computing power requirements. The underlying decoding system includes the following functional modules: The state-active conversion module is used to serially read multiple adjacent codewords in the data frame to be decoded and, based on the length threshold and number of concurrent paths in the configuration parameters, perform serial-to-parallel conversion on long codewords exceeding the preset length threshold to form multiple channels of data for concurrent processing. This module corresponds to the functional application of the state machine and can support the reconfiguration of the number of concurrent paths, flexibly reconstruct the programmable logic path for decoding long codewords in the satellite's large-bandwidth signal, and construct multiple channels of data for concurrent processing. The message matrix cache module is used to cache the data frames to be decoded that are serially read into the state active conversion module; Node iterative calculation module (including Figure 2 The variable node calculation module and the check node calculation module in the message matrix cache module are used to perform iterative calculations of the variable nodes and the check nodes in the long codeword in a multi-channel concurrent manner based on the data cached in the message matrix cache module, and update the message values of the corresponding nodes; A decision processing integration module is used to determine the decoding bit sequence based on the symbol decision according to the message values of the variable nodes and the check nodes after the current iteration update when the iteration stop strategy is met, and integrate it into the decoding result data corresponding to the data frame to be decoded; The result data uploading module uploads the decoding result data obtained by the decision processing integration module to the user drive system based on the data frame to be decoded and the configuration parameters obtained by the state active conversion module.

[0046] In this embodiment, Figure 2 As shown, the node iteration calculation module is also used to store the message values of the variable nodes and the check nodes after each iterative calculation update into the calculation data storage call array; the decision processing integration module obtains the message values of the variable nodes and the check nodes when the iteration stops from the calculation data storage call array.

[0047] In this embodiment, the user-driven system mainly includes a data transmission and display component and a business function service component. The system can use the industrial version system model Tengrui D2000 / 8, which is a domestically produced system equipped with this type of CPU chip. It can undertake business function services such as interactive control, data display, auxiliary storage and analysis. The built-in data transmission and display component can be dedicated to data transmission and interface display services.

[0048] In this embodiment, the underlying decoding system is built based on FPGA, and the FPGA chip model used is SMQ7VX690TFFG1927IP. It is mainly responsible for the active conversion control of FPGA hardware status, update calculation of two types of key node message values, storage and call of calculation data, node address generation, decision decoding bit results and result upload and output.

[0049] Figure 3 The flowchart of how the decoding device of this embodiment performs decoding is shown, and this embodiment is described as follows: First, a complete frame of data to be decoded is input into the user-driven system, along with corresponding configuration parameters; the frame of data to be decoded will include consecutive codewords, wherein codewords whose length exceeds a preset length threshold will be determined as long codewords.

[0050] The user-driven system can display the device status of the decoding device through its window interface. After the device status is normal and the parameter configuration input is completed, the underlying decoding system can be started.

[0051] After receiving the data frame to be decoded, the state active conversion module converts the long codeword into serial-to-parallel according to the preset concurrent paths, initializes the variable nodes therein, and sends the initial message values of the variable nodes to the message matrix cache module; this message matrix cache module can further ensure multi-path concurrent processing within the long codeword and reduce decoding processing delay.

[0052] Subsequently, the information data related to the configuration parameters in the active state transition module and the initial message values in the message matrix cache module are fed into the variable node calculation module. The corresponding check node message values can also be directly fed into the check node calculation module based on the active state transition module. Both are decoded using a multi-path concurrent processing method, resulting in an iterative process with several times the computational efficiency compared to single-path processing of long codewords. The larger the number of concurrent paths, the lower the processing latency of a single iteration and the higher the computational efficiency.

[0053] During each iterative calculation process, the corresponding verification node calculation module is started, and after calculating the message value passed to the verification node by the variable node, it is sent to the calculation data storage call array, and finally the update process of the variable node is completed alternately under the restriction of the iterative stop strategy.

[0054] When the state active conversion module detects that the current number of iterations has reached the preset maximum number threshold, the iteration stop condition is triggered. The decision processing integration module sequentially reads the variable node update messages and initial messages cached during the decoding process and performs summation processing; after performing a logical judgment based on the sign bit on the summation result, the decoding bit sequence corresponding to the long codeword is obtained.

[0055] Finally, the result data upload module reads the decoding result data from the decision processing integration module based on the configuration parameters and other relevant information issued by the user-driven system. The data is also cached and then uploaded to the user-driven system for external output or business application; at this time, the relevant cache data in the underlying decoding system is cleared, waiting for the input of the next frame of data to be decoded and decoding processing.

[0056] Example 4 Based on the above embodiments, this embodiment analyzes and introduces two simulation cases of applying the decoding method or using the decoding device.

[0057] In simulation case 1, a short frame of a satellite system physical layer signal is processed and simulated based on a decoding device that applies the decoding method. The signal is a continuous signal. Through parameter estimation, its signal bandwidth parameter BW=10MHz is obtained. The modulation method is Quadrature Phase Shift Keying (QPSK). The LDPC codeword length is 16200 bits and the coding rate is 3 / 4, that is, for every 4 bits sent, 3 are valid information bits and 1 is a redundant bit for error correction. The EB / N0 value of the simulation test environment is a channel condition of 0 to 6dB. After demodulation, the test signal is sent to the decoding device corresponding to the decoding method introduced in the above embodiment. The obtained bit error rate (BER) is as follows: Figure 4 shown.

[0058] Depend on Figure 4 It can be seen that after the LDPC decoding of the currently collected satellite broadband signal, the processing effect is about 10 when EB / N0>3.25dB. -4 When EB / N0>5.0dB, the bit error rate performance will be less than 10 -7 This effect indicates that it has extremely high reliability, that is, when the signal-to-noise ratio is greater than 5.0dB, there is a possibility of less than 1 bit error in every 10,000,000 bits transmitted. Therefore, it is suitable for occasions with very strict error requirements, such as satellite communications, deep space exploration and other fields.

[0059] In Simulation Case 2, a decoding device employing this decoding method uses a (7200, 16200) LDPC code as an example. The maximum row weight parameter for the check node processing stage is 7, requiring a design of up to 7M check node processing units. The maximum column weight parameter for the variable node processing stage is 8, requiring a design of 8P variable node processing units. The resource usage and design of the decoding device are shown in Table 1 below. These include various processing units and memory blocks, such as lookup tables (LUTs), block RAMs (BRAMs), digital signal processor (DSP) slices, input / output ports (IOs), and mixed-mode clock managers (MMCMs).

[0060] Table 1 Schematic diagram of decoding device resource usage

[0061] Based on the resource occupation and design, the decoding device processing results described below can be obtained: This decoding device achieves high-speed decoding processing for signal bandwidths up to 50 MHz, with a throughput parameter of up to 477.54 Mbps. Because the decoding device used in this embodiment has a decoding processing structure that combines single-channel serial and multi-channel concurrent decoding, it eliminates the need to pre-store all column and row parameters on the underlying FPGA. This optimizes the message value storage strategy and calculation in the decoding design, omits and simplifies multiplication operations, and reuses various hardware resources, completing high-speed decoding processing of satellite broadband signals with low computing power requirements.

Claims

1. A high-speed LDPC decoding method for broadband signals with low computing power requirements, characterized in that: The steps include: S1. Obtain a data frame to be decoded consisting of an LDPC code, preset configuration parameters including a length threshold, and then cache the data frame to be decoded and the configuration parameters; S2. Reading and processing a plurality of adjacent codewords in the data frame to be decoded in a serial manner, and determining a codeword whose length exceeds a preset length threshold as a long codeword; Design control logic timing based on FPGA, which is used to extract long codewords from satellite signals. Soft switching of parallelism parameters is used to achieve multi-channel concurrent processing of long codewords with low computing power requirements. S3. During multi-channel concurrent processing, design the concurrent decoding processing path within the long codeword, that is, complete the decoding iteration of various node states: Firstly, the message values of each variable node are initialized and updated based on the improved NMSA decoding algorithm; Secondly, based on the improved OMSA algorithm, an offset is introduced to update the check node message value. Based on the long codeword multi-channel concurrent processing method that supports soft switching of parallelism parameters, an improved maximum value comparison control timing is used to accelerate the update calculation of this step. Finally, the design improves the partial sum of the intermediate calculation amount to participate in the calculation to obtain the iterative state value of the variable node, thereby executing the iterative update process; S4, the iterative update process stops after the iterative stopping strategy is satisfied, and a decoding bit sequence corresponding to the long codeword is obtained; After all code words in the data frame to be decoded obtain corresponding decoding bit sequences and output them, decoding result data is obtained.

2. The high-speed LDPC decoding method for wideband signals with low computing power requirements according to claim 1, characterized in that: In step S1, the data frame to be decoded is acquired by locking the satellite broadband signal parameters including carrier frequency, signal bandwidth, and modulation mode. The preset configuration parameters include length threshold, coding rate, and number of concurrent paths. The number of concurrent paths is supported by a control logic timing based on an FPGA design. This control logic timing is used to adjust the underlying processing structure and timing functions for the data input of long and short codewords. Under user-driven operation, the data cache and processing path parameter reset during the decoding process are completed, and the memory resource usage bit width and depth configuration parameters during the decoding process are reconstructed, thereby extracting and loading long codewords within the satellite signal. The buffering of data frames to be decoded adopts the message matrix mode.

3. The high-speed LDPC decoding method for wideband signals with low computing power requirements according to claim 2, characterized in that: In step S2, based on the preset number of concurrent paths, the long codeword is internally divided into multiple paths of concurrent data; when processing the long codeword, each path of data is decoded in a concurrent manner.

4. The high-speed LDPC decoding method for wideband signals with low computing power requirements according to claim 3, characterized in that: In step S3, the iteration is started based on the improved NMSA decoding algorithm. First, the priori message corresponding to each channel of data of the long codeword currently being decoded in the data frame to be decoded is obtained from the message matrix, and the entry of the initial message value is completed to obtain the corresponding multi-channel data before the first iteration. variable nodes The message value of Represents the iterations; Then, according to the parity check matrix in the prior message, determine variable nodes and The connection relationship between the check nodes is then calculated based on the logarithmic field. During the iteration, the long code word corresponds to the variable node in the multi-channel data and check nodes The message value is cached.

5. The high-speed LDPC decoding method for wideband signals with low computing power requirements according to claim 4, characterized in that: When processing the data frames to be decoded and the cache of the variable node and check node message values in the iterative process, a dual-port RAM is used for ping-pong cache management.

6. The high-speed LDPC decoding method for wideband signals with low computing power requirements according to claim 4, characterized in that: Based on the improved OMSA algorithm, for the check node update operation of each data path during the iteration process, the update message value transmitted by the check node is expressed as follows: Where, is the offset parameter, and its value range is 0 to 1; Represents the verification node Calculated and sent to the variable node The message value, Representative The bit reliability of the message value at iterations; Represents the relevant product term when the check node calculates the update message value; In the calculation and update process of the check node, the improved optimization design is based on the multi-channel concurrent maximum value comparison control timing to complete the filtering and screening comparison of the minimum sum of the message values.

7. The high-speed LDPC decoding method for wideband signals with low computing power requirements according to claim 4, characterized in that: Based on the improved NMSA decoding algorithm, the variable node update operation of each data channel in the iterative process is optimized. First, the initial message value of the current variable node is determined. Then, based on the optimized algorithm principle, a data substitution subtraction processing method is designed to obtain the updated message value of the variable node, as shown in the following formula: Where, Represents a slave variable node To the verification node The message value, Representative The bit reliability of the message value at iterations; Represents variable node The initial message value of is the partial sum value, which includes all nodes except the check node Except for the variable nodes The sum of the message values transmitted by the connected check nodes; partial sum Cache as an intermediate variable during iteration.

8. The high-speed LDPC decoding method for wideband signals with low computing power requirements according to claim 1, characterized in that: In step S4, after the iteration stop strategy is satisfied, the variable node update messages and initial messages cached during the decoding process are read in sequence and summed up; after performing a logical judgment based on the sign bit on the summation result, the decoding bit sequence corresponding to the long codeword is obtained.

9. A high-speed LDPC decoding device for broadband signals with low computing power requirements, characterized in that: The device includes a user-driven system and an underlying decoding system in communication connection, wherein: The user-driven system is used to receive input of data frames to be decoded and configuration parameters, and transmit them to the underlying decoding system. At the same time, it receives the decoding result data uploaded by the underlying decoding system after decoding, and performs business function applications. It is also used to issue commands to perform soft switching of parallelism parameters of the decoding device to meet the requirements of multi-channel concurrent processing of long codewords of large-bandwidth satellite signals under low computing power requirements. The underlying decoding system includes the following functional modules: The state active conversion module is used to serially read multiple adjacent codewords in the data frame to be decoded and, based on the length threshold and number of concurrent paths in the configuration parameters, perform serial-to-parallel conversion on long codewords whose length exceeds the preset threshold. It is also used to support concurrent path reconfiguration, reconstruct the programmable logic path for decoding long codewords in the satellite's large-bandwidth signal, and construct multiple channels of data for concurrent processing. The message matrix cache module is used to cache the data frames to be decoded that are serially read into the state active conversion module; The node iterative calculation module is used to perform iterative calculations on variable nodes and check nodes in the long codeword in a multi-channel concurrent manner based on the data cached in the message matrix cache module, and update the message value of the corresponding node; A decision processing integration module is used to determine the decoding bit sequence based on the symbol decision according to the message values of the variable nodes and the check nodes after the current iteration update when the iteration stop strategy is met, and integrate it into the decoding result data corresponding to the data frame to be decoded; The result data uploading module uploads the decoding result data obtained by the decision processing integration module to the user drive system based on the data frame to be decoded and the configuration parameters obtained by the state active conversion module.

10. The high-speed LDPC decoding device for wideband signals with low computing power requirements according to claim 9, characterized in that: The node iteration calculation module is also used to store the message values of the variable nodes and the verification nodes updated after each iteration calculation into the calculation data storage call array; the decision processing integration module obtains the message values of the variable nodes and the verification nodes when the iteration stops from the calculation data storage call array.

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