Method and circuit for switching transmitting and receiving directions of half-duplex serial communication

Abstract

The invention provides a method and a circuit for switching transmitting and receiving directions of half-duplex serial communication, and the method comprises the steps: collecting an electric signal of an A-end serial receiving data line in real time, and obtaining a first waveform containing an L1 level different from an idle state L0 level on the serial receiving data line, carrying out lagging and extension conversion on the first waveform to obtain a second waveform, carrying out union operation on L1 level time periods of the first waveform and the second waveform to obtain a third waveform, and setting half-duplex serial communication in an A-end sending state in the L1 level time period of the third waveform; and setting half-duplex serial communication to be in an A-end receiving state outside the L1 level time period of the third waveform. The circuit comprises an input circuit, a level delay circuit and an output circuit. According to the invention, automatic switching of transmitting and receiving directions of half-duplex communication can be realized, and the reliability of communication can be ensured especially in an occasion with a high communication rate.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, in particular to a method and a circuit for switching the transmitting and receiving directions of half-duplex serial communication. Background Art

[0002] Half-duplex communication, especially half-duplex communication based on RS485 interface technology, is widely used due to its advantages such as strong anti-interference ability, long transmission distance, simple wiring, and suitability for multi-machine networking communication. However, half-duplex communication involves switching the direction of sending and receiving data, which also brings additional troubles to users.

[0003] Existing solutions include: Solution 1: Programming controls the microprocessor pins to switch the transmit and receive directions of the half-duplex communication chip. This solution requires a program to detect and determine the communication transmission status, which increases the cost of software and hardware.

[0004] Solution 2: By connecting an inverter in series between the single-ended data receiving pin and the direction control pin of the half-duplex communication chip, the single-ended data level is inverted and then the transmit and receive direction of the half-duplex communication chip is controlled. This solution will cause the transmit and receive direction of the half-duplex communication chip to switch too frequently, so it is susceptible to interference and is only suitable for occasions with low baud rates.

[0005] Solution 3, based on Solution 2, adds an RC integrator circuit between the inverter and the single-ended data receiving pin. Although this solution can keep the half-duplex communication chip in the transmitting state during the communication process, the RC integrator circuit will cause signal delay, resulting in the direction control signal arriving at the corresponding pin of the duplex communication chip later than the single-ended data signal. Especially in the case of high baud rate, data transmission errors will occur. Summary of the Invention

[0006] In order to solve the problems in the prior art of high cost of controlling the receiving and transmitting directions in half-duplex communication and unsuitability for high baud rate applications, the present invention aims to provide a method and circuit for switching the receiving and transmitting directions of half-duplex serial communication.

[0007] In a first aspect, the present invention provides a method for switching the transmission and reception direction of half-duplex serial communication, comprising: collecting data from a serial receive data line at end A in real time, obtaining a first waveform including an L1 level different from an idle state L0 level on the serial receive data line at end A, performing a hysteresis and extension transformation on the first waveform to obtain a second waveform, performing a union operation on the L1 level time periods of the first and second waveforms to obtain a third waveform, setting half-duplex serial communication as a transmitting state for end A during the L1 level time period of the third waveform, and setting half-duplex serial communication as a receiving state for end A outside the L1 level time period of the third waveform; Wherein, the half-duplex communication chip includes two data ports, end A and end B, and a direction control end; The A port includes a data receiving pin and a data sending pin; The serial A-end receiving data line is directly or indirectly connected to the A-end data receiving pin of the half-duplex communication chip; The L0 level can be a high level, a low level or a high-impedance state; the L1 level can be a high level or a low level; The lag and extension transformation of the first waveform comprises the following steps: when the first waveform starts at level L1, high-frequency filtering with a cutoff frequency of F0 is performed on the first waveform, so that the start time of the L1 level of the second waveform is delayed by a time duration of T0 for the start time of the L1 level of the first waveform; when the first waveform ends at level L1, high-frequency filtering with a cutoff frequency of F1 is performed on the first waveform, so that the end time of the L1 level of the second waveform is delayed by a time duration of T1 for the end time of the L1 level of the first waveform; and setting F0 to be greater than F1 so that the T0 duration is shorter than the T1 duration. The union operation is specifically a logic OR operation when the L1 level is high, and a logic AND operation when the L1 level is low; The receiving state of the A end is: the data flow of the half-duplex communication chip flows from the B end to the A end; The sending state of the A end is: the data flow of the half-duplex communication chip flows from the A end to the B end; The setting of the sending / receiving state of end A: when the L1 level and the sending state control enable level of end A are opposite, the L1 level is inverted and connected to the sending / receiving state control end of end A; when the L1 level and the sending state control enable level of end A are the same, the L1 level is directly connected to the sending / receiving state control end of end A.

[0008] In one possible scenario, when the first waveform has more than one L1 level segment, a lag and extension transformation is performed on each L1 level segment of the first waveform. If the transformed L1 level segments have temporal intersection, a union operation is performed on the temporally overlapping L1 level segments to obtain a second waveform.

[0009] In one possible scenario, a hysteresis transformation is performed on the first waveform to obtain a fourth waveform, and the fourth waveform is input to the A-end serial data receiving pin of a half-duplex serial communication chip.

[0010] The hysteresis transformation method described therein: High-frequency filtering is performed on the first waveform to slow down the level flip edge and delay the signal flip to reach the high / low level trigger threshold.

[0011] Alternatively, a delay trigger is used to input the first waveform into a digital circuit or microprocessor with a delay function, and then output it after a delay operation.

[0012] In one possible scenario, the half-duplex serial communication is RS485 communication: the RS485 single-ended serial receive data line electrical signal is collected in real time, a first waveform including a voltage of the serial receive data line at a low level is obtained, the first waveform is subjected to the hysteresis and extension transformation to obtain a second waveform, a low-level logic AND operation is performed on the first waveform and the second waveform to obtain a third waveform, the RS485 communication within the low-level time period of the third waveform is set to a single-ended signal to differential signal transmission direction; the RS485 communication outside the low-level time period of the third waveform is set to a differential signal to single-ended signal transmission direction.

[0013] In a second aspect, a circuit for switching the receiving and transmitting direction of half-duplex serial communication is provided, comprising: an input circuit, a level delay circuit, and an output circuit.

[0014] The input circuit is used to increase the driving capability of the input single-ended signal and isolate the influence of the level delay circuit on the input single-ended signal. The input circuit is provided with an input port and an output port; The level delay circuit for extending the low level holding time of the input single-ended signal, the level delay circuit is provided with at least one input port and an output port; The output circuit is used to set the direction of the circuit for half-duplex serial communication transmission and reception, the output circuit is provided with at least two input ports and one output port, and the working logic of the output circuit is: when all its input ports input high level, its output port outputs low level, otherwise its output port outputs high level; The connection relationship between the input circuit, the level delay circuit, and the output circuit is as follows: Two input port states are set for the level delay circuit: the input port of the input circuit, one input port of the level delay circuit, and one input port of the output circuit are connected to each other, the output port of the input circuit is connected to the other input port of the level delay circuit, and the output port of the level delay circuit is connected to the other input port of the output circuit; When the level delay circuit sets an input port state: the input port of the input circuit is connected to one of the input ports of the output circuit, the output port of the input circuit is connected to an input port of the level delay circuit, and the output port of the level delay circuit is connected to another input port of the output circuit.

[0015] Preferably, the input circuit may be, but is not limited to, any one of a voltage / current driver, a voltage follower, a voltage / current amplifier, a buffer gate circuit, an OC gate circuit, a push-pull output circuit, a Smith trigger, an optoelectronic isolator, and a magnetic coupling isolator.

[0016] Preferably: the level delay circuit includes a diode D1, a resistor R1 and a capacitor C1; For the level delay circuit, two input port states are set: The cathode of the diode D1 serves as an input port of the level delay circuit and is connected to the output port of the input circuit. The anode of the diode D1 is connected to one end of the resistor R1 and one end of the capacitor C1 as the output port of the level delay circuit. The other end of the resistor R1 serves as another input port of the level delay circuit and is connected to the input port of the input circuit. The other end of the capacitor C1 is grounded.

[0017] For the level delay circuit, an input port state is set: The cathode of the diode D1 serves as an input port of the level delay circuit and is connected to the output port of the input circuit. The anode of the diode D1 is connected to one end of the resistor R1 and one end of the capacitor C1 as the output port of the level delay circuit. The other end of the resistor R1 is connected to a power supply or the cathode of the diode D1, and the other end of the capacitor C1 is grounded.

[0018] Preferably, the output circuit is a NAND gate circuit or other circuits that can meet the working logic of the output circuit.

[0019] Further preferably, a waveform hysteresis circuit is connected in series between the single-ended serial receive data line and the single-ended data receiving end of the half-duplex transceiver chip, so as to cause the waveform to lag for a certain time in time, thereby ensuring that the transmitted data signal arrives at the corresponding pin of the half-duplex transceiver chip later than the transmit and receive direction control signal.

[0020] The waveform hysteresis circuit is a circuit that has the function of delaying the time for generating the rising / falling edge of a digital signal, and may be, but is not limited to, a low-pass filter, a gate circuit, or a programmable logic circuit.

[0021] In a third aspect, the present invention provides a computer device comprising a memory, a processor and a transceiver which are communicatively connected in sequence, wherein the memory is used to store a computer program, the transceiver is used to send and receive messages, and the processor is used to read the computer program and execute the method for switching the transmission and reception direction of half-duplex serial communication as described in the first aspect or any possible design of the first aspect.

[0022] In a fourth aspect, the present invention provides a computer-readable storage medium having instructions stored thereon. When the instructions are executed on a computer, the method for switching the transmission and reception direction of half-duplex serial communication as described in the first aspect or any possible design of the first aspect is executed.

[0023] In a fifth aspect, the present invention provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute the method for switching the transmitting and receiving directions of half-duplex serial communications as described in the first aspect or any possible design of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of waveforms and levels involved in the method for switching the transmitting and receiving directions of half-duplex serial communication provided by the present invention.

[0026] Figure 2 The present invention provides an example of using the circuit for switching the receiving and transmitting directions of half-duplex serial communication in the mutual conversion between LVDS and single-ended signals.

[0027] Figure 3 The present invention provides an example of using the circuit for switching the receiving and transmitting directions of half-duplex serial communication in RS485 communication.

[0028] Figure 4 The fourth waveform and level diagram is expanded in the method for switching the transmitting and receiving directions of half-duplex serial communication provided by the present invention.

[0029] Figure 5 This is an implementation example of the circuit expansion waveform hysteresis circuit for switching the transmitting and receiving directions of half-duplex serial communication provided by the present invention.

[0030] Figure 6 This is the first level delay circuit implementation case provided by the present invention.

[0031] Figure 7 This is an implementation example of the second level delay circuit provided by the present invention.

[0032] Figure 8 This is an example of using a voltage follower to implement an input circuit provided by the present invention.

[0033] Figure 9 The present invention provides an example of using a Smith trigger to implement an input circuit and a NOR gate to implement an output circuit. DETAILED DESCRIPTION

[0034] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that although the description of these embodiments is intended to help understand the present invention, it does not constitute a limitation of the present invention. The specific structural and functional details disclosed herein are merely intended to describe exemplary embodiments of the present invention. However, the present invention can be embodied in many alternative forms, and it should not be understood that the present invention is limited to the embodiments set forth herein.

[0035] It should be understood that although the terms first, second, etc. may be used herein to describe various objects, these objects should not be limited by these terms. These terms are merely used to distinguish one object from another. For example, a first object can be referred to as a second object, and similarly, a second object can be referred to as a first object without departing from the scope of the exemplary embodiments of the present invention.

[0036] It should be understood that the term "and / or" that may appear in this document is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may indicate three situations: A exists alone, B exists alone, or A and B exist at the same time. The term " / and" that may appear in this document describes another type of association object relationship, indicating that two relationships may exist. For example, A / and B may indicate two situations: A exists alone, or A and B exist at the same time. In addition, the character " / " that may appear in this document generally indicates that the previous and subsequent associated objects are in an "or" relationship.

[0037] like Figure 1As shown, the waveform and level diagram involved in the method for switching the transmission and reception direction of half-duplex serial communication provided by this embodiment is used to describe the control signal generation principle and process of switching the transmission and reception direction of half-duplex serial communication. It can be executed in, but not limited to, digital circuits, analog circuits, mixed digital-analog circuits, microprocessors, programmable logic devices, and computer equipment with certain computing resources and data acquisition functions to achieve automatic switching of the transmission and reception direction of half-duplex serial communication, especially to ensure communication reliability in situations where the communication rate is high! like Figure 1 As shown, the method of switching the receiving and transmitting direction of half-duplex serial communication may include but is not limited to The first waveform, the second waveform, the third waveform, and the transmit and receive direction control level waveform, The specific implementation process is as follows: Using an input circuit to collect in real time an electrical signal of a serial receive data line at end A of a half-duplex serial communication chip, and obtaining a first waveform including an L1 level on the serial receive data line that is different from an L0 level in an idle state; Using a level delay circuit to delay and extend the first waveform to obtain a second waveform; Using an output circuit, performing a union operation on the L1 level time periods of the first waveform and the second waveform to obtain a third waveform; The output port of the output circuit sets the half-duplex serial communication to the A-end sending state during the L1 level time period of the third waveform; and sets the half-duplex serial communication to the A-end receiving state outside the L1 level time period of the third waveform; like Figure 2 The circuit for switching the receiving and transmitting direction of half-duplex serial communication provided in the first aspect of this embodiment is used to switch the receiving and transmitting direction of the LVDS differential signal and single-ended signal conversion chip SN65MLVD200A based on half-duplex communication.

[0038] like Figure 2 As shown in the figure: SN65MLVD200A chip U3 has two data ports, single-ended and differential, and transceiver control pins, where the single-ended port includes DI (driver input) pin and RO (Receive output) pin; the differential port includes two LVDS input and output pins A and B; the transceiver control pins include RE (Receiver Output Enable Active Low) pin and DE (Driver Output Enable Active HIGH) pin.

[0039] like Figure 2The circuit shown for switching the receiving and transmitting direction of half-duplex serial communication includes an input circuit implemented by a buffer chip U1 (the input circuit can also be, but is not limited to, implemented by a voltage / current driver, a voltage follower, a voltage / current amplifier, an OC gate circuit, a push-pull output circuit, a Smith trigger, an optoelectronic isolator, and a magnetic coupling isolator), a level delay circuit composed of a resistor R1, a capacitor C1, and a diode D1, and an output circuit implemented by a NAND gate U2 (the output circuit can also be a NOR gate (NOR gate: each input signal is logically inverted and then a logical OR operation is performed) circuit or other circuits that can meet the working logic of the output circuit).

[0040] The circuit for switching the receiving and transmitting direction of half-duplex serial communication is connected to the SN65MLVD200A chip U3 in the following way: the DI (driver input) pin of U3, the input pin of U1, and one input pin of U2 are short-circuited to each other, and the short-circuit point is set as node A (node A is Figure 1 The first waveform collection point shown in the figure); short-circuit the output pin of U2, the RE (Receiver Output Enable Active Low) pin of U3, and the DE (Driver Output Enable Active HIGH) pin to each other, and set this short-circuit point as node C (node C is Figure 1 The third waveform shown is collected after being inverted).

[0041] In addition, the anode of diode D1, capacitor C1, resistor R1 and the input port of the output circuit are short-circuited to form node B (node B is Figure 1 The second waveform acquisition point is shown).

[0042] The working principle of this circuit embodiment is as follows: 1. Data to be sent ( Figure 1 The first waveform shown in FIG. 1 is serially input to the node A. When the data is in the idle state, the node A is at a high level, the output of the buffer U1 is at a high level, the diode D1 is in the cut-off state, the capacitor C1 is charged through the resistor R1, the node B is at a high level, and the output pin (node C) of the NAND gate U2 is at a low level, so that the U3 chip is in the receiving state.

[0043] 2. When the data stream to be sent ( Figure 1 When the first waveform shown in FIG1 is the start bit (low level), the input pin of the NAND gate U2 connected to the node A is low, and the output of the NAND gate U2 (node C) is high, so that the U3 chip state is in the sending state; at the same time, the output of the buffer U1 is low, and the capacitor C1 is discharged through the diode D1.

[0044] 3. When the data stream to be sent sends payload data: if the data is at a low level, the capacitor C1 continues to discharge through the diode D1; if the data is at a high level, the diode D1 is cut off, and the capacitor C1 is charged through the resistor R1. Here, the resistance of the resistor R1 is set to be greater than or equal to 8 times the forward resistance of the diode, so that the charging time of the capacitor C1 is greater than or equal to 8 times the discharge time, that is, it can be ensured that during the data transmission process, only the low level holding time of the start bit is required to discharge the capacitor C1, that is, it can be ensured that the voltage of the node B during the communication byte cycle (except the start bit) is maintained within the low level threshold range, ensuring that the input pin of the NAND gate U2 connected to the node B inputs a low level, and the output of the NAND gate U2 (node C) is high, so that the U3 chip state is in the sending state.

[0045] 4. When the data to be sent is completed, that is, the data is in the idle state: the node A is high, the output of the buffer U1 is high, the diode D1 is in the cut-off state, and the capacitor C1 is charged through the resistor R1; the node B returns to a high level, and the output pin (node C) of the NAND gate U2 is low, causing U3 to automatically switch to the receiving state.

[0046] The advantage of using this embodiment is that it can realize automatic switching of the receiving and transmitting directions when the baud rate of the LVDS differential signal and the single-ended signal communication is greater than 500K. When the node A receives data, the delay of the node C switching from the low level to the high level is small, and only a low level of the data start bit is required to ensure that the state of the node C always remains at a high level during the entire data transmission cycle, ensuring that the LVDS differential signal is in the transmission state during the entire transmission cycle.

[0047] like Figure 3 The circuit for switching the receiving and transmitting direction of half-duplex serial communication provided by the second aspect of the present embodiment is used to switch the receiving and transmitting direction of the RS485 communication interface chip MAX485 based on half-duplex communication:

[0048] like Figure 3 As shown: The MAX485 chip U3 has two data ports, single-ended and differential, and transceiver control pins, wherein the single-ended port includes the DI (driver input) pin and the RO (Receive output) pin; the differential port includes two RS485 differential signal input and output pins A and B; the transceiver control pins include the RE (Receiver Output Enable Active Low) pin and the DE (Driver Output Enable Active HIGH) pin.

[0049] like Figure 3The circuit shown for switching the receiving and transmitting direction of half-duplex serial communication includes an input circuit composed of a voltage follower implemented by U1 (the input circuit can also be, but is not limited to, implemented by a voltage / current driver, a voltage / current amplifier, a buffer gate circuit, an OC gate circuit, a push-pull output circuit, a Smith trigger, an optoelectronic isolator, and a magnetic coupling isolator), a level delay circuit composed of a resistor R1, a capacitor C1, and a diode D1, and an output circuit implemented by a NAND gate U2 (the output circuit can also be a NOR gate (NOR gate: each input signal is logically inverted and then a logical OR operation is performed) circuit or other circuits that can meet the working logic of the output circuit).

[0050] The circuit for switching the receiving and transmitting direction of half-duplex serial communication is connected to the MAX485 chip U3 in the following way: the DI (driver input) pin of U3, the input pin of U1, and one input pin of U2 are short-circuited to each other, and the short-circuit point is set as node A (node A is Figure 1 The first waveform collection point shown); short-circuit the output pin of U2, the RE (Receiver Output Enable Active Low) pin of U3, and the DE (Driver Output Enable Active HIGH) pin to each other, and set this short-circuit point as node C (node C is Figure 1 The third waveform shown is collected after being inverted).

[0051] In addition, the anode of diode D1, capacitor C1, resistor R1 and the input port of the output circuit are short-circuited to form node B (node B is Figure 1 The second waveform acquisition point is shown).

[0052] The working principle of this circuit embodiment is as follows: 1. The data to be sent (single-ended signal to differential signal) is serially input to the node A. When the data is in the idle state: the node A is high, the output of the buffer U1 is high, the diode D1 is in the cut-off state, the capacitor C1 is charged through the resistor R1, the node B is high, and the output pin of the NAND gate U2 (node C) is low, so that the RS485 transceiver chip is in the receiving state.

[0053] 2. When the data stream to be sent is the start bit (low level): the input pin of the NOT gate U2 connected to the node A is low level, and the output of the NOT gate U2 (node C) is high level, so that the RS485 transceiver chip is in the sending state; at the same time, the output of the buffer U1 is low level, and the capacitor C1 is discharged through the diode D1.

[0054] 3. When the data stream to be sent sends payload data: if the data is at a low level, capacitor C1 continues to discharge through diode D1; if the data is at a high level, diode D1 is cut off, and capacitor C1 is charged through resistor R1. The resistance of resistor R1 is set to be greater than or equal to 8 times the forward resistance of the diode, so that the charging time of capacitor C1 is greater than or equal to 8 times the discharge time. This ensures that during the data transmission process, only the low level holding time of the start bit is required to discharge capacitor C1. This ensures that the voltage of node B remains within the low level threshold range during the communication byte cycle (excluding the start bit), ensures that the input pin of the NAND gate U2 connected to node B inputs a low level, and the output of the NAND gate U2 (node C) is high, so that the RS485 transceiver chip is in the sending state.

[0055] 4. When the data to be sent is completed, that is, the data is in the idle state: the node A is high, the output of the buffer U1 is high, the diode D1 is in the cut-off state, and the capacitor C1 is charged through the resistor R1; the node B returns to a high level, and the output pin (node C) of the NAND gate U2 is low, so that the RS485 transceiver chip automatically switches to the receiving state.

[0056] The advantage of using this circuit is that it can realize automatic switching of the sending and receiving directions when the RS485 communication baud rate is greater than 500K. When the node A receives data, the node C switches from a low level to a high level with a small delay, and only a low level of the data start bit is required to ensure that the state of the node C always remains at a high level during the entire data sending cycle, ensuring that the RS485 is in a sending state during the entire sending cycle.

[0057] Furthermore, this circuit is also applicable when the RS485 communication baud rate is less than or equal to 500K. When the entire data transmission cycle (single-ended signal to differential signal) is greater than the charging cycle of capacitor C1, during the data transmission process, both node B and node A are in a high-level state, causing node C to be in a low-level state. At this time, the RS485 transceiver chip is in a receiving state, and RS485 A and B are in a high-impedance input state. A is pulled high by the pull-up resistor, and B is pulled low by the pull-down resistor. AB>0, the 485 bus is in a logic 1 state, and the 485 differential level output is a logic 1 when the transmitted single-ended level is high.

[0058] Based on the technical solutions of the first and second aspects, this embodiment further provides a third possible design, namely: Figure 4As shown, the first waveform is also delayed to obtain the fourth waveform, ensuring that the third waveform switches the half-duplex chip to the A-end sending state earlier than the valid data contained in the fourth waveform reaches the DI (driver input) pin of the half-duplex chip. like Figure 5 As shown, in Figure 2 、 Figure 3 Based on the circuit for switching the receiving and transmitting direction of half-duplex serial communication shown in FIG, at the DI (driver input) pin of the half-duplex chip (assuming the DI pin is node D, node D is Figure 4 Before the fourth waveform collection point shown in FIG4 , at least one signal hysteresis chip U4 is connected in series (a plurality of the signal hysteresis chips are connected in cascade, and the signal hysteresis chip can be implemented by, but is not limited to, a voltage / current driver, a voltage follower, a voltage / current amplifier, an OC gate circuit, a push-pull output circuit, a Smith trigger, an optoelectronic isolator, a magnetic coupling isolator, or a combination of the above chips).

[0059] Based on the technical solutions of the first and second aspects, this embodiment further provides a fourth possible design, such as Figure 6 As shown, a circuit for switching the receiving and transmitting directions of half-duplex serial communication is shown: wherein the delay circuit is composed of a resistor R1, a capacitor C1, and a diode D1. One end of the resistor R1 is connected to the node B, and the other end can also be connected to the node A. When the level at point A is low, the resistor R1 serves as a discharge path for the capacitor C1.

[0060] Based on the technical solutions of the first and second aspects, this embodiment further provides a fifth possible design, such as Figure 7 As shown, the circuit for switching the receiving and transmitting direction of half-duplex serial communication: wherein the delay circuit is composed of a resistor R1, a capacitor C1, and a diode D1. The resistor R1 can also be directly connected in parallel with the diode D1, so that when the output of U1 is low, the resistor R1 serves as a discharge path for the capacitor C1.

[0061] Based on the technical solutions of the first and second aspects, this embodiment further provides a sixth possible design, such as Figure 8 As shown, the circuit for switching the receiving and transmitting direction of half-duplex serial communication: wherein the input circuit is implemented by a voltage follower formed by an operational amplifier U1.

[0062] Based on the technical solutions of the first and second aspects, this embodiment further provides a possible design seven, such as Figure 9 As shown, the circuit for switching the receiving and transmitting direction of half-duplex serial communication: wherein the input circuit is implemented by a Smith trigger U1, and the output circuit is implemented by a NOT-OR gate U2.

[0063] Finally, it should be noted that the present invention is not limited to the aforementioned optional embodiments. Anyone can derive various other product forms based on the teachings of this invention. The aforementioned specific embodiments should not be construed as limiting the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of protection of the present invention. The scope of protection of the present invention shall be based on the definition in the claims, and the specification shall be used to interpret the claims.

Claims

1. A method for switching the transmission and reception direction of half-duplex serial communication, characterized in that: include: An electrical signal of a serial receive data line at end A is collected in real time to obtain a first waveform including an L1 level on the serial receive data line that is different from an L0 level in an idle state. The first waveform is subjected to a hysteresis and extension transformation to obtain a second waveform. A union operation is performed on the L1 level time periods of the first and second waveforms to obtain a third waveform. During the L1 level time period of the third waveform, half-duplex serial communication is set to a transmitting state at end A; and outside the L1 level time period of the third waveform, half-duplex serial communication is set to a receiving state at end A.

2. The method for switching the transmission and reception direction of half-duplex serial communication according to claim 1, characterized in that When the first waveform has more than one L1 level segment, a lag and extension transformation is performed on each L1 level segment of the first waveform. If the transformed L1 level segments have temporal intersection, a union operation is performed on the temporally intersecting L1 level segments to obtain a second waveform.

3. The method for switching the transmitting and receiving directions of half-duplex serial communication according to claim 1, characterized in that: A fourth waveform is obtained by performing a hysteresis transformation on the first waveform, and the fourth waveform is input to the A-end serial data receiving pin of the half-duplex serial communication chip.

4. The method for switching the transmitting and receiving directions of half-duplex serial communication according to claim 1, characterized in that: When the half-duplex serial communication is RS485 communication: The method includes collecting an electrical signal of an RS485 single-ended serial receive data line in real time, obtaining a first waveform including a voltage of the serial receive data line at a low level, performing a hysteresis and extension transformation on the first waveform to obtain a second waveform, performing a low-level logical AND operation on the first waveform and the second waveform to obtain a third waveform, setting the RS485 communication within a low-level time period of the third waveform to a single-ended signal to differential signal transmission direction, and setting the RS485 communication outside the low-level time period of the third waveform to a differential signal to single-ended signal transmission direction.

5. A circuit for switching the receiving and transmitting direction of half-duplex serial communication, characterized in that The circuit comprises: An input circuit, configured to increase the driving capability of an input single-ended signal and isolate the influence of the level delay circuit on the input single-ended signal, wherein the input circuit is provided with an input port and an output port; Level delay circuit for extending the low level holding time of the input single-ended signal, the level delay circuit is provided with at least one input port and an output port; an output circuit, configured to set the transmit and receive direction of the half-duplex serial communication circuit, the output circuit being provided with at least two input ports and one output port, wherein the output circuit operates in such a manner that when all input ports input a high level, the output port outputs a low level; otherwise, the output port outputs a high level; Two input port states are set for the level delay circuit: the input port of the input circuit, one input port of the level delay circuit, and one input port of the output circuit are connected to each other, the output port of the input circuit is connected to the other input port of the level delay circuit, and the output port of the level delay circuit is connected to the other input port of the output circuit; When the level delay circuit sets an input port state: the input port of the input circuit is connected to one of the input ports of the output circuit, the output port of the input circuit is connected to an input port of the level delay circuit, and the output port of the level delay circuit is connected to another input port of the output circuit.

6. The circuit for switching the transmitting and receiving directions of half-duplex serial communication according to claim 5, wherein The input circuit may be, but is not limited to, any one of a voltage / current driver, a voltage follower, a voltage / current amplifier, a buffer gate circuit, an OC gate circuit, a push-pull output circuit, a Smith trigger, an optoelectronic isolator, and a magnetic coupling isolator.

7. The circuit for switching the transmitting and receiving directions of half-duplex serial communication according to claim 5, wherein , the level delay circuit includes a diode D1, a resistor R1 and a capacitor C1; For the level delay circuit, two input port states are set: The cathode of the diode D1 serves as an input port of the level delay circuit and is connected to the output port of the input circuit. The anode of the diode D1 is connected to one end of the resistor R1 and one end of the capacitor C1 to serve as the output port of the level delay circuit. The other end of the resistor R1 serves as another input port of the level delay circuit and is connected to the input port of the input circuit. The other end of the capacitor C1 is grounded. For the level delay circuit, an input port state is set: The cathode of the diode D1 serves as an input port of the level delay circuit and is connected to the output port of the input circuit. The anode of the diode D1 is connected to one end of the resistor R1 and one end of the capacitor C1 as the output port of the level delay circuit. The other end of the resistor R1 is connected to a power supply or the cathode of the diode D1, and the other end of the capacitor C1 is grounded.

8. The circuit for switching the receiving and transmitting directions of half-duplex serial communication according to claim 5, characterized in that the output circuit is a NAND gate circuit or other circuit that can meet the working logic of the output circuit.

9. The circuit for switching the transmitting and receiving directions of half-duplex serial communication according to claim 5, characterized in that: A waveform hysteresis circuit is connected in series between the single-ended serial receive data line and the single-ended data receiving end of the half-duplex transceiver chip. The waveform hysteresis circuit is used to lag the waveform for a certain time, ensuring that the transmitted data signal arrives at the corresponding pin of the half-duplex transceiver chip later than the transmit / receive direction control signal.

10. A computer device, characterized in that: The invention comprises a memory, a processor and a transceiver which are communicatively connected in sequence, wherein the memory is used to store a computer program, the transceiver is used to send and receive messages, and the processor is used to read the computer program and execute the method for switching the sending and receiving direction of half-duplex serial communication according to any one of claims 1 to 4.

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